From d352ec615a6568e65f4d440a242e299b2acbbc26 Mon Sep 17 00:00:00 2001 From: Sudeep Mohanty Date: Mon, 12 Feb 2024 13:53:11 +0100 Subject: [PATCH] feat(ulp-riscv): Added utility functions for atomicity This commit adds utility functions to enter and exit critical sections in the code flow by disabling and enabling interrupts. --- .../ulp_core/include/ulp_riscv_utils.h | 26 +++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/components/ulp/ulp_riscv/ulp_core/include/ulp_riscv_utils.h b/components/ulp/ulp_riscv/ulp_core/include/ulp_riscv_utils.h index 463da9d37c..acc47a28bf 100644 --- a/components/ulp/ulp_riscv/ulp_core/include/ulp_riscv_utils.h +++ b/components/ulp/ulp_riscv/ulp_core/include/ulp_riscv_utils.h @@ -132,6 +132,32 @@ void ulp_riscv_disable_sw_intr(void); */ void ulp_riscv_trigger_sw_intr(void); +/** + * @brief Enter a critical section by disabling all interrupts + * This inline assembly construct uses the t0 register and is equivalent to: + * + * li t0, 0x80000007 + * maskirq_insn(zero, t0) // Mask all interrupt bits + */ +#define ULP_RISCV_ENTER_CRITICAL() \ + asm volatile ( \ + "li t0, 0x80000007\n" \ + ".word 0x0602e00b" \ + ); \ + +/** + * @brief Exit a critical section by enabling all interrupts + * This inline assembly construct is equivalent to: + * + * maskirq_insn(zero, zero) // Unmask all interrupt bits + */ +#define ULP_RISCV_EXIT_CRITICAL() asm volatile (".word 0x0600600b"); + +#else /* CONFIG_ULP_RISCV_INTERRUPT_ENABLE */ + +#define ULP_RISCV_ENTER_CRITICAL() +#define ULP_RISCV_EXIT_CRITICAL() + #endif /* CONFIG_ULP_RISCV_INTERRUPT_ENABLE */ #ifdef __cplusplus