From 95133c179f82b2b3b68d0e0ec815ab34dab47518 Mon Sep 17 00:00:00 2001 From: Song Ruo Jing Date: Wed, 31 Jan 2024 17:08:15 +0800 Subject: [PATCH] feat(clk): preliminary clock tree support for ESP32C5 --- .../src/bootloader_clock_init.c | 2 +- components/esp_hw_support/CMakeLists.txt | 9 - .../port/esp32c5/esp_clk_tree.c | 40 +++- .../port/esp32c5/include/soc/rtc.h | 6 +- .../esp_hw_support/port/esp32c5/rtc_clk.c | 74 +++--- .../port/esp32c5/rtc_clk_init.c | 2 +- .../esp_hw_support/port/esp32c5/rtc_time.c | 81 ++++--- components/esp_pm/pm_impl.c | 18 +- .../patches/esp_rom_hp_regi2c_esp32c5.c | 159 +++++++------ .../esp_system/port/soc/esp32c5/Kconfig.cpu | 4 - .../port/soc/esp32c5/system_internal.c | 2 +- components/hal/esp32c5/clk_tree_hal.c | 6 +- .../hal/esp32c5/include/hal/clk_tree_ll.h | 113 +++++---- .../soc/esp32c5/include/soc/clk_tree_defs.h | 17 +- .../soc/esp32c5/include/soc/i2c_ana_mst_reg.h | 220 ++++++++++++++++++ components/soc/esp32c5/include/soc/reg_base.h | 1 + 16 files changed, 512 insertions(+), 242 deletions(-) create mode 100644 components/soc/esp32c5/include/soc/i2c_ana_mst_reg.h diff --git a/components/bootloader_support/src/bootloader_clock_init.c b/components/bootloader_support/src/bootloader_clock_init.c index 1f0dd50857..c42d885c2e 100644 --- a/components/bootloader_support/src/bootloader_clock_init.c +++ b/components/bootloader_support/src/bootloader_clock_init.c @@ -86,7 +86,7 @@ __attribute__((weak)) void bootloader_clock_configure(void) need to change back SPLL(480M) and set divider to 6 to use the 80M MSPIļ¼Œ and we need to check flash freq before restart as well */ clk_ll_mspi_fast_set_divider(1); - clk_ll_mspi_fast_sel_clk(MSPI_CLK_SRC_XTAL); + clk_ll_mspi_fast_set_src(MSPI_CLK_SRC_XTAL); #endif /* As a slight optimization, if 32k XTAL was enabled in sdkconfig, we enable diff --git a/components/esp_hw_support/CMakeLists.txt b/components/esp_hw_support/CMakeLists.txt index 5f044a4296..6b95e82235 100644 --- a/components/esp_hw_support/CMakeLists.txt +++ b/components/esp_hw_support/CMakeLists.txt @@ -180,15 +180,6 @@ if(NOT BOOTLOADER_BUILD) "port/esp_clk_tree_common.c" # TODO: [ESP32C5] IDF-8638, IDF-8640 ) endif() - if(CONFIG_IDF_TARGET_ESP32C5) - list(REMOVE_ITEM srcs - "sleep_cpu.c" # TODO: [ESP32C5] IDF-8638, IDF-8640 - "sleep_modes.c" # TODO: [ESP32C5] IDF-8638, IDF-8640 - "sleep_wake_stub.c" # TODO: [ESP32C5] IDF-8638, IDF-8640 - "sleep_gpio.c" # TODO: [ESP32C5] IDF-8638, IDF-8640 - "port/esp_clk_tree_common.c" # TODO: [ESP32C5] IDF-8638, IDF-8640 - ) - endif() else() # Requires "_esp_error_check_failed()" function list(APPEND priv_requires "esp_system") diff --git a/components/esp_hw_support/port/esp32c5/esp_clk_tree.c b/components/esp_hw_support/port/esp32c5/esp_clk_tree.c index b5ccf2ccbd..74560e1eb4 100644 --- a/components/esp_hw_support/port/esp32c5/esp_clk_tree.c +++ b/components/esp_hw_support/port/esp32c5/esp_clk_tree.c @@ -11,7 +11,8 @@ #include "soc/rtc.h" #include "hal/clk_tree_hal.h" #include "hal/clk_tree_ll.h" -#include "esp_private/esp_clk_tree_common.h" +// #include "esp_private/esp_clk_tree_common.h" +#include "sdkconfig.h" static const char *TAG = "esp_clk_tree"; @@ -19,7 +20,40 @@ esp_err_t esp_clk_tree_src_get_freq_hz(soc_module_clk_t clk_src, esp_clk_tree_sr uint32_t *freq_value) { // TODO: [ESP32C5] IDF-8642 - ESP_LOGW(TAG, "esp_clk_tree_src_get_freq_hz() has not implemented yet"); - *freq_value = 0; + ESP_RETURN_ON_FALSE(clk_src > 0 && clk_src < SOC_MOD_CLK_INVALID, ESP_ERR_INVALID_ARG, TAG, "unknown clk src"); + ESP_RETURN_ON_FALSE(precision < ESP_CLK_TREE_SRC_FREQ_PRECISION_INVALID, ESP_ERR_INVALID_ARG, TAG, "unknown precision"); + ESP_RETURN_ON_FALSE(freq_value, ESP_ERR_INVALID_ARG, TAG, "null pointer"); + + uint32_t clk_src_freq = 0; + switch (clk_src) { + case SOC_MOD_CLK_XTAL: + clk_src_freq = CONFIG_XTAL_FREQ * MHZ; + break; + case SOC_MOD_CLK_PLL_F80M: + clk_src_freq = CLK_LL_PLL_80M_FREQ_MHZ * MHZ; + break; + case SOC_MOD_CLK_PLL_F160M: + clk_src_freq = CLK_LL_PLL_160M_FREQ_MHZ * MHZ; + break; + case SOC_MOD_CLK_PLL_F240M: + clk_src_freq = CLK_LL_PLL_240M_FREQ_MHZ * MHZ; + break; + case SOC_MOD_CLK_SPLL: + clk_src_freq = CLK_LL_PLL_480M_FREQ_MHZ * MHZ; + break; + case SOC_MOD_CLK_RC_FAST: + // C5-beta3 unable to calibrate to get exact RC_FAST frequency + clk_src_freq = SOC_CLK_RC_FAST_FREQ_APPROX; + break; + case SOC_MOD_CLK_XTAL_D2: + clk_src_freq = (CONFIG_XTAL_FREQ * MHZ) >> 1; + break; + default: + break; + } + + ESP_RETURN_ON_FALSE(clk_src_freq, ESP_FAIL, TAG, + "freq shouldn't be 0, calibration failed"); + *freq_value = clk_src_freq; return ESP_OK; } diff --git a/components/esp_hw_support/port/esp32c5/include/soc/rtc.h b/components/esp_hw_support/port/esp32c5/include/soc/rtc.h index cef28d92b7..4e956d412b 100644 --- a/components/esp_hw_support/port/esp32c5/include/soc/rtc.h +++ b/components/esp_hw_support/port/esp32c5/include/soc/rtc.h @@ -134,7 +134,7 @@ typedef enum { RTC_CAL_RC32K = SOC_RTC_SLOW_CLK_SRC_RC32K, //!< Internal 32kHz RC oscillator, as one type of 32k clock RTC_CAL_32K_XTAL = SOC_RTC_SLOW_CLK_SRC_XTAL32K, //!< External 32kHz XTAL, as one type of 32k clock RTC_CAL_32K_OSC_SLOW = SOC_RTC_SLOW_CLK_SRC_OSC_SLOW, //!< External slow clock signal input by lp_pad_gpio0, as one type of 32k clock - RTC_CAL_RC_FAST //!< Internal 20MHz RC oscillator + // RTC_CAL_RC_FAST //!< Internal 20MHz RC oscillator } rtc_cal_sel_t; /** @@ -450,6 +450,10 @@ bool rtc_dig_8m_enabled(void); */ uint32_t rtc_clk_freq_cal(uint32_t cal_val); + +// -------------------------- CLOCK TREE DEFS ALIAS ---------------------------- +// **WARNING**: The following are only for backwards compatibility. +// Please use the declarations in soc/clk_tree_defs.h instead. /** * @brief Possible main XTAL frequency values. TODO: To be removed! */ diff --git a/components/esp_hw_support/port/esp32c5/rtc_clk.c b/components/esp_hw_support/port/esp32c5/rtc_clk.c index bb00b22231..7ce9bb4cff 100644 --- a/components/esp_hw_support/port/esp32c5/rtc_clk.c +++ b/components/esp_hw_support/port/esp32c5/rtc_clk.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -159,21 +159,20 @@ static void rtc_clk_enable_i2c_ana_master_clock(bool enable) static void rtc_clk_bbpll_configure(soc_xtal_freq_t xtal_freq, int pll_freq) { - assert((pll_freq == CLK_LL_PLL_160M_FREQ_MHZ) || \ - (pll_freq == CLK_LL_PLL_240M_FREQ_MHZ)); /* Digital part */ - clk_ll_bbpll_set_freq_mhz(CLK_LL_PLL_480M_FREQ_MHZ); + clk_ll_bbpll_set_freq_mhz(pll_freq); /* Analog part */ rtc_clk_enable_i2c_ana_master_clock(true); /* BBPLL CALIBRATION START */ regi2c_ctrl_ll_bbpll_calibration_start(); - clk_ll_bbpll_set_config(CLK_LL_PLL_480M_FREQ_MHZ, xtal_freq); + clk_ll_bbpll_set_config(pll_freq, xtal_freq); /* WAIT CALIBRATION DONE */ while(!regi2c_ctrl_ll_bbpll_calibration_is_done()); + esp_rom_delay_us(10); // wait for true stop // TODO: check this /* BBPLL CALIBRATION STOP */ regi2c_ctrl_ll_bbpll_calibration_stop(); rtc_clk_enable_i2c_ana_master_clock(false); - s_cur_pll_freq = CLK_LL_PLL_480M_FREQ_MHZ; + s_cur_pll_freq = pll_freq; } /** @@ -184,24 +183,26 @@ static void rtc_clk_bbpll_configure(soc_xtal_freq_t xtal_freq, int pll_freq) static void rtc_clk_cpu_freq_to_xtal(int cpu_freq, int div) { /* Configure clk mspi fast to XTAL*/ - clk_ll_mspi_fast_sel_clk(SOC_MOD_CLK_XTAL); + clk_ll_mspi_fast_set_src(MSPI_CLK_SRC_XTAL); clk_ll_mspi_fast_set_divider(1); - clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_XTAL); - clk_ll_ahb_set_divider(div); clk_ll_cpu_set_divider(div); + clk_ll_ahb_set_divider(div); + clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_XTAL); + clk_ll_bus_update(); esp_rom_set_cpu_ticks_per_us(cpu_freq); } static void rtc_clk_cpu_freq_to_8m(void) { /* Configure clk mspi fast to XTAL*/ - clk_ll_mspi_fast_sel_clk(SOC_MOD_CLK_XTAL); + clk_ll_mspi_fast_set_src(MSPI_CLK_SRC_XTAL); clk_ll_mspi_fast_set_divider(1); - clk_ll_ahb_set_divider(1); clk_ll_cpu_set_divider(1); + clk_ll_ahb_set_divider(1); clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_RC_FAST); + clk_ll_bus_update(); esp_rom_set_cpu_ticks_per_us(20); } @@ -218,11 +219,12 @@ static void rtc_clk_cpu_freq_to_pll_mhz(int cpu_freq_mhz) clk_ll_ahb_set_divider(cfg.source_freq_mhz / 40); clk_ll_cpu_set_divider(cfg.div); clk_ll_cpu_set_src(cfg.source); + clk_ll_bus_update(); esp_rom_set_cpu_ticks_per_us(cpu_freq_mhz); /* Configure clk mspi fast to 80m*/ clk_ll_mspi_fast_set_divider(6); - clk_ll_mspi_fast_sel_clk(MSPI_CLK_SRC_SPLL); + clk_ll_mspi_fast_set_src(MSPI_CLK_SRC_SPLL); } bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t *out_config) @@ -233,19 +235,34 @@ bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t *ou uint32_t real_freq_mhz; uint32_t xtal_freq = (uint32_t)rtc_clk_xtal_freq_get(); - if (freq_mhz == 48 || freq_mhz == 24 || freq_mhz == 16 || freq_mhz == 12 || freq_mhz == 8) { +#if (CONFIG_XTAL_FREQ == 48) + // To maintain APB_MAX (40MHz) while lowering CPU frequency when using a 48MHz XTAL, have to let CPU frequnecy be + // 40MHz with PLL_F160M or PLL_F240M clock source. This is a special case, has to handle separately. + if (freq_mhz == 40) { + real_freq_mhz = freq_mhz; + source = SOC_CPU_CLK_SRC_PLL_F160M; + source_freq_mhz = CLK_LL_PLL_160M_FREQ_MHZ; + divider = CLK_LL_PLL_160M_FREQ_MHZ / freq_mhz; + } else +#endif + if (freq_mhz <= xtal_freq && freq_mhz != 0) { divider = xtal_freq / freq_mhz; + real_freq_mhz = (xtal_freq + divider / 2) / divider; /* round */ + if (real_freq_mhz != freq_mhz) { + // no suitable divider + return false; + } + source_freq_mhz = xtal_freq; source = SOC_CPU_CLK_SRC_XTAL; + } else if (freq_mhz == 240) { real_freq_mhz = freq_mhz; - } else if (freq_mhz == 240 || freq_mhz == 120) { - real_freq_mhz = freq_mhz; - source = SOC_CPU_CLK_SRC_PLL_F240; + source = SOC_CPU_CLK_SRC_PLL_F240M; source_freq_mhz = CLK_LL_PLL_240M_FREQ_MHZ; divider = CLK_LL_PLL_240M_FREQ_MHZ / freq_mhz; - }else if (freq_mhz == 160 || freq_mhz == 80 || freq_mhz == 40) { + } else if (freq_mhz == 160 || freq_mhz == 80) { // TODO: 80MHz can be get from PLL_F240M or PLL_F160M, which is better? real_freq_mhz = freq_mhz; - source = SOC_CPU_CLK_SRC_PLL_F160; + source = SOC_CPU_CLK_SRC_PLL_F160M; source_freq_mhz = CLK_LL_PLL_160M_FREQ_MHZ; divider = CLK_LL_PLL_160M_FREQ_MHZ / freq_mhz; } else { @@ -271,21 +288,22 @@ void rtc_clk_cpu_freq_set_config(const rtc_cpu_freq_config_t *config) if (config->source == SOC_CPU_CLK_SRC_XTAL) { /* Configure clk mspi fast to 80m*/ rtc_clk_cpu_freq_to_xtal(config->freq_mhz, config->div); - if (((old_cpu_clk_src == SOC_CPU_CLK_SRC_PLL_F160) || (old_cpu_clk_src == SOC_CPU_CLK_SRC_PLL_F240)) && !s_bbpll_digi_consumers_ref_count) { + if (((old_cpu_clk_src == SOC_CPU_CLK_SRC_PLL_F160M) || (old_cpu_clk_src == SOC_CPU_CLK_SRC_PLL_F240M)) && !s_bbpll_digi_consumers_ref_count) { // We don't turn off the bbpll if some consumers depend on bbpll rtc_clk_bbpll_disable(); } - } else if ((config->source == SOC_CPU_CLK_SRC_PLL_F160) || (config->source == SOC_CPU_CLK_SRC_PLL_F240)) { - if ((old_cpu_clk_src != SOC_CPU_CLK_SRC_PLL_F160) && (old_cpu_clk_src != SOC_CPU_CLK_SRC_PLL_F240)) { + } else if ((config->source == SOC_CPU_CLK_SRC_PLL_F160M) || (config->source == SOC_CPU_CLK_SRC_PLL_F240M)) { + if ((old_cpu_clk_src != SOC_CPU_CLK_SRC_PLL_F160M) && (old_cpu_clk_src != SOC_CPU_CLK_SRC_PLL_F240M)) { + // PLL_F160M and PLL_F240M both derived from S(BB)PLL (480MHz) rtc_clk_set_cpu_switch_to_bbpll(SLEEP_EVENT_HW_BBPLL_EN_START); rtc_clk_bbpll_enable(); - rtc_clk_bbpll_configure(rtc_clk_xtal_freq_get(), config->source_freq_mhz); + rtc_clk_bbpll_configure(rtc_clk_xtal_freq_get(), CLK_LL_PLL_480M_FREQ_MHZ); } rtc_clk_cpu_freq_to_pll_mhz(config->freq_mhz); rtc_clk_set_cpu_switch_to_bbpll(SLEEP_EVENT_HW_BBPLL_EN_STOP); } else if (config->source == SOC_CPU_CLK_SRC_RC_FAST) { rtc_clk_cpu_freq_to_8m(); - if (((old_cpu_clk_src == SOC_CPU_CLK_SRC_PLL_F160) || (old_cpu_clk_src == SOC_CPU_CLK_SRC_PLL_F240)) && !s_bbpll_digi_consumers_ref_count) { + if (((old_cpu_clk_src == SOC_CPU_CLK_SRC_PLL_F160M) || (old_cpu_clk_src == SOC_CPU_CLK_SRC_PLL_F240M)) && !s_bbpll_digi_consumers_ref_count) { // We don't turn off the bbpll if some consumers depend on bbpll rtc_clk_bbpll_disable(); } @@ -305,13 +323,13 @@ void rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t *out_config) freq_mhz = source_freq_mhz / div; break; } - case SOC_CPU_CLK_SRC_PLL_F160: { + case SOC_CPU_CLK_SRC_PLL_F160M: { div = clk_ll_cpu_get_divider(); source_freq_mhz = CLK_LL_PLL_160M_FREQ_MHZ; freq_mhz = source_freq_mhz / div; break; } - case SOC_CPU_CLK_SRC_PLL_F240: { + case SOC_CPU_CLK_SRC_PLL_F240M: { div = clk_ll_cpu_get_divider(); source_freq_mhz = CLK_LL_PLL_240M_FREQ_MHZ; freq_mhz = source_freq_mhz / div; @@ -338,7 +356,7 @@ void rtc_clk_cpu_freq_set_config_fast(const rtc_cpu_freq_config_t *config) { if (config->source == SOC_CPU_CLK_SRC_XTAL) { rtc_clk_cpu_freq_to_xtal(config->freq_mhz, config->div); - } else if (((config->source == SOC_CPU_CLK_SRC_PLL_F160) || (config->source == SOC_CPU_CLK_SRC_PLL_F240)) && + } else if (((config->source == SOC_CPU_CLK_SRC_PLL_F160M) || (config->source == SOC_CPU_CLK_SRC_PLL_F240M)) && s_cur_pll_freq == config->source_freq_mhz) { rtc_clk_cpu_freq_to_pll_mhz(config->freq_mhz); } else if (config->source == SOC_CPU_CLK_SRC_RC_FAST) { @@ -391,11 +409,11 @@ static uint32_t rtc_clk_ahb_freq_get(void) soc_root_freq_mhz = rtc_clk_xtal_freq_get(); divider = clk_ll_ahb_get_divider(); break; - case SOC_CPU_CLK_SRC_PLL_F160: + case SOC_CPU_CLK_SRC_PLL_F160M: soc_root_freq_mhz = CLK_LL_PLL_160M_FREQ_MHZ; divider = clk_ll_ahb_get_divider(); break; - case SOC_CPU_CLK_SRC_PLL_F240: + case SOC_CPU_CLK_SRC_PLL_F240M: soc_root_freq_mhz = CLK_LL_PLL_240M_FREQ_MHZ; divider = clk_ll_ahb_get_divider(); break; diff --git a/components/esp_hw_support/port/esp32c5/rtc_clk_init.c b/components/esp_hw_support/port/esp32c5/rtc_clk_init.c index 9a0efba6cb..b65f8e250e 100644 --- a/components/esp_hw_support/port/esp32c5/rtc_clk_init.c +++ b/components/esp_hw_support/port/esp32c5/rtc_clk_init.c @@ -78,7 +78,7 @@ void rtc_clk_init(rtc_clk_config_t cfg) REG_SET_FIELD(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_HP_ACTIVE_HP_REGULATOR_DBIAS, HP_CALI_DBIAS); REG_SET_FIELD(PMU_HP_SLEEP_LP_REGULATOR0_REG, PMU_HP_SLEEP_LP_REGULATOR_DBIAS, LP_CALI_DBIAS); - clk_ll_rc_fast_tick_conf(); + clk_ll_rc_fast_tick_conf(); // TODO: IDF-8642 Unnecessary or not? soc_xtal_freq_t xtal_freq = cfg.xtal_freq; esp_rom_output_tx_wait_idle(0); diff --git a/components/esp_hw_support/port/esp32c5/rtc_time.c b/components/esp_hw_support/port/esp32c5/rtc_time.c index 31c0d4df07..0306546152 100644 --- a/components/esp_hw_support/port/esp32c5/rtc_time.c +++ b/components/esp_hw_support/port/esp32c5/rtc_time.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -69,13 +69,13 @@ static uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cyc if (cal_clk == RTC_CAL_RTC_MUX) { cal_clk = (rtc_cal_sel_t)slow_clk_src; } - if (cal_clk == RTC_CAL_RC_FAST) { - cali_clk_sel = TIMG_RTC_CALI_CLK_SEL_RC_FAST; -#if !CONFIG_IDF_TARGET_ESP32C5 // TODO: [ESP32C5] IDF-8642 Seems RC_SLOW can't be calibrated - } else if (cal_clk == RTC_CAL_RC_SLOW) { - cali_clk_sel = TIMG_RTC_CALI_CLK_SEL_RC_SLOW; -#endif // !CONFIG_IDF_TARGET_ESP32C5 - } else { + // TODO: [ESP32C5] IDF-8642 Seems RC_SLOW, RC_FAST can't be calibrated on beta3 + // if (cal_clk == RTC_CAL_RC_FAST) { + // cali_clk_sel = TIMG_RTC_CALI_CLK_SEL_RC_FAST; + // } else if (cal_clk == RTC_CAL_RC_SLOW) { + // cali_clk_sel = TIMG_RTC_CALI_CLK_SEL_RC_SLOW; + // } else + { cali_clk_sel = TIMG_RTC_CALI_CLK_SEL_32K; clk_ll_32k_calibration_set_target((soc_rtc_slow_clk_src_t)cal_clk); } @@ -90,16 +90,16 @@ static uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cyc clk_ll_xtal32k_digi_enable(); } - bool rc_fast_enabled = clk_ll_rc_fast_is_enabled(); - bool dig_rc_fast_enabled = clk_ll_rc_fast_digi_is_enabled(); - if (cal_clk == RTC_CAL_RC_FAST) { - if (!rc_fast_enabled) { - rtc_clk_8m_enable(true); - } - if (!dig_rc_fast_enabled) { - rtc_dig_clk8m_enable(); - } - } + // bool rc_fast_enabled = clk_ll_rc_fast_is_enabled(); + // bool dig_rc_fast_enabled = clk_ll_rc_fast_digi_is_enabled(); + // if (cal_clk == RTC_CAL_RC_FAST) { + // if (!rc_fast_enabled) { + // rtc_clk_8m_enable(true); + // } + // if (!dig_rc_fast_enabled) { + // rtc_dig_clk8m_enable(); + // } + // } bool rc32k_enabled = clk_ll_rc32k_is_enabled(); bool dig_rc32k_enabled = clk_ll_rc32k_digi_is_enabled(); @@ -155,14 +155,12 @@ static uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cyc if (GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_RDY)) { cal_val = REG_GET_FIELD(TIMG_RTCCALICFG1_REG(0), TIMG_RTC_CALI_VALUE); - /*The Fosc CLK of calibration circuit is divided by 32 for ECO1. - So we need to multiply the frequency of the Fosc for ECO1 and above chips by 32 times. - And ensure that this modification will not affect ECO0.*/ - if (ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 1)) { - if (cal_clk == RTC_CAL_RC_FAST) { - cal_val = cal_val >> 5; - } - } + // TODO: IDF-8642 Check whether this workaround still need for C5 + // /*The Fosc CLK of calibration circuit is divided by 32. + // So we need to multiply the frequency of the FOSC by 32 times.*/ + // if (cal_clk == RTC_CAL_RC_FAST) { + // cal_val = cal_val >> 5; + // } break; } if (GET_PERI_REG_MASK(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT)) { @@ -177,14 +175,14 @@ static uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cyc clk_ll_xtal32k_digi_disable(); } - if (cal_clk == RTC_CAL_RC_FAST) { - if (!dig_rc_fast_enabled) { - rtc_dig_clk8m_disable(); - } - if (!rc_fast_enabled) { - rtc_clk_8m_enable(false); - } - } + // if (cal_clk == RTC_CAL_RC_FAST) { + // if (!dig_rc_fast_enabled) { + // rtc_dig_clk8m_disable(); + // } + // if (!rc_fast_enabled) { + // rtc_clk_8m_enable(false); + // } + // } if (cal_clk == RTC_CAL_RC32K) { if (!dig_rc32k_enabled) { @@ -214,14 +212,13 @@ uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles) { soc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get(); - /*The Fosc CLK of calibration circuit is divided by 32 for ECO1. - So we need to divide the calibrate cycles of the FOSC for ECO1 and above chips by 32 to - avoid excessive calibration time.*/ - if (ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 1)) { - if (cal_clk == RTC_CAL_RC_FAST) { - slowclk_cycles = slowclk_cycles >> 5; - } - } + // TODO: IDF-8642 Check whether this workaround still need for C5 + // /*The Fosc CLK of calibration circuit is divided by 32. + // So we need to divide the calibrate cycles of the FOSC by 32 to + // avoid excessive calibration time.*/ + // if (cal_clk == RTC_CAL_RC_FAST) { + // slowclk_cycles = slowclk_cycles >> 5; + // } uint64_t xtal_cycles = rtc_clk_cal_internal(cal_clk, slowclk_cycles); diff --git a/components/esp_pm/pm_impl.c b/components/esp_pm/pm_impl.c index b09da860e2..6a3e4ca47f 100644 --- a/components/esp_pm/pm_impl.c +++ b/components/esp_pm/pm_impl.c @@ -645,17 +645,17 @@ static void IRAM_ATTR do_switch(pm_mode_t new_mode) if (switch_down) { on_freq_update(old_ticks_per_us, new_ticks_per_us); } - if (new_config.source == SOC_CPU_CLK_SRC_PLL) { - rtc_clk_cpu_freq_set_config_fast(&new_config); #if SOC_SPI_MEM_SUPPORT_TIMING_TUNING - mspi_timing_change_speed_mode_cache_safe(false); + if (new_config.source == SOC_CPU_CLK_SRC_PLL) { + rtc_clk_cpu_freq_set_config_fast(&new_config); + mspi_timing_change_speed_mode_cache_safe(false); + } else { + mspi_timing_change_speed_mode_cache_safe(true); + rtc_clk_cpu_freq_set_config_fast(&new_config); + } +#else + rtc_clk_cpu_freq_set_config_fast(&new_config); #endif - } else { -#if SOC_SPI_MEM_SUPPORT_TIMING_TUNING - mspi_timing_change_speed_mode_cache_safe(true); -#endif - rtc_clk_cpu_freq_set_config_fast(&new_config); - } if (!switch_down) { on_freq_update(old_ticks_per_us, new_ticks_per_us); } diff --git a/components/esp_rom/patches/esp_rom_hp_regi2c_esp32c5.c b/components/esp_rom/patches/esp_rom_hp_regi2c_esp32c5.c index c9695022ec..46e0b989e5 100644 --- a/components/esp_rom/patches/esp_rom_hp_regi2c_esp32c5.c +++ b/components/esp_rom/patches/esp_rom_hp_regi2c_esp32c5.c @@ -1,13 +1,13 @@ /* - * SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ #include "esp_rom_sys.h" #include "esp_attr.h" // TODO: [ESP32C5] IDF-8824 (inherit from C6) -// #include "soc/i2c_ana_mst_reg.h" -// #include "modem/modem_lpcon_reg.h" +#include "soc/i2c_ana_mst_reg.h" +#include "modem/modem_lpcon_reg.h" /** * BB - 0x67 - BIT0 * TXRF - 0x6B - BIT1 @@ -87,111 +87,108 @@ __attribute__((unused)) static IRAM_ATTR uint8_t regi2c_enable_block(uint8_t block) { // TODO: [ESP32C5] IDF-8824 (inherit from C6) - // uint32_t i2c_sel = 0; + uint32_t i2c_sel = 0; - // REG_SET_BIT(MODEM_LPCON_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_EN); - // REG_SET_BIT(MODEM_LPCON_I2C_MST_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_SEL_160M); + REG_SET_BIT(MODEM_LPCON_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_EN); + REG_SET_BIT(MODEM_LPCON_I2C_MST_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_SEL_160M); - // /* Before config I2C register, enable corresponding slave. */ - // switch (block) { - // case REGI2C_BBPLL : - // i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_BBPLL_MST_SEL); - // REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, REGI2C_BBPLL_RD_MASK); - // break; - // case REGI2C_BIAS : - // i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_BIAS_MST_SEL); - // REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, REGI2C_BIAS_RD_MASK); - // break; - // case REGI2C_DIG_REG: - // i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_DIG_REG_MST_SEL); - // REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, REGI2C_DIG_REG_RD_MASK); - // break; - // case REGI2C_ULP_CAL: - // i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_ULP_CAL_MST_SEL); - // REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, REGI2C_ULP_CAL_RD_MASK); - // break; - // case REGI2C_SAR_I2C: - // i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_SAR_I2C_MST_SEL); - // REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, REGI2C_SAR_I2C_RD_MASK); - // break; - // } + /* Before config I2C register, enable corresponding slave. */ + switch (block) { + case REGI2C_BBPLL : + i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_BBPLL_MST_SEL); + REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, REGI2C_BBPLL_RD_MASK); + break; + case REGI2C_BIAS : + i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_BIAS_MST_SEL); + REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, REGI2C_BIAS_RD_MASK); + break; + case REGI2C_DIG_REG: + i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_DIG_REG_MST_SEL); + REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, REGI2C_DIG_REG_RD_MASK); + break; + case REGI2C_ULP_CAL: + i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_ULP_CAL_MST_SEL); + REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, REGI2C_ULP_CAL_RD_MASK); + break; + case REGI2C_SAR_I2C: + i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_SAR_I2C_MST_SEL); + REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, REGI2C_SAR_I2C_RD_MASK); + break; + } - // return (uint8_t)(i2c_sel ? 0: 1); - return (uint8_t)0; + return (uint8_t)(i2c_sel ? 0: 1); } uint8_t IRAM_ATTR regi2c_read_impl(uint8_t block, uint8_t host_id, uint8_t reg_add) { // TODO: [ESP32C5] IDF-8824 (inherit from C6) - // (void)host_id; - // uint8_t i2c_sel = regi2c_enable_block(block); + (void)host_id; + uint8_t i2c_sel = regi2c_enable_block(block); - // while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); // wait i2c idle - // uint32_t temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S) - // | (reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S; - // REG_WRITE(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), temp); - // while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); - // uint8_t ret = REG_GET_FIELD(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_DATA); + while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); // wait i2c idle + uint32_t temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S) + | (reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S; + REG_WRITE(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), temp); + while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); + uint8_t ret = REG_GET_FIELD(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_DATA); - // return ret; - return (uint8_t)0; + return ret; } uint8_t IRAM_ATTR regi2c_read_mask_impl(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb) { // TODO: [ESP32C5] IDF-8824 (inherit from C6) - // assert(msb - lsb < 8); - // uint8_t i2c_sel = regi2c_enable_block(block); + assert(msb - lsb < 8); + uint8_t i2c_sel = regi2c_enable_block(block); - // (void)host_id; - // while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); // wait i2c idle - // uint32_t temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S) - // | (reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S; - // REG_WRITE(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), temp); - // while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); - // uint32_t data = REG_GET_FIELD(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_DATA); - // uint8_t ret = (uint8_t)((data >> lsb) & (~(0xFFFFFFFF << (msb - lsb + 1)))); + (void)host_id; + while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); // wait i2c idle + uint32_t temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S) + | (reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S; + REG_WRITE(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), temp); + while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); + uint32_t data = REG_GET_FIELD(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_DATA); + uint8_t ret = (uint8_t)((data >> lsb) & (~(0xFFFFFFFF << (msb - lsb + 1)))); - // return ret; - return (uint8_t)0; + return ret; } void IRAM_ATTR regi2c_write_impl(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data) { // TODO: [ESP32C5] IDF-8824 (inherit from C6) - // (void)host_id; - // uint8_t i2c_sel = regi2c_enable_block(block); + (void)host_id; + uint8_t i2c_sel = regi2c_enable_block(block); - // while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); // wait i2c idle - // uint32_t temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S) - // | ((reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S) - // | ((0x1 & REGI2C_RTC_WR_CNTL_V) << REGI2C_RTC_WR_CNTL_S) // 0: READ I2C register; 1: Write I2C register; - // | (((uint32_t)data & REGI2C_RTC_DATA_V) << REGI2C_RTC_DATA_S); - // REG_WRITE(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), temp); - // while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); + while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); // wait i2c idle + uint32_t temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S) + | ((reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S) + | ((0x1 & REGI2C_RTC_WR_CNTL_V) << REGI2C_RTC_WR_CNTL_S) // 0: READ I2C register; 1: Write I2C register; + | (((uint32_t)data & REGI2C_RTC_DATA_V) << REGI2C_RTC_DATA_S); + REG_WRITE(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), temp); + while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); } void IRAM_ATTR regi2c_write_mask_impl(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data) { // TODO: [ESP32C5] IDF-8824 (inherit from C6) - // (void)host_id; - // assert(msb - lsb < 8); - // uint8_t i2c_sel = regi2c_enable_block(block); + (void)host_id; + assert(msb - lsb < 8); + uint8_t i2c_sel = regi2c_enable_block(block); - // while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); - // /*Read the i2c bus register*/ - // uint32_t temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S) - // | (reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S; - // REG_WRITE(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), temp); - // while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); - // temp = REG_GET_FIELD(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_DATA); - // /*Write the i2c bus register*/ - // temp &= ((~(0xFFFFFFFF << lsb)) | (0xFFFFFFFF << (msb + 1))); - // temp = (((uint32_t)data & (~(0xFFFFFFFF << (msb - lsb + 1)))) << lsb) | temp; - // temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S) - // | ((reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S) - // | ((0x1 & REGI2C_RTC_WR_CNTL_V) << REGI2C_RTC_WR_CNTL_S) - // | ((temp & REGI2C_RTC_DATA_V) << REGI2C_RTC_DATA_S); - // REG_WRITE(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), temp); - // while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); + while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); + /*Read the i2c bus register*/ + uint32_t temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S) + | (reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S; + REG_WRITE(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), temp); + while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); + temp = REG_GET_FIELD(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_DATA); + /*Write the i2c bus register*/ + temp &= ((~(0xFFFFFFFF << lsb)) | (0xFFFFFFFF << (msb + 1))); + temp = (((uint32_t)data & (~(0xFFFFFFFF << (msb - lsb + 1)))) << lsb) | temp; + temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S) + | ((reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S) + | ((0x1 & REGI2C_RTC_WR_CNTL_V) << REGI2C_RTC_WR_CNTL_S) + | ((temp & REGI2C_RTC_DATA_V) << REGI2C_RTC_DATA_S); + REG_WRITE(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), temp); + while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); } diff --git a/components/esp_system/port/soc/esp32c5/Kconfig.cpu b/components/esp_system/port/soc/esp32c5/Kconfig.cpu index bd6b177c23..0ce4f03b2b 100644 --- a/components/esp_system/port/soc/esp32c5/Kconfig.cpu +++ b/components/esp_system/port/soc/esp32c5/Kconfig.cpu @@ -10,8 +10,6 @@ choice ESP_DEFAULT_CPU_FREQ_MHZ depends on IDF_ENV_FPGA config ESP_DEFAULT_CPU_FREQ_MHZ_80 bool "80 MHz" - config ESP_DEFAULT_CPU_FREQ_MHZ_120 - bool "120 MHz" config ESP_DEFAULT_CPU_FREQ_MHZ_160 bool "160 MHz" config ESP_DEFAULT_CPU_FREQ_MHZ_240 @@ -21,8 +19,6 @@ endchoice config ESP_DEFAULT_CPU_FREQ_MHZ int default 40 if ESP_DEFAULT_CPU_FREQ_MHZ_40 - default 60 if ESP_DEFAULT_CPU_FREQ_MHZ_60 default 80 if ESP_DEFAULT_CPU_FREQ_MHZ_80 - default 120 if ESP_DEFAULT_CPU_FREQ_MHZ_120 default 160 if ESP_DEFAULT_CPU_FREQ_MHZ_160 default 240 if ESP_DEFAULT_CPU_FREQ_MHZ_240 diff --git a/components/esp_system/port/soc/esp32c5/system_internal.c b/components/esp_system/port/soc/esp32c5/system_internal.c index 892a70dfbc..a2d8056081 100644 --- a/components/esp_system/port/soc/esp32c5/system_internal.c +++ b/components/esp_system/port/soc/esp32c5/system_internal.c @@ -39,7 +39,7 @@ void IRAM_ATTR esp_system_reset_modules_on_exit(void) modem_lpcon_ll_reset_all(&MODEM_LPCON); // Set SPI Flash Freq to 40M - clk_ll_mspi_fast_sel_clk(MSPI_CLK_SRC_XTAL); + clk_ll_mspi_fast_set_src(MSPI_CLK_SRC_XTAL); clk_ll_mspi_fast_set_divider(1); // Set Peripheral clk rst diff --git a/components/hal/esp32c5/clk_tree_hal.c b/components/hal/esp32c5/clk_tree_hal.c index 057ffc8d17..04ed3ad680 100644 --- a/components/hal/esp32c5/clk_tree_hal.c +++ b/components/hal/esp32c5/clk_tree_hal.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -16,9 +16,9 @@ uint32_t clk_hal_soc_root_get_freq_mhz(soc_cpu_clk_src_t cpu_clk_src) switch (cpu_clk_src) { case SOC_CPU_CLK_SRC_XTAL: return clk_hal_xtal_get_freq_mhz(); - case SOC_CPU_CLK_SRC_PLL_F160: + case SOC_CPU_CLK_SRC_PLL_F160M: return CLK_LL_PLL_160M_FREQ_MHZ; - case SOC_CPU_CLK_SRC_PLL_F240: + case SOC_CPU_CLK_SRC_PLL_F240M: return CLK_LL_PLL_240M_FREQ_MHZ; case SOC_CPU_CLK_SRC_RC_FAST: return SOC_CLK_RC_FAST_FREQ_APPROX / MHZ; diff --git a/components/hal/esp32c5/include/hal/clk_tree_ll.h b/components/hal/esp32c5/include/hal/clk_tree_ll.h index 5f1e637653..d575f21532 100644 --- a/components/hal/esp32c5/include/hal/clk_tree_ll.h +++ b/components/hal/esp32c5/include/hal/clk_tree_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -42,10 +42,10 @@ extern "C" { /* Set the frequency division factor of ref_tick -The FOSC of rtc calibration uses the 32 frequency division clock for ECO1, +The FOSC of rtc calibration uses the 32 frequency division clock, So the frequency division factor of ref_tick must be greater than or equal to 32 */ -#define REG_FOSC_TICK_NUM 255 +#define REG_FOSC_TICK_NUM 255 // TODO: IDF-8642 No need? Can calibrate on RC_FAST directly? /** * @brief XTAL32K_CLK enable modes @@ -344,6 +344,15 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_set_config(uint32 REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_VCO_DBIAS, dbias); } +/** + * @brief To enable the change of soc_clk_sel, cpu_div_num, and ahb_div_num + */ +static inline __attribute__((always_inline)) void clk_ll_bus_update(void) +{ + PCR.bus_clk_update.bus_clock_update = 1; + while (PCR.bus_clk_update.bus_clock_update); +} + /** * @brief Select the clock source for CPU_CLK (SOC Clock Root) * @@ -358,17 +367,16 @@ static inline __attribute__((always_inline)) void clk_ll_cpu_set_src(soc_cpu_clk case SOC_CPU_CLK_SRC_RC_FAST: PCR.sysclk_conf.soc_clk_sel = 1; break; - case SOC_CPU_CLK_SRC_PLL_F160: + case SOC_CPU_CLK_SRC_PLL_F160M: PCR.sysclk_conf.soc_clk_sel = 2; break; - case SOC_CPU_CLK_SRC_PLL_F240: + case SOC_CPU_CLK_SRC_PLL_F240M: PCR.sysclk_conf.soc_clk_sel = 3; break; default: // Unsupported SOC_CLK mux input sel abort(); } - HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.bus_clk_update, bus_clock_update, 1); } /** @@ -385,27 +393,15 @@ static inline __attribute__((always_inline)) soc_cpu_clk_src_t clk_ll_cpu_get_sr case 1: return SOC_CPU_CLK_SRC_RC_FAST; case 2: - return SOC_CPU_CLK_SRC_PLL_F160; + return SOC_CPU_CLK_SRC_PLL_F160M; case 3: - return SOC_CPU_CLK_SRC_PLL_F240; + return SOC_CPU_CLK_SRC_PLL_F240M; default: // Invalid SOC_CLK_SEL value return SOC_CPU_CLK_SRC_INVALID; } } -/** - * @brief Get AHB_CLK's low-speed divider - * - * @return Divider. Divider = (PCR_LS_DIV_NUM + 1) * (PCR_AHB_LS_DIV_NUM + 1). - */ -static inline __attribute__((always_inline)) uint32_t clk_ll_ahb_get_divider(void) -{ - uint32_t ahb_div = HAL_FORCE_READ_U32_REG_FIELD(PCR.ahb_freq_conf, ahb_div_num); - uint32_t hp_root_ls_div = HAL_FORCE_READ_U32_REG_FIELD(PCR.sysclk_conf, ls_div_num); - return (hp_root_ls_div + 1) * (ahb_div + 1); -} - /** * @brief Set CPU_CLK's divider * @@ -418,19 +414,6 @@ static inline __attribute__((always_inline)) void clk_ll_cpu_set_divider(uint32_ // divider option: 1, 2, 4 (PCR_CPU_HS_DIV_NUM=0, 1, 3) HAL_ASSERT(divider == 1 || divider == 2 || divider == 3 || divider == 4 || divider == 6); HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.cpu_freq_conf, cpu_div_num, (divider) - 1); - HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.bus_clk_update, bus_clock_update, 1); -} - -/** - * @brief Set AHB_CLK's low-speed divider (valid when SOC_ROOT clock source is XTAL/RC_FAST) - * - * @param divider Divider. (PCR_LS_DIV_NUM + 1) * (PCR_AHB_LS_DIV_NUM + 1) = divider. - */ -static inline __attribute__((always_inline)) void clk_ll_ahb_set_divider(uint32_t divider) -{ - // SOC_ROOT_CLK ---(1)---> HP_ROOT_CLK ---(2)---> AHB_CLK - HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.ahb_freq_conf, ahb_div_num, divider - 1); - HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.bus_clk_update, bus_clock_update, 1); } /** @@ -444,6 +427,29 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_cpu_get_divider(voi return (cpu_div + 1); } +/** + * @brief Set AHB_CLK's low-speed divider (valid when SOC_ROOT clock source is XTAL/RC_FAST) + * + * @param divider Divider. (PCR_LS_DIV_NUM + 1) * (PCR_AHB_LS_DIV_NUM + 1) = divider. + */ +static inline __attribute__((always_inline)) void clk_ll_ahb_set_divider(uint32_t divider) +{ + // SOC_ROOT_CLK ---(1)---> HP_ROOT_CLK ---(2)---> AHB_CLK + HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.ahb_freq_conf, ahb_div_num, divider - 1); +} + +/** + * @brief Get AHB_CLK's low-speed divider + * + * @return Divider. Divider = (PCR_LS_DIV_NUM + 1) * (PCR_AHB_LS_DIV_NUM + 1). + */ +static inline __attribute__((always_inline)) uint32_t clk_ll_ahb_get_divider(void) +{ + uint32_t ahb_div = HAL_FORCE_READ_U32_REG_FIELD(PCR.ahb_freq_conf, ahb_div_num); + uint32_t hp_root_ls_div = HAL_FORCE_READ_U32_REG_FIELD(PCR.sysclk_conf, ls_div_num); + return (hp_root_ls_div + 1) * (ahb_div + 1); +} + /** * @brief Set APB_CLK divider. freq of APB_CLK = freq of AHB_CLK / divider * @@ -467,25 +473,31 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_apb_get_divider(voi return HAL_FORCE_READ_U32_REG_FIELD(PCR.apb_freq_conf, apb_div_num) + 1; } -static inline __attribute__((always_inline)) void clk_ll_mspi_fast_sel_clk(soc_periph_mspi_clk_src_t mspi_clk_src) +/** + * @brief Select the clock source for MSPI_FAST_CLK + * + * @param in_sel One of the clock sources in soc_periph_mspi_clk_src_t + */ +static inline __attribute__((always_inline)) void clk_ll_mspi_fast_set_src(soc_periph_mspi_clk_src_t in_sel) { - switch (mspi_clk_src) { - case MSPI_CLK_SRC_XTAL: - PCR.mspi_clk_conf.mspi_func_clk_sel = 0; - break; - case MSPI_CLK_SRC_RC_FAST: - PCR.mspi_clk_conf.mspi_func_clk_sel = 1; - break; - case SOC_MOD_CLK_PLL_F480M: - PCR.mspi_clk_conf.mspi_func_clk_sel = 2; - break; - default: - abort(); + switch (in_sel) { + case MSPI_CLK_SRC_XTAL: + PCR.mspi_clk_conf.mspi_func_clk_sel = 0; + break; + case MSPI_CLK_SRC_RC_FAST: + PCR.mspi_clk_conf.mspi_func_clk_sel = 1; + break; + case MSPI_CLK_SRC_SPLL: + PCR.mspi_clk_conf.mspi_func_clk_sel = 2; + break; + default: + // Unsupported MSPI_FAST_CLK mux input sel + abort(); } } /** - * @brief Set MSPI_FAST_CLK's low-speed divider (valid when SOC_ROOT clock source is XTAL/RC_FAST) + * @brief Set MSPI_FAST_CLK's divider * * @param divider Divider. */ @@ -515,7 +527,6 @@ static inline __attribute__((always_inline)) void clk_ll_32k_calibration_set_tar // Unsupported 32K_SEL mux input abort(); } - HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.bus_clk_update, bus_clock_update, 1); } /** @@ -600,7 +611,7 @@ static inline __attribute__((always_inline)) void clk_ll_rtc_fast_set_src(soc_rt case SOC_RTC_FAST_CLK_SRC_XTAL_D2: LP_CLKRST.lp_clk_conf.fast_clk_sel = 1; break; - case SOC_RTC_FAST_CLK_SRC_XTAL_D1: + case SOC_RTC_FAST_CLK_SRC_XTAL: LP_CLKRST.lp_clk_conf.fast_clk_sel = 2; break; default: @@ -622,8 +633,10 @@ static inline __attribute__((always_inline)) soc_rtc_fast_clk_src_t clk_ll_rtc_f return SOC_RTC_FAST_CLK_SRC_RC_FAST; case 1: return SOC_RTC_FAST_CLK_SRC_XTAL_D2; + case 2: + return SOC_RTC_FAST_CLK_SRC_XTAL; default: - return SOC_RTC_FAST_CLK_SRC_XTAL_D1; + return SOC_RTC_FAST_CLK_SRC_INVALID; } } diff --git a/components/soc/esp32c5/include/soc/clk_tree_defs.h b/components/soc/esp32c5/include/soc/clk_tree_defs.h index c55583494b..acda20271a 100644 --- a/components/soc/esp32c5/include/soc/clk_tree_defs.h +++ b/components/soc/esp32c5/include/soc/clk_tree_defs.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -17,7 +17,7 @@ extern "C" { * * The exact frequency of RC_FAST_CLK can be computed in runtime through calibration. * - * 2) External 40MHz Crystal Clock: XTAL + * 2) External 40/48MHz Crystal Clock: XTAL * * 3) Internal 136kHz RC Oscillator: RC_SLOW (may also referrred as SOSC in TRM or reg. description) * @@ -74,9 +74,8 @@ typedef enum { // TODO: [ESP32C5] IDF-8642 (inherit from C6) typedef enum { // TODO: [ESP32C5] IDF-8642 (inherit from C6) SOC_CPU_CLK_SRC_XTAL = 0, /*!< Select XTAL_CLK as CPU_CLK source */ SOC_CPU_CLK_SRC_RC_FAST = 1, /*!< Select RC_FAST_CLK as CPU_CLK source */ - SOC_CPU_CLK_SRC_PLL_F160 = 2, /*!< Select PLL_CLK as CPU_CLK source (PLL_CLK is the output of 40MHz crystal oscillator frequency multiplier, 480MHz) */ - SOC_CPU_CLK_SRC_PLL = SOC_CPU_CLK_SRC_PLL_F160, /*!< Select PLL_CLK as CPU_CLK source (PLL_CLK is the output of 40MHz crystal oscillator frequency multiplier, 480MHz) */ - SOC_CPU_CLK_SRC_PLL_F240 = 3, /*!< Select PLL_CLK as CPU_CLK source (PLL_CLK is the output of 40MHz crystal oscillator frequency multiplier, 480MHz) */ + SOC_CPU_CLK_SRC_PLL_F160M = 2, /*!< Select PLL_F160M_CLK as CPU_CLK source (PLL_F160M_CLK is derived from SPLL (480MHz), which is the output of the main crystal oscillator frequency multiplier) */ + SOC_CPU_CLK_SRC_PLL_F240M = 3, /*!< Select PLL_F240M_CLK as CPU_CLK source (PLL_F240M_CLK is derived from SPLL (480MHz), which is the output of the main crystal oscillator frequency multiplier) */ SOC_CPU_CLK_SRC_INVALID, /*!< Invalid CPU_CLK source */ } soc_cpu_clk_src_t; @@ -99,8 +98,8 @@ typedef enum { // TODO: [ESP32C5] IDF-8642 (inherit from C6) typedef enum { // TODO: [ESP32C5] IDF-8642 (inherit from C6) SOC_RTC_FAST_CLK_SRC_RC_FAST = 0, /*!< Select RC_FAST_CLK as RTC_FAST_CLK source */ SOC_RTC_FAST_CLK_SRC_XTAL_D2 = 1, /*!< Select XTAL_D2_CLK as RTC_FAST_CLK source */ - SOC_RTC_FAST_CLK_SRC_XTAL_D1 = 2, /*!< Select XTAL_D1_CLK as RTC_FAST_CLK source */ SOC_RTC_FAST_CLK_SRC_XTAL_DIV = SOC_RTC_FAST_CLK_SRC_XTAL_D2, /*!< Alias name for `SOC_RTC_FAST_CLK_SRC_XTAL_D2` */ + SOC_RTC_FAST_CLK_SRC_XTAL = 2, /*!< Select XTAL_CLK as RTC_FAST_CLK source */ SOC_RTC_FAST_CLK_SRC_INVALID, /*!< Invalid RTC_FAST_CLK source */ } soc_rtc_fast_clk_src_t; @@ -133,7 +132,7 @@ typedef enum { // TODO: [ESP32C5] IDF-8642 (inherit from C6) SOC_MOD_CLK_PLL_F80M, /*!< PLL_F80M_CLK is derived from PLL (clock gating + fixed divider of 6), it has a fixed frequency of 80MHz */ SOC_MOD_CLK_PLL_F160M, /*!< PLL_F160M_CLK is derived from PLL (clock gating + fixed divider of 3), it has a fixed frequency of 160MHz */ SOC_MOD_CLK_PLL_F240M, /*!< PLL_F240M_CLK is derived from PLL (clock gating + fixed divider of 2), it has a fixed frequency of 240MHz */ - SOC_MOD_CLK_PLL_F480M, + SOC_MOD_CLK_SPLL, /*!< SPLL is from the main XTAL oscillator frequency multipliers, it has a "fixed" frequency of 480MHz */ SOC_MOD_CLK_XTAL32K, /*!< XTAL32K_CLK comes from the external 32kHz crystal, passing a clock gating to the peripherals */ SOC_MOD_CLK_RC_FAST, /*!< RC_FAST_CLK comes from the internal 20MHz rc oscillator, passing a clock gating to the peripherals */ SOC_MOD_CLK_XTAL, /*!< XTAL_CLK comes from the external 40MHz crystal */ @@ -483,14 +482,14 @@ typedef enum { // TODO: [ESP32C5] IDF-8685, IDF-8686 (inherit from C6) /** * @brief Array initializer for all supported clock sources of MSPI digital controller */ -#define SOC_MSPI_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_PLL_F480M} +#define SOC_MSPI_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_SPLL} /** * @brief MSPI digital controller clock source */ typedef enum { // TODO: [ESP32C5] IDF-8649 MSPI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ MSPI_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */ - MSPI_CLK_SRC_SPLL = SOC_MOD_CLK_PLL_F480M, /*!< Select PLL_F64M as the source clock */ + MSPI_CLK_SRC_SPLL = SOC_MOD_CLK_SPLL, /*!< Select SPLL as the source clock */ MSPI_CLK_SRC_ROM_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as ROM default clock source */ } soc_periph_mspi_clk_src_t; diff --git a/components/soc/esp32c5/include/soc/i2c_ana_mst_reg.h b/components/soc/esp32c5/include/soc/i2c_ana_mst_reg.h new file mode 100644 index 0000000000..4089e68b3e --- /dev/null +++ b/components/soc/esp32c5/include/soc/i2c_ana_mst_reg.h @@ -0,0 +1,220 @@ +/** + * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include "soc/soc.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define I2C_ANA_MST_I2C0_CTRL_REG (DR_REG_I2C_ANA_MST_BASE + 0x0) +/* I2C_MST_I2C0_BUSY : RO ;bitpos:[25] ;default: 1'h0 ; */ +/*description: .*/ +#define I2C_ANA_MST_I2C0_BUSY (BIT(25)) +#define I2C_ANA_MST_I2C0_BUSY_M (BIT(25)) +#define I2C_ANA_MST_I2C0_BUSY_V 0x1 +#define I2C_ANA_MST_I2C0_BUSY_S 25 +/* I2C_MST_I2C0_CTRL : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: .*/ +#define I2C_ANA_MST_I2C0_CTRL 0x01FFFFFF +#define I2C_ANA_MST_I2C0_CTRL_M ((I2C_MST_I2C0_CTRL_V)<<(I2C_MST_I2C0_CTRL_S)) +#define I2C_ANA_MST_I2C0_CTRL_V 0x1FFFFFF +#define I2C_ANA_MST_I2C0_CTRL_S 0 + +#define I2C_ANA_MST_I2C1_CTRL_REG (DR_REG_I2C_ANA_MST_BASE + 0x4) +/* I2C_MST_I2C1_BUSY : RO ;bitpos:[25] ;default: 1'h0 ; */ +/*description: .*/ +#define I2C_ANA_MST_I2C1_BUSY (BIT(25)) +#define I2C_ANA_MST_I2C1_BUSY_M (BIT(25)) +#define I2C_ANA_MST_I2C1_BUSY_V 0x1 +#define I2C_ANA_MST_I2C1_BUSY_S 25 +/* I2C_MST_I2C1_CTRL : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: .*/ +#define I2C_ANA_MST_I2C1_CTRL 0x01FFFFFF +#define I2C_ANA_MST_I2C1_CTRL_M ((I2C_MST_I2C1_CTRL_V)<<(I2C_MST_I2C1_CTRL_S)) +#define I2C_ANA_MST_I2C1_CTRL_V 0x1FFFFFF +#define I2C_ANA_MST_I2C1_CTRL_S 0 + +#define I2C_ANA_MST_I2C0_CONF_REG (DR_REG_I2C_ANA_MST_BASE + 0x8) +/* I2C_MST_I2C0_STATUS : RO ;bitpos:[31:24] ;default: 8'h0 ; */ +/*description: .*/ +#define I2C_ANA_MST_I2C0_STATUS 0x000000FF +#define I2C_ANA_MST_I2C0_STATUS_M ((I2C_MST_I2C0_STATUS_V)<<(I2C_MST_I2C0_STATUS_S)) +#define I2C_ANA_MST_I2C0_STATUS_V 0xFF +#define I2C_ANA_MST_I2C0_STATUS_S 24 +/* I2C_MST_I2C0_CONF : R/W ;bitpos:[23:0] ;default: 24'h0 ; */ +/*description: .*/ +#define I2C_ANA_MST_I2C0_CONF 0x00FFFFFF +#define I2C_ANA_MST_I2C0_CONF_M ((I2C_MST_I2C0_CONF_V)<<(I2C_MST_I2C0_CONF_S)) +#define I2C_ANA_MST_I2C0_CONF_V 0xFFFFFF +#define I2C_ANA_MST_I2C0_CONF_S 0 + +#define I2C_ANA_MST_I2C1_CONF_REG (DR_REG_I2C_ANA_MST_BASE + 0xC) +/* I2C_MST_I2C1_STATUS : RO ;bitpos:[31:24] ;default: 8'h0 ; */ +/*description: .*/ +#define I2C_ANA_MST_I2C1_STATUS 0x000000FF +#define I2C_ANA_MST_I2C1_STATUS_M ((I2C_MST_I2C1_STATUS_V)<<(I2C_MST_I2C1_STATUS_S)) +#define I2C_ANA_MST_I2C1_STATUS_V 0xFF +#define I2C_ANA_MST_I2C1_STATUS_S 24 +/* I2C_MST_I2C1_CONF : R/W ;bitpos:[23:0] ;default: 24'h0 ; */ +/*description: .*/ +#define I2C_ANA_MST_I2C1_CONF 0x00FFFFFF +#define I2C_ANA_MST_I2C1_CONF_M ((I2C_MST_I2C1_CONF_V)<<(I2C_MST_I2C1_CONF_S)) +#define I2C_ANA_MST_I2C1_CONF_V 0xFFFFFF +#define I2C_ANA_MST_I2C1_CONF_S 0 + +#define I2C_ANA_MST_I2C_BURST_CONF_REG (DR_REG_I2C_ANA_MST_BASE + 0x10) +/* I2C_MST_BURST_CTRL : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: .*/ +#define I2C_ANA_MST_BURST_CTRL 0xFFFFFFFF +#define I2C_ANA_MST_BURST_CTRL_M ((I2C_MST_BURST_CTRL_V)<<(I2C_MST_BURST_CTRL_S)) +#define I2C_ANA_MST_BURST_CTRL_V 0xFFFFFFFF +#define I2C_ANA_MST_BURST_CTRL_S 0 + +#define I2C_ANA_MST_I2C_BURST_STATUS_REG (DR_REG_I2C_ANA_MST_BASE + 0x14) +/* I2C_MST_BURST_TIMEOUT_CNT : R/W ;bitpos:[31:20] ;default: 12'h400 ; */ +/*description: .*/ +#define I2C_ANA_MST_BURST_TIMEOUT_CNT 0x00000FFF +#define I2C_ANA_MST_BURST_TIMEOUT_CNT_M ((I2C_MST_BURST_TIMEOUT_CNT_V)<<(I2C_MST_BURST_TIMEOUT_CNT_S)) +#define I2C_ANA_MST_BURST_TIMEOUT_CNT_V 0xFFF +#define I2C_ANA_MST_BURST_TIMEOUT_CNT_S 20 +/* I2C_MST1_BURST_ERR_FLAG : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_ANA_MST1_BURST_ERR_FLAG (BIT(2)) +#define I2C_ANA_MST1_BURST_ERR_FLAG_M (BIT(2)) +#define I2C_ANA_MST1_BURST_ERR_FLAG_V 0x1 +#define I2C_ANA_MST1_BURST_ERR_FLAG_S 2 +/* I2C_MST0_BURST_ERR_FLAG : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_ANA_MST0_BURST_ERR_FLAG (BIT(1)) +#define I2C_ANA_MST0_BURST_ERR_FLAG_M (BIT(1)) +#define I2C_ANA_MST0_BURST_ERR_FLAG_V 0x1 +#define I2C_ANA_MST0_BURST_ERR_FLAG_S 1 +/* I2C_MST_BURST_DONE : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: .*/ +#define I2C_ANA_MST_BURST_DONE (BIT(0)) +#define I2C_ANA_MST_BURST_DONE_M (BIT(0)) +#define I2C_ANA_MST_BURST_DONE_V 0x1 +#define I2C_ANA_MST_BURST_DONE_S 0 + +#define I2C_ANA_MST_ANA_CONF0_REG (DR_REG_I2C_ANA_MST_BASE + 0x18) +/* I2C_ANA_MST_STATUS0 : RO ;bitpos:[31:24] ;default: 8'h0 ; */ +/*description: .*/ +#define I2C_ANA_MST_ANA_STATUS0 0x000000FF +#define I2C_ANA_MST_ANA_STATUS0_M ((I2C_ANA_MST_STATUS0_V)<<(I2C_ANA_MST_STATUS0_S)) +#define I2C_ANA_MST_ANA_STATUS0_V 0xFF +#define I2C_ANA_MST_ANA_STATUS0_S 24 +/* I2C_ANA_MST_ANA_CONF0 : R/W ;bitpos:[23:0] ;default: 24'h00_e408 ; */ +/*description: .*/ +#define I2C_ANA_MST_ANA_CONF0 0x00FFFFFF +#define I2C_ANA_MST_ANA_CONF0_M ((I2C_ANA_MST_ANA_CONF0_V)<<(I2C_ANA_MST_ANA_CONF0_S)) +#define I2C_ANA_MST_ANA_CONF0_V 0xFFFFFF +#define I2C_ANA_MST_ANA_CONF0_S 0 + +#define I2C_ANA_MST_ANA_CONF1_REG (DR_REG_I2C_ANA_MST_BASE + 0x1C) +/* I2C_ANA_MST_STATUS1 : RO ;bitpos:[31:24] ;default: 8'h0 ; */ +/*description: .*/ +#define I2C_ANA_MST_ANA_STATUS1 0x000000FF +#define I2C_ANA_MST_ANA_STATUS1_M ((I2C_ANA_MST_STATUS1_V)<<(I2C_ANA_MST_STATUS1_S)) +#define I2C_ANA_MST_ANA_STATUS1_V 0xFF +#define I2C_ANA_MST_ANA_STATUS1_S 24 +/* I2C_MST_AANA_NA_CONF1 : R/W ;bitpos:[23:0] ;default: 24'h00_002d ; */ +/*description: .*/ +#define I2C_ANA_MST_ANA_CONF1 0x00FFFFFF +#define I2C_ANA_MST_ANA_CONF1_M ((I2C_ANA_MST_ANA_CONF1_V)<<(I2C_ANA_MST_ANA_CONF1_S)) +#define I2C_ANA_MST_ANA_CONF1_V 0xFFFFFF +#define I2C_ANA_MST_ANA_CONF1_S 0 + +#define I2C_ANA_MST_ANA_CONF2_REG (DR_REG_I2C_ANA_MST_BASE + 0x20) +/* I2C_ANA_MST_STATUS2 : RO ;bitpos:[31:24] ;default: 8'h0 ; */ +/*description: .*/ +#define I2C_ANA_MST_ANA_STATUS2 0x000000FF +#define I2C_ANA_MST_ANA_STATUS2_M ((I2C_ANA_MST_STATUS2_V)<<(I2C_ANA_MST_STATUS2_S)) +#define I2C_ANA_MST_ANA_STATUS2_V 0xFF +#define I2C_ANA_MST_ANA_STATUS2_S 24 +/* I2C_ANA_MST_ANA_CONF2 : R/W ;bitpos:[23:0] ;default: 24'h00_0004 ; */ +/*description: .*/ +#define I2C_ANA_MST_ANA_CONF2 0x00FFFFFF +#define I2C_ANA_MST_ANA_CONF2_M ((I2C_ANA_MST_ANA_CONF2_V)<<(I2C_ANA_MST_ANA_CONF2_S)) +#define I2C_ANA_MST_ANA_CONF2_V 0xFFFFFF +#define I2C_ANA_MST_ANA_CONF2_S 0 + +#define I2C_ANA_MST_I2C0_CTRL1_REG (DR_REG_I2C_ANA_MST_BASE + 0x24) +/* I2C_MST_I2C0_SDA_SIDE_GUARD : R/W ;bitpos:[10:6] ;default: 5'h1 ; */ +/*description: .*/ +#define I2C_ANA_MST_I2C0_SDA_SIDE_GUARD 0x0000001F +#define I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_M ((I2C_MST_I2C0_SDA_SIDE_GUARD_V)<<(I2C_MST_I2C0_SDA_SIDE_GUARD_S)) +#define I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_V 0x1F +#define I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_S 6 +/* I2C_MST_I2C0_SCL_PULSE_DUR : R/W ;bitpos:[5:0] ;default: 6'h2 ; */ +/*description: .*/ +#define I2C_ANA_MST_I2C0_SCL_PULSE_DUR 0x0000003F +#define I2C_ANA_MST_I2C0_SCL_PULSE_DUR_M ((I2C_MST_I2C0_SCL_PULSE_DUR_V)<<(I2C_MST_I2C0_SCL_PULSE_DUR_S)) +#define I2C_ANA_MST_I2C0_SCL_PULSE_DUR_V 0x3F +#define I2C_ANA_MST_I2C0_SCL_PULSE_DUR_S 0 + +#define I2C_ANA_MST_I2C1_CTRL1_REG (DR_REG_I2C_ANA_MST_BASE + 0x28) +/* I2C_MST_I2C1_SDA_SIDE_GUARD : R/W ;bitpos:[10:6] ;default: 5'h1 ; */ +/*description: .*/ +#define I2C_ANA_MST_I2C1_SDA_SIDE_GUARD 0x0000001F +#define I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_M ((I2C_MST_I2C1_SDA_SIDE_GUARD_V)<<(I2C_MST_I2C1_SDA_SIDE_GUARD_S)) +#define I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_V 0x1F +#define I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_S 6 +/* I2C_MST_I2C1_SCL_PULSE_DUR : R/W ;bitpos:[5:0] ;default: 6'h2 ; */ +/*description: .*/ +#define I2C_ANA_MST_I2C1_SCL_PULSE_DUR 0x0000003F +#define I2C_ANA_MST_I2C1_SCL_PULSE_DUR_M ((I2C_MST_I2C1_SCL_PULSE_DUR_V)<<(I2C_MST_I2C1_SCL_PULSE_DUR_S)) +#define I2C_ANA_MST_I2C1_SCL_PULSE_DUR_V 0x3F +#define I2C_ANA_MST_I2C1_SCL_PULSE_DUR_S 0 + +#define I2C_ANA_MST_HW_I2C_CTRL_REG (DR_REG_I2C_ANA_MST_BASE + 0x2C) +/* I2C_MST_ARBITER_DIS : R/W ;bitpos:[11] ;default: 1'h0 ; */ +/*description: .*/ +#define I2C_ANA_MST_ARBITER_DIS (BIT(11)) +#define I2C_ANA_MST_ARBITER_DIS_M (BIT(11)) +#define I2C_ANA_MST_ARBITER_DIS_V 0x1 +#define I2C_ANA_MST_ARBITER_DIS_S 11 +/* I2C_MST_HW_I2C_SDA_SIDE_GUARD : R/W ;bitpos:[10:6] ;default: 5'h1 ; */ +/*description: .*/ +#define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD 0x0000001F +#define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_M ((I2C_MST_HW_I2C_SDA_SIDE_GUARD_V)<<(I2C_MST_HW_I2C_SDA_SIDE_GUARD_S)) +#define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_V 0x1F +#define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_S 6 +/* I2C_MST_HW_I2C_SCL_PULSE_DUR : R/W ;bitpos:[5:0] ;default: 6'h2 ; */ +/*description: .*/ +#define I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR 0x0000003F +#define I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_M ((I2C_MST_HW_I2C_SCL_PULSE_DUR_V)<<(I2C_MST_HW_I2C_SCL_PULSE_DUR_S)) +#define I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_V 0x3F +#define I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_S 0 + +#define I2C_ANA_MST_NOUSE_REG (DR_REG_I2C_ANA_MST_BASE + 0x30) +/* I2C_MST_NOUSE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: .*/ +#define I2C_ANA_MST_NOUSE 0xFFFFFFFF +#define I2C_ANA_MST_NOUSE_M ((I2C_MST_NOUSE_V)<<(I2C_MST_NOUSE_S)) +#define I2C_ANA_MST_NOUSE_V 0xFFFFFFFF +#define I2C_ANA_MST_NOUSE_S 0 + +#define I2C_ANA_MST_DATE_REG (DR_REG_I2C_ANA_MST_BASE + 0x34) +/* I2C_MST_CLK_EN : R/W ;bitpos:[28] ;default: 1'h0 ; */ +/*description: .*/ +#define I2C_ANA_MST_CLK_EN (BIT(28)) +#define I2C_ANA_MST_CLK_EN_M (BIT(28)) +#define I2C_ANA_MST_CLK_EN_V 0x1 +#define I2C_ANA_MST_CLK_EN_S 28 +/* I2C_MST_DATE : R/W ;bitpos:[27:0] ;default: 28'h2201300 ; */ +/*description: .*/ +#define I2C_ANA_MST_DATE 0x0FFFFFFF +#define I2C_ANA_MST_DATE_M ((I2C_MST_DATE_V)<<(I2C_MST_DATE_S)) +#define I2C_ANA_MST_DATE_V 0xFFFFFFF +#define I2C_ANA_MST_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/reg_base.h b/components/soc/esp32c5/include/soc/reg_base.h index ce5adec458..d681b6ffe6 100644 --- a/components/soc/esp32c5/include/soc/reg_base.h +++ b/components/soc/esp32c5/include/soc/reg_base.h @@ -70,6 +70,7 @@ */ #define DR_REG_MODEM_BASE 0x600A4000 #define DR_REG_MODEM_PWR_BASE 0x600AD000 +#define DR_REG_I2C_ANA_MST_BASE 0x600AF800 /** * @brief LP System (RTC) Modules