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Merge branch 'fix/fix_flash_encryption_esp32p4_v5.3' into 'release/v5.3'

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fix(bootloader_support): Fix flash encryption for esp32p4 (v5.3)

See merge request espressif/esp-idf!30921
This commit is contained in:
Mahavir Jain
2024-05-20 12:29:18 +08:00
parent 41ff5a2f43 3640c1ecba
commit d638267741
2 changed files with 23 additions and 7 deletions
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15
components/bootloader_support/src/flash_encryption/flash_encrypt.c
View File

@@ -18,6 +18,7 @@
#if SOC_KEY_MANAGER_SUPPORTED #if SOC_KEY_MANAGER_SUPPORTED
#include "hal/key_mgr_hal.h" #include "hal/key_mgr_hal.h"
#include "hal/mspi_timing_tuning_ll.h"
#include "soc/keymng_reg.h" #include "soc/keymng_reg.h"
#endif #endif
@@ -217,8 +218,15 @@ static esp_err_t check_and_generate_encryption_keys(void)
} }
#if SOC_KEY_MANAGER_SUPPORTED #if SOC_KEY_MANAGER_SUPPORTED
#if CONFIG_IDF_TARGET_ESP32C5 && SOC_KEY_MANAGER_SUPPORTED
// TODO: [ESP32C5] IDF-8622 find a more proper place for these codes
REG_SET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_FLASH);
REG_SET_BIT(PCR_MSPI_CLK_CONF_REG, PCR_MSPI_AXI_RST_EN);
REG_CLR_BIT(PCR_MSPI_CLK_CONF_REG, PCR_MSPI_AXI_RST_EN);
#endif
// Force Key Manager to use eFuse key for XTS-AES operation // Force Key Manager to use eFuse key for XTS-AES operation
key_mgr_hal_set_key_usage(ESP_KEY_MGR_XTS_AES_128_KEY, ESP_KEY_MGR_USE_EFUSE_KEY); key_mgr_hal_set_key_usage(ESP_KEY_MGR_XTS_AES_128_KEY, ESP_KEY_MGR_USE_EFUSE_KEY);
_mspi_timing_ll_reset_mspi();
#endif #endif
return ESP_OK; return ESP_OK;
@@ -263,13 +271,6 @@ esp_err_t esp_flash_encrypt_contents(void)
esp_partition_info_t partition_table[ESP_PARTITION_TABLE_MAX_ENTRIES]; esp_partition_info_t partition_table[ESP_PARTITION_TABLE_MAX_ENTRIES];
int num_partitions; int num_partitions;
#if CONFIG_IDF_TARGET_ESP32C5 && SOC_KEY_MANAGER_SUPPORTED
// TODO: [ESP32C5] IDF-8622 find a more proper place for these codes
REG_SET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_FLASH);
REG_SET_BIT(PCR_MSPI_CLK_CONF_REG, PCR_MSPI_AXI_RST_EN);
REG_CLR_BIT(PCR_MSPI_CLK_CONF_REG, PCR_MSPI_AXI_RST_EN);
#endif
#ifdef CONFIG_SOC_EFUSE_CONSISTS_OF_ONE_KEY_BLOCK #ifdef CONFIG_SOC_EFUSE_CONSISTS_OF_ONE_KEY_BLOCK
REG_WRITE(SENSITIVE_XTS_AES_KEY_UPDATE_REG, 1); REG_WRITE(SENSITIVE_XTS_AES_KEY_UPDATE_REG, 1);
#endif #endif

15
components/hal/esp32p4/include/hal/mspi_timing_tuning_ll.h
View File

@@ -18,6 +18,7 @@
#include "soc/soc.h" #include "soc/soc.h"
#include "soc/iomux_mspi_pin_reg.h" #include "soc/iomux_mspi_pin_reg.h"
#include "soc/iomux_mspi_pin_struct.h" #include "soc/iomux_mspi_pin_struct.h"
#include "soc/hp_sys_clkrst_reg.h"
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
@@ -71,6 +72,20 @@ typedef enum {
MSPI_LL_PIN_MAX, MSPI_LL_PIN_MAX,
} mspi_ll_pin_t; } mspi_ll_pin_t;
/**
* Reset the MSPI clock
*/
__attribute__((always_inline))
static inline void _mspi_timing_ll_reset_mspi(void)
{
REG_SET_BIT(HP_SYS_CLKRST_HP_RST_EN0_REG, HP_SYS_CLKRST_REG_RST_EN_MSPI_AXI);
REG_CLR_BIT(HP_SYS_CLKRST_HP_RST_EN0_REG, HP_SYS_CLKRST_REG_RST_EN_MSPI_AXI);
}
/// use a macro to wrap the function, force the caller to use it in a critical section
/// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance
#define mspi_timing_ll_reset_mspi(...) (void)__DECLARE_RCC_RC_ATOMIC_ENV; _mspi_timing_ll_reset_mspi(__VA_ARGS__)
/** /**
* Set all MSPI DQS phase * Set all MSPI DQS phase
* *