diff --git a/components/esp_hw_support/port/esp32c5/rtc_clk.c b/components/esp_hw_support/port/esp32c5/rtc_clk.c
index e5ab6c0f41..ca16e4969a 100644
--- a/components/esp_hw_support/port/esp32c5/rtc_clk.c
+++ b/components/esp_hw_support/port/esp32c5/rtc_clk.c
@@ -408,8 +408,12 @@ void rtc_clk_cpu_freq_set_xtal_for_sleep(void)
 
 void rtc_clk_cpu_freq_to_pll_and_pll_lock_release(int cpu_freq_mhz)
 {
-    // TODO: IDF-8641 CPU_MAX_FREQ don't know what to do... pll_240 or pll_160...
-    rtc_clk_cpu_freq_to_pll_240_mhz(cpu_freq_mhz);
+    //                          IDF-11064
+    if (cpu_freq_mhz == 240 || (cpu_freq_mhz == 80 && !ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 1))) {
+        rtc_clk_cpu_freq_to_pll_240_mhz(cpu_freq_mhz);
+    } else { // cpu_freq_mhz is 160 or 80 (fixed for chip rev. >= ECO1)
+        rtc_clk_cpu_freq_to_pll_160_mhz(cpu_freq_mhz);
+    }
     clk_ll_cpu_clk_src_lock_release();
 }