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Merge branch 'change/sync_trm_csv_update_5_27' into 'master'

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change(csv_update): sync the csv update to idf

See merge request espressif/esp-idf!39459
This commit is contained in:
Kevin (Lao Kaiyao)
2025-05-30 16:00:04 +08:00
parent a9cdd337ce fb32407754
commit d86a84edfd
9 changed files with 248 additions and 384 deletions
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1
components/soc/esp32c5/include/soc/pmu_icg_mapping.h
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@@ -33,6 +33,7 @@
#define PMU_ICG_APB_ENA_MEM_MONITOR 25 #define PMU_ICG_APB_ENA_MEM_MONITOR 25
#define PMU_ICG_APB_ENA_IOMUX 26 #define PMU_ICG_APB_ENA_IOMUX 26
#define PMU_ICG_APB_ENA_PVT_MONITOR 27 #define PMU_ICG_APB_ENA_PVT_MONITOR 27
#define PMU_ICG_APB_ENA_BS 28
#define PMU_ICG_FUNC_ENA_GDMA 0 #define PMU_ICG_FUNC_ENA_GDMA 0
#define PMU_ICG_FUNC_ENA_SPI2 1 #define PMU_ICG_FUNC_ENA_SPI2 1
#define PMU_ICG_FUNC_ENA_I2S_RX 2 #define PMU_ICG_FUNC_ENA_I2S_RX 2

152
components/soc/esp32h21/register/soc/ecdsa_reg.h
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@@ -1,5 +1,5 @@
/** /**
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -12,62 +12,66 @@ extern "C" {
#endif #endif
/** ECDSA_CONF_REG register /** ECDSA_CONF_REG register
* ECDSA configure register * ECDSA configuration register
*/ */
#define ECDSA_CONF_REG (DR_REG_ECDSA_BASE + 0x4) #define ECDSA_CONF_REG (DR_REG_ECDSA_BASE + 0x4)
/** ECDSA_WORK_MODE : R/W; bitpos: [1:0]; default: 0; /** ECDSA_WORK_MODE : R/W; bitpos: [1:0]; default: 0;
* The work mode bits of ECDSA Accelerator. 0: Signature Verify Mode. 1: Signature * Configures the working mode of ECDSA accelerator.
* Generate Mode. 2: Export Public Key Mode. 3: invalid. * 0: Signature Verification Mode
* 1: Signature Generation Mode
* 2: Public Key Export Mode
* 3: Invalid
*/ */
#define ECDSA_WORK_MODE 0x00000003U #define ECDSA_WORK_MODE 0x00000003U
#define ECDSA_WORK_MODE_M (ECDSA_WORK_MODE_V << ECDSA_WORK_MODE_S) #define ECDSA_WORK_MODE_M (ECDSA_WORK_MODE_V << ECDSA_WORK_MODE_S)
#define ECDSA_WORK_MODE_V 0x00000003U #define ECDSA_WORK_MODE_V 0x00000003U
#define ECDSA_WORK_MODE_S 0 #define ECDSA_WORK_MODE_S 0
/** ECDSA_ECC_CURVE : R/W; bitpos: [2]; default: 0; /** ECDSA_ECC_CURVE : R/W; bitpos: [2]; default: 0;
* The ecc curve select bit of ECDSA Accelerator. 0: P-192. 1: P-256. * Configures the elliptic curve used.
* 0: P-192
* 1: P-256
*/ */
#define ECDSA_ECC_CURVE (BIT(2)) #define ECDSA_ECC_CURVE (BIT(2))
#define ECDSA_ECC_CURVE_M (ECDSA_ECC_CURVE_V << ECDSA_ECC_CURVE_S) #define ECDSA_ECC_CURVE_M (ECDSA_ECC_CURVE_V << ECDSA_ECC_CURVE_S)
#define ECDSA_ECC_CURVE_V 0x00000001U #define ECDSA_ECC_CURVE_V 0x00000001U
#define ECDSA_ECC_CURVE_S 2 #define ECDSA_ECC_CURVE_S 2
/** ECDSA_SOFTWARE_SET_K : R/W; bitpos: [3]; default: 0; /** ECDSA_SOFTWARE_SET_K : R/W; bitpos: [3]; default: 0;
* The source of k select bit. 0: k is automatically generated by hardware. 1: k is * Configures the generation source of k.
* written by software. * 0: k is automatically generated by hardware
* 1: k is written by software
*/ */
#define ECDSA_SOFTWARE_SET_K (BIT(3)) #define ECDSA_SOFTWARE_SET_K (BIT(3))
#define ECDSA_SOFTWARE_SET_K_M (ECDSA_SOFTWARE_SET_K_V << ECDSA_SOFTWARE_SET_K_S) #define ECDSA_SOFTWARE_SET_K_M (ECDSA_SOFTWARE_SET_K_V << ECDSA_SOFTWARE_SET_K_S)
#define ECDSA_SOFTWARE_SET_K_V 0x00000001U #define ECDSA_SOFTWARE_SET_K_V 0x00000001U
#define ECDSA_SOFTWARE_SET_K_S 3 #define ECDSA_SOFTWARE_SET_K_S 3
/** ECDSA_SOFTWARE_SET_Z : R/W; bitpos: [4]; default: 0; /** ECDSA_SOFTWARE_SET_Z : R/W; bitpos: [4]; default: 0;
* The source of z select bit. 0: z is generated from SHA result. 1: z is written by * Configures how the parameter $z$ is set.
* software. * 0: Generated from SHA result
* 1: Written by software
*/ */
#define ECDSA_SOFTWARE_SET_Z (BIT(4)) #define ECDSA_SOFTWARE_SET_Z (BIT(4))
#define ECDSA_SOFTWARE_SET_Z_M (ECDSA_SOFTWARE_SET_Z_V << ECDSA_SOFTWARE_SET_Z_S) #define ECDSA_SOFTWARE_SET_Z_M (ECDSA_SOFTWARE_SET_Z_V << ECDSA_SOFTWARE_SET_Z_S)
#define ECDSA_SOFTWARE_SET_Z_V 0x00000001U #define ECDSA_SOFTWARE_SET_Z_V 0x00000001U
#define ECDSA_SOFTWARE_SET_Z_S 4 #define ECDSA_SOFTWARE_SET_Z_S 4
/** ECDSA_DETERMINISTIC_K : R/W; bitpos: [5]; default: 0; /** ECDSA_DETERMINISTIC_K : R/W; bitpos: [5]; default: 0;
* The source of hardware generated k. 0: k is generated by TRNG. 1: k is generated by *
* deterministic derivation algorithm. * Configures how the parameter $k$ is set.
* 0: Automatically generated by TRNG
* 1: Generated by the deterministic derivation algorithm
*/ */
#define ECDSA_DETERMINISTIC_K (BIT(5)) #define ECDSA_DETERMINISTIC_K (BIT(5))
#define ECDSA_DETERMINISTIC_K_M (ECDSA_DETERMINISTIC_K_V << ECDSA_DETERMINISTIC_K_S) #define ECDSA_DETERMINISTIC_K_M (ECDSA_DETERMINISTIC_K_V << ECDSA_DETERMINISTIC_K_S)
#define ECDSA_DETERMINISTIC_K_V 0x00000001U #define ECDSA_DETERMINISTIC_K_V 0x00000001U
#define ECDSA_DETERMINISTIC_K_S 5 #define ECDSA_DETERMINISTIC_K_S 5
/** ECDSA_DETERMINISTIC_LOOP : R/W; bitpos: [21:6]; default: 0;
* The (loop number - 1) value in the deterministic derivation algorithm to derive k.
*/
#define ECDSA_DETERMINISTIC_LOOP 0x0000FFFFU
#define ECDSA_DETERMINISTIC_LOOP_M (ECDSA_DETERMINISTIC_LOOP_V << ECDSA_DETERMINISTIC_LOOP_S)
#define ECDSA_DETERMINISTIC_LOOP_V 0x0000FFFFU
#define ECDSA_DETERMINISTIC_LOOP_S 6
/** ECDSA_CLK_REG register /** ECDSA_CLK_REG register
* ECDSA clock gate register * ECDSA clock gate register
*/ */
#define ECDSA_CLK_REG (DR_REG_ECDSA_BASE + 0x8) #define ECDSA_CLK_REG (DR_REG_ECDSA_BASE + 0x8)
/** ECDSA_CLK_GATE_FORCE_ON : R/W; bitpos: [0]; default: 0; /** ECDSA_CLK_GATE_FORCE_ON : R/W; bitpos: [0]; default: 0;
* Write 1 to force on register clock gate. * Configures whether to force on ECDSA memory clock gate.
* 0: No effect
* 1: Force on
*/ */
#define ECDSA_CLK_GATE_FORCE_ON (BIT(0)) #define ECDSA_CLK_GATE_FORCE_ON (BIT(0))
#define ECDSA_CLK_GATE_FORCE_ON_M (ECDSA_CLK_GATE_FORCE_ON_V << ECDSA_CLK_GATE_FORCE_ON_S) #define ECDSA_CLK_GATE_FORCE_ON_M (ECDSA_CLK_GATE_FORCE_ON_V << ECDSA_CLK_GATE_FORCE_ON_S)
@@ -75,32 +79,32 @@ extern "C" {
#define ECDSA_CLK_GATE_FORCE_ON_S 0 #define ECDSA_CLK_GATE_FORCE_ON_S 0
/** ECDSA_INT_RAW_REG register /** ECDSA_INT_RAW_REG register
* ECDSA interrupt raw register, valid in level. * ECDSA interrupt raw register
*/ */
#define ECDSA_INT_RAW_REG (DR_REG_ECDSA_BASE + 0xc) #define ECDSA_INT_RAW_REG (DR_REG_ECDSA_BASE + 0xc)
/** ECDSA_PREP_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0; /** ECDSA_PREP_DONE_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0;
* The raw interrupt status bit for the ecdsa_prep_done_int interrupt * The raw interrupt status of the ECDSA_PREP_DONE_INT interrupt.
*/ */
#define ECDSA_PREP_DONE_INT_RAW (BIT(0)) #define ECDSA_PREP_DONE_INT_RAW (BIT(0))
#define ECDSA_PREP_DONE_INT_RAW_M (ECDSA_PREP_DONE_INT_RAW_V << ECDSA_PREP_DONE_INT_RAW_S) #define ECDSA_PREP_DONE_INT_RAW_M (ECDSA_PREP_DONE_INT_RAW_V << ECDSA_PREP_DONE_INT_RAW_S)
#define ECDSA_PREP_DONE_INT_RAW_V 0x00000001U #define ECDSA_PREP_DONE_INT_RAW_V 0x00000001U
#define ECDSA_PREP_DONE_INT_RAW_S 0 #define ECDSA_PREP_DONE_INT_RAW_S 0
/** ECDSA_PROC_DONE_INT_RAW : RO/WTC/SS; bitpos: [1]; default: 0; /** ECDSA_PROC_DONE_INT_RAW : R/SS/WTC; bitpos: [1]; default: 0;
* The raw interrupt status bit for the ecdsa_proc_done_int interrupt * The raw interrupt status of the ECDSA_PROC_DONE_INT interrupt.
*/ */
#define ECDSA_PROC_DONE_INT_RAW (BIT(1)) #define ECDSA_PROC_DONE_INT_RAW (BIT(1))
#define ECDSA_PROC_DONE_INT_RAW_M (ECDSA_PROC_DONE_INT_RAW_V << ECDSA_PROC_DONE_INT_RAW_S) #define ECDSA_PROC_DONE_INT_RAW_M (ECDSA_PROC_DONE_INT_RAW_V << ECDSA_PROC_DONE_INT_RAW_S)
#define ECDSA_PROC_DONE_INT_RAW_V 0x00000001U #define ECDSA_PROC_DONE_INT_RAW_V 0x00000001U
#define ECDSA_PROC_DONE_INT_RAW_S 1 #define ECDSA_PROC_DONE_INT_RAW_S 1
/** ECDSA_POST_DONE_INT_RAW : RO/WTC/SS; bitpos: [2]; default: 0; /** ECDSA_POST_DONE_INT_RAW : R/SS/WTC; bitpos: [2]; default: 0;
* The raw interrupt status bit for the ecdsa_post_done_int interrupt * The raw interrupt status of the ECDSA_POST_DONE_INT interrupt.
*/ */
#define ECDSA_POST_DONE_INT_RAW (BIT(2)) #define ECDSA_POST_DONE_INT_RAW (BIT(2))
#define ECDSA_POST_DONE_INT_RAW_M (ECDSA_POST_DONE_INT_RAW_V << ECDSA_POST_DONE_INT_RAW_S) #define ECDSA_POST_DONE_INT_RAW_M (ECDSA_POST_DONE_INT_RAW_V << ECDSA_POST_DONE_INT_RAW_S)
#define ECDSA_POST_DONE_INT_RAW_V 0x00000001U #define ECDSA_POST_DONE_INT_RAW_V 0x00000001U
#define ECDSA_POST_DONE_INT_RAW_S 2 #define ECDSA_POST_DONE_INT_RAW_S 2
/** ECDSA_SHA_RELEASE_INT_RAW : RO/WTC/SS; bitpos: [3]; default: 0; /** ECDSA_SHA_RELEASE_INT_RAW : R/SS/WTC; bitpos: [3]; default: 0;
* The raw interrupt status bit for the ecdsa_sha_release_int interrupt * The raw interrupt status of the ECDSA_SHA_RELEASE_INT interrupt.
*/ */
#define ECDSA_SHA_RELEASE_INT_RAW (BIT(3)) #define ECDSA_SHA_RELEASE_INT_RAW (BIT(3))
#define ECDSA_SHA_RELEASE_INT_RAW_M (ECDSA_SHA_RELEASE_INT_RAW_V << ECDSA_SHA_RELEASE_INT_RAW_S) #define ECDSA_SHA_RELEASE_INT_RAW_M (ECDSA_SHA_RELEASE_INT_RAW_V << ECDSA_SHA_RELEASE_INT_RAW_S)
@@ -108,32 +112,32 @@ extern "C" {
#define ECDSA_SHA_RELEASE_INT_RAW_S 3 #define ECDSA_SHA_RELEASE_INT_RAW_S 3
/** ECDSA_INT_ST_REG register /** ECDSA_INT_ST_REG register
* ECDSA interrupt status register. * ECDSA interrupt status register
*/ */
#define ECDSA_INT_ST_REG (DR_REG_ECDSA_BASE + 0x10) #define ECDSA_INT_ST_REG (DR_REG_ECDSA_BASE + 0x10)
/** ECDSA_PREP_DONE_INT_ST : RO; bitpos: [0]; default: 0; /** ECDSA_PREP_DONE_INT_ST : RO; bitpos: [0]; default: 0;
* The masked interrupt status bit for the ecdsa_prep_done_int interrupt * The masked interrupt status of the ECDSA_PREP_DONE_INT interrupt.
*/ */
#define ECDSA_PREP_DONE_INT_ST (BIT(0)) #define ECDSA_PREP_DONE_INT_ST (BIT(0))
#define ECDSA_PREP_DONE_INT_ST_M (ECDSA_PREP_DONE_INT_ST_V << ECDSA_PREP_DONE_INT_ST_S) #define ECDSA_PREP_DONE_INT_ST_M (ECDSA_PREP_DONE_INT_ST_V << ECDSA_PREP_DONE_INT_ST_S)
#define ECDSA_PREP_DONE_INT_ST_V 0x00000001U #define ECDSA_PREP_DONE_INT_ST_V 0x00000001U
#define ECDSA_PREP_DONE_INT_ST_S 0 #define ECDSA_PREP_DONE_INT_ST_S 0
/** ECDSA_PROC_DONE_INT_ST : RO; bitpos: [1]; default: 0; /** ECDSA_PROC_DONE_INT_ST : RO; bitpos: [1]; default: 0;
* The masked interrupt status bit for the ecdsa_proc_done_int interrupt * The masked interrupt status of the ECDSA_PROC_DONE_INT interrupt.
*/ */
#define ECDSA_PROC_DONE_INT_ST (BIT(1)) #define ECDSA_PROC_DONE_INT_ST (BIT(1))
#define ECDSA_PROC_DONE_INT_ST_M (ECDSA_PROC_DONE_INT_ST_V << ECDSA_PROC_DONE_INT_ST_S) #define ECDSA_PROC_DONE_INT_ST_M (ECDSA_PROC_DONE_INT_ST_V << ECDSA_PROC_DONE_INT_ST_S)
#define ECDSA_PROC_DONE_INT_ST_V 0x00000001U #define ECDSA_PROC_DONE_INT_ST_V 0x00000001U
#define ECDSA_PROC_DONE_INT_ST_S 1 #define ECDSA_PROC_DONE_INT_ST_S 1
/** ECDSA_POST_DONE_INT_ST : RO; bitpos: [2]; default: 0; /** ECDSA_POST_DONE_INT_ST : RO; bitpos: [2]; default: 0;
* The masked interrupt status bit for the ecdsa_post_done_int interrupt * The masked interrupt status of the ECDSA_POST_DONE_INT interrupt.
*/ */
#define ECDSA_POST_DONE_INT_ST (BIT(2)) #define ECDSA_POST_DONE_INT_ST (BIT(2))
#define ECDSA_POST_DONE_INT_ST_M (ECDSA_POST_DONE_INT_ST_V << ECDSA_POST_DONE_INT_ST_S) #define ECDSA_POST_DONE_INT_ST_M (ECDSA_POST_DONE_INT_ST_V << ECDSA_POST_DONE_INT_ST_S)
#define ECDSA_POST_DONE_INT_ST_V 0x00000001U #define ECDSA_POST_DONE_INT_ST_V 0x00000001U
#define ECDSA_POST_DONE_INT_ST_S 2 #define ECDSA_POST_DONE_INT_ST_S 2
/** ECDSA_SHA_RELEASE_INT_ST : RO; bitpos: [3]; default: 0; /** ECDSA_SHA_RELEASE_INT_ST : RO; bitpos: [3]; default: 0;
* The masked interrupt status bit for the ecdsa_sha_release_int interrupt * The masked interrupt status of the ECDSA_SHA_RELEASE_INT interrupt.
*/ */
#define ECDSA_SHA_RELEASE_INT_ST (BIT(3)) #define ECDSA_SHA_RELEASE_INT_ST (BIT(3))
#define ECDSA_SHA_RELEASE_INT_ST_M (ECDSA_SHA_RELEASE_INT_ST_V << ECDSA_SHA_RELEASE_INT_ST_S) #define ECDSA_SHA_RELEASE_INT_ST_M (ECDSA_SHA_RELEASE_INT_ST_V << ECDSA_SHA_RELEASE_INT_ST_S)
@@ -141,32 +145,32 @@ extern "C" {
#define ECDSA_SHA_RELEASE_INT_ST_S 3 #define ECDSA_SHA_RELEASE_INT_ST_S 3
/** ECDSA_INT_ENA_REG register /** ECDSA_INT_ENA_REG register
* ECDSA interrupt enable register. * ECDSA interrupt enable register
*/ */
#define ECDSA_INT_ENA_REG (DR_REG_ECDSA_BASE + 0x14) #define ECDSA_INT_ENA_REG (DR_REG_ECDSA_BASE + 0x14)
/** ECDSA_PREP_DONE_INT_ENA : R/W; bitpos: [0]; default: 0; /** ECDSA_PREP_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
* The interrupt enable bit for the ecdsa_prep_done_int interrupt * Write 1 to enable the ECDSA_PREP_DONE_INT interrupt.
*/ */
#define ECDSA_PREP_DONE_INT_ENA (BIT(0)) #define ECDSA_PREP_DONE_INT_ENA (BIT(0))
#define ECDSA_PREP_DONE_INT_ENA_M (ECDSA_PREP_DONE_INT_ENA_V << ECDSA_PREP_DONE_INT_ENA_S) #define ECDSA_PREP_DONE_INT_ENA_M (ECDSA_PREP_DONE_INT_ENA_V << ECDSA_PREP_DONE_INT_ENA_S)
#define ECDSA_PREP_DONE_INT_ENA_V 0x00000001U #define ECDSA_PREP_DONE_INT_ENA_V 0x00000001U
#define ECDSA_PREP_DONE_INT_ENA_S 0 #define ECDSA_PREP_DONE_INT_ENA_S 0
/** ECDSA_PROC_DONE_INT_ENA : R/W; bitpos: [1]; default: 0; /** ECDSA_PROC_DONE_INT_ENA : R/W; bitpos: [1]; default: 0;
* The interrupt enable bit for the ecdsa_proc_done_int interrupt * Write 1 to enable the ECDSA_PROC_DONE_INT interrupt.
*/ */
#define ECDSA_PROC_DONE_INT_ENA (BIT(1)) #define ECDSA_PROC_DONE_INT_ENA (BIT(1))
#define ECDSA_PROC_DONE_INT_ENA_M (ECDSA_PROC_DONE_INT_ENA_V << ECDSA_PROC_DONE_INT_ENA_S) #define ECDSA_PROC_DONE_INT_ENA_M (ECDSA_PROC_DONE_INT_ENA_V << ECDSA_PROC_DONE_INT_ENA_S)
#define ECDSA_PROC_DONE_INT_ENA_V 0x00000001U #define ECDSA_PROC_DONE_INT_ENA_V 0x00000001U
#define ECDSA_PROC_DONE_INT_ENA_S 1 #define ECDSA_PROC_DONE_INT_ENA_S 1
/** ECDSA_POST_DONE_INT_ENA : R/W; bitpos: [2]; default: 0; /** ECDSA_POST_DONE_INT_ENA : R/W; bitpos: [2]; default: 0;
* The interrupt enable bit for the ecdsa_post_done_int interrupt * Write 1 to enable the ECDSA_POST_DONE_INT interrupt.
*/ */
#define ECDSA_POST_DONE_INT_ENA (BIT(2)) #define ECDSA_POST_DONE_INT_ENA (BIT(2))
#define ECDSA_POST_DONE_INT_ENA_M (ECDSA_POST_DONE_INT_ENA_V << ECDSA_POST_DONE_INT_ENA_S) #define ECDSA_POST_DONE_INT_ENA_M (ECDSA_POST_DONE_INT_ENA_V << ECDSA_POST_DONE_INT_ENA_S)
#define ECDSA_POST_DONE_INT_ENA_V 0x00000001U #define ECDSA_POST_DONE_INT_ENA_V 0x00000001U
#define ECDSA_POST_DONE_INT_ENA_S 2 #define ECDSA_POST_DONE_INT_ENA_S 2
/** ECDSA_SHA_RELEASE_INT_ENA : R/W; bitpos: [3]; default: 0; /** ECDSA_SHA_RELEASE_INT_ENA : R/W; bitpos: [3]; default: 0;
* The interrupt enable bit for the ecdsa_sha_release_int interrupt * Write 1 to enable the ECDSA_SHA_RELEASE_INT interrupt.
*/ */
#define ECDSA_SHA_RELEASE_INT_ENA (BIT(3)) #define ECDSA_SHA_RELEASE_INT_ENA (BIT(3))
#define ECDSA_SHA_RELEASE_INT_ENA_M (ECDSA_SHA_RELEASE_INT_ENA_V << ECDSA_SHA_RELEASE_INT_ENA_S) #define ECDSA_SHA_RELEASE_INT_ENA_M (ECDSA_SHA_RELEASE_INT_ENA_V << ECDSA_SHA_RELEASE_INT_ENA_S)
@@ -174,32 +178,32 @@ extern "C" {
#define ECDSA_SHA_RELEASE_INT_ENA_S 3 #define ECDSA_SHA_RELEASE_INT_ENA_S 3
/** ECDSA_INT_CLR_REG register /** ECDSA_INT_CLR_REG register
* ECDSA interrupt clear register. * ECDSA interrupt clear register
*/ */
#define ECDSA_INT_CLR_REG (DR_REG_ECDSA_BASE + 0x18) #define ECDSA_INT_CLR_REG (DR_REG_ECDSA_BASE + 0x18)
/** ECDSA_PREP_DONE_INT_CLR : WT; bitpos: [0]; default: 0; /** ECDSA_PREP_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
* Set this bit to clear the ecdsa_prep_done_int interrupt * Write 1 to clear the ECDSA_PREP_DONE_INT interrupt.
*/ */
#define ECDSA_PREP_DONE_INT_CLR (BIT(0)) #define ECDSA_PREP_DONE_INT_CLR (BIT(0))
#define ECDSA_PREP_DONE_INT_CLR_M (ECDSA_PREP_DONE_INT_CLR_V << ECDSA_PREP_DONE_INT_CLR_S) #define ECDSA_PREP_DONE_INT_CLR_M (ECDSA_PREP_DONE_INT_CLR_V << ECDSA_PREP_DONE_INT_CLR_S)
#define ECDSA_PREP_DONE_INT_CLR_V 0x00000001U #define ECDSA_PREP_DONE_INT_CLR_V 0x00000001U
#define ECDSA_PREP_DONE_INT_CLR_S 0 #define ECDSA_PREP_DONE_INT_CLR_S 0
/** ECDSA_PROC_DONE_INT_CLR : WT; bitpos: [1]; default: 0; /** ECDSA_PROC_DONE_INT_CLR : WT; bitpos: [1]; default: 0;
* Set this bit to clear the ecdsa_proc_done_int interrupt * Write 1 to clear the ECDSA_PROC_DONE_INT interrupt.
*/ */
#define ECDSA_PROC_DONE_INT_CLR (BIT(1)) #define ECDSA_PROC_DONE_INT_CLR (BIT(1))
#define ECDSA_PROC_DONE_INT_CLR_M (ECDSA_PROC_DONE_INT_CLR_V << ECDSA_PROC_DONE_INT_CLR_S) #define ECDSA_PROC_DONE_INT_CLR_M (ECDSA_PROC_DONE_INT_CLR_V << ECDSA_PROC_DONE_INT_CLR_S)
#define ECDSA_PROC_DONE_INT_CLR_V 0x00000001U #define ECDSA_PROC_DONE_INT_CLR_V 0x00000001U
#define ECDSA_PROC_DONE_INT_CLR_S 1 #define ECDSA_PROC_DONE_INT_CLR_S 1
/** ECDSA_POST_DONE_INT_CLR : WT; bitpos: [2]; default: 0; /** ECDSA_POST_DONE_INT_CLR : WT; bitpos: [2]; default: 0;
* Set this bit to clear the ecdsa_post_done_int interrupt * Write 1 to clear the ECDSA_POST_DONE_INT interrupt.
*/ */
#define ECDSA_POST_DONE_INT_CLR (BIT(2)) #define ECDSA_POST_DONE_INT_CLR (BIT(2))
#define ECDSA_POST_DONE_INT_CLR_M (ECDSA_POST_DONE_INT_CLR_V << ECDSA_POST_DONE_INT_CLR_S) #define ECDSA_POST_DONE_INT_CLR_M (ECDSA_POST_DONE_INT_CLR_V << ECDSA_POST_DONE_INT_CLR_S)
#define ECDSA_POST_DONE_INT_CLR_V 0x00000001U #define ECDSA_POST_DONE_INT_CLR_V 0x00000001U
#define ECDSA_POST_DONE_INT_CLR_S 2 #define ECDSA_POST_DONE_INT_CLR_S 2
/** ECDSA_SHA_RELEASE_INT_CLR : WT; bitpos: [3]; default: 0; /** ECDSA_SHA_RELEASE_INT_CLR : WT; bitpos: [3]; default: 0;
* Set this bit to clear the ecdsa_sha_release_int interrupt * Write 1 to clear the ECDSA_SHA_RELEASE_INT interrupt.
*/ */
#define ECDSA_SHA_RELEASE_INT_CLR (BIT(3)) #define ECDSA_SHA_RELEASE_INT_CLR (BIT(3))
#define ECDSA_SHA_RELEASE_INT_CLR_M (ECDSA_SHA_RELEASE_INT_CLR_V << ECDSA_SHA_RELEASE_INT_CLR_S) #define ECDSA_SHA_RELEASE_INT_CLR_M (ECDSA_SHA_RELEASE_INT_CLR_V << ECDSA_SHA_RELEASE_INT_CLR_S)
@@ -211,24 +215,26 @@ extern "C" {
*/ */
#define ECDSA_START_REG (DR_REG_ECDSA_BASE + 0x1c) #define ECDSA_START_REG (DR_REG_ECDSA_BASE + 0x1c)
/** ECDSA_START : WT; bitpos: [0]; default: 0; /** ECDSA_START : WT; bitpos: [0]; default: 0;
* Write 1 to start calculation of ECDSA Accelerator. This bit will be self-cleared * Configures whether to start the ECDSA operation. This bit will be self-cleared
* after configuration. * after configuration.
* 0: No effect
* 1: Start the ECDSA operation
*/ */
#define ECDSA_START (BIT(0)) #define ECDSA_START (BIT(0))
#define ECDSA_START_M (ECDSA_START_V << ECDSA_START_S) #define ECDSA_START_M (ECDSA_START_V << ECDSA_START_S)
#define ECDSA_START_V 0x00000001U #define ECDSA_START_V 0x00000001U
#define ECDSA_START_S 0 #define ECDSA_START_S 0
/** ECDSA_LOAD_DONE : WT; bitpos: [1]; default: 0; /** ECDSA_LOAD_DONE : WT; bitpos: [1]; default: 0;
* Write 1 to input load done signal of ECDSA Accelerator. This bit will be * Write 1 to generate a signal indicating the ECDSA accelerator's LOAD operation is
* self-cleared after configuration. * done. This bit will be self-cleared after configuration.
*/ */
#define ECDSA_LOAD_DONE (BIT(1)) #define ECDSA_LOAD_DONE (BIT(1))
#define ECDSA_LOAD_DONE_M (ECDSA_LOAD_DONE_V << ECDSA_LOAD_DONE_S) #define ECDSA_LOAD_DONE_M (ECDSA_LOAD_DONE_V << ECDSA_LOAD_DONE_S)
#define ECDSA_LOAD_DONE_V 0x00000001U #define ECDSA_LOAD_DONE_V 0x00000001U
#define ECDSA_LOAD_DONE_S 1 #define ECDSA_LOAD_DONE_S 1
/** ECDSA_GET_DONE : WT; bitpos: [2]; default: 0; /** ECDSA_GET_DONE : WT; bitpos: [2]; default: 0;
* Write 1 to input get done signal of ECDSA Accelerator. This bit will be * Write 1 to generate a signal indicating the ECDSA accelerator's GAIN operation is
* self-cleared after configuration. * done. This bit will be self-cleared after configuration.
*/ */
#define ECDSA_GET_DONE (BIT(2)) #define ECDSA_GET_DONE (BIT(2))
#define ECDSA_GET_DONE_M (ECDSA_GET_DONE_V << ECDSA_GET_DONE_S) #define ECDSA_GET_DONE_M (ECDSA_GET_DONE_V << ECDSA_GET_DONE_S)
@@ -240,8 +246,11 @@ extern "C" {
*/ */
#define ECDSA_STATE_REG (DR_REG_ECDSA_BASE + 0x20) #define ECDSA_STATE_REG (DR_REG_ECDSA_BASE + 0x20)
/** ECDSA_BUSY : RO; bitpos: [1:0]; default: 0; /** ECDSA_BUSY : RO; bitpos: [1:0]; default: 0;
* The status bits of ECDSA Accelerator. ECDSA is at 0: IDLE, 1: LOAD, 2: GET, 3: BUSY * Represents the working status of the ECDSA accelerator.
* state. * 0: IDLE
* 1: LOAD
* 2: GAIN
* 3: BUSY
*/ */
#define ECDSA_BUSY 0x00000003U #define ECDSA_BUSY 0x00000003U
#define ECDSA_BUSY_M (ECDSA_BUSY_V << ECDSA_BUSY_S) #define ECDSA_BUSY_M (ECDSA_BUSY_V << ECDSA_BUSY_S)
@@ -253,28 +262,22 @@ extern "C" {
*/ */
#define ECDSA_RESULT_REG (DR_REG_ECDSA_BASE + 0x24) #define ECDSA_RESULT_REG (DR_REG_ECDSA_BASE + 0x24)
/** ECDSA_OPERATION_RESULT : RO/SS; bitpos: [0]; default: 0; /** ECDSA_OPERATION_RESULT : RO/SS; bitpos: [0]; default: 0;
* The operation result bit of ECDSA Accelerator, only valid when ECDSA calculation is * Indicates if the ECDSA operation is successful.
* done. * 0: Not successful
* 1: Successful
* Only valid when the ECDSA operation is done.
*/ */
#define ECDSA_OPERATION_RESULT (BIT(0)) #define ECDSA_OPERATION_RESULT (BIT(0))
#define ECDSA_OPERATION_RESULT_M (ECDSA_OPERATION_RESULT_V << ECDSA_OPERATION_RESULT_S) #define ECDSA_OPERATION_RESULT_M (ECDSA_OPERATION_RESULT_V << ECDSA_OPERATION_RESULT_S)
#define ECDSA_OPERATION_RESULT_V 0x00000001U #define ECDSA_OPERATION_RESULT_V 0x00000001U
#define ECDSA_OPERATION_RESULT_S 0 #define ECDSA_OPERATION_RESULT_S 0
/** ECDSA_K_VALUE_WARNING : RO/SS; bitpos: [1]; default: 0;
* The k value warning bit of ECDSA Accelerator, valid when k value is bigger than the
* curve order, then actually taken k = k mod n.
*/
#define ECDSA_K_VALUE_WARNING (BIT(1))
#define ECDSA_K_VALUE_WARNING_M (ECDSA_K_VALUE_WARNING_V << ECDSA_K_VALUE_WARNING_S)
#define ECDSA_K_VALUE_WARNING_V 0x00000001U
#define ECDSA_K_VALUE_WARNING_S 1
/** ECDSA_DATE_REG register /** ECDSA_DATE_REG register
* Version control register * Version control register
*/ */
#define ECDSA_DATE_REG (DR_REG_ECDSA_BASE + 0xfc) #define ECDSA_DATE_REG (DR_REG_ECDSA_BASE + 0xfc)
/** ECDSA_DATE : R/W; bitpos: [27:0]; default: 37761312; /** ECDSA_DATE : R/W; bitpos: [27:0]; default: 37761312;
* ECDSA version control register * The ECDSA version control register.
*/ */
#define ECDSA_DATE 0x0FFFFFFFU #define ECDSA_DATE 0x0FFFFFFFU
#define ECDSA_DATE_M (ECDSA_DATE_V << ECDSA_DATE_S) #define ECDSA_DATE_M (ECDSA_DATE_V << ECDSA_DATE_S)
@@ -282,12 +285,14 @@ extern "C" {
#define ECDSA_DATE_S 0 #define ECDSA_DATE_S 0
/** ECDSA_SHA_MODE_REG register /** ECDSA_SHA_MODE_REG register
* ECDSA control SHA register * ECDSA SHA-control register (Hash algrithm)
*/ */
#define ECDSA_SHA_MODE_REG (DR_REG_ECDSA_BASE + 0x200) #define ECDSA_SHA_MODE_REG (DR_REG_ECDSA_BASE + 0x200)
/** ECDSA_SHA_MODE : R/W; bitpos: [2:0]; default: 0; /** ECDSA_SHA_MODE : R/W; bitpos: [2:0]; default: 0;
* The work mode bits of SHA Calculator in ECDSA Accelerator. 1: SHA-224. 2: SHA-256. * Configures SHA algorithms for message hash.
* Others: invalid. * 1: SHA-224
* 2: SHA-256
* Others: invalid
*/ */
#define ECDSA_SHA_MODE 0x00000007U #define ECDSA_SHA_MODE 0x00000007U
#define ECDSA_SHA_MODE_M (ECDSA_SHA_MODE_V << ECDSA_SHA_MODE_S) #define ECDSA_SHA_MODE_M (ECDSA_SHA_MODE_V << ECDSA_SHA_MODE_S)
@@ -295,12 +300,12 @@ extern "C" {
#define ECDSA_SHA_MODE_S 0 #define ECDSA_SHA_MODE_S 0
/** ECDSA_SHA_START_REG register /** ECDSA_SHA_START_REG register
* ECDSA control SHA register * ECDSA SHA-control register (operation)
*/ */
#define ECDSA_SHA_START_REG (DR_REG_ECDSA_BASE + 0x210) #define ECDSA_SHA_START_REG (DR_REG_ECDSA_BASE + 0x210)
/** ECDSA_SHA_START : WT; bitpos: [0]; default: 0; /** ECDSA_SHA_START : WT; bitpos: [0]; default: 0;
* Write 1 to start the first calculation of SHA Calculator in ECDSA Accelerator. This * Write 1 to start the first SHA operation in the ECDSA process. This bit will be
* bit will be self-cleared after configuration. * self-cleared after configuration.
*/ */
#define ECDSA_SHA_START (BIT(0)) #define ECDSA_SHA_START (BIT(0))
#define ECDSA_SHA_START_M (ECDSA_SHA_START_V << ECDSA_SHA_START_S) #define ECDSA_SHA_START_M (ECDSA_SHA_START_V << ECDSA_SHA_START_S)
@@ -308,12 +313,12 @@ extern "C" {
#define ECDSA_SHA_START_S 0 #define ECDSA_SHA_START_S 0
/** ECDSA_SHA_CONTINUE_REG register /** ECDSA_SHA_CONTINUE_REG register
* ECDSA control SHA register * ECDSA SHA-control register (operation)
*/ */
#define ECDSA_SHA_CONTINUE_REG (DR_REG_ECDSA_BASE + 0x214) #define ECDSA_SHA_CONTINUE_REG (DR_REG_ECDSA_BASE + 0x214)
/** ECDSA_SHA_CONTINUE : WT; bitpos: [0]; default: 0; /** ECDSA_SHA_CONTINUE : WT; bitpos: [0]; default: 0;
* Write 1 to start the latter calculation of SHA Calculator in ECDSA Accelerator. This * Write 1 to start the latter SHA operation in the ECDSA process. This bit will be
* bit will be self-cleared after configuration. * self-cleared after configuration.
*/ */
#define ECDSA_SHA_CONTINUE (BIT(0)) #define ECDSA_SHA_CONTINUE (BIT(0))
#define ECDSA_SHA_CONTINUE_M (ECDSA_SHA_CONTINUE_V << ECDSA_SHA_CONTINUE_S) #define ECDSA_SHA_CONTINUE_M (ECDSA_SHA_CONTINUE_V << ECDSA_SHA_CONTINUE_S)
@@ -321,12 +326,13 @@ extern "C" {
#define ECDSA_SHA_CONTINUE_S 0 #define ECDSA_SHA_CONTINUE_S 0
/** ECDSA_SHA_BUSY_REG register /** ECDSA_SHA_BUSY_REG register
* ECDSA status register * ECDSA SHA-control status register
*/ */
#define ECDSA_SHA_BUSY_REG (DR_REG_ECDSA_BASE + 0x218) #define ECDSA_SHA_BUSY_REG (DR_REG_ECDSA_BASE + 0x218)
/** ECDSA_SHA_BUSY : RO; bitpos: [0]; default: 0; /** ECDSA_SHA_BUSY : RO; bitpos: [0]; default: 0;
* The busy status bit of SHA Calculator in ECDSA Accelerator. 1:SHA is in * Represents the working status of the SHA accelerator in the ECDSA process.
* calculation. 0: SHA is idle. * 0: IDLE
* 1: BUSY
*/ */
#define ECDSA_SHA_BUSY (BIT(0)) #define ECDSA_SHA_BUSY (BIT(0))
#define ECDSA_SHA_BUSY_M (ECDSA_SHA_BUSY_V << ECDSA_SHA_BUSY_S) #define ECDSA_SHA_BUSY_M (ECDSA_SHA_BUSY_V << ECDSA_SHA_BUSY_S)

151
components/soc/esp32h21/register/soc/ecdsa_struct.h
View File

@@ -1,5 +1,5 @@
/** /**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -12,34 +12,43 @@ extern "C" {
/** Group: Data Memory */ /** Group: Data Memory */
/** Group: Configuration registers */ /** Group: Configuration Registers */
/** Type of conf register /** Type of conf register
* ECDSA configure register * ECDSA configuration register
*/ */
typedef union { typedef union {
struct { struct {
/** work_mode : R/W; bitpos: [1:0]; default: 0; /** work_mode : R/W; bitpos: [1:0]; default: 0;
* The work mode bits of ECDSA Accelerator. 0: Signature Verify Mode. 1: Signature * Configures the working mode of ECDSA accelerator.
* Generate Mode. 2: Export Public Key Mode. 3: invalid. * 0: Signature Verification Mode
* 1: Signature Generation Mode
* 2: Public Key Export Mode
* 3: Invalid
*/ */
uint32_t work_mode:2; uint32_t work_mode:2;
/** ecc_curve : R/W; bitpos: [2]; default: 0; /** ecc_curve : R/W; bitpos: [2]; default: 0;
* The ecc curve select bit of ECDSA Accelerator. 0: P-192. 1: P-256. * Configures the elliptic curve used.
* 0: P-192
* 1: P-256
*/ */
uint32_t ecc_curve:1; uint32_t ecc_curve:1;
/** software_set_k : R/W; bitpos: [3]; default: 0; /** software_set_k : R/W; bitpos: [3]; default: 0;
* The source of k select bit. 0: k is automatically generated by hardware. 1: k is * Configures the generation source of k.
* written by software. * 0: k is automatically generated by hardware
* 1: k is written by software
*/ */
uint32_t software_set_k:1; uint32_t software_set_k:1;
/** software_set_z : R/W; bitpos: [4]; default: 0; /** software_set_z : R/W; bitpos: [4]; default: 0;
* The source of z select bit. 0: z is generated from SHA result. 1: z is written by * Configures how the parameter $z$ is set.
* software. * 0: Generated from SHA result
* 1: Written by software
*/ */
uint32_t software_set_z:1; uint32_t software_set_z:1;
/** deterministic_k : R/W; bitpos: [5]; default: 0; /** deterministic_k : R/W; bitpos: [5]; default: 0;
* The source of hardware generated k. 0: k is generated by TRNG. 1: k is generated by *
* deterministic derivation algorithm. * Configures how the parameter $k$ is set.
* 0: Automatically generated by TRNG
* 1: Generated by the deterministic derivation algorithm
*/ */
uint32_t deterministic_k:1; uint32_t deterministic_k:1;
uint32_t reserved_6:26; uint32_t reserved_6:26;
@@ -53,18 +62,20 @@ typedef union {
typedef union { typedef union {
struct { struct {
/** start : WT; bitpos: [0]; default: 0; /** start : WT; bitpos: [0]; default: 0;
* Write 1 to start calculation of ECDSA Accelerator. This bit will be self-cleared * Configures whether to start the ECDSA operation. This bit will be self-cleared
* after configuration. * after configuration.
* 0: No effect
* 1: Start the ECDSA operation
*/ */
uint32_t start:1; uint32_t start:1;
/** load_done : WT; bitpos: [1]; default: 0; /** load_done : WT; bitpos: [1]; default: 0;
* Write 1 to input load done signal of ECDSA Accelerator. This bit will be * Write 1 to generate a signal indicating the ECDSA accelerator's LOAD operation is
* self-cleared after configuration. * done. This bit will be self-cleared after configuration.
*/ */
uint32_t load_done:1; uint32_t load_done:1;
/** get_done : WT; bitpos: [2]; default: 0; /** get_done : WT; bitpos: [2]; default: 0;
* Write 1 to input get done signal of ECDSA Accelerator. This bit will be * Write 1 to generate a signal indicating the ECDSA accelerator's GAIN operation is
* self-cleared after configuration. * done. This bit will be self-cleared after configuration.
*/ */
uint32_t get_done:1; uint32_t get_done:1;
uint32_t reserved_3:29; uint32_t reserved_3:29;
@@ -73,14 +84,16 @@ typedef union {
} ecdsa_start_reg_t; } ecdsa_start_reg_t;
/** Group: Clock and reset registers */ /** Group: Clock and Reset Register */
/** Type of clk register /** Type of clk register
* ECDSA clock gate register * ECDSA clock gate register
*/ */
typedef union { typedef union {
struct { struct {
/** clk_gate_force_on : R/W; bitpos: [0]; default: 0; /** clk_gate_force_on : R/W; bitpos: [0]; default: 0;
* Write 1 to force on register clock gate. * Configures whether to force on ECDSA memory clock gate.
* 0: No effect
* 1: Force on
*/ */
uint32_t clk_gate_force_on:1; uint32_t clk_gate_force_on:1;
uint32_t reserved_1:31; uint32_t reserved_1:31;
@@ -89,26 +102,26 @@ typedef union {
} ecdsa_clk_reg_t; } ecdsa_clk_reg_t;
/** Group: Interrupt registers */ /** Group: Interrupt Registers */
/** Type of int_raw register /** Type of int_raw register
* ECDSA interrupt raw register, valid in level. * ECDSA interrupt raw register
*/ */
typedef union { typedef union {
struct { struct {
/** prep_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0; /** prep_done_int_raw : R/SS/WTC; bitpos: [0]; default: 0;
* The raw interrupt status bit for the ecdsa_prep_done_int interrupt * The raw interrupt status of the ECDSA_PREP_DONE_INT interrupt.
*/ */
uint32_t prep_done_int_raw:1; uint32_t prep_done_int_raw:1;
/** proc_done_int_raw : RO/WTC/SS; bitpos: [1]; default: 0; /** proc_done_int_raw : R/SS/WTC; bitpos: [1]; default: 0;
* The raw interrupt status bit for the ecdsa_proc_done_int interrupt * The raw interrupt status of the ECDSA_PROC_DONE_INT interrupt.
*/ */
uint32_t proc_done_int_raw:1; uint32_t proc_done_int_raw:1;
/** post_done_int_raw : RO/WTC/SS; bitpos: [2]; default: 0; /** post_done_int_raw : R/SS/WTC; bitpos: [2]; default: 0;
* The raw interrupt status bit for the ecdsa_post_done_int interrupt * The raw interrupt status of the ECDSA_POST_DONE_INT interrupt.
*/ */
uint32_t post_done_int_raw:1; uint32_t post_done_int_raw:1;
/** sha_release_int_raw : RO/WTC/SS; bitpos: [3]; default: 0; /** sha_release_int_raw : R/SS/WTC; bitpos: [3]; default: 0;
* The raw interrupt status bit for the ecdsa_sha_release_int interrupt * The raw interrupt status of the ECDSA_SHA_RELEASE_INT interrupt.
*/ */
uint32_t sha_release_int_raw:1; uint32_t sha_release_int_raw:1;
uint32_t reserved_4:28; uint32_t reserved_4:28;
@@ -117,24 +130,24 @@ typedef union {
} ecdsa_int_raw_reg_t; } ecdsa_int_raw_reg_t;
/** Type of int_st register /** Type of int_st register
* ECDSA interrupt status register. * ECDSA interrupt status register
*/ */
typedef union { typedef union {
struct { struct {
/** prep_done_int_st : RO; bitpos: [0]; default: 0; /** prep_done_int_st : RO; bitpos: [0]; default: 0;
* The masked interrupt status bit for the ecdsa_prep_done_int interrupt * The masked interrupt status of the ECDSA_PREP_DONE_INT interrupt.
*/ */
uint32_t prep_done_int_st:1; uint32_t prep_done_int_st:1;
/** proc_done_int_st : RO; bitpos: [1]; default: 0; /** proc_done_int_st : RO; bitpos: [1]; default: 0;
* The masked interrupt status bit for the ecdsa_proc_done_int interrupt * The masked interrupt status of the ECDSA_PROC_DONE_INT interrupt.
*/ */
uint32_t proc_done_int_st:1; uint32_t proc_done_int_st:1;
/** post_done_int_st : RO; bitpos: [2]; default: 0; /** post_done_int_st : RO; bitpos: [2]; default: 0;
* The masked interrupt status bit for the ecdsa_post_done_int interrupt * The masked interrupt status of the ECDSA_POST_DONE_INT interrupt.
*/ */
uint32_t post_done_int_st:1; uint32_t post_done_int_st:1;
/** sha_release_int_st : RO; bitpos: [3]; default: 0; /** sha_release_int_st : RO; bitpos: [3]; default: 0;
* The masked interrupt status bit for the ecdsa_sha_release_int interrupt * The masked interrupt status of the ECDSA_SHA_RELEASE_INT interrupt.
*/ */
uint32_t sha_release_int_st:1; uint32_t sha_release_int_st:1;
uint32_t reserved_4:28; uint32_t reserved_4:28;
@@ -143,24 +156,24 @@ typedef union {
} ecdsa_int_st_reg_t; } ecdsa_int_st_reg_t;
/** Type of int_ena register /** Type of int_ena register
* ECDSA interrupt enable register. * ECDSA interrupt enable register
*/ */
typedef union { typedef union {
struct { struct {
/** prep_done_int_ena : R/W; bitpos: [0]; default: 0; /** prep_done_int_ena : R/W; bitpos: [0]; default: 0;
* The interrupt enable bit for the ecdsa_prep_done_int interrupt * Write 1 to enable the ECDSA_PREP_DONE_INT interrupt.
*/ */
uint32_t prep_done_int_ena:1; uint32_t prep_done_int_ena:1;
/** proc_done_int_ena : R/W; bitpos: [1]; default: 0; /** proc_done_int_ena : R/W; bitpos: [1]; default: 0;
* The interrupt enable bit for the ecdsa_proc_done_int interrupt * Write 1 to enable the ECDSA_PROC_DONE_INT interrupt.
*/ */
uint32_t proc_done_int_ena:1; uint32_t proc_done_int_ena:1;
/** post_done_int_ena : R/W; bitpos: [2]; default: 0; /** post_done_int_ena : R/W; bitpos: [2]; default: 0;
* The interrupt enable bit for the ecdsa_post_done_int interrupt * Write 1 to enable the ECDSA_POST_DONE_INT interrupt.
*/ */
uint32_t post_done_int_ena:1; uint32_t post_done_int_ena:1;
/** sha_release_int_ena : R/W; bitpos: [3]; default: 0; /** sha_release_int_ena : R/W; bitpos: [3]; default: 0;
* The interrupt enable bit for the ecdsa_sha_release_int interrupt * Write 1 to enable the ECDSA_SHA_RELEASE_INT interrupt.
*/ */
uint32_t sha_release_int_ena:1; uint32_t sha_release_int_ena:1;
uint32_t reserved_4:28; uint32_t reserved_4:28;
@@ -169,24 +182,24 @@ typedef union {
} ecdsa_int_ena_reg_t; } ecdsa_int_ena_reg_t;
/** Type of int_clr register /** Type of int_clr register
* ECDSA interrupt clear register. * ECDSA interrupt clear register
*/ */
typedef union { typedef union {
struct { struct {
/** prep_done_int_clr : WT; bitpos: [0]; default: 0; /** prep_done_int_clr : WT; bitpos: [0]; default: 0;
* Set this bit to clear the ecdsa_prep_done_int interrupt * Write 1 to clear the ECDSA_PREP_DONE_INT interrupt.
*/ */
uint32_t prep_done_int_clr:1; uint32_t prep_done_int_clr:1;
/** proc_done_int_clr : WT; bitpos: [1]; default: 0; /** proc_done_int_clr : WT; bitpos: [1]; default: 0;
* Set this bit to clear the ecdsa_proc_done_int interrupt * Write 1 to clear the ECDSA_PROC_DONE_INT interrupt.
*/ */
uint32_t proc_done_int_clr:1; uint32_t proc_done_int_clr:1;
/** post_done_int_clr : WT; bitpos: [2]; default: 0; /** post_done_int_clr : WT; bitpos: [2]; default: 0;
* Set this bit to clear the ecdsa_post_done_int interrupt * Write 1 to clear the ECDSA_POST_DONE_INT interrupt.
*/ */
uint32_t post_done_int_clr:1; uint32_t post_done_int_clr:1;
/** sha_release_int_clr : WT; bitpos: [3]; default: 0; /** sha_release_int_clr : WT; bitpos: [3]; default: 0;
* Set this bit to clear the ecdsa_sha_release_int interrupt * Write 1 to clear the ECDSA_SHA_RELEASE_INT interrupt.
*/ */
uint32_t sha_release_int_clr:1; uint32_t sha_release_int_clr:1;
uint32_t reserved_4:28; uint32_t reserved_4:28;
@@ -195,15 +208,18 @@ typedef union {
} ecdsa_int_clr_reg_t; } ecdsa_int_clr_reg_t;
/** Group: Status registers */ /** Group: Status Registers */
/** Type of state register /** Type of state register
* ECDSA status register * ECDSA status register
*/ */
typedef union { typedef union {
struct { struct {
/** busy : RO; bitpos: [1:0]; default: 0; /** busy : RO; bitpos: [1:0]; default: 0;
* The status bits of ECDSA Accelerator. ECDSA is at 0: IDLE, 1: LOAD, 2: GET, 3: BUSY * Represents the working status of the ECDSA accelerator.
* state. * 0: IDLE
* 1: LOAD
* 2: GAIN
* 3: BUSY
*/ */
uint32_t busy:2; uint32_t busy:2;
uint32_t reserved_2:30; uint32_t reserved_2:30;
@@ -212,15 +228,17 @@ typedef union {
} ecdsa_state_reg_t; } ecdsa_state_reg_t;
/** Group: Result registers */ /** Group: Result Register */
/** Type of result register /** Type of result register
* ECDSA result register * ECDSA result register
*/ */
typedef union { typedef union {
struct { struct {
/** operation_result : RO/SS; bitpos: [0]; default: 0; /** operation_result : RO/SS; bitpos: [0]; default: 0;
* The operation result bit of ECDSA Accelerator, only valid when ECDSA calculation is * Indicates if the ECDSA operation is successful.
* done. * 0: Not successful
* 1: Successful
* Only valid when the ECDSA operation is done.
*/ */
uint32_t operation_result:1; uint32_t operation_result:1;
uint32_t reserved_1:31; uint32_t reserved_1:31;
@@ -229,15 +247,17 @@ typedef union {
} ecdsa_result_reg_t; } ecdsa_result_reg_t;
/** Group: SHA register */ /** Group: SHA Registers */
/** Type of sha_mode register /** Type of sha_mode register
* ECDSA control SHA register * ECDSA SHA-control register (Hash algrithm)
*/ */
typedef union { typedef union {
struct { struct {
/** sha_mode : R/W; bitpos: [2:0]; default: 0; /** sha_mode : R/W; bitpos: [2:0]; default: 0;
* The work mode bits of SHA Calculator in ECDSA Accelerator. 1: SHA-224. 2: SHA-256. * Configures SHA algorithms for message hash.
* Others: invalid. * 1: SHA-224
* 2: SHA-256
* Others: invalid
*/ */
uint32_t sha_mode:3; uint32_t sha_mode:3;
uint32_t reserved_3:29; uint32_t reserved_3:29;
@@ -246,13 +266,13 @@ typedef union {
} ecdsa_sha_mode_reg_t; } ecdsa_sha_mode_reg_t;
/** Type of sha_start register /** Type of sha_start register
* ECDSA control SHA register * ECDSA SHA-control register (operation)
*/ */
typedef union { typedef union {
struct { struct {
/** sha_start : WT; bitpos: [0]; default: 0; /** sha_start : WT; bitpos: [0]; default: 0;
* Write 1 to start the first calculation of SHA Calculator in ECDSA Accelerator. This * Write 1 to start the first SHA operation in the ECDSA process. This bit will be
* bit will be self-cleared after configuration. * self-cleared after configuration.
*/ */
uint32_t sha_start:1; uint32_t sha_start:1;
uint32_t reserved_1:31; uint32_t reserved_1:31;
@@ -261,13 +281,13 @@ typedef union {
} ecdsa_sha_start_reg_t; } ecdsa_sha_start_reg_t;
/** Type of sha_continue register /** Type of sha_continue register
* ECDSA control SHA register * ECDSA SHA-control register (operation)
*/ */
typedef union { typedef union {
struct { struct {
/** sha_continue : WT; bitpos: [0]; default: 0; /** sha_continue : WT; bitpos: [0]; default: 0;
* Write 1 to start the latter calculation of SHA Calculator in ECDSA Accelerator. This * Write 1 to start the latter SHA operation in the ECDSA process. This bit will be
* bit will be self-cleared after configuration. * self-cleared after configuration.
*/ */
uint32_t sha_continue:1; uint32_t sha_continue:1;
uint32_t reserved_1:31; uint32_t reserved_1:31;
@@ -276,13 +296,14 @@ typedef union {
} ecdsa_sha_continue_reg_t; } ecdsa_sha_continue_reg_t;
/** Type of sha_busy register /** Type of sha_busy register
* ECDSA status register * ECDSA SHA-control status register
*/ */
typedef union { typedef union {
struct { struct {
/** sha_busy : RO; bitpos: [0]; default: 0; /** sha_busy : RO; bitpos: [0]; default: 0;
* The busy status bit of SHA Calculator in ECDSA Accelerator. 1:SHA is in * Represents the working status of the SHA accelerator in the ECDSA process.
* calculation. 0: SHA is idle. * 0: IDLE
* 1: BUSY
*/ */
uint32_t sha_busy:1; uint32_t sha_busy:1;
uint32_t reserved_1:31; uint32_t reserved_1:31;
@@ -291,14 +312,14 @@ typedef union {
} ecdsa_sha_busy_reg_t; } ecdsa_sha_busy_reg_t;
/** Group: Version register */ /** Group: Version Register */
/** Type of date register /** Type of date register
* Version control register * Version control register
*/ */
typedef union { typedef union {
struct { struct {
/** date : R/W; bitpos: [27:0]; default: 37761312; /** date : R/W; bitpos: [27:0]; default: 37761312;
* ECDSA version control register * The ECDSA version control register.
*/ */
uint32_t date:28; uint32_t date:28;
uint32_t reserved_28:4; uint32_t reserved_28:4;

68
components/soc/esp32p4/register/soc/dma_pms_reg.h
View File

@@ -1,5 +1,5 @@
/** /**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -1555,65 +1555,35 @@ extern "C" {
#define PMS_DMA_L2MEM_MON_W_PMS_V 0xFFFFFFFFU #define PMS_DMA_L2MEM_MON_W_PMS_V 0xFFFFFFFFU
#define PMS_DMA_L2MEM_MON_W_PMS_S 0 #define PMS_DMA_L2MEM_MON_W_PMS_S 0
/** PMS_DMA_TCM_MON_PMS_R_REG register /** PMS_DMA_SPM_MON_PMS_R_REG register
* TCM Monitor read permission control register * SPM Monitor read permission control register
*/ */
#define PMS_DMA_TCM_MON_PMS_R_REG (DR_REG_DMA_PMS_BASE + 0x1e4) #define PMS_DMA_SPM_MON_PMS_R_REG (DR_REG_DMA_PMS_BASE + 0x1e4)
/** PMS_DMA_TCM_MON_R_PMS : R/W; bitpos: [31:0]; default: 4294967295; /** PMS_DMA_SPM_MON_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
* Configures read permission for TCM MON. Each bit corresponds to a region. Bit 0 * Configures read permission for SPM MON. Each bit corresponds to a region. Bit 0
* corresponds to region0, and so on. * corresponds to region0, and so on.
* 0: Disable read permission. * 0: Disable read permission.
* 1: Enable read permission. * 1: Enable read permission.
*/ */
#define PMS_DMA_TCM_MON_R_PMS 0xFFFFFFFFU #define PMS_DMA_SPM_MON_R_PMS 0xFFFFFFFFU
#define PMS_DMA_TCM_MON_R_PMS_M (PMS_DMA_TCM_MON_R_PMS_V << PMS_DMA_TCM_MON_R_PMS_S) #define PMS_DMA_SPM_MON_R_PMS_M (PMS_DMA_SPM_MON_R_PMS_V << PMS_DMA_SPM_MON_R_PMS_S)
#define PMS_DMA_TCM_MON_R_PMS_V 0xFFFFFFFFU #define PMS_DMA_SPM_MON_R_PMS_V 0xFFFFFFFFU
#define PMS_DMA_TCM_MON_R_PMS_S 0 #define PMS_DMA_SPM_MON_R_PMS_S 0
/** PMS_DMA_TCM_MON_PMS_W_REG register /** PMS_DMA_SPM_MON_PMS_W_REG register
* TCM Monitor write permission control register * SPM Monitor write permission control register
*/ */
#define PMS_DMA_TCM_MON_PMS_W_REG (DR_REG_DMA_PMS_BASE + 0x1e8) #define PMS_DMA_SPM_MON_PMS_W_REG (DR_REG_DMA_PMS_BASE + 0x1e8)
/** PMS_DMA_TCM_MON_W_PMS : R/W; bitpos: [31:0]; default: 4294967295; /** PMS_DMA_SPM_MON_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
* Configures write permission for TCM monitor to access 32 address ranges. Bit 0 * Configures write permission for SPM monitor to access 32 address ranges. Bit 0
* corresponds to region0, and so on. * corresponds to region0, and so on.
* 0: Disable write permission. * 0: Disable write permission.
* 1: Enable write permission. * 1: Enable write permission.
*/ */
#define PMS_DMA_TCM_MON_W_PMS 0xFFFFFFFFU #define PMS_DMA_SPM_MON_W_PMS 0xFFFFFFFFU
#define PMS_DMA_TCM_MON_W_PMS_M (PMS_DMA_TCM_MON_W_PMS_V << PMS_DMA_TCM_MON_W_PMS_S) #define PMS_DMA_SPM_MON_W_PMS_M (PMS_DMA_SPM_MON_W_PMS_V << PMS_DMA_SPM_MON_W_PMS_S)
#define PMS_DMA_TCM_MON_W_PMS_V 0xFFFFFFFFU #define PMS_DMA_SPM_MON_W_PMS_V 0xFFFFFFFFU
#define PMS_DMA_TCM_MON_W_PMS_S 0 #define PMS_DMA_SPM_MON_W_PMS_S 0
/** PMS_DMA_REGDMA_PMS_R_REG register
* REGDMA read permission control register
*/
#define PMS_DMA_REGDMA_PMS_R_REG (DR_REG_DMA_PMS_BASE + 0x1ec)
/** PMS_DMA_REGDMA_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
* Configures read permission for REGDMA. Each bit corresponds to a region. Bit 0
* corresponds to region0, and so on.
* 0: Disable read permission.
* 1: Enable read permission.
*/
#define PMS_DMA_REGDMA_R_PMS 0xFFFFFFFFU
#define PMS_DMA_REGDMA_R_PMS_M (PMS_DMA_REGDMA_R_PMS_V << PMS_DMA_REGDMA_R_PMS_S)
#define PMS_DMA_REGDMA_R_PMS_V 0xFFFFFFFFU
#define PMS_DMA_REGDMA_R_PMS_S 0
/** PMS_DMA_REGDMA_PMS_W_REG register
* REGDMA write permission control register
*/
#define PMS_DMA_REGDMA_PMS_W_REG (DR_REG_DMA_PMS_BASE + 0x1f0)
/** PMS_DMA_REGDMA_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
* Configures write permission for REGDMA. Each bit corresponds to a region. Bit 0
* corresponds to region0, and so on.
* 0: Disable write permission.
* 1: Enable write permission.
*/
#define PMS_DMA_REGDMA_W_PMS 0xFFFFFFFFU
#define PMS_DMA_REGDMA_W_PMS_M (PMS_DMA_REGDMA_W_PMS_V << PMS_DMA_REGDMA_W_PMS_S)
#define PMS_DMA_REGDMA_W_PMS_V 0xFFFFFFFFU
#define PMS_DMA_REGDMA_W_PMS_S 0
/** PMS_DMA_H264_PMS_R_REG register /** PMS_DMA_H264_PMS_R_REG register
* H264 DMA read permission control register * H264 DMA read permission control register

66
components/soc/esp32p4/register/soc/dma_pms_struct.h
View File

@@ -1,5 +1,5 @@
/** /**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -778,69 +778,37 @@ typedef union {
uint32_t val; uint32_t val;
} pms_dma_l2mem_mon_pms_w_reg_t; } pms_dma_l2mem_mon_pms_w_reg_t;
/** Type of tcm_mon_pms_r register /** Type of spm_mon_pms_r register
* TCM Monitor read permission control register * SPM Monitor read permission control register
*/ */
typedef union { typedef union {
struct { struct {
/** tcm_mon_r_pms : R/W; bitpos: [31:0]; default: 4294967295; /** spm_mon_r_pms : R/W; bitpos: [31:0]; default: 4294967295;
* Configures read permission for TCM MON. Each bit corresponds to a region. Bit 0 * Configures read permission for SPM MON. Each bit corresponds to a region. Bit 0
* corresponds to region0, and so on. * corresponds to region0, and so on.
* 0: Disable read permission. * 0: Disable read permission.
* 1: Enable read permission. * 1: Enable read permission.
*/ */
uint32_t tcm_mon_r_pms:32; uint32_t spm_mon_r_pms:32;
}; };
uint32_t val; uint32_t val;
} pms_dma_tcm_mon_pms_r_reg_t; } pms_dma_spm_mon_pms_r_reg_t;
/** Type of tcm_mon_pms_w register /** Type of spm_mon_pms_w register
* TCM Monitor write permission control register * SPM Monitor write permission control register
*/ */
typedef union { typedef union {
struct { struct {
/** tcm_mon_w_pms : R/W; bitpos: [31:0]; default: 4294967295; /** spm_mon_w_pms : R/W; bitpos: [31:0]; default: 4294967295;
* Configures write permission for TCM monitor to access 32 address ranges. Bit 0 * Configures write permission for SPM monitor to access 32 address ranges. Bit 0
* corresponds to region0, and so on. * corresponds to region0, and so on.
* 0: Disable write permission. * 0: Disable write permission.
* 1: Enable write permission. * 1: Enable write permission.
*/ */
uint32_t tcm_mon_w_pms:32; uint32_t spm_mon_w_pms:32;
}; };
uint32_t val; uint32_t val;
} pms_dma_tcm_mon_pms_w_reg_t; } pms_dma_spm_mon_pms_w_reg_t;
/** Type of regdma_pms_r register
* REGDMA read permission control register
*/
typedef union {
struct {
/** regdma_r_pms : R/W; bitpos: [31:0]; default: 4294967295;
* Configures read permission for REGDMA. Each bit corresponds to a region. Bit 0
* corresponds to region0, and so on.
* 0: Disable read permission.
* 1: Enable read permission.
*/
uint32_t regdma_r_pms:32;
};
uint32_t val;
} pms_dma_regdma_pms_r_reg_t;
/** Type of regdma_pms_w register
* REGDMA write permission control register
*/
typedef union {
struct {
/** regdma_w_pms : R/W; bitpos: [31:0]; default: 4294967295;
* Configures write permission for REGDMA. Each bit corresponds to a region. Bit 0
* corresponds to region0, and so on.
* 0: Disable write permission.
* 1: Enable write permission.
*/
uint32_t regdma_w_pms:32;
};
uint32_t val;
} pms_dma_regdma_pms_w_reg_t;
/** Type of h264_pms_r register /** Type of h264_pms_r register
* H264 DMA read permission control register * H264 DMA read permission control register
@@ -1121,11 +1089,9 @@ typedef struct {
volatile pms_dma_trace1_pms_w_reg_t trace1_pms_w; volatile pms_dma_trace1_pms_w_reg_t trace1_pms_w;
volatile pms_dma_l2mem_mon_pms_r_reg_t l2mem_mon_pms_r; volatile pms_dma_l2mem_mon_pms_r_reg_t l2mem_mon_pms_r;
volatile pms_dma_l2mem_mon_pms_w_reg_t l2mem_mon_pms_w; volatile pms_dma_l2mem_mon_pms_w_reg_t l2mem_mon_pms_w;
volatile pms_dma_tcm_mon_pms_r_reg_t tcm_mon_pms_r; volatile pms_dma_spm_mon_pms_r_reg_t spm_mon_pms_r;
volatile pms_dma_tcm_mon_pms_w_reg_t tcm_mon_pms_w; volatile pms_dma_spm_mon_pms_w_reg_t spm_mon_pms_w;
volatile pms_dma_regdma_pms_r_reg_t regdma_pms_r; uint32_t reserved_1ec[4];
volatile pms_dma_regdma_pms_w_reg_t regdma_pms_w;
uint32_t reserved_1f4[2];
volatile pms_dma_h264_pms_r_reg_t h264_pms_r; volatile pms_dma_h264_pms_r_reg_t h264_pms_r;
volatile pms_dma_h264_pms_w_reg_t h264_pms_w; volatile pms_dma_h264_pms_w_reg_t h264_pms_w;
volatile pms_dma_dma2d_ppa_pms_r_reg_t dma2d_ppa_pms_r; volatile pms_dma_dma2d_ppa_pms_r_reg_t dma2d_ppa_pms_r;

103
components/soc/esp32p4/register/soc/hp_peri_pms_reg.h
View File

@@ -1,5 +1,5 @@
/** /**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -118,15 +118,15 @@ extern "C" {
#define PMS_CORE0_MM_L2MEM_MON_ALLOW_M (PMS_CORE0_MM_L2MEM_MON_ALLOW_V << PMS_CORE0_MM_L2MEM_MON_ALLOW_S) #define PMS_CORE0_MM_L2MEM_MON_ALLOW_M (PMS_CORE0_MM_L2MEM_MON_ALLOW_V << PMS_CORE0_MM_L2MEM_MON_ALLOW_S)
#define PMS_CORE0_MM_L2MEM_MON_ALLOW_V 0x00000001U #define PMS_CORE0_MM_L2MEM_MON_ALLOW_V 0x00000001U
#define PMS_CORE0_MM_L2MEM_MON_ALLOW_S 9 #define PMS_CORE0_MM_L2MEM_MON_ALLOW_S 9
/** PMS_CORE0_MM_TCM_MON_ALLOW : R/W; bitpos: [10]; default: 1; /** PMS_CORE0_MM_SPM_MON_ALLOW : R/W; bitpos: [10]; default: 1;
* Configures whether HP CPU0 in machine mode has permission to access TCM monitor. * Configures whether HP CPU0 in machine mode has permission to access SPM monitor.
* 0: Not allowed * 0: Not allowed
* 1: Allowed * 1: Allowed
*/ */
#define PMS_CORE0_MM_TCM_MON_ALLOW (BIT(10)) #define PMS_CORE0_MM_SPM_MON_ALLOW (BIT(10))
#define PMS_CORE0_MM_TCM_MON_ALLOW_M (PMS_CORE0_MM_TCM_MON_ALLOW_V << PMS_CORE0_MM_TCM_MON_ALLOW_S) #define PMS_CORE0_MM_SPM_MON_ALLOW_M (PMS_CORE0_MM_SPM_MON_ALLOW_V << PMS_CORE0_MM_SPM_MON_ALLOW_S)
#define PMS_CORE0_MM_TCM_MON_ALLOW_V 0x00000001U #define PMS_CORE0_MM_SPM_MON_ALLOW_V 0x00000001U
#define PMS_CORE0_MM_TCM_MON_ALLOW_S 10 #define PMS_CORE0_MM_SPM_MON_ALLOW_S 10
/** PMS_CORE0_MM_CACHE_ALLOW : R/W; bitpos: [11]; default: 1; /** PMS_CORE0_MM_CACHE_ALLOW : R/W; bitpos: [11]; default: 1;
* Configures whether HP CPU0 in machine mode has permission to access cache. * Configures whether HP CPU0 in machine mode has permission to access cache.
* 0: Not allowed * 0: Not allowed
@@ -180,16 +180,6 @@ extern "C" {
#define PMS_CORE0_MM_HP_GDMA_ALLOW_M (PMS_CORE0_MM_HP_GDMA_ALLOW_V << PMS_CORE0_MM_HP_GDMA_ALLOW_S) #define PMS_CORE0_MM_HP_GDMA_ALLOW_M (PMS_CORE0_MM_HP_GDMA_ALLOW_V << PMS_CORE0_MM_HP_GDMA_ALLOW_S)
#define PMS_CORE0_MM_HP_GDMA_ALLOW_V 0x00000001U #define PMS_CORE0_MM_HP_GDMA_ALLOW_V 0x00000001U
#define PMS_CORE0_MM_HP_GDMA_ALLOW_S 3 #define PMS_CORE0_MM_HP_GDMA_ALLOW_S 3
/** PMS_CORE0_MM_HP_REGDMA_ALLOW : R/W; bitpos: [4]; default: 1;
* Configures whether HP CPU0 in machine mode has permission to access HP GDMA (DW
* GDMA).
* 0: Not allowed
* 1: Allow
*/
#define PMS_CORE0_MM_HP_REGDMA_ALLOW (BIT(4))
#define PMS_CORE0_MM_HP_REGDMA_ALLOW_M (PMS_CORE0_MM_HP_REGDMA_ALLOW_V << PMS_CORE0_MM_HP_REGDMA_ALLOW_S)
#define PMS_CORE0_MM_HP_REGDMA_ALLOW_V 0x00000001U
#define PMS_CORE0_MM_HP_REGDMA_ALLOW_S 4
/** PMS_CORE0_MM_HP_SDMMC_ALLOW : R/W; bitpos: [5]; default: 1; /** PMS_CORE0_MM_HP_SDMMC_ALLOW : R/W; bitpos: [5]; default: 1;
* Configures whether HP CPU0 in machine mode has permission to access HP SDMMC. * Configures whether HP CPU0 in machine mode has permission to access HP SDMMC.
* 0: Not allowed * 0: Not allowed
@@ -831,15 +821,15 @@ extern "C" {
#define PMS_CORE0_UM_L2MEM_MON_ALLOW_M (PMS_CORE0_UM_L2MEM_MON_ALLOW_V << PMS_CORE0_UM_L2MEM_MON_ALLOW_S) #define PMS_CORE0_UM_L2MEM_MON_ALLOW_M (PMS_CORE0_UM_L2MEM_MON_ALLOW_V << PMS_CORE0_UM_L2MEM_MON_ALLOW_S)
#define PMS_CORE0_UM_L2MEM_MON_ALLOW_V 0x00000001U #define PMS_CORE0_UM_L2MEM_MON_ALLOW_V 0x00000001U
#define PMS_CORE0_UM_L2MEM_MON_ALLOW_S 9 #define PMS_CORE0_UM_L2MEM_MON_ALLOW_S 9
/** PMS_CORE0_UM_TCM_MON_ALLOW : R/W; bitpos: [10]; default: 1; /** PMS_CORE0_UM_SPM_MON_ALLOW : R/W; bitpos: [10]; default: 1;
* Configures whether HP CPU0 in user mode has permission to access TCM monitor. * Configures whether HP CPU0 in user mode has permission to access SPM monitor.
* 0: Not allowed * 0: Not allowed
* 1: Allowed * 1: Allowed
*/ */
#define PMS_CORE0_UM_TCM_MON_ALLOW (BIT(10)) #define PMS_CORE0_UM_SPM_MON_ALLOW (BIT(10))
#define PMS_CORE0_UM_TCM_MON_ALLOW_M (PMS_CORE0_UM_TCM_MON_ALLOW_V << PMS_CORE0_UM_TCM_MON_ALLOW_S) #define PMS_CORE0_UM_SPM_MON_ALLOW_M (PMS_CORE0_UM_SPM_MON_ALLOW_V << PMS_CORE0_UM_SPM_MON_ALLOW_S)
#define PMS_CORE0_UM_TCM_MON_ALLOW_V 0x00000001U #define PMS_CORE0_UM_SPM_MON_ALLOW_V 0x00000001U
#define PMS_CORE0_UM_TCM_MON_ALLOW_S 10 #define PMS_CORE0_UM_SPM_MON_ALLOW_S 10
/** PMS_CORE0_UM_CACHE_ALLOW : R/W; bitpos: [11]; default: 1; /** PMS_CORE0_UM_CACHE_ALLOW : R/W; bitpos: [11]; default: 1;
* Configures whether HP CPU0 in user mode has permission to access cache. * Configures whether HP CPU0 in user mode has permission to access cache.
* 0: Not allowed * 0: Not allowed
@@ -895,15 +885,6 @@ extern "C" {
#define PMS_CORE0_UM_HP_GDMA_ALLOW_M (PMS_CORE0_UM_HP_GDMA_ALLOW_V << PMS_CORE0_UM_HP_GDMA_ALLOW_S) #define PMS_CORE0_UM_HP_GDMA_ALLOW_M (PMS_CORE0_UM_HP_GDMA_ALLOW_V << PMS_CORE0_UM_HP_GDMA_ALLOW_S)
#define PMS_CORE0_UM_HP_GDMA_ALLOW_V 0x00000001U #define PMS_CORE0_UM_HP_GDMA_ALLOW_V 0x00000001U
#define PMS_CORE0_UM_HP_GDMA_ALLOW_S 3 #define PMS_CORE0_UM_HP_GDMA_ALLOW_S 3
/** PMS_CORE0_UM_HP_REGDMA_ALLOW : R/W; bitpos: [4]; default: 1;
* Configures whether HP CPU0 in user mode has permission to access HP regdma.
* 0: Not allowed
* 1: Allow
*/
#define PMS_CORE0_UM_HP_REGDMA_ALLOW (BIT(4))
#define PMS_CORE0_UM_HP_REGDMA_ALLOW_M (PMS_CORE0_UM_HP_REGDMA_ALLOW_V << PMS_CORE0_UM_HP_REGDMA_ALLOW_S)
#define PMS_CORE0_UM_HP_REGDMA_ALLOW_V 0x00000001U
#define PMS_CORE0_UM_HP_REGDMA_ALLOW_S 4
/** PMS_CORE0_UM_HP_SDMMC_ALLOW : R/W; bitpos: [5]; default: 1; /** PMS_CORE0_UM_HP_SDMMC_ALLOW : R/W; bitpos: [5]; default: 1;
* Configures whether HP CPU0 in user mode has permission to access HP SDMMC. * Configures whether HP CPU0 in user mode has permission to access HP SDMMC.
* 0: Not allowed * 0: Not allowed
@@ -1536,15 +1517,15 @@ extern "C" {
#define PMS_CORE1_MM_L2MEM_MON_ALLOW_M (PMS_CORE1_MM_L2MEM_MON_ALLOW_V << PMS_CORE1_MM_L2MEM_MON_ALLOW_S) #define PMS_CORE1_MM_L2MEM_MON_ALLOW_M (PMS_CORE1_MM_L2MEM_MON_ALLOW_V << PMS_CORE1_MM_L2MEM_MON_ALLOW_S)
#define PMS_CORE1_MM_L2MEM_MON_ALLOW_V 0x00000001U #define PMS_CORE1_MM_L2MEM_MON_ALLOW_V 0x00000001U
#define PMS_CORE1_MM_L2MEM_MON_ALLOW_S 9 #define PMS_CORE1_MM_L2MEM_MON_ALLOW_S 9
/** PMS_CORE1_MM_TCM_MON_ALLOW : R/W; bitpos: [10]; default: 1; /** PMS_CORE1_MM_SPM_MON_ALLOW : R/W; bitpos: [10]; default: 1;
* Configures whether HP CPU1 in machine mode has permission to access TCM monitor. * Configures whether HP CPU1 in machine mode has permission to access SPM monitor.
* 0: Not allowed * 0: Not allowed
* 1: Allowed * 1: Allowed
*/ */
#define PMS_CORE1_MM_TCM_MON_ALLOW (BIT(10)) #define PMS_CORE1_MM_SPM_MON_ALLOW (BIT(10))
#define PMS_CORE1_MM_TCM_MON_ALLOW_M (PMS_CORE1_MM_TCM_MON_ALLOW_V << PMS_CORE1_MM_TCM_MON_ALLOW_S) #define PMS_CORE1_MM_SPM_MON_ALLOW_M (PMS_CORE1_MM_SPM_MON_ALLOW_V << PMS_CORE1_MM_SPM_MON_ALLOW_S)
#define PMS_CORE1_MM_TCM_MON_ALLOW_V 0x00000001U #define PMS_CORE1_MM_SPM_MON_ALLOW_V 0x00000001U
#define PMS_CORE1_MM_TCM_MON_ALLOW_S 10 #define PMS_CORE1_MM_SPM_MON_ALLOW_S 10
/** PMS_CORE1_MM_CACHE_ALLOW : R/W; bitpos: [11]; default: 1; /** PMS_CORE1_MM_CACHE_ALLOW : R/W; bitpos: [11]; default: 1;
* Configures whether HP CPU1 in machine mode has permission to access cache. * Configures whether HP CPU1 in machine mode has permission to access cache.
* 0: Not allowed * 0: Not allowed
@@ -1598,16 +1579,6 @@ extern "C" {
#define PMS_CORE1_MM_HP_GDMA_ALLOW_M (PMS_CORE1_MM_HP_GDMA_ALLOW_V << PMS_CORE1_MM_HP_GDMA_ALLOW_S) #define PMS_CORE1_MM_HP_GDMA_ALLOW_M (PMS_CORE1_MM_HP_GDMA_ALLOW_V << PMS_CORE1_MM_HP_GDMA_ALLOW_S)
#define PMS_CORE1_MM_HP_GDMA_ALLOW_V 0x00000001U #define PMS_CORE1_MM_HP_GDMA_ALLOW_V 0x00000001U
#define PMS_CORE1_MM_HP_GDMA_ALLOW_S 3 #define PMS_CORE1_MM_HP_GDMA_ALLOW_S 3
/** PMS_CORE1_MM_HP_REGDMA_ALLOW : R/W; bitpos: [4]; default: 1;
* Configures whether HP CPU1 in machine mode has permission to access HP GDMA (DW
* GDMA).
* 0: Not allowed
* 1: Allow
*/
#define PMS_CORE1_MM_HP_REGDMA_ALLOW (BIT(4))
#define PMS_CORE1_MM_HP_REGDMA_ALLOW_M (PMS_CORE1_MM_HP_REGDMA_ALLOW_V << PMS_CORE1_MM_HP_REGDMA_ALLOW_S)
#define PMS_CORE1_MM_HP_REGDMA_ALLOW_V 0x00000001U
#define PMS_CORE1_MM_HP_REGDMA_ALLOW_S 4
/** PMS_CORE1_MM_HP_SDMMC_ALLOW : R/W; bitpos: [5]; default: 1; /** PMS_CORE1_MM_HP_SDMMC_ALLOW : R/W; bitpos: [5]; default: 1;
* Configures whether HP CPU1 in machine mode has permission to access HP SDMMC. * Configures whether HP CPU1 in machine mode has permission to access HP SDMMC.
* 0: Not allowed * 0: Not allowed
@@ -2249,15 +2220,15 @@ extern "C" {
#define PMS_CORE1_UM_L2MEM_MON_ALLOW_M (PMS_CORE1_UM_L2MEM_MON_ALLOW_V << PMS_CORE1_UM_L2MEM_MON_ALLOW_S) #define PMS_CORE1_UM_L2MEM_MON_ALLOW_M (PMS_CORE1_UM_L2MEM_MON_ALLOW_V << PMS_CORE1_UM_L2MEM_MON_ALLOW_S)
#define PMS_CORE1_UM_L2MEM_MON_ALLOW_V 0x00000001U #define PMS_CORE1_UM_L2MEM_MON_ALLOW_V 0x00000001U
#define PMS_CORE1_UM_L2MEM_MON_ALLOW_S 9 #define PMS_CORE1_UM_L2MEM_MON_ALLOW_S 9
/** PMS_CORE1_UM_TCM_MON_ALLOW : R/W; bitpos: [10]; default: 1; /** PMS_CORE1_UM_SPM_MON_ALLOW : R/W; bitpos: [10]; default: 1;
* Configures whether HP CPU1 in user mode has permission to access TCM monitor. * Configures whether HP CPU1 in user mode has permission to access SPM monitor.
* 0: Not allowed * 0: Not allowed
* 1: Allowed * 1: Allowed
*/ */
#define PMS_CORE1_UM_TCM_MON_ALLOW (BIT(10)) #define PMS_CORE1_UM_SPM_MON_ALLOW (BIT(10))
#define PMS_CORE1_UM_TCM_MON_ALLOW_M (PMS_CORE1_UM_TCM_MON_ALLOW_V << PMS_CORE1_UM_TCM_MON_ALLOW_S) #define PMS_CORE1_UM_SPM_MON_ALLOW_M (PMS_CORE1_UM_SPM_MON_ALLOW_V << PMS_CORE1_UM_SPM_MON_ALLOW_S)
#define PMS_CORE1_UM_TCM_MON_ALLOW_V 0x00000001U #define PMS_CORE1_UM_SPM_MON_ALLOW_V 0x00000001U
#define PMS_CORE1_UM_TCM_MON_ALLOW_S 10 #define PMS_CORE1_UM_SPM_MON_ALLOW_S 10
/** PMS_CORE1_UM_CACHE_ALLOW : R/W; bitpos: [11]; default: 1; /** PMS_CORE1_UM_CACHE_ALLOW : R/W; bitpos: [11]; default: 1;
* Configures whether HP CPU1 in user mode has permission to access cache. * Configures whether HP CPU1 in user mode has permission to access cache.
* 0: Not allowed * 0: Not allowed
@@ -2313,15 +2284,6 @@ extern "C" {
#define PMS_CORE1_UM_HP_GDMA_ALLOW_M (PMS_CORE1_UM_HP_GDMA_ALLOW_V << PMS_CORE1_UM_HP_GDMA_ALLOW_S) #define PMS_CORE1_UM_HP_GDMA_ALLOW_M (PMS_CORE1_UM_HP_GDMA_ALLOW_V << PMS_CORE1_UM_HP_GDMA_ALLOW_S)
#define PMS_CORE1_UM_HP_GDMA_ALLOW_V 0x00000001U #define PMS_CORE1_UM_HP_GDMA_ALLOW_V 0x00000001U
#define PMS_CORE1_UM_HP_GDMA_ALLOW_S 3 #define PMS_CORE1_UM_HP_GDMA_ALLOW_S 3
/** PMS_CORE1_UM_HP_REGDMA_ALLOW : R/W; bitpos: [4]; default: 1;
* Configures whether HP CPU1 in user mode has permission to access HP regdma.
* 0: Not allowed
* 1: Allow
*/
#define PMS_CORE1_UM_HP_REGDMA_ALLOW (BIT(4))
#define PMS_CORE1_UM_HP_REGDMA_ALLOW_M (PMS_CORE1_UM_HP_REGDMA_ALLOW_V << PMS_CORE1_UM_HP_REGDMA_ALLOW_S)
#define PMS_CORE1_UM_HP_REGDMA_ALLOW_V 0x00000001U
#define PMS_CORE1_UM_HP_REGDMA_ALLOW_S 4
/** PMS_CORE1_UM_HP_SDMMC_ALLOW : R/W; bitpos: [5]; default: 1; /** PMS_CORE1_UM_HP_SDMMC_ALLOW : R/W; bitpos: [5]; default: 1;
* Configures whether HP CPU1 in user mode has permission to access HP SDMMC. * Configures whether HP CPU1 in user mode has permission to access HP SDMMC.
* 0: Not allowed * 0: Not allowed
@@ -2873,21 +2835,6 @@ extern "C" {
#define PMS_CORE1_UM_HP_CLKRST_ALLOW_V 0x00000001U #define PMS_CORE1_UM_HP_CLKRST_ALLOW_V 0x00000001U
#define PMS_CORE1_UM_HP_CLKRST_ALLOW_S 4 #define PMS_CORE1_UM_HP_CLKRST_ALLOW_S 4
/** PMS_REGDMA_PERI_PMS_REG register
* Permission register for REGDMA
*/
#define PMS_REGDMA_PERI_PMS_REG (DR_REG_HP_PERI_PMS_BASE + 0x48)
/** PMS_REGDMA_PERI_ALLOW : R/W; bitpos: [0]; default: 1;
* Configures whether REGDMA has permission to access all HP peripheral (including CPU
* peripherals).
* 0: Not allowed
* 1: Allow
*/
#define PMS_REGDMA_PERI_ALLOW (BIT(0))
#define PMS_REGDMA_PERI_ALLOW_M (PMS_REGDMA_PERI_ALLOW_V << PMS_REGDMA_PERI_ALLOW_S)
#define PMS_REGDMA_PERI_ALLOW_V 0x00000001U
#define PMS_REGDMA_PERI_ALLOW_S 0
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif

51
components/soc/esp32p4/register/soc/hp_peri_pms_struct.h
View File

@@ -1,5 +1,5 @@
/** /**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -103,12 +103,12 @@ typedef union {
* 1: Allowed * 1: Allowed
*/ */
uint32_t coren_mm_l2mem_mon_allow:1; uint32_t coren_mm_l2mem_mon_allow:1;
/** coren_mm_tcm_mon_allow : R/W; bitpos: [10]; default: 1; /** coren_mm_spm_mon_allow : R/W; bitpos: [10]; default: 1;
* Configures whether HP CPUn in machine mode has permission to access TCM monitor. * Configures whether HP CPUn in machine mode has permission to access SPM monitor.
* 0: Not allowed * 0: Not allowed
* 1: Allowed * 1: Allowed
*/ */
uint32_t coren_mm_tcm_mon_allow:1; uint32_t coren_mm_spm_mon_allow:1;
/** coren_mm_cache_allow : R/W; bitpos: [11]; default: 1; /** coren_mm_cache_allow : R/W; bitpos: [11]; default: 1;
* Configures whether HP CPUn in machine mode has permission to access cache. * Configures whether HP CPUn in machine mode has permission to access cache.
* 0: Not allowed * 0: Not allowed
@@ -152,13 +152,7 @@ typedef union {
* 1: Allowed * 1: Allowed
*/ */
uint32_t coren_mm_hp_gdma_allow:1; uint32_t coren_mm_hp_gdma_allow:1;
/** coren_mm_hp_regdma_allow : R/W; bitpos: [4]; default: 1; uint32_t reserved_4:1;
* Configures whether HP CPUn in machine mode has permission to access HP GDMA (DW
* GDMA).
* 0: Not allowed
* 1: Allow
*/
uint32_t coren_mm_hp_regdma_allow:1;
/** coren_mm_hp_sdmmc_allow : R/W; bitpos: [5]; default: 1; /** coren_mm_hp_sdmmc_allow : R/W; bitpos: [5]; default: 1;
* Configures whether HP CPUn in machine mode has permission to access HP SDMMC. * Configures whether HP CPUn in machine mode has permission to access HP SDMMC.
* 0: Not allowed * 0: Not allowed
@@ -616,12 +610,12 @@ typedef union {
* 1: Allowed * 1: Allowed
*/ */
uint32_t coren_um_l2mem_mon_allow:1; uint32_t coren_um_l2mem_mon_allow:1;
/** coren_um_tcm_mon_allow : R/W; bitpos: [10]; default: 1; /** coren_um_spm_mon_allow : R/W; bitpos: [10]; default: 1;
* Configures whether HP CPUn in user mode has permission to access TCM monitor. * Configures whether HP CPUn in user mode has permission to access SPM monitor.
* 0: Not allowed * 0: Not allowed
* 1: Allowed * 1: Allowed
*/ */
uint32_t coren_um_tcm_mon_allow:1; uint32_t coren_um_spm_mon_allow:1;
/** coren_um_cache_allow : R/W; bitpos: [11]; default: 1; /** coren_um_cache_allow : R/W; bitpos: [11]; default: 1;
* Configures whether HP CPUn in user mode has permission to access cache. * Configures whether HP CPUn in user mode has permission to access cache.
* 0: Not allowed * 0: Not allowed
@@ -667,12 +661,7 @@ typedef union {
* 1: Allowed * 1: Allowed
*/ */
uint32_t coren_um_hp_gdma_allow:1; uint32_t coren_um_hp_gdma_allow:1;
/** coren_um_hp_regdma_allow : R/W; bitpos: [4]; default: 1; uint32_t reserved_4:1;
* Configures whether HP CPUn in user mode has permission to access HP regdma.
* 0: Not allowed
* 1: Allow
*/
uint32_t coren_um_hp_regdma_allow:1;
/** coren_um_hp_sdmmc_allow : R/W; bitpos: [5]; default: 1; /** coren_um_hp_sdmmc_allow : R/W; bitpos: [5]; default: 1;
* Configures whether HP CPUn in user mode has permission to access HP SDMMC. * Configures whether HP CPUn in user mode has permission to access HP SDMMC.
* 0: Not allowed * 0: Not allowed
@@ -1063,25 +1052,6 @@ typedef union {
} pms_coren_um_hp_peri_pms_reg3_reg_t; } pms_coren_um_hp_peri_pms_reg3_reg_t;
/** Group: TEE Peripheral Permission Control Registers */
/** Type of regdma_peri_pms register
* Permission register for REGDMA
*/
typedef union {
struct {
/** regdma_peri_allow : R/W; bitpos: [0]; default: 1;
* Configures whether REGDMA has permission to access all HP peripheral (including CPU
* peripherals).
* 0: Not allowed
* 1: Allow
*/
uint32_t regdma_peri_allow:1;
uint32_t reserved_1:31;
};
uint32_t val;
} pms_regdma_peri_pms_reg_t;
typedef struct { typedef struct {
volatile pms_hp_peri_pms_date_reg_t hp_peri_pms_date; volatile pms_hp_peri_pms_date_reg_t hp_peri_pms_date;
volatile pms_hp_peri_pms_clk_en_reg_t hp_peri_pms_clk_en; volatile pms_hp_peri_pms_clk_en_reg_t hp_peri_pms_clk_en;
@@ -1101,13 +1071,12 @@ typedef struct {
volatile pms_coren_um_hp_peri_pms_reg1_reg_t core1_um_hp_peri_pms_reg1; volatile pms_coren_um_hp_peri_pms_reg1_reg_t core1_um_hp_peri_pms_reg1;
volatile pms_coren_um_hp_peri_pms_reg2_reg_t core1_um_hp_peri_pms_reg2; volatile pms_coren_um_hp_peri_pms_reg2_reg_t core1_um_hp_peri_pms_reg2;
volatile pms_coren_um_hp_peri_pms_reg3_reg_t core1_um_hp_peri_pms_reg3; volatile pms_coren_um_hp_peri_pms_reg3_reg_t core1_um_hp_peri_pms_reg3;
volatile pms_regdma_peri_pms_reg_t regdma_peri_pms;
} hp_peri_pms_dev_t; } hp_peri_pms_dev_t;
extern hp_peri_pms_dev_t HP_PERI_PMS; extern hp_peri_pms_dev_t HP_PERI_PMS;
#ifndef __cplusplus #ifndef __cplusplus
_Static_assert(sizeof(hp_peri_pms_dev_t) == 0x4c, "Invalid size of hp_peri_pms_dev_t structure"); _Static_assert(sizeof(hp_peri_pms_dev_t) == 0x48, "Invalid size of hp_peri_pms_dev_t structure");
#endif #endif
#ifdef __cplusplus #ifdef __cplusplus

24
components/soc/esp32p4/register/soc/lp2hp_peri_pms_reg.h
View File

@@ -1,5 +1,5 @@
/** /**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -119,15 +119,15 @@ extern "C" {
#define PMS_LP_MM_L2MEM_MON_ALLOW_M (PMS_LP_MM_L2MEM_MON_ALLOW_V << PMS_LP_MM_L2MEM_MON_ALLOW_S) #define PMS_LP_MM_L2MEM_MON_ALLOW_M (PMS_LP_MM_L2MEM_MON_ALLOW_V << PMS_LP_MM_L2MEM_MON_ALLOW_S)
#define PMS_LP_MM_L2MEM_MON_ALLOW_V 0x00000001U #define PMS_LP_MM_L2MEM_MON_ALLOW_V 0x00000001U
#define PMS_LP_MM_L2MEM_MON_ALLOW_S 9 #define PMS_LP_MM_L2MEM_MON_ALLOW_S 9
/** PMS_LP_MM_TCM_MON_ALLOW : R/W; bitpos: [10]; default: 1; /** PMS_LP_MM_SPM_MON_ALLOW : R/W; bitpos: [10]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access TCM monitor. * Configures whether the LP CPU in machine mode has permission to access SPM monitor.
* 0: Not allowed * 0: Not allowed
* 1: Allowed * 1: Allowed
*/ */
#define PMS_LP_MM_TCM_MON_ALLOW (BIT(10)) #define PMS_LP_MM_SPM_MON_ALLOW (BIT(10))
#define PMS_LP_MM_TCM_MON_ALLOW_M (PMS_LP_MM_TCM_MON_ALLOW_V << PMS_LP_MM_TCM_MON_ALLOW_S) #define PMS_LP_MM_SPM_MON_ALLOW_M (PMS_LP_MM_SPM_MON_ALLOW_V << PMS_LP_MM_SPM_MON_ALLOW_S)
#define PMS_LP_MM_TCM_MON_ALLOW_V 0x00000001U #define PMS_LP_MM_SPM_MON_ALLOW_V 0x00000001U
#define PMS_LP_MM_TCM_MON_ALLOW_S 10 #define PMS_LP_MM_SPM_MON_ALLOW_S 10
/** PMS_LP_MM_CACHE_ALLOW : R/W; bitpos: [11]; default: 1; /** PMS_LP_MM_CACHE_ALLOW : R/W; bitpos: [11]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access cache. * Configures whether the LP CPU in machine mode has permission to access cache.
* 0: Not allowed * 0: Not allowed
@@ -181,16 +181,6 @@ extern "C" {
#define PMS_LP_MM_HP_GDMA_ALLOW_M (PMS_LP_MM_HP_GDMA_ALLOW_V << PMS_LP_MM_HP_GDMA_ALLOW_S) #define PMS_LP_MM_HP_GDMA_ALLOW_M (PMS_LP_MM_HP_GDMA_ALLOW_V << PMS_LP_MM_HP_GDMA_ALLOW_S)
#define PMS_LP_MM_HP_GDMA_ALLOW_V 0x00000001U #define PMS_LP_MM_HP_GDMA_ALLOW_V 0x00000001U
#define PMS_LP_MM_HP_GDMA_ALLOW_S 3 #define PMS_LP_MM_HP_GDMA_ALLOW_S 3
/** PMS_LP_MM_HP_REGDMA_ALLOW : R/W; bitpos: [4]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP GDMA (DW
* GDMA).
* 0: Not allowed
* 1: Allow
*/
#define PMS_LP_MM_HP_REGDMA_ALLOW (BIT(4))
#define PMS_LP_MM_HP_REGDMA_ALLOW_M (PMS_LP_MM_HP_REGDMA_ALLOW_V << PMS_LP_MM_HP_REGDMA_ALLOW_S)
#define PMS_LP_MM_HP_REGDMA_ALLOW_V 0x00000001U
#define PMS_LP_MM_HP_REGDMA_ALLOW_S 4
/** PMS_LP_MM_HP_SDMMC_ALLOW : R/W; bitpos: [5]; default: 1; /** PMS_LP_MM_HP_SDMMC_ALLOW : R/W; bitpos: [5]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP SDMMC. * Configures whether the LP CPU in machine mode has permission to access HP SDMMC.
* 0: Not allowed * 0: Not allowed

16
components/soc/esp32p4/register/soc/lp2hp_peri_pms_struct.h
View File

@@ -1,5 +1,5 @@
/** /**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -104,12 +104,12 @@ typedef union {
* 1: Allowed * 1: Allowed
*/ */
uint32_t lp_mm_l2mem_mon_allow:1; uint32_t lp_mm_l2mem_mon_allow:1;
/** lp_mm_tcm_mon_allow : R/W; bitpos: [10]; default: 1; /** lp_mm_spm_mon_allow : R/W; bitpos: [10]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access TCM monitor. * Configures whether the LP CPU in machine mode has permission to access SPM monitor.
* 0: Not allowed * 0: Not allowed
* 1: Allowed * 1: Allowed
*/ */
uint32_t lp_mm_tcm_mon_allow:1; uint32_t lp_mm_spm_mon_allow:1;
/** lp_mm_cache_allow : R/W; bitpos: [11]; default: 1; /** lp_mm_cache_allow : R/W; bitpos: [11]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access cache. * Configures whether the LP CPU in machine mode has permission to access cache.
* 0: Not allowed * 0: Not allowed
@@ -153,13 +153,7 @@ typedef union {
* 1: Allowed * 1: Allowed
*/ */
uint32_t lp_mm_hp_gdma_allow:1; uint32_t lp_mm_hp_gdma_allow:1;
/** lp_mm_hp_regdma_allow : R/W; bitpos: [4]; default: 1; uint32_t reserved_4:1;
* Configures whether the LP CPU in machine mode has permission to access HP GDMA (DW
* GDMA).
* 0: Not allowed
* 1: Allow
*/
uint32_t lp_mm_hp_regdma_allow:1;
/** lp_mm_hp_sdmmc_allow : R/W; bitpos: [5]; default: 1; /** lp_mm_hp_sdmmc_allow : R/W; bitpos: [5]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP SDMMC. * Configures whether the LP CPU in machine mode has permission to access HP SDMMC.
* 0: Not allowed * 0: Not allowed