From e3f27822ba4b00e2be9bc3b251160a08915be70d Mon Sep 17 00:00:00 2001 From: Chen Jichang Date: Fri, 7 Mar 2025 17:14:09 +0800 Subject: [PATCH] fix(parlio): fix non-free running test case --- .../test_apps/parlio/main/test_parlio_tx.c | 6 ++++-- .../esp_driver_parlio/test_apps/parlio/sdkconfig.ci.release | 1 + 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/components/esp_driver_parlio/test_apps/parlio/main/test_parlio_tx.c b/components/esp_driver_parlio/test_apps/parlio/main/test_parlio_tx.c index 249bb084bb..ba22f8e072 100644 --- a/components/esp_driver_parlio/test_apps/parlio/main/test_parlio_tx.c +++ b/components/esp_driver_parlio/test_apps/parlio/main/test_parlio_tx.c @@ -364,8 +364,10 @@ static void test_use_external_non_free_running_clock(parlio_tx_unit_handle_t tx_ uint32_t clock_div = config.input_clk_src_freq_hz / config.output_clk_freq_hz; TEST_ESP_OK(parlio_new_tx_unit(&config, &tx_unit)); TEST_ESP_OK(parlio_tx_unit_enable(tx_unit)); - // let core clock running for a while to update the clock divider threshold - esp_rom_delay_us(100 * 1000); + // let core clock running for a while to update the clock divider threshold, this is a hardware limitation + // the following rising edge count is not a magic value, we just need it to be larger than the clock divider value in the previous test case + test_gpio_simulate_rising_edge(TEST_EXT_CLK_GPIO, 100); + esp_rom_delay_us(1000); parlio_transmit_config_t transmit_config = { .idle_value = 0xAA, }; diff --git a/components/esp_driver_parlio/test_apps/parlio/sdkconfig.ci.release b/components/esp_driver_parlio/test_apps/parlio/sdkconfig.ci.release index 17aaee1e8e..b9a047d536 100644 --- a/components/esp_driver_parlio/test_apps/parlio/sdkconfig.ci.release +++ b/components/esp_driver_parlio/test_apps/parlio/sdkconfig.ci.release @@ -1,5 +1,6 @@ CONFIG_PM_ENABLE=y CONFIG_FREERTOS_USE_TICKLESS_IDLE=y +CONFIG_PM_DFS_INIT_AUTO=y CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP=y CONFIG_COMPILER_OPTIMIZATION_SIZE=y CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE=y