diff --git a/components/esp_hw_support/sleep_modes.c b/components/esp_hw_support/sleep_modes.c
index ca088feb69..f62400b62a 100644
--- a/components/esp_hw_support/sleep_modes.c
+++ b/components/esp_hw_support/sleep_modes.c
@@ -59,8 +59,8 @@
 #include "esp_private/sleep_modem.h"
 #include "esp_private/esp_clk.h"
 #include "esp_private/esp_task_wdt.h"
-#include "esp_private/spi_flash_os.h"
 #include "esp_private/sar_periph_ctrl.h"
+#include "esp_private/mspi_timing_tuning.h"
 
 #ifdef CONFIG_IDF_TARGET_ESP32
 #include "esp32/rom/cache.h"
@@ -500,15 +500,8 @@ static uint32_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags, esp_sleep_mode_t mo
         pd_flags &= ~RTC_SLEEP_PD_INT_8M;
     }
 
-    // Turn down mspi clock speed
-#if SOC_SPI_MEM_SUPPORT_TIME_TUNING
+    //turn down MSPI speed
     mspi_timing_change_speed_mode_cache_safe(true);
-#endif
-
-    // Set mspi clock to a low-power one.
-#if SOC_MEMSPI_CLOCK_IS_INDEPENDENT
-    spi_flash_set_clock_src(MSPI_CLK_SRC_ROM_DEFAULT);
-#endif
 
     // Save current frequency and switch to XTAL
     rtc_cpu_freq_config_t cpu_freq_config;
@@ -686,15 +679,8 @@ static uint32_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags, esp_sleep_mode_t mo
         rtc_clk_cpu_freq_set_config(&cpu_freq_config);
     }
 
-    // Set mspi clock to ROM default one.
-#if SOC_MEMSPI_CLOCK_IS_INDEPENDENT
-    spi_flash_set_clock_src(MSPI_CLK_SRC_DEFAULT);
-#endif
-
-    // Speed up mspi clock freq
-#if SOC_SPI_MEM_SUPPORT_TIME_TUNING
+    //restore MSPI speed
     mspi_timing_change_speed_mode_cache_safe(false);
-#endif
 
     if (!deep_sleep) {
         s_config.ccount_ticks_record = esp_cpu_get_cycle_count();
diff --git a/components/esp_system/port/esp_system_chip.c b/components/esp_system/port/esp_system_chip.c
index d965c04382..440a0f1a7a 100644
--- a/components/esp_system/port/esp_system_chip.c
+++ b/components/esp_system/port/esp_system_chip.c
@@ -11,7 +11,7 @@
 #include "esp_private/rtc_clk.h"
 #include "esp_private/panic_internal.h"
 #include "esp_private/system_internal.h"
-#include "esp_private/spi_flash_os.h"
+#include "esp_private/mspi_timing_tuning.h"
 #include "esp_heap_caps.h"
 #include "esp_rom_uart.h"
 #include "esp_rom_sys.h"
@@ -33,9 +33,15 @@ void IRAM_ATTR esp_restart_noos_dig(void)
         esp_rom_uart_tx_wait_idle(CONFIG_ESP_CONSOLE_UART_NUM);
     }
 
-#if SOC_MEMSPI_CLOCK_IS_INDEPENDENT
-    spi_flash_set_clock_src(MSPI_CLK_SRC_ROM_DEFAULT);
-#endif
+#if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
+    /**
+     * Turn down MSPI speed
+     *
+     * We set MSPI clock to a high speed one before, ROM doesn't have such high speed clock source option.
+     * This function will change clock source to a ROM supported one when system restarts.
+     */
+    mspi_timing_change_speed_mode_cache_safe(true);
+#endif  //#if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
 
     // switch to XTAL (otherwise we will keep running from the PLL)
     rtc_clk_cpu_set_to_default_config();
diff --git a/components/esp_system/port/soc/esp32h2/system_internal.c b/components/esp_system/port/soc/esp32h2/system_internal.c
index 62037572d6..afe2424ffc 100644
--- a/components/esp_system/port/soc/esp32h2/system_internal.c
+++ b/components/esp_system/port/soc/esp32h2/system_internal.c
@@ -23,7 +23,7 @@
 #include "hal/wdt_hal.h"
 #include "hal/spimem_flash_ll.h"
 #include "esp_private/cache_err_int.h"
-#include "esp_private/spi_flash_os.h"
+#include "esp_private/mspi_timing_tuning.h"
 
 #include "esp32h2/rom/cache.h"
 #include "esp32h2/rom/rtc.h"
@@ -89,8 +89,15 @@ void IRAM_ATTR esp_restart_noos(void)
     CLEAR_PERI_REG_MASK(PCR_GDMA_CONF_REG, PCR_GDMA_RST_EN);
     CLEAR_PERI_REG_MASK(PCR_MODEM_CONF_REG, PCR_MODEM_RST_EN);
 
-    // If we set mspi clock frequency to PLL, but ROM does not have such clock source option. So reset the clock to XTAL when software restart.
-    spi_flash_set_clock_src(MSPI_CLK_SRC_ROM_DEFAULT);
+#if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
+    /**
+     * Turn down MSPI speed
+     *
+     * We set MSPI clock to a high speed one before, ROM doesn't have such high speed clock source option.
+     * This function will change clock source to a ROM supported one when system restarts.
+     */
+    mspi_timing_change_speed_mode_cache_safe(true);
+#endif  //#if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
 
     // Set CPU back to XTAL source, same as hard reset, but keep BBPLL on so that USB Serial JTAG can log at 1st stage bootloader.
 #if !CONFIG_IDF_ENV_FPGA
diff --git a/components/spi_flash/flash_ops.c b/components/spi_flash/flash_ops.c
index c65547d18a..430811bd65 100644
--- a/components/spi_flash/flash_ops.c
+++ b/components/spi_flash/flash_ops.c
@@ -287,13 +287,3 @@ uint8_t esp_mspi_get_io(esp_mspi_io_t io)
     return s_mspi_io_num_default[io];
 #endif // SOC_SPI_MEM_SUPPORT_CONFIG_GPIO_BY_EFUSE
 }
-
-#if SOC_MEMSPI_CLOCK_IS_INDEPENDENT
-
-IRAM_ATTR void spi_flash_set_clock_src(soc_periph_mspi_clk_src_t clk_src)
-{
-    cache_hal_freeze(CACHE_TYPE_INSTRUCTION);
-    spimem_flash_ll_set_clock_source(clk_src);
-    cache_hal_unfreeze(CACHE_TYPE_INSTRUCTION);
-}
-#endif // SOC_MEMSPI_CLOCK_IS_INDEPENDENT
diff --git a/components/spi_flash/include/esp_private/spi_flash_os.h b/components/spi_flash/include/esp_private/spi_flash_os.h
index 15ef0bf4a2..1461e3964a 100644
--- a/components/spi_flash/include/esp_private/spi_flash_os.h
+++ b/components/spi_flash/include/esp_private/spi_flash_os.h
@@ -246,16 +246,7 @@ extern const spi_flash_guard_funcs_t g_flash_guard_no_os_ops;
  */
 void spi_flash_rom_impl_init(void);
 
-#if SOC_MEMSPI_CLOCK_IS_INDEPENDENT
-/**
- * @brief This functions is used to change spi flash clock source between PLL and others, which is used after system wake up from a low power mode or
- * enter low-power mode like sleep.
- * @param clk_src mspi(flash) clock source.
- *
- * @note Only called in startup. User should not call this function.
- */
-void spi_flash_set_clock_src(soc_periph_mspi_clk_src_t clk_src);
-#endif
+
 
 #ifdef __cplusplus
 }