diff --git a/components/esp_hw_support/sleep_cpu.c b/components/esp_hw_support/sleep_cpu.c index 2f01bdc779..318e8b85f3 100644 --- a/components/esp_hw_support/sleep_cpu.c +++ b/components/esp_hw_support/sleep_cpu.c @@ -307,8 +307,8 @@ static inline void * cpu_domain_intpri_sleep_frame_alloc_and_init(void) static inline void * cpu_domain_cache_config_sleep_frame_alloc_and_init(void) { const static cpu_domain_dev_regs_region_t regions[] = { - { .start = EXTMEM_DCACHE_CTRL_REG, .end = EXTMEM_DCACHE_CTRL_REG + 4 }, - { .start = EXTMEM_CACHE_WRAP_AROUND_CTRL_REG, .end = EXTMEM_CACHE_WRAP_AROUND_CTRL_REG + 4 } + { .start = EXTMEM_L1_CACHE_CTRL_REG, .end = EXTMEM_L1_CACHE_CTRL_REG + 4 }, + { .start = EXTMEM_L1_CACHE_WRAP_AROUND_CTRL_REG, .end = EXTMEM_L1_CACHE_WRAP_AROUND_CTRL_REG + 4 } }; return cpu_domain_dev_sleep_frame_alloc_and_init(regions, sizeof(regions) / sizeof(regions[0])); } diff --git a/components/esp_system/port/soc/esp32c6/cache_err_int.c b/components/esp_system/port/soc/esp32c6/cache_err_int.c index 12cc81c03c..772df0f616 100644 --- a/components/esp_system/port/soc/esp32c6/cache_err_int.c +++ b/components/esp_system/port/soc/esp32c6/cache_err_int.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -22,8 +22,6 @@ static const char *TAG = "CACHE_ERR"; void esp_cache_err_int_init(void) { - ESP_EARLY_LOGW(TAG, "esp_cache_err_int_init() has not been implemented yet"); -#if 0 // TODO: IDF-5656 const uint32_t core_id = 0; /* Disable cache interrupts if enabled. */ @@ -32,27 +30,13 @@ void esp_cache_err_int_init(void) /** * Bind all cache errors to ETS_CACHEERR_INUM interrupt. we will deal with * them in handler by different types - * I) Cache access error - * 1. dbus trying to write to icache - * 2. dbus authentication fail - * 3. cpu access icache while dbus is disabled [1] - * 4. ibus authentication fail - * 5. ibus trying to write icache - * 6. cpu access icache while ibus is disabled - * II) Cache illegal error - * 1. dbus counter overflow - * 2. ibus counter overflow - * 3. mmu entry fault - * 4. icache preload configurations fault - * 5. icache sync configuration fault * - * [1]: On ESP32C6 boards, the caches are shared but buses are still - * distinct. So, we have an ibus and a dbus sharing the same cache. - * This error can occur if the dbus performs a request but the icache - * (or simply cache) is disabled. + * On ESP32C6 boards, the cache is a shared one but buses are still + * distinct. So, we have an bus0 and a bus1 sharing the same cache. + * This error can occur if a bus performs a request but the cache + * is disabled. */ - esp_rom_route_intr_matrix(core_id, ETS_CACHE_IA_INTR_SOURCE, ETS_CACHEERR_INUM); - esp_rom_route_intr_matrix(core_id, ETS_CACHE_CORE0_ACS_INTR_SOURCE, ETS_CACHEERR_INUM); + esp_rom_route_intr_matrix(core_id, ETS_CACHE_INTR_SOURCE, ETS_CACHEERR_INUM); /* Set the type and priority to cache error interrupts. */ esprv_intc_int_set_type(ETS_CACHEERR_INUM, INTR_TYPE_LEVEL); @@ -64,15 +48,8 @@ void esp_cache_err_int_init(void) /* Then enable cache access error interrupts. */ cache_ll_l1_enable_access_error_intr(0, CACHE_LL_L1_ACCESS_EVENT_MASK); - /* Same goes for cache illegal error: start by clearing the bits and then - * set them back. */ - ESP_DRAM_LOGV(TAG, "illegal error intr clr & ena mask is: 0x%x", CACHE_LL_L1_ILG_EVENT_MASK); - cache_ll_l1_clear_illegal_error_intr(0, CACHE_LL_L1_ILG_EVENT_MASK); - cache_ll_l1_enable_illegal_error_intr(0, CACHE_LL_L1_ILG_EVENT_MASK); - /* Enable the interrupts for cache error. */ ESP_INTR_ENABLE(ETS_CACHEERR_INUM); -#endif } int IRAM_ATTR esp_cache_err_get_cpuid(void) diff --git a/components/esp_system/port/soc/esp32h2/cache_err_int.c b/components/esp_system/port/soc/esp32h2/cache_err_int.c index 382a0f6a5b..f6c2a151d6 100644 --- a/components/esp_system/port/soc/esp32h2/cache_err_int.c +++ b/components/esp_system/port/soc/esp32h2/cache_err_int.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -22,8 +22,6 @@ static const char *TAG = "CACHE_ERR"; void esp_cache_err_int_init(void) { - ESP_EARLY_LOGW(TAG, "esp_cache_err_int_init() has not been implemented yet"); -#if 0// ESP32H2-TODO : IDF-5656 const uint32_t core_id = 0; /* Disable cache interrupts if enabled. */ @@ -32,30 +30,16 @@ void esp_cache_err_int_init(void) /** * Bind all cache errors to ETS_CACHEERR_INUM interrupt. we will deal with * them in handler by different types - * I) Cache access error - * 1. dbus trying to write to icache - * 2. dbus authentication fail - * 3. cpu access icache while dbus is disabled [1] - * 4. ibus authentication fail - * 5. ibus trying to write icache - * 6. cpu access icache while ibus is disabled - * II) Cache illegal error - * 1. dbus counter overflow - * 2. ibus counter overflow - * 3. mmu entry fault - * 4. icache preload configurations fault - * 5. icache sync configuration fault * - * [1]: On ESP32H2 boards, the caches are shared but buses are still - * distinct. So, we have an ibus and a dbus sharing the same cache. - * This error can occur if the dbus performs a request but the icache - * (or simply cache) is disabled. + * On ESP32H2 boards, the cache is a shared one but buses are still + * distinct. So, we have an bus0 and a bus1 sharing the same cache. + * This error can occur if a bus performs a request but the cache + * is disabled. */ - esp_rom_route_intr_matrix(core_id, ETS_CACHE_IA_INTR_SOURCE, ETS_CACHEERR_INUM); - esp_rom_route_intr_matrix(core_id, ETS_CACHE_CORE0_ACS_INTR_SOURCE, ETS_CACHEERR_INUM); + esp_rom_route_intr_matrix(core_id, ETS_CACHE_INTR_SOURCE, ETS_CACHEERR_INUM); /* Set the type and priority to cache error interrupts. */ - esprv_intc_int_set_type(BIT(ETS_CACHEERR_INUM), INTR_TYPE_LEVEL); + esprv_intc_int_set_type(ETS_CACHEERR_INUM, INTR_TYPE_LEVEL); esprv_intc_int_set_priority(ETS_CACHEERR_INUM, SOC_INTERRUPT_LEVEL_MEDIUM); ESP_DRAM_LOGV(TAG, "access error intr clr & ena mask is: 0x%x", CACHE_LL_L1_ACCESS_EVENT_MASK); @@ -64,15 +48,8 @@ void esp_cache_err_int_init(void) /* Then enable cache access error interrupts. */ cache_ll_l1_enable_access_error_intr(0, CACHE_LL_L1_ACCESS_EVENT_MASK); - /* Same goes for cache illegal error: start by clearing the bits and then - * set them back. */ - ESP_DRAM_LOGV(TAG, "illegal error intr clr & ena mask is: 0x%x", CACHE_LL_L1_ILG_EVENT_MASK); - cache_ll_l1_clear_illegal_error_intr(0, CACHE_LL_L1_ILG_EVENT_MASK); - cache_ll_l1_enable_illegal_error_intr(0, CACHE_LL_L1_ILG_EVENT_MASK); - /* Enable the interrupts for cache error. */ ESP_INTR_ENABLE(ETS_CACHEERR_INUM); -#endif } int IRAM_ATTR esp_cache_err_get_cpuid(void) diff --git a/components/hal/esp32c6/include/hal/cache_ll.h b/components/hal/esp32c6/include/hal/cache_ll.h index 5a826c2e0f..c135c5a8d4 100644 --- a/components/hal/esp32c6/include/hal/cache_ll.h +++ b/components/hal/esp32c6/include/hal/cache_ll.h @@ -21,18 +21,8 @@ extern "C" { #define CACHE_LL_DEFAULT_IBUS_MASK CACHE_BUS_IBUS0 #define CACHE_LL_DEFAULT_DBUS_MASK CACHE_BUS_DBUS0 -#define CACHE_LL_L1_ACCESS_EVENT_MASK (0x3f) -#define CACHE_LL_L1_ACCESS_EVENT_DBUS_WR_IC (1<<5) -#define CACHE_LL_L1_ACCESS_EVENT_DBUS_REJECT (1<<4) -#define CACHE_LL_L1_ACCESS_EVENT_DBUS_ACS_MSK_IC (1<<3) -#define CACHE_LL_L1_ACCESS_EVENT_IBUS_REJECT (1<<2) -#define CACHE_LL_L1_ACCESS_EVENT_IBUS_WR_IC (1<<1) -#define CACHE_LL_L1_ACCESS_EVENT_IBUS_ACS_MSK_IC (1<<0) - -#define CACHE_LL_L1_ILG_EVENT_MASK (0x23) -#define CACHE_LL_L1_ILG_EVENT_MMU_ENTRY_FAULT (1<<5) -#define CACHE_LL_L1_ILG_EVENT_PRELOAD_OP_FAULT (1<<1) -#define CACHE_LL_L1_ILG_EVENT_SYNC_OP_FAULT (1<<0) +#define CACHE_LL_L1_ACCESS_EVENT_MASK (1<<4) +#define CACHE_LL_L1_ACCESS_EVENT_CACHE_FAIL (1<<4) /** @@ -55,9 +45,8 @@ static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t v uint32_t vaddr_end = vaddr_start + len - 1; if (vaddr_start >= IRAM0_CACHE_ADDRESS_LOW && vaddr_end < IRAM0_CACHE_ADDRESS_HIGH) { - mask |= CACHE_BUS_IBUS0; - } else if (vaddr_start >= DRAM0_CACHE_ADDRESS_LOW && vaddr_end < DRAM0_CACHE_ADDRESS_HIGH) { - mask |= CACHE_BUS_DBUS0; + //c6 the I/D bus memory are shared, so we always return `CACHE_BUS_IBUS0 | CACHE_BUS_DBUS0` + mask |= CACHE_BUS_IBUS0 | CACHE_BUS_DBUS0; } else { HAL_ASSERT(0); //Out of region } @@ -77,16 +66,16 @@ __attribute__((always_inline)) static inline void cache_ll_l1_enable_bus(uint32_t cache_id, cache_bus_mask_t mask) { HAL_ASSERT(cache_id == 0); - //On esp32c3, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first - HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2| CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0); + //On esp32c6, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first + HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0); uint32_t ibus_mask = 0; - ibus_mask |= (mask & CACHE_BUS_IBUS0) ? EXTMEM_DCACHE_SHUT_DBUS0 : 0; - REG_CLR_BIT(EXTMEM_ICACHE_CTRL_REG, ibus_mask); + ibus_mask |= (mask & CACHE_BUS_IBUS0) ? EXTMEM_L1_CACHE_SHUT_IBUS : 0; + REG_CLR_BIT(EXTMEM_L1_CACHE_CTRL_REG, ibus_mask); uint32_t dbus_mask = 0; - dbus_mask |= (mask & CACHE_BUS_DBUS0) ? EXTMEM_DCACHE_SHUT_DBUS1 : 0; - REG_CLR_BIT(EXTMEM_ICACHE_CTRL_REG, dbus_mask); + dbus_mask |= (mask & CACHE_BUS_DBUS0) ? EXTMEM_L1_CACHE_SHUT_DBUS : 0; + REG_CLR_BIT(EXTMEM_L1_CACHE_CTRL_REG, dbus_mask); } /** @@ -99,16 +88,16 @@ __attribute__((always_inline)) static inline void cache_ll_l1_disable_bus(uint32_t cache_id, cache_bus_mask_t mask) { HAL_ASSERT(cache_id == 0); - //On esp32c3, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first - HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2| CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0); + //On esp32c6, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first + HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0); uint32_t ibus_mask = 0; - ibus_mask |= (mask & CACHE_BUS_IBUS0) ? EXTMEM_DCACHE_SHUT_DBUS0 : 0; - REG_SET_BIT(EXTMEM_ICACHE_CTRL_REG, ibus_mask); + ibus_mask |= (mask & CACHE_BUS_IBUS0) ? EXTMEM_L1_CACHE_SHUT_IBUS : 0; + REG_SET_BIT(EXTMEM_L1_CACHE_CTRL_REG, ibus_mask); uint32_t dbus_mask = 0; - dbus_mask |= (mask & CACHE_BUS_DBUS0) ? EXTMEM_DCACHE_SHUT_DBUS1 : 0; - REG_SET_BIT(EXTMEM_ICACHE_CTRL_REG, dbus_mask); + dbus_mask |= (mask & CACHE_BUS_DBUS0) ? EXTMEM_L1_CACHE_SHUT_DBUS : 0; + REG_SET_BIT(EXTMEM_L1_CACHE_CTRL_REG, dbus_mask); } /*------------------------------------------------------------------------------ @@ -122,8 +111,7 @@ static inline void cache_ll_l1_disable_bus(uint32_t cache_id, cache_bus_mask_t m */ static inline void cache_ll_l1_enable_access_error_intr(uint32_t cache_id, uint32_t mask) { - // TODO: IDF-5656 - // SET_PERI_REG_MASK(EXTMEM_CORE0_ACS_CACHE_INT_ENA_REG, mask); + SET_PERI_REG_MASK(EXTMEM_L1_CACHE_ACS_FAIL_INT_ENA_REG, mask); } /** @@ -134,8 +122,7 @@ static inline void cache_ll_l1_enable_access_error_intr(uint32_t cache_id, uint3 */ static inline void cache_ll_l1_clear_access_error_intr(uint32_t cache_id, uint32_t mask) { - // TODO: IDF-5656 - // SET_PERI_REG_MASK(EXTMEM_CORE0_ACS_CACHE_INT_CLR_REG, mask); + SET_PERI_REG_MASK(EXTMEM_L1_CACHE_ACS_FAIL_INT_CLR_REG, mask); } /** @@ -148,48 +135,7 @@ static inline void cache_ll_l1_clear_access_error_intr(uint32_t cache_id, uint32 */ static inline uint32_t cache_ll_l1_get_access_error_intr_status(uint32_t cache_id, uint32_t mask) { - // TODO: IDF-5656 - // return GET_PERI_REG_MASK(EXTMEM_CORE0_ACS_CACHE_INT_ST_REG, mask); - return 0; -} - -/** - * @brief Enable Cache illegal error interrupt - * - * @param cache_id Cache ID, not used on C3. For compabitlity - * @param mask Interrupt mask - */ -static inline void cache_ll_l1_enable_illegal_error_intr(uint32_t cache_id, uint32_t mask) -{ - // TODO: IDF-5656 - // SET_PERI_REG_MASK(EXTMEM_CACHE_ILG_INT_ENA_REG, mask); -} - -/** - * @brief Clear Cache illegal error interrupt status - * - * @param cache_id Cache ID, not used on C3. For compabitlity - * @param mask Interrupt mask - */ -static inline void cache_ll_l1_clear_illegal_error_intr(uint32_t cache_id, uint32_t mask) -{ - // TODO: IDF-5656 - // SET_PERI_REG_MASK(EXTMEM_CACHE_ILG_INT_CLR_REG, mask); -} - -/** - * @brief Get Cache illegal error interrupt status - * - * @param cache_id Cache ID, not used on C3. For compabitlity - * @param mask Interrupt mask - * - * @return Status mask - */ -static inline uint32_t cache_ll_l1_get_illegal_error_intr_status(uint32_t cache_id, uint32_t mask) -{ - // TODO: IDF-5656 - // return GET_PERI_REG_MASK(EXTMEM_CACHE_ILG_INT_ST_REG, mask); - return 0; + return GET_PERI_REG_MASK(EXTMEM_L1_CACHE_ACS_FAIL_INT_ST_REG, mask); } #ifdef __cplusplus diff --git a/components/hal/esp32h2/include/hal/cache_ll.h b/components/hal/esp32h2/include/hal/cache_ll.h index 1928e9d290..7b50600dd3 100644 --- a/components/hal/esp32h2/include/hal/cache_ll.h +++ b/components/hal/esp32h2/include/hal/cache_ll.h @@ -21,18 +21,8 @@ extern "C" { #define CACHE_LL_DEFAULT_IBUS_MASK CACHE_BUS_IBUS0 #define CACHE_LL_DEFAULT_DBUS_MASK CACHE_BUS_DBUS0 -#define CACHE_LL_L1_ACCESS_EVENT_MASK (0x3f) -#define CACHE_LL_L1_ACCESS_EVENT_DBUS_WR_IC (1<<5) -#define CACHE_LL_L1_ACCESS_EVENT_DBUS_REJECT (1<<4) -#define CACHE_LL_L1_ACCESS_EVENT_DBUS_ACS_MSK_IC (1<<3) -#define CACHE_LL_L1_ACCESS_EVENT_IBUS_REJECT (1<<2) -#define CACHE_LL_L1_ACCESS_EVENT_IBUS_WR_IC (1<<1) -#define CACHE_LL_L1_ACCESS_EVENT_IBUS_ACS_MSK_IC (1<<0) - -#define CACHE_LL_L1_ILG_EVENT_MASK (0x23) -#define CACHE_LL_L1_ILG_EVENT_MMU_ENTRY_FAULT (1<<5) -#define CACHE_LL_L1_ILG_EVENT_PRELOAD_OP_FAULT (1<<1) -#define CACHE_LL_L1_ILG_EVENT_SYNC_OP_FAULT (1<<0) +#define CACHE_LL_L1_ACCESS_EVENT_MASK (1<<4) +#define CACHE_LL_L1_ACCESS_EVENT_CACHE_FAIL (1<<4) /** @@ -55,9 +45,8 @@ static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t v uint32_t vaddr_end = vaddr_start + len - 1; if (vaddr_start >= IRAM0_CACHE_ADDRESS_LOW && vaddr_end < IRAM0_CACHE_ADDRESS_HIGH) { - mask |= CACHE_BUS_IBUS0; - } else if (vaddr_start >= DRAM0_CACHE_ADDRESS_LOW && vaddr_end < DRAM0_CACHE_ADDRESS_HIGH) { - mask |= CACHE_BUS_DBUS0; + //h2 the I/D bus memory are shared, so we always return `CACHE_BUS_IBUS0 | CACHE_BUS_DBUS0` + mask |= CACHE_BUS_IBUS0 | CACHE_BUS_DBUS0; } else { HAL_ASSERT(0); //Out of region } @@ -78,15 +67,15 @@ static inline void cache_ll_l1_enable_bus(uint32_t cache_id, cache_bus_mask_t ma { HAL_ASSERT(cache_id == 0); //On esp32h2, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first - HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2| CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0); + HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0); uint32_t ibus_mask = 0; - ibus_mask |= (mask & CACHE_BUS_IBUS0) ? EXTMEM_DCACHE_SHUT_DBUS0 : 0; - REG_CLR_BIT(EXTMEM_ICACHE_CTRL_REG, ibus_mask); + ibus_mask |= (mask & CACHE_BUS_IBUS0) ? CACHE_L1_CACHE_SHUT_BUS0 : 0; + REG_CLR_BIT(CACHE_L1_CACHE_CTRL_REG, ibus_mask); uint32_t dbus_mask = 0; - dbus_mask |= (mask & CACHE_BUS_DBUS0) ? EXTMEM_DCACHE_SHUT_DBUS1 : 0; - REG_CLR_BIT(EXTMEM_ICACHE_CTRL_REG, dbus_mask); + dbus_mask |= (mask & CACHE_BUS_DBUS0) ? CACHE_L1_CACHE_SHUT_BUS1 : 0; + REG_CLR_BIT(CACHE_L1_CACHE_CTRL_REG, dbus_mask); } /** @@ -100,15 +89,15 @@ static inline void cache_ll_l1_disable_bus(uint32_t cache_id, cache_bus_mask_t m { HAL_ASSERT(cache_id == 0); //On esp32h2, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first - HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2| CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0); + HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0); uint32_t ibus_mask = 0; - ibus_mask |= (mask & CACHE_BUS_IBUS0) ? EXTMEM_DCACHE_SHUT_DBUS0 : 0; - REG_SET_BIT(EXTMEM_ICACHE_CTRL_REG, ibus_mask); + ibus_mask |= (mask & CACHE_BUS_IBUS0) ? CACHE_L1_CACHE_SHUT_BUS0 : 0; + REG_SET_BIT(CACHE_L1_CACHE_CTRL_REG, ibus_mask); uint32_t dbus_mask = 0; - dbus_mask |= (mask & CACHE_BUS_DBUS0) ? EXTMEM_DCACHE_SHUT_DBUS1 : 0; - REG_SET_BIT(EXTMEM_ICACHE_CTRL_REG, dbus_mask); + dbus_mask |= (mask & CACHE_BUS_DBUS0) ? CACHE_L1_CACHE_SHUT_BUS1 : 0; + REG_SET_BIT(CACHE_L1_CACHE_CTRL_REG, dbus_mask); } /*------------------------------------------------------------------------------ @@ -117,79 +106,36 @@ static inline void cache_ll_l1_disable_bus(uint32_t cache_id, cache_bus_mask_t m /** * @brief Enable Cache access error interrupt * - * @param cache_id Cache ID, not used on H2. For compabitlity + * @param cache_id Cache ID, not used on C3. For compabitlity * @param mask Interrupt mask */ static inline void cache_ll_l1_enable_access_error_intr(uint32_t cache_id, uint32_t mask) { - // ESP32H2-TODO - // SET_PERI_REG_MASK(EXTMEM_CORE0_ACS_CACHE_INT_ENA_REG, mask); + SET_PERI_REG_MASK(CACHE_L1_CACHE_ACS_FAIL_INT_ENA_REG, mask); } /** * @brief Clear Cache access error interrupt status * - * @param cache_id Cache ID, not used on H2. For compabitlity + * @param cache_id Cache ID, not used on C3. For compabitlity * @param mask Interrupt mask */ static inline void cache_ll_l1_clear_access_error_intr(uint32_t cache_id, uint32_t mask) { - // ESP32H2-TODO: IDF-6255 - // SET_PERI_REG_MASK(EXTMEM_CORE0_ACS_CACHE_INT_CLR_REG, mask); + SET_PERI_REG_MASK(CACHE_L1_CACHE_ACS_FAIL_INT_CLR_REG, mask); } /** * @brief Get Cache access error interrupt status * - * @param cache_id Cache ID, not used on H2. For compabitlity + * @param cache_id Cache ID, not used on C3. For compabitlity * @param mask Interrupt mask * * @return Status mask */ static inline uint32_t cache_ll_l1_get_access_error_intr_status(uint32_t cache_id, uint32_t mask) { - // ESP32H2-TODO: IDF-6255 - // return GET_PERI_REG_MASK(EXTMEM_CORE0_ACS_CACHE_INT_ST_REG, mask); - return 0; -} - -/** - * @brief Enable Cache illegal error interrupt - * - * @param cache_id Cache ID, not used on H2. For compabitlity - * @param mask Interrupt mask - */ -static inline void cache_ll_l1_enable_illegal_error_intr(uint32_t cache_id, uint32_t mask) -{ - // ESP32H2-TODO: IDF-6255 - // SET_PERI_REG_MASK(EXTMEM_CACHE_ILG_INT_ENA_REG, mask); -} - -/** - * @brief Clear Cache illegal error interrupt status - * - * @param cache_id Cache ID, not used on H2. For compabitlity - * @param mask Interrupt mask - */ -static inline void cache_ll_l1_clear_illegal_error_intr(uint32_t cache_id, uint32_t mask) -{ - // ESP32H2-TODO: IDF-6255 - // SET_PERI_REG_MASK(EXTMEM_CACHE_ILG_INT_CLR_REG, mask); -} - -/** - * @brief Get Cache illegal error interrupt status - * - * @param cache_id Cache ID, not used on H2. For compabitlity - * @param mask Interrupt mask - * - * @return Status mask - */ -static inline uint32_t cache_ll_l1_get_illegal_error_intr_status(uint32_t cache_id, uint32_t mask) -{ - // ESP32H2-TODO: IDF-6255 - // return GET_PERI_REG_MASK(EXTMEM_CACHE_ILG_INT_ST_REG, mask); - return 0; + return GET_PERI_REG_MASK(CACHE_L1_CACHE_ACS_FAIL_INT_ST_REG, mask); } #ifdef __cplusplus diff --git a/components/soc/esp32c6/include/soc/extmem_reg.h b/components/soc/esp32c6/include/soc/extmem_reg.h index 42cea3bdb3..a9cb693586 100644 --- a/components/soc/esp32c6/include/soc/extmem_reg.h +++ b/components/soc/esp32c6/include/soc/extmem_reg.h @@ -1,7 +1,7 @@ -/* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 */ #pragma once @@ -11,930 +11,851 @@ extern "C" { #endif -// TODO: IDF-5797 +#define EXTMEM_L1_CACHE_CTRL_REG (DR_REG_EXTMEM_BASE + 0x4) +/* EXTMEM_L1_CACHE_SHUT_DBUS : R/W ;bitpos:[1] ;default: 1'h0 ; */ +/*description: The bit is used to disable core0 dbus access L1-Cache, 0: enable, 1: disable.*/ +#define EXTMEM_L1_CACHE_SHUT_DBUS (BIT(1)) +#define EXTMEM_L1_CACHE_SHUT_DBUS_M (BIT(1)) +#define EXTMEM_L1_CACHE_SHUT_DBUS_V 0x1 +#define EXTMEM_L1_CACHE_SHUT_DBUS_S 1 +/* EXTMEM_L1_CACHE_SHUT_IBUS : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: The bit is used to disable core0 dbus access L1-Cache, 0: enable, 1: disable.*/ +#define EXTMEM_L1_CACHE_SHUT_IBUS (BIT(0)) +#define EXTMEM_L1_CACHE_SHUT_IBUS_M (BIT(0)) +#define EXTMEM_L1_CACHE_SHUT_IBUS_V 0x1 +#define EXTMEM_L1_CACHE_SHUT_IBUS_S 0 -#define EXTMEM_ICACHE_CTRL_REG (DR_REG_EXTMEM_BASE + 0x0) - -#define EXTMEM_DCACHE_CTRL_REG (DR_REG_EXTMEM_BASE + 0x4) -/* EXTMEM_DCACHE_SHUT_DBUS1 : R/W ;bitpos:[1] ;default: 1'h0 ; */ -/*description: The bit is used to disable core1 dbus access L1-DCache, 0: enable, 1: disable.*/ -#define EXTMEM_DCACHE_SHUT_DBUS1 (BIT(1)) -#define EXTMEM_DCACHE_SHUT_DBUS1_M (BIT(1)) -#define EXTMEM_DCACHE_SHUT_DBUS1_V 0x1 -#define EXTMEM_DCACHE_SHUT_DBUS1_S 1 -/* EXTMEM_DCACHE_SHUT_DBUS0 : R/W ;bitpos:[0] ;default: 1'h0 ; */ -/*description: The bit is used to disable core0 dbus access L1-DCache, 0: enable, 1: disable.*/ -#define EXTMEM_DCACHE_SHUT_DBUS0 (BIT(0)) -#define EXTMEM_DCACHE_SHUT_DBUS0_M (BIT(0)) -#define EXTMEM_DCACHE_SHUT_DBUS0_V 0x1 -#define EXTMEM_DCACHE_SHUT_DBUS0_S 0 - -#define EXTMEM_CACHE_WRAP_AROUND_CTRL_REG (DR_REG_EXTMEM_BASE + 0x20) -/* EXTMEM_DCACHE_WRAP : R/W ;bitpos:[4] ;default: 1'h0 ; */ +#define EXTMEM_L1_CACHE_WRAP_AROUND_CTRL_REG (DR_REG_EXTMEM_BASE + 0x20) +/* EXTMEM_L1_CACHE_WRAP : R/W ;bitpos:[4] ;default: 1'h0 ; */ /*description: Set this bit as 1 to enable L1-DCache wrap around mode..*/ -#define EXTMEM_CACHE_FLASH_WRAP_AROUND (BIT(4)) -#define EXTMEM_CACHE_FLASH_WRAP_AROUND_M (BIT(4)) -#define EXTMEM_CACHE_FLASH_WRAP_AROUND_V 0x1 -#define EXTMEM_CACHE_FLASH_WRAP_AROUND_S 4 +#define EXTMEM_L1_CACHE_WRAP (BIT(4)) +#define EXTMEM_L1_CACHE_WRAP_M (BIT(4)) +#define EXTMEM_L1_CACHE_WRAP_V 0x1 +#define EXTMEM_L1_CACHE_WRAP_S 4 -#define EXTMEM_CACHE_TAG_MEM_POWER_CTRL_REG (DR_REG_EXTMEM_BASE + 0x24) -/* EXTMEM_DCACHE_TAG_MEM_FORCE_PU : R/W ;bitpos:[18] ;default: 1'h1 ; */ -/*description: The bit is used to power L1-DCache tag memory up. 0: follow rtc_lslp, 1: power u +#define EXTMEM_L1_CACHE_TAG_MEM_POWER_CTRL_REG (DR_REG_EXTMEM_BASE + 0x24) +/* EXTMEM_L1_CACHE_TAG_MEM_FORCE_PU : R/W ;bitpos:[18] ;default: 1'h1 ; */ +/*description: The bit is used to power L1-Cache tag memory up. 0: follow rtc_lslp, 1: power up.*/ +#define EXTMEM_L1_CACHE_TAG_MEM_FORCE_PU (BIT(18)) +#define EXTMEM_L1_CACHE_TAG_MEM_FORCE_PU_M (BIT(18)) +#define EXTMEM_L1_CACHE_TAG_MEM_FORCE_PU_V 0x1 +#define EXTMEM_L1_CACHE_TAG_MEM_FORCE_PU_S 18 +/* EXTMEM_L1_CACHE_TAG_MEM_FORCE_PD : R/W ;bitpos:[17] ;default: 1'h0 ; */ +/*description: The bit is used to power L1-Cache tag memory down. 0: follow rtc_lslp, 1: power +down.*/ +#define EXTMEM_L1_CACHE_TAG_MEM_FORCE_PD (BIT(17)) +#define EXTMEM_L1_CACHE_TAG_MEM_FORCE_PD_M (BIT(17)) +#define EXTMEM_L1_CACHE_TAG_MEM_FORCE_PD_V 0x1 +#define EXTMEM_L1_CACHE_TAG_MEM_FORCE_PD_S 17 +/* EXTMEM_L1_CACHE_TAG_MEM_FORCE_ON : R/W ;bitpos:[16] ;default: 1'h1 ; */ +/*description: The bit is used to close clock gating of L1-Cache tag memory. 1: close gating, +0: open clock gating..*/ +#define EXTMEM_L1_CACHE_TAG_MEM_FORCE_ON (BIT(16)) +#define EXTMEM_L1_CACHE_TAG_MEM_FORCE_ON_M (BIT(16)) +#define EXTMEM_L1_CACHE_TAG_MEM_FORCE_ON_V 0x1 +#define EXTMEM_L1_CACHE_TAG_MEM_FORCE_ON_S 16 + +#define EXTMEM_L1_CACHE_DATA_MEM_POWER_CTRL_REG (DR_REG_EXTMEM_BASE + 0x28) +/* EXTMEM_L1_CACHE_DATA_MEM_FORCE_PU : R/W ;bitpos:[18] ;default: 1'h1 ; */ +/*description: The bit is used to power L1-Cache data memory up. 0: follow rtc_lslp, 1: power u p.*/ -#define EXTMEM_DCACHE_TAG_MEM_FORCE_PU (BIT(18)) -#define EXTMEM_DCACHE_TAG_MEM_FORCE_PU_M (BIT(18)) -#define EXTMEM_DCACHE_TAG_MEM_FORCE_PU_V 0x1 -#define EXTMEM_DCACHE_TAG_MEM_FORCE_PU_S 18 -/* EXTMEM_DCACHE_TAG_MEM_FORCE_PD : R/W ;bitpos:[17] ;default: 1'h0 ; */ -/*description: The bit is used to power L1-DCache tag memory down. 0: follow rtc_lslp, 1: power +#define EXTMEM_L1_CACHE_DATA_MEM_FORCE_PU (BIT(18)) +#define EXTMEM_L1_CACHE_DATA_MEM_FORCE_PU_M (BIT(18)) +#define EXTMEM_L1_CACHE_DATA_MEM_FORCE_PU_V 0x1 +#define EXTMEM_L1_CACHE_DATA_MEM_FORCE_PU_S 18 +/* EXTMEM_L1_CACHE_DATA_MEM_FORCE_PD : R/W ;bitpos:[17] ;default: 1'h0 ; */ +/*description: The bit is used to power L1-Cache data memory down. 0: follow rtc_lslp, 1: power down.*/ -#define EXTMEM_DCACHE_TAG_MEM_FORCE_PD (BIT(17)) -#define EXTMEM_DCACHE_TAG_MEM_FORCE_PD_M (BIT(17)) -#define EXTMEM_DCACHE_TAG_MEM_FORCE_PD_V 0x1 -#define EXTMEM_DCACHE_TAG_MEM_FORCE_PD_S 17 -/* EXTMEM_DCACHE_TAG_MEM_FORCE_ON : R/W ;bitpos:[16] ;default: 1'h1 ; */ -/*description: The bit is used to close clock gating of L1-DCache tag memory. 1: close gating, +#define EXTMEM_L1_CACHE_DATA_MEM_FORCE_PD (BIT(17)) +#define EXTMEM_L1_CACHE_DATA_MEM_FORCE_PD_M (BIT(17)) +#define EXTMEM_L1_CACHE_DATA_MEM_FORCE_PD_V 0x1 +#define EXTMEM_L1_CACHE_DATA_MEM_FORCE_PD_S 17 +/* EXTMEM_L1_CACHE_DATA_MEM_FORCE_ON : R/W ;bitpos:[16] ;default: 1'h1 ; */ +/*description: The bit is used to close clock gating of L1-Cache data memory. 1: close gating, 0: open clock gating..*/ -#define EXTMEM_DCACHE_TAG_MEM_FORCE_ON (BIT(16)) -#define EXTMEM_DCACHE_TAG_MEM_FORCE_ON_M (BIT(16)) -#define EXTMEM_DCACHE_TAG_MEM_FORCE_ON_V 0x1 -#define EXTMEM_DCACHE_TAG_MEM_FORCE_ON_S 16 +#define EXTMEM_L1_CACHE_DATA_MEM_FORCE_ON (BIT(16)) +#define EXTMEM_L1_CACHE_DATA_MEM_FORCE_ON_M (BIT(16)) +#define EXTMEM_L1_CACHE_DATA_MEM_FORCE_ON_V 0x1 +#define EXTMEM_L1_CACHE_DATA_MEM_FORCE_ON_S 16 -#define EXTMEM_CACHE_DATA_MEM_POWER_CTRL_REG (DR_REG_EXTMEM_BASE + 0x28) -/* EXTMEM_DCACHE_DATA_MEM_FORCE_PU : R/W ;bitpos:[18] ;default: 1'h1 ; */ -/*description: The bit is used to power L1-DCache data memory up. 0: follow rtc_lslp, 1: power -up.*/ -#define EXTMEM_DCACHE_DATA_MEM_FORCE_PU (BIT(18)) -#define EXTMEM_DCACHE_DATA_MEM_FORCE_PU_M (BIT(18)) -#define EXTMEM_DCACHE_DATA_MEM_FORCE_PU_V 0x1 -#define EXTMEM_DCACHE_DATA_MEM_FORCE_PU_S 18 -/* EXTMEM_DCACHE_DATA_MEM_FORCE_PD : R/W ;bitpos:[17] ;default: 1'h0 ; */ -/*description: The bit is used to power L1-DCache data memory down. 0: follow rtc_lslp, 1: powe -r down.*/ -#define EXTMEM_DCACHE_DATA_MEM_FORCE_PD (BIT(17)) -#define EXTMEM_DCACHE_DATA_MEM_FORCE_PD_M (BIT(17)) -#define EXTMEM_DCACHE_DATA_MEM_FORCE_PD_V 0x1 -#define EXTMEM_DCACHE_DATA_MEM_FORCE_PD_S 17 -/* EXTMEM_DCACHE_DATA_MEM_FORCE_ON : R/W ;bitpos:[16] ;default: 1'h1 ; */ -/*description: The bit is used to close clock gating of L1-DCache data memory. 1: close gating -, 0: open clock gating..*/ -#define EXTMEM_DCACHE_DATA_MEM_FORCE_ON (BIT(16)) -#define EXTMEM_DCACHE_DATA_MEM_FORCE_ON_M (BIT(16)) -#define EXTMEM_DCACHE_DATA_MEM_FORCE_ON_V 0x1 -#define EXTMEM_DCACHE_DATA_MEM_FORCE_ON_S 16 +#define EXTMEM_L1_CACHE_FREEZE_CTRL_REG (DR_REG_EXTMEM_BASE + 0x2C) +/* EXTMEM_L1_CACHE_FREEZE_DONE : RO ;bitpos:[18] ;default: 1'h0 ; */ +/*description: The bit is used to indicate whether freeze operation on L1-Cache is finished or +not. 0: not finished. 1: finished..*/ +#define EXTMEM_L1_CACHE_FREEZE_DONE (BIT(18)) +#define EXTMEM_L1_CACHE_FREEZE_DONE_M (BIT(18)) +#define EXTMEM_L1_CACHE_FREEZE_DONE_V 0x1 +#define EXTMEM_L1_CACHE_FREEZE_DONE_S 18 +/* EXTMEM_L1_CACHE_FREEZE_MODE : R/W ;bitpos:[17] ;default: 1'h0 ; */ +/*description: The bit is used to configure mode of freeze operation L1-Cache. 0: a miss-access + will not stuck. 1: a miss-access will stuck..*/ +#define EXTMEM_L1_CACHE_FREEZE_MODE (BIT(17)) +#define EXTMEM_L1_CACHE_FREEZE_MODE_M (BIT(17)) +#define EXTMEM_L1_CACHE_FREEZE_MODE_V 0x1 +#define EXTMEM_L1_CACHE_FREEZE_MODE_S 17 +/* EXTMEM_L1_CACHE_FREEZE_EN : R/W ;bitpos:[16] ;default: 1'h0 ; */ +/*description: The bit is used to enable freeze operation on L1-Cache. It can be cleared by sof +tware..*/ +#define EXTMEM_L1_CACHE_FREEZE_EN (BIT(16)) +#define EXTMEM_L1_CACHE_FREEZE_EN_M (BIT(16)) +#define EXTMEM_L1_CACHE_FREEZE_EN_V 0x1 +#define EXTMEM_L1_CACHE_FREEZE_EN_S 16 -#define EXTMEM_CACHE_FREEZE_CTRL_REG (DR_REG_EXTMEM_BASE + 0x2C) -/* EXTMEM_DCACHE_FREEZE_DONE : RO ;bitpos:[18] ;default: 1'h0 ; */ -/*description: The bit is used to indicate whether freeze operation on L1-DCache is finished or - not. 0: not finished. 1: finished..*/ -#define EXTMEM_DCACHE_FREEZE_DONE (BIT(18)) -#define EXTMEM_DCACHE_FREEZE_DONE_M (BIT(18)) -#define EXTMEM_DCACHE_FREEZE_DONE_V 0x1 -#define EXTMEM_DCACHE_FREEZE_DONE_S 18 -/* EXTMEM_DCACHE_FREEZE_MODE : R/W ;bitpos:[17] ;default: 1'h0 ; */ -/*description: The bit is used to configure mode of freeze operation L1-DCache. 0: a miss-acces -s will not stuck. 1: a miss-access will stuck..*/ -#define EXTMEM_DCACHE_FREEZE_MODE (BIT(17)) -#define EXTMEM_DCACHE_FREEZE_MODE_M (BIT(17)) -#define EXTMEM_DCACHE_FREEZE_MODE_V 0x1 -#define EXTMEM_DCACHE_FREEZE_MODE_S 17 -/* EXTMEM_DCACHE_FREEZE_EN : R/W ;bitpos:[16] ;default: 1'h0 ; */ -/*description: The bit is used to enable freeze operation on L1-DCache. It can be cleared by so -ftware..*/ -#define EXTMEM_DCACHE_FREEZE_EN (BIT(16)) -#define EXTMEM_DCACHE_FREEZE_EN_M (BIT(16)) -#define EXTMEM_DCACHE_FREEZE_EN_V 0x1 -#define EXTMEM_DCACHE_FREEZE_EN_S 16 - -#define EXTMEM_CACHE_DATA_MEM_ACS_CONF_REG (DR_REG_EXTMEM_BASE + 0x30) -/* EXTMEM_DCACHE_DATA_MEM_WR_EN : R/W ;bitpos:[17] ;default: 1'h1 ; */ -/*description: The bit is used to enable config-bus write L1-DCache data memoryory. 0: disable, - 1: enable..*/ -#define EXTMEM_DCACHE_DATA_MEM_WR_EN (BIT(17)) -#define EXTMEM_DCACHE_DATA_MEM_WR_EN_M (BIT(17)) -#define EXTMEM_DCACHE_DATA_MEM_WR_EN_V 0x1 -#define EXTMEM_DCACHE_DATA_MEM_WR_EN_S 17 -/* EXTMEM_DCACHE_DATA_MEM_RD_EN : R/W ;bitpos:[16] ;default: 1'h1 ; */ -/*description: The bit is used to enable config-bus read L1-DCache data memoryory. 0: disable, +#define EXTMEM_L1_CACHE_DATA_MEM_ACS_CONF_REG (DR_REG_EXTMEM_BASE + 0x30) +/* EXTMEM_L1_CACHE_DATA_MEM_WR_EN : R/W ;bitpos:[17] ;default: 1'h1 ; */ +/*description: The bit is used to enable config-bus write L1-Cache data memoryory. 0: disable, 1: enable..*/ -#define EXTMEM_DCACHE_DATA_MEM_RD_EN (BIT(16)) -#define EXTMEM_DCACHE_DATA_MEM_RD_EN_M (BIT(16)) -#define EXTMEM_DCACHE_DATA_MEM_RD_EN_V 0x1 -#define EXTMEM_DCACHE_DATA_MEM_RD_EN_S 16 - -#define EXTMEM_CACHE_TAG_MEM_ACS_CONF_REG (DR_REG_EXTMEM_BASE + 0x34) -/* EXTMEM_DCACHE_TAG_MEM_WR_EN : R/W ;bitpos:[17] ;default: 1'h1 ; */ -/*description: The bit is used to enable config-bus write L1-DCache tag memoryory. 0: disable, -1: enable..*/ -#define EXTMEM_DCACHE_TAG_MEM_WR_EN (BIT(17)) -#define EXTMEM_DCACHE_TAG_MEM_WR_EN_M (BIT(17)) -#define EXTMEM_DCACHE_TAG_MEM_WR_EN_V 0x1 -#define EXTMEM_DCACHE_TAG_MEM_WR_EN_S 17 -/* EXTMEM_DCACHE_TAG_MEM_RD_EN : R/W ;bitpos:[16] ;default: 1'h1 ; */ -/*description: The bit is used to enable config-bus read L1-DCache tag memoryory. 0: disable, 1 +#define EXTMEM_L1_CACHE_DATA_MEM_WR_EN (BIT(17)) +#define EXTMEM_L1_CACHE_DATA_MEM_WR_EN_M (BIT(17)) +#define EXTMEM_L1_CACHE_DATA_MEM_WR_EN_V 0x1 +#define EXTMEM_L1_CACHE_DATA_MEM_WR_EN_S 17 +/* EXTMEM_L1_CACHE_DATA_MEM_RD_EN : R/W ;bitpos:[16] ;default: 1'h1 ; */ +/*description: The bit is used to enable config-bus read L1-Cache data memoryory. 0: disable, 1 : enable..*/ -#define EXTMEM_DCACHE_TAG_MEM_RD_EN (BIT(16)) -#define EXTMEM_DCACHE_TAG_MEM_RD_EN_M (BIT(16)) -#define EXTMEM_DCACHE_TAG_MEM_RD_EN_V 0x1 -#define EXTMEM_DCACHE_TAG_MEM_RD_EN_S 16 +#define EXTMEM_L1_CACHE_DATA_MEM_RD_EN (BIT(16)) +#define EXTMEM_L1_CACHE_DATA_MEM_RD_EN_M (BIT(16)) +#define EXTMEM_L1_CACHE_DATA_MEM_RD_EN_V 0x1 +#define EXTMEM_L1_CACHE_DATA_MEM_RD_EN_S 16 -#define EXTMEM_DCACHE_PRELOCK_CONF_REG (DR_REG_EXTMEM_BASE + 0x78) -/* EXTMEM_DCACHE_PRELOCK_RGID : HRO ;bitpos:[5:2] ;default: 4'h0 ; */ -/*description: The bit is used to set the gid of l1 dcache prelock..*/ -#define EXTMEM_DCACHE_PRELOCK_RGID 0x0000000F -#define EXTMEM_DCACHE_PRELOCK_RGID_M ((EXTMEM_DCACHE_PRELOCK_RGID_V)<<(EXTMEM_DCACHE_PRELOCK_RGID_S)) -#define EXTMEM_DCACHE_PRELOCK_RGID_V 0xF -#define EXTMEM_DCACHE_PRELOCK_RGID_S 2 -/* EXTMEM_DCACHE_PRELOCK_SCT1_EN : R/W ;bitpos:[1] ;default: 1'h0 ; */ -/*description: The bit is used to enable the second section of prelock function on L1-DCache..*/ -#define EXTMEM_DCACHE_PRELOCK_SCT1_EN (BIT(1)) -#define EXTMEM_DCACHE_PRELOCK_SCT1_EN_M (BIT(1)) -#define EXTMEM_DCACHE_PRELOCK_SCT1_EN_V 0x1 -#define EXTMEM_DCACHE_PRELOCK_SCT1_EN_S 1 -/* EXTMEM_DCACHE_PRELOCK_SCT0_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */ -/*description: The bit is used to enable the first section of prelock function on L1-DCache..*/ -#define EXTMEM_DCACHE_PRELOCK_SCT0_EN (BIT(0)) -#define EXTMEM_DCACHE_PRELOCK_SCT0_EN_M (BIT(0)) -#define EXTMEM_DCACHE_PRELOCK_SCT0_EN_V 0x1 -#define EXTMEM_DCACHE_PRELOCK_SCT0_EN_S 0 +#define EXTMEM_L1_CACHE_TAG_MEM_ACS_CONF_REG (DR_REG_EXTMEM_BASE + 0x34) +/* EXTMEM_L1_CACHE_TAG_MEM_WR_EN : R/W ;bitpos:[17] ;default: 1'h1 ; */ +/*description: The bit is used to enable config-bus write L1-Cache tag memoryory. 0: disable, 1 +: enable..*/ +#define EXTMEM_L1_CACHE_TAG_MEM_WR_EN (BIT(17)) +#define EXTMEM_L1_CACHE_TAG_MEM_WR_EN_M (BIT(17)) +#define EXTMEM_L1_CACHE_TAG_MEM_WR_EN_V 0x1 +#define EXTMEM_L1_CACHE_TAG_MEM_WR_EN_S 17 +/* EXTMEM_L1_CACHE_TAG_MEM_RD_EN : R/W ;bitpos:[16] ;default: 1'h1 ; */ +/*description: The bit is used to enable config-bus read L1-Cache tag memoryory. 0: disable, 1: + enable..*/ +#define EXTMEM_L1_CACHE_TAG_MEM_RD_EN (BIT(16)) +#define EXTMEM_L1_CACHE_TAG_MEM_RD_EN_M (BIT(16)) +#define EXTMEM_L1_CACHE_TAG_MEM_RD_EN_V 0x1 +#define EXTMEM_L1_CACHE_TAG_MEM_RD_EN_S 16 -#define EXTMEM_DCACHE_PRELOCK_SCT0_ADDR_REG (DR_REG_EXTMEM_BASE + 0x7C) -/* EXTMEM_DCACHE_PRELOCK_SCT0_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +#define EXTMEM_L1_CACHE_PRELOCK_CONF_REG (DR_REG_EXTMEM_BASE + 0x78) +/* EXTMEM_L1_CACHE_PRELOCK_SCT1_EN : R/W ;bitpos:[1] ;default: 1'h0 ; */ +/*description: The bit is used to enable the second section of prelock function on L1-Cache..*/ +#define EXTMEM_L1_CACHE_PRELOCK_SCT1_EN (BIT(1)) +#define EXTMEM_L1_CACHE_PRELOCK_SCT1_EN_M (BIT(1)) +#define EXTMEM_L1_CACHE_PRELOCK_SCT1_EN_V 0x1 +#define EXTMEM_L1_CACHE_PRELOCK_SCT1_EN_S 1 +/* EXTMEM_L1_CACHE_PRELOCK_SCT0_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: The bit is used to enable the first section of prelock function on L1-Cache..*/ +#define EXTMEM_L1_CACHE_PRELOCK_SCT0_EN (BIT(0)) +#define EXTMEM_L1_CACHE_PRELOCK_SCT0_EN_M (BIT(0)) +#define EXTMEM_L1_CACHE_PRELOCK_SCT0_EN_V 0x1 +#define EXTMEM_L1_CACHE_PRELOCK_SCT0_EN_S 0 + +#define EXTMEM_L1_CACHE_PRELOCK_SCT0_ADDR_REG (DR_REG_EXTMEM_BASE + 0x7C) +/* EXTMEM_L1_CACHE_PRELOCK_SCT0_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ /*description: Those bits are used to configure the start virtual address of the first section -of prelock on L1-DCache, which should be used together with L1_DCACHE_PRELOCK_SC -T0_SIZE_REG.*/ -#define EXTMEM_DCACHE_PRELOCK_SCT0_ADDR 0xFFFFFFFF -#define EXTMEM_DCACHE_PRELOCK_SCT0_ADDR_M ((EXTMEM_DCACHE_PRELOCK_SCT0_ADDR_V)<<(EXTMEM_DCACHE_PRELOCK_SCT0_ADDR_S)) -#define EXTMEM_DCACHE_PRELOCK_SCT0_ADDR_V 0xFFFFFFFF -#define EXTMEM_DCACHE_PRELOCK_SCT0_ADDR_S 0 +of prelock on L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT0 +_SIZE_REG.*/ +#define EXTMEM_L1_CACHE_PRELOCK_SCT0_ADDR 0xFFFFFFFF +#define EXTMEM_L1_CACHE_PRELOCK_SCT0_ADDR_M ((EXTMEM_L1_CACHE_PRELOCK_SCT0_ADDR_V)<<(EXTMEM_L1_CACHE_PRELOCK_SCT0_ADDR_S)) +#define EXTMEM_L1_CACHE_PRELOCK_SCT0_ADDR_V 0xFFFFFFFF +#define EXTMEM_L1_CACHE_PRELOCK_SCT0_ADDR_S 0 -#define EXTMEM_DCACHE_PRELOCK_SCT1_ADDR_REG (DR_REG_EXTMEM_BASE + 0x80) -/* EXTMEM_DCACHE_PRELOCK_SCT1_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +#define EXTMEM_L1_CACHE_PRELOCK_SCT1_ADDR_REG (DR_REG_EXTMEM_BASE + 0x80) +/* EXTMEM_L1_CACHE_PRELOCK_SCT1_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ /*description: Those bits are used to configure the start virtual address of the second section - of prelock on L1-DCache, which should be used together with L1_DCACHE_PRELOCK_S -CT1_SIZE_REG.*/ -#define EXTMEM_DCACHE_PRELOCK_SCT1_ADDR 0xFFFFFFFF -#define EXTMEM_DCACHE_PRELOCK_SCT1_ADDR_M ((EXTMEM_DCACHE_PRELOCK_SCT1_ADDR_V)<<(EXTMEM_DCACHE_PRELOCK_SCT1_ADDR_S)) -#define EXTMEM_DCACHE_PRELOCK_SCT1_ADDR_V 0xFFFFFFFF -#define EXTMEM_DCACHE_PRELOCK_SCT1_ADDR_S 0 + of prelock on L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT +1_SIZE_REG.*/ +#define EXTMEM_L1_CACHE_PRELOCK_SCT1_ADDR 0xFFFFFFFF +#define EXTMEM_L1_CACHE_PRELOCK_SCT1_ADDR_M ((EXTMEM_L1_CACHE_PRELOCK_SCT1_ADDR_V)<<(EXTMEM_L1_CACHE_PRELOCK_SCT1_ADDR_S)) +#define EXTMEM_L1_CACHE_PRELOCK_SCT1_ADDR_V 0xFFFFFFFF +#define EXTMEM_L1_CACHE_PRELOCK_SCT1_ADDR_S 0 -#define EXTMEM_DCACHE_PRELOCK_SCT_SIZE_REG (DR_REG_EXTMEM_BASE + 0x84) -/* EXTMEM_DCACHE_PRELOCK_SCT1_SIZE : R/W ;bitpos:[29:16] ;default: 14'h3fff ; */ +#define EXTMEM_L1_CACHE_PRELOCK_SCT_SIZE_REG (DR_REG_EXTMEM_BASE + 0x84) +/* EXTMEM_L1_CACHE_PRELOCK_SCT1_SIZE : R/W ;bitpos:[29:16] ;default: 14'h3fff ; */ /*description: Those bits are used to configure the size of the second section of prelock on L1 --DCache, which should be used together with L1_DCACHE_PRELOCK_SCT1_ADDR_REG.*/ -#define EXTMEM_DCACHE_PRELOCK_SCT1_SIZE 0x00003FFF -#define EXTMEM_DCACHE_PRELOCK_SCT1_SIZE_M ((EXTMEM_DCACHE_PRELOCK_SCT1_SIZE_V)<<(EXTMEM_DCACHE_PRELOCK_SCT1_SIZE_S)) -#define EXTMEM_DCACHE_PRELOCK_SCT1_SIZE_V 0x3FFF -#define EXTMEM_DCACHE_PRELOCK_SCT1_SIZE_S 16 -/* EXTMEM_DCACHE_PRELOCK_SCT0_SIZE : R/W ;bitpos:[13:0] ;default: 14'h3fff ; */ +-Cache, which should be used together with L1_CACHE_PRELOCK_SCT1_ADDR_REG.*/ +#define EXTMEM_L1_CACHE_PRELOCK_SCT1_SIZE 0x00003FFF +#define EXTMEM_L1_CACHE_PRELOCK_SCT1_SIZE_M ((EXTMEM_L1_CACHE_PRELOCK_SCT1_SIZE_V)<<(EXTMEM_L1_CACHE_PRELOCK_SCT1_SIZE_S)) +#define EXTMEM_L1_CACHE_PRELOCK_SCT1_SIZE_V 0x3FFF +#define EXTMEM_L1_CACHE_PRELOCK_SCT1_SIZE_S 16 +/* EXTMEM_L1_CACHE_PRELOCK_SCT0_SIZE : R/W ;bitpos:[13:0] ;default: 14'h3fff ; */ /*description: Those bits are used to configure the size of the first section of prelock on L1- -DCache, which should be used together with L1_DCACHE_PRELOCK_SCT0_ADDR_REG.*/ -#define EXTMEM_DCACHE_PRELOCK_SCT0_SIZE 0x00003FFF -#define EXTMEM_DCACHE_PRELOCK_SCT0_SIZE_M ((EXTMEM_DCACHE_PRELOCK_SCT0_SIZE_V)<<(EXTMEM_DCACHE_PRELOCK_SCT0_SIZE_S)) -#define EXTMEM_DCACHE_PRELOCK_SCT0_SIZE_V 0x3FFF -#define EXTMEM_DCACHE_PRELOCK_SCT0_SIZE_S 0 +Cache, which should be used together with L1_CACHE_PRELOCK_SCT0_ADDR_REG.*/ +#define EXTMEM_L1_CACHE_PRELOCK_SCT0_SIZE 0x00003FFF +#define EXTMEM_L1_CACHE_PRELOCK_SCT0_SIZE_M ((EXTMEM_L1_CACHE_PRELOCK_SCT0_SIZE_V)<<(EXTMEM_L1_CACHE_PRELOCK_SCT0_SIZE_S)) +#define EXTMEM_L1_CACHE_PRELOCK_SCT0_SIZE_V 0x3FFF +#define EXTMEM_L1_CACHE_PRELOCK_SCT0_SIZE_S 0 -#define EXTMEM_CACHE_LOCK_CTRL_REG (DR_REG_EXTMEM_BASE + 0x88) -/* EXTMEM_CACHE_LOCK_RGID : HRO ;bitpos:[6:3] ;default: 4'h0 ; */ -/*description: The bit is used to set the gid of cache lock/unlock..*/ -#define EXTMEM_CACHE_LOCK_RGID 0x0000000F -#define EXTMEM_CACHE_LOCK_RGID_M ((EXTMEM_CACHE_LOCK_RGID_V)<<(EXTMEM_CACHE_LOCK_RGID_S)) -#define EXTMEM_CACHE_LOCK_RGID_V 0xF -#define EXTMEM_CACHE_LOCK_RGID_S 3 -/* EXTMEM_CACHE_LOCK_DONE : RO ;bitpos:[2] ;default: 1'h1 ; */ +#define EXTMEM_L1_CACHE_LOCK_CTRL_REG (DR_REG_EXTMEM_BASE + 0x88) +/* EXTMEM_L1_CACHE_LOCK_DONE : RO ;bitpos:[2] ;default: 1'h1 ; */ /*description: The bit is used to indicate whether unlock/lock operation is finished or not. 0: not finished. 1: finished..*/ -#define EXTMEM_CACHE_LOCK_DONE (BIT(2)) -#define EXTMEM_CACHE_LOCK_DONE_M (BIT(2)) -#define EXTMEM_CACHE_LOCK_DONE_V 0x1 -#define EXTMEM_CACHE_LOCK_DONE_S 2 -/* EXTMEM_CACHE_UNLOCK_ENA : R/W/SC ;bitpos:[1] ;default: 1'h0 ; */ +#define EXTMEM_L1_CACHE_LOCK_DONE (BIT(2)) +#define EXTMEM_L1_CACHE_LOCK_DONE_M (BIT(2)) +#define EXTMEM_L1_CACHE_LOCK_DONE_V 0x1 +#define EXTMEM_L1_CACHE_LOCK_DONE_S 2 +/* EXTMEM_L1_CACHE_UNLOCK_ENA : R/W/SC ;bitpos:[1] ;default: 1'h0 ; */ /*description: The bit is used to enable unlock operation. It will be cleared by hardware after - unlock operation done. Note that (1) this bit and lock_ena bit are mutually exc -lusive, that is, those bits can not be set to 1 at the same time. (2) unlock ope -ration can be applied on L1-ICache, L1-DCache and L2-Cache..*/ -#define EXTMEM_CACHE_UNLOCK_ENA (BIT(1)) -#define EXTMEM_CACHE_UNLOCK_ENA_M (BIT(1)) -#define EXTMEM_CACHE_UNLOCK_ENA_V 0x1 -#define EXTMEM_CACHE_UNLOCK_ENA_S 1 -/* EXTMEM_CACHE_LOCK_ENA : R/W/SC ;bitpos:[0] ;default: 1'h0 ; */ + unlock operation done.*/ +#define EXTMEM_L1_CACHE_UNLOCK_ENA (BIT(1)) +#define EXTMEM_L1_CACHE_UNLOCK_ENA_M (BIT(1)) +#define EXTMEM_L1_CACHE_UNLOCK_ENA_V 0x1 +#define EXTMEM_L1_CACHE_UNLOCK_ENA_S 1 +/* EXTMEM_L1_CACHE_LOCK_ENA : R/W/SC ;bitpos:[0] ;default: 1'h0 ; */ /*description: The bit is used to enable lock operation. It will be cleared by hardware after l -ock operation done. Note that (1) this bit and unlock_ena bit are mutually exclu -sive, that is, those bits can not be set to 1 at the same time. (2) lock operati -on can be applied on LL1-ICache, L1-DCache and L2-Cache..*/ -#define EXTMEM_CACHE_LOCK_ENA (BIT(0)) -#define EXTMEM_CACHE_LOCK_ENA_M (BIT(0)) -#define EXTMEM_CACHE_LOCK_ENA_V 0x1 -#define EXTMEM_CACHE_LOCK_ENA_S 0 +ock operation done.*/ +#define EXTMEM_L1_CACHE_LOCK_ENA (BIT(0)) +#define EXTMEM_L1_CACHE_LOCK_ENA_M (BIT(0)) +#define EXTMEM_L1_CACHE_LOCK_ENA_V 0x1 +#define EXTMEM_L1_CACHE_LOCK_ENA_S 0 -#define EXTMEM_CACHE_LOCK_MAP_REG (DR_REG_EXTMEM_BASE + 0x8C) -/* EXTMEM_CACHE_LOCK_MAP : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +#define EXTMEM_L1_CACHE_LOCK_MAP_REG (DR_REG_EXTMEM_BASE + 0x8C) +/* EXTMEM_L1_CACHE_LOCK_MAP : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: Those bits are used to indicate which caches in the two-level cache structure wi -ll apply this lock/unlock operation. [0]: L1-ICache0, [1]: L1-ICache1, [2]: L1-I -Cache2, [3]: L1-ICache3, [4]: L1-DCache, [5]: L2-Cache..*/ -#define EXTMEM_CACHE_LOCK_MAP 0x0000003F -#define EXTMEM_CACHE_LOCK_MAP_M ((EXTMEM_CACHE_LOCK_MAP_V)<<(EXTMEM_CACHE_LOCK_MAP_S)) -#define EXTMEM_CACHE_LOCK_MAP_V 0x3F -#define EXTMEM_CACHE_LOCK_MAP_S 0 +ll apply this lock/unlock operation. [4]: L1-Cache.*/ +#define EXTMEM_L1_CACHE_LOCK_MAP 0x0000003F +#define EXTMEM_L1_CACHE_LOCK_MAP_M ((EXTMEM_L1_CACHE_LOCK_MAP_V)<<(EXTMEM_L1_CACHE_LOCK_MAP_S)) +#define EXTMEM_L1_CACHE_LOCK_MAP_V 0x3F +#define EXTMEM_L1_CACHE_LOCK_MAP_S 0 -#define EXTMEM_CACHE_LOCK_ADDR_REG (DR_REG_EXTMEM_BASE + 0x90) -/* EXTMEM_CACHE_LOCK_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +#define EXTMEM_L1_CACHE_LOCK_ADDR_REG (DR_REG_EXTMEM_BASE + 0x90) +/* EXTMEM_L1_CACHE_LOCK_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ /*description: Those bits are used to configure the start virtual address of the lock/unlock op eration, which should be used together with CACHE_LOCK_SIZE_REG.*/ -#define EXTMEM_CACHE_LOCK_ADDR 0xFFFFFFFF -#define EXTMEM_CACHE_LOCK_ADDR_M ((EXTMEM_CACHE_LOCK_ADDR_V)<<(EXTMEM_CACHE_LOCK_ADDR_S)) -#define EXTMEM_CACHE_LOCK_ADDR_V 0xFFFFFFFF -#define EXTMEM_CACHE_LOCK_ADDR_S 0 +#define EXTMEM_L1_CACHE_LOCK_ADDR 0xFFFFFFFF +#define EXTMEM_L1_CACHE_LOCK_ADDR_M ((EXTMEM_L1_CACHE_LOCK_ADDR_V)<<(EXTMEM_L1_CACHE_LOCK_ADDR_S)) +#define EXTMEM_L1_CACHE_LOCK_ADDR_V 0xFFFFFFFF +#define EXTMEM_L1_CACHE_LOCK_ADDR_S 0 -#define EXTMEM_CACHE_LOCK_SIZE_REG (DR_REG_EXTMEM_BASE + 0x94) -/* EXTMEM_CACHE_LOCK_SIZE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ +#define EXTMEM_L1_CACHE_LOCK_SIZE_REG (DR_REG_EXTMEM_BASE + 0x94) +/* EXTMEM_L1_CACHE_LOCK_SIZE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ /*description: Those bits are used to configure the size of the lock/unlock operation, which sh ould be used together with CACHE_LOCK_ADDR_REG.*/ -#define EXTMEM_CACHE_LOCK_SIZE 0x0000FFFF -#define EXTMEM_CACHE_LOCK_SIZE_M ((EXTMEM_CACHE_LOCK_SIZE_V)<<(EXTMEM_CACHE_LOCK_SIZE_S)) -#define EXTMEM_CACHE_LOCK_SIZE_V 0xFFFF -#define EXTMEM_CACHE_LOCK_SIZE_S 0 +#define EXTMEM_L1_CACHE_LOCK_SIZE 0x0000FFFF +#define EXTMEM_L1_CACHE_LOCK_SIZE_M ((EXTMEM_L1_CACHE_LOCK_SIZE_V)<<(EXTMEM_L1_CACHE_LOCK_SIZE_S)) +#define EXTMEM_L1_CACHE_LOCK_SIZE_V 0xFFFF +#define EXTMEM_L1_CACHE_LOCK_SIZE_S 0 -#define EXTMEM_CACHE_SYNC_CTRL_REG (DR_REG_EXTMEM_BASE + 0x98) -/* EXTMEM_CACHE_SYNC_RGID : HRO ;bitpos:[8:5] ;default: 4'h0 ; */ -/*description: The bit is used to set the gid of cache sync operation (invalidate, clean, writ -eback, writeback_invalidate).*/ -#define EXTMEM_CACHE_SYNC_RGID 0x0000000F -#define EXTMEM_CACHE_SYNC_RGID_M ((EXTMEM_CACHE_SYNC_RGID_V)<<(EXTMEM_CACHE_SYNC_RGID_S)) -#define EXTMEM_CACHE_SYNC_RGID_V 0xF -#define EXTMEM_CACHE_SYNC_RGID_S 5 -/* EXTMEM_CACHE_SYNC_DONE : RO ;bitpos:[4] ;default: 1'h0 ; */ +#define EXTMEM_L1_CACHE_SYNC_CTRL_REG (DR_REG_EXTMEM_BASE + 0x98) +/* EXTMEM_L1_CACHE_SYNC_DONE : RO ;bitpos:[4] ;default: 1'h0 ; */ /*description: The bit is used to indicate whether sync operation (invalidate, clean, writeback , writeback_invalidate) is finished or not. 0: not finished. 1: finished..*/ -#define EXTMEM_CACHE_SYNC_DONE (BIT(4)) -#define EXTMEM_CACHE_SYNC_DONE_M (BIT(4)) -#define EXTMEM_CACHE_SYNC_DONE_V 0x1 -#define EXTMEM_CACHE_SYNC_DONE_S 4 -/* EXTMEM_CACHE_WRITEBACK_INVALIDATE_ENA : R/W/SC ;bitpos:[3] ;default: 1'h0 ; */ +#define EXTMEM_L1_CACHE_SYNC_DONE (BIT(4)) +#define EXTMEM_L1_CACHE_SYNC_DONE_M (BIT(4)) +#define EXTMEM_L1_CACHE_SYNC_DONE_V 0x1 +#define EXTMEM_L1_CACHE_SYNC_DONE_S 4 +/* EXTMEM_L1_CACHE_WRITEBACK_INVALIDATE_ENA : R/W/SC ;bitpos:[3] ;default: 1'h0 ; */ /*description: The bit is used to enable writeback-invalidate operation. It will be cleared by hardware after writeback-invalidate operation done. Note that this bit and the o ther sync-bits (invalidate_ena, clean_ena, writeback_ena) are mutually exclusive , that is, those bits can not be set to 1 at the same time..*/ -#define EXTMEM_CACHE_WRITEBACK_INVALIDATE_ENA (BIT(3)) -#define EXTMEM_CACHE_WRITEBACK_INVALIDATE_ENA_M (BIT(3)) -#define EXTMEM_CACHE_WRITEBACK_INVALIDATE_ENA_V 0x1 -#define EXTMEM_CACHE_WRITEBACK_INVALIDATE_ENA_S 3 -/* EXTMEM_CACHE_WRITEBACK_ENA : R/W/SC ;bitpos:[2] ;default: 1'h0 ; */ +#define EXTMEM_L1_CACHE_WRITEBACK_INVALIDATE_ENA (BIT(3)) +#define EXTMEM_L1_CACHE_WRITEBACK_INVALIDATE_ENA_M (BIT(3)) +#define EXTMEM_L1_CACHE_WRITEBACK_INVALIDATE_ENA_V 0x1 +#define EXTMEM_L1_CACHE_WRITEBACK_INVALIDATE_ENA_S 3 +/* EXTMEM_L1_CACHE_WRITEBACK_ENA : R/W/SC ;bitpos:[2] ;default: 1'h0 ; */ /*description: The bit is used to enable writeback operation. It will be cleared by hardware af ter writeback operation done. Note that this bit and the other sync-bits (invali date_ena, clean_ena, writeback_invalidate_ena) are mutually exclusive, that is, those bits can not be set to 1 at the same time..*/ -#define EXTMEM_CACHE_WRITEBACK_ENA (BIT(2)) -#define EXTMEM_CACHE_WRITEBACK_ENA_M (BIT(2)) -#define EXTMEM_CACHE_WRITEBACK_ENA_V 0x1 -#define EXTMEM_CACHE_WRITEBACK_ENA_S 2 -/* EXTMEM_CACHE_CLEAN_ENA : R/W/SC ;bitpos:[1] ;default: 1'h0 ; */ +#define EXTMEM_L1_CACHE_WRITEBACK_ENA (BIT(2)) +#define EXTMEM_L1_CACHE_WRITEBACK_ENA_M (BIT(2)) +#define EXTMEM_L1_CACHE_WRITEBACK_ENA_V 0x1 +#define EXTMEM_L1_CACHE_WRITEBACK_ENA_S 2 +/* EXTMEM_L1_CACHE_CLEAN_ENA : R/W/SC ;bitpos:[1] ;default: 1'h0 ; */ /*description: The bit is used to enable clean operation. It will be cleared by hardware after clean operation done. Note that this bit and the other sync-bits (invalidate_ena , writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is, thos e bits can not be set to 1 at the same time..*/ -#define EXTMEM_CACHE_CLEAN_ENA (BIT(1)) -#define EXTMEM_CACHE_CLEAN_ENA_M (BIT(1)) -#define EXTMEM_CACHE_CLEAN_ENA_V 0x1 -#define EXTMEM_CACHE_CLEAN_ENA_S 1 -/* EXTMEM_CACHE_INVALIDATE_ENA : R/W/SC ;bitpos:[0] ;default: 1'h1 ; */ +#define EXTMEM_L1_CACHE_CLEAN_ENA (BIT(1)) +#define EXTMEM_L1_CACHE_CLEAN_ENA_M (BIT(1)) +#define EXTMEM_L1_CACHE_CLEAN_ENA_V 0x1 +#define EXTMEM_L1_CACHE_CLEAN_ENA_S 1 +/* EXTMEM_L1_CACHE_INVALIDATE_ENA : R/W/SC ;bitpos:[0] ;default: 1'h1 ; */ /*description: The bit is used to enable invalidate operation. It will be cleared by hardware a fter invalidate operation done. Note that this bit and the other sync-bits (clea n_ena, writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is, those bits can not be set to 1 at the same time..*/ -#define EXTMEM_CACHE_INVALIDATE_ENA (BIT(0)) -#define EXTMEM_CACHE_INVALIDATE_ENA_M (BIT(0)) -#define EXTMEM_CACHE_INVALIDATE_ENA_V 0x1 -#define EXTMEM_CACHE_INVALIDATE_ENA_S 0 +#define EXTMEM_L1_CACHE_INVALIDATE_ENA (BIT(0)) +#define EXTMEM_L1_CACHE_INVALIDATE_ENA_M (BIT(0)) +#define EXTMEM_L1_CACHE_INVALIDATE_ENA_V 0x1 +#define EXTMEM_L1_CACHE_INVALIDATE_ENA_S 0 -#define EXTMEM_CACHE_SYNC_MAP_REG (DR_REG_EXTMEM_BASE + 0x9C) -/* EXTMEM_CACHE_SYNC_MAP : R/W ;bitpos:[5:0] ;default: 6'h3f ; */ +#define EXTMEM_L1_CACHE_SYNC_MAP_REG (DR_REG_EXTMEM_BASE + 0x9C) +/* EXTMEM_L1_CACHE_SYNC_MAP : R/W ;bitpos:[5:0] ;default: 6'h3f ; */ /*description: Those bits are used to indicate which caches in the two-level cache structure wi -ll apply the sync operation. [0]: L1-ICache0, [1]: L1-ICache1, [2]: L1-ICache2, -[3]: L1-ICache3, [4]: L1-DCache, [5]: L2-Cache..*/ -#define EXTMEM_CACHE_SYNC_MAP 0x0000003F -#define EXTMEM_CACHE_SYNC_MAP_M ((EXTMEM_CACHE_SYNC_MAP_V)<<(EXTMEM_CACHE_SYNC_MAP_S)) -#define EXTMEM_CACHE_SYNC_MAP_V 0x3F -#define EXTMEM_CACHE_SYNC_MAP_S 0 +ll apply the sync operation. [4]: L1-Cache.*/ +#define EXTMEM_L1_CACHE_SYNC_MAP 0x0000003F +#define EXTMEM_L1_CACHE_SYNC_MAP_M ((EXTMEM_L1_CACHE_SYNC_MAP_V)<<(EXTMEM_L1_CACHE_SYNC_MAP_S)) +#define EXTMEM_L1_CACHE_SYNC_MAP_V 0x3F +#define EXTMEM_L1_CACHE_SYNC_MAP_S 0 -#define EXTMEM_CACHE_SYNC_ADDR_REG (DR_REG_EXTMEM_BASE + 0xA0) -/* EXTMEM_CACHE_SYNC_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +#define EXTMEM_L1_CACHE_SYNC_ADDR_REG (DR_REG_EXTMEM_BASE + 0xA0) +/* EXTMEM_L1_CACHE_SYNC_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ /*description: Those bits are used to configure the start virtual address of the sync operation , which should be used together with CACHE_SYNC_SIZE_REG.*/ -#define EXTMEM_CACHE_SYNC_ADDR 0xFFFFFFFF -#define EXTMEM_CACHE_SYNC_ADDR_M ((EXTMEM_CACHE_SYNC_ADDR_V)<<(EXTMEM_CACHE_SYNC_ADDR_S)) -#define EXTMEM_CACHE_SYNC_ADDR_V 0xFFFFFFFF -#define EXTMEM_CACHE_SYNC_ADDR_S 0 +#define EXTMEM_L1_CACHE_SYNC_ADDR 0xFFFFFFFF +#define EXTMEM_L1_CACHE_SYNC_ADDR_M ((EXTMEM_L1_CACHE_SYNC_ADDR_V)<<(EXTMEM_L1_CACHE_SYNC_ADDR_S)) +#define EXTMEM_L1_CACHE_SYNC_ADDR_V 0xFFFFFFFF +#define EXTMEM_L1_CACHE_SYNC_ADDR_S 0 -#define EXTMEM_CACHE_SYNC_SIZE_REG (DR_REG_EXTMEM_BASE + 0xA4) -/* EXTMEM_CACHE_SYNC_SIZE : R/W ;bitpos:[23:0] ;default: 24'h0 ; */ +#define EXTMEM_L1_CACHE_SYNC_SIZE_REG (DR_REG_EXTMEM_BASE + 0xA4) +/* EXTMEM_L1_CACHE_SYNC_SIZE : R/W ;bitpos:[23:0] ;default: 24'h0 ; */ /*description: Those bits are used to configure the size of the sync operation, which should be used together with CACHE_SYNC_ADDR_REG.*/ -#define EXTMEM_CACHE_SYNC_SIZE 0x00FFFFFF -#define EXTMEM_CACHE_SYNC_SIZE_M ((EXTMEM_CACHE_SYNC_SIZE_V)<<(EXTMEM_CACHE_SYNC_SIZE_S)) -#define EXTMEM_CACHE_SYNC_SIZE_V 0xFFFFFF -#define EXTMEM_CACHE_SYNC_SIZE_S 0 +#define EXTMEM_L1_CACHE_SYNC_SIZE 0x00FFFFFF +#define EXTMEM_L1_CACHE_SYNC_SIZE_M ((EXTMEM_L1_CACHE_SYNC_SIZE_V)<<(EXTMEM_L1_CACHE_SYNC_SIZE_S)) +#define EXTMEM_L1_CACHE_SYNC_SIZE_V 0xFFFFFF +#define EXTMEM_L1_CACHE_SYNC_SIZE_S 0 -#define EXTMEM_DCACHE_PRELOAD_CTRL_REG (DR_REG_EXTMEM_BASE + 0xD8) -/* EXTMEM_DCACHE_PRELOAD_RGID : HRO ;bitpos:[6:3] ;default: 4'h0 ; */ -/*description: The bit is used to set the gid of l1 dcache preload..*/ -#define EXTMEM_DCACHE_PRELOAD_RGID 0x0000000F -#define EXTMEM_DCACHE_PRELOAD_RGID_M ((EXTMEM_DCACHE_PRELOAD_RGID_V)<<(EXTMEM_DCACHE_PRELOAD_RGID_S)) -#define EXTMEM_DCACHE_PRELOAD_RGID_V 0xF -#define EXTMEM_DCACHE_PRELOAD_RGID_S 3 -/* EXTMEM_DCACHE_PRELOAD_ORDER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +#define EXTMEM_L1_CACHE_PRELOAD_CTRL_REG (DR_REG_EXTMEM_BASE + 0xD8) +/* EXTMEM_L1_CACHE_PRELOAD_RGID : HRO ;bitpos:[6:3] ;default: 4'h0 ; */ +/*description: The bit is used to set the gid of l1 cache preload..*/ +#define EXTMEM_L1_CACHE_PRELOAD_RGID 0x0000000F +#define EXTMEM_L1_CACHE_PRELOAD_RGID_M ((EXTMEM_L1_CACHE_PRELOAD_RGID_V)<<(EXTMEM_L1_CACHE_PRELOAD_RGID_S)) +#define EXTMEM_L1_CACHE_PRELOAD_RGID_V 0xF +#define EXTMEM_L1_CACHE_PRELOAD_RGID_S 3 +/* EXTMEM_L1_CACHE_PRELOAD_ORDER : R/W ;bitpos:[2] ;default: 1'h0 ; */ /*description: The bit is used to configure the direction of preload operation. 0: ascending, 1 : descending..*/ -#define EXTMEM_DCACHE_PRELOAD_ORDER (BIT(2)) -#define EXTMEM_DCACHE_PRELOAD_ORDER_M (BIT(2)) -#define EXTMEM_DCACHE_PRELOAD_ORDER_V 0x1 -#define EXTMEM_DCACHE_PRELOAD_ORDER_S 2 -/* EXTMEM_DCACHE_PRELOAD_DONE : RO ;bitpos:[1] ;default: 1'h1 ; */ +#define EXTMEM_L1_CACHE_PRELOAD_ORDER (BIT(2)) +#define EXTMEM_L1_CACHE_PRELOAD_ORDER_M (BIT(2)) +#define EXTMEM_L1_CACHE_PRELOAD_ORDER_V 0x1 +#define EXTMEM_L1_CACHE_PRELOAD_ORDER_S 2 +/* EXTMEM_L1_CACHE_PRELOAD_DONE : RO ;bitpos:[1] ;default: 1'h1 ; */ /*description: The bit is used to indicate whether preload operation is finished or not. 0: not finished. 1: finished..*/ -#define EXTMEM_DCACHE_PRELOAD_DONE (BIT(1)) -#define EXTMEM_DCACHE_PRELOAD_DONE_M (BIT(1)) -#define EXTMEM_DCACHE_PRELOAD_DONE_V 0x1 -#define EXTMEM_DCACHE_PRELOAD_DONE_S 1 -/* EXTMEM_DCACHE_PRELOAD_ENA : R/W/SC ;bitpos:[0] ;default: 1'h0 ; */ -/*description: The bit is used to enable preload operation on L1-DCache. It will be cleared by -hardware automatically after preload operation is done..*/ -#define EXTMEM_DCACHE_PRELOAD_ENA (BIT(0)) -#define EXTMEM_DCACHE_PRELOAD_ENA_M (BIT(0)) -#define EXTMEM_DCACHE_PRELOAD_ENA_V 0x1 -#define EXTMEM_DCACHE_PRELOAD_ENA_S 0 +#define EXTMEM_L1_CACHE_PRELOAD_DONE (BIT(1)) +#define EXTMEM_L1_CACHE_PRELOAD_DONE_M (BIT(1)) +#define EXTMEM_L1_CACHE_PRELOAD_DONE_V 0x1 +#define EXTMEM_L1_CACHE_PRELOAD_DONE_S 1 +/* EXTMEM_L1_CACHE_PRELOAD_ENA : R/W/SC ;bitpos:[0] ;default: 1'h0 ; */ +/*description: The bit is used to enable preload operation on L1-Cache. It will be cleared by h +ardware automatically after preload operation is done..*/ +#define EXTMEM_L1_CACHE_PRELOAD_ENA (BIT(0)) +#define EXTMEM_L1_CACHE_PRELOAD_ENA_M (BIT(0)) +#define EXTMEM_L1_CACHE_PRELOAD_ENA_V 0x1 +#define EXTMEM_L1_CACHE_PRELOAD_ENA_S 0 -#define EXTMEM_DCACHE_PRELOAD_ADDR_REG (DR_REG_EXTMEM_BASE + 0xDC) -/* EXTMEM_DCACHE_PRELOAD_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Those bits are used to configure the start virtual address of preload on L1-DCac -he, which should be used together with L1_DCACHE_PRELOAD_SIZE_REG.*/ -#define EXTMEM_DCACHE_PRELOAD_ADDR 0xFFFFFFFF -#define EXTMEM_DCACHE_PRELOAD_ADDR_M ((EXTMEM_DCACHE_PRELOAD_ADDR_V)<<(EXTMEM_DCACHE_PRELOAD_ADDR_S)) -#define EXTMEM_DCACHE_PRELOAD_ADDR_V 0xFFFFFFFF -#define EXTMEM_DCACHE_PRELOAD_ADDR_S 0 +#define EXTMEM_L1_DCACHE_PRELOAD_ADDR_REG (DR_REG_EXTMEM_BASE + 0xDC) +/* EXTMEM_L1_CACHE_PRELOAD_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Those bits are used to configure the start virtual address of preload on L1-Cach +e, which should be used together with L1_CACHE_PRELOAD_SIZE_REG.*/ +#define EXTMEM_L1_CACHE_PRELOAD_ADDR 0xFFFFFFFF +#define EXTMEM_L1_CACHE_PRELOAD_ADDR_M ((EXTMEM_L1_CACHE_PRELOAD_ADDR_V)<<(EXTMEM_L1_CACHE_PRELOAD_ADDR_S)) +#define EXTMEM_L1_CACHE_PRELOAD_ADDR_V 0xFFFFFFFF +#define EXTMEM_L1_CACHE_PRELOAD_ADDR_S 0 -#define EXTMEM_DCACHE_PRELOAD_SIZE_REG (DR_REG_EXTMEM_BASE + 0xE0) -/* EXTMEM_DCACHE_PRELOAD_SIZE : R/W ;bitpos:[13:0] ;default: 14'h0 ; */ +#define EXTMEM_L1_DCACHE_PRELOAD_SIZE_REG (DR_REG_EXTMEM_BASE + 0xE0) +/* EXTMEM_L1_CACHE_PRELOAD_SIZE : R/W ;bitpos:[13:0] ;default: 14'h0 ; */ /*description: Those bits are used to configure the size of the first section of prelock on L1- -DCache, which should be used together with L1_DCACHE_PRELOAD_ADDR_REG.*/ -#define EXTMEM_DCACHE_PRELOAD_SIZE 0x00003FFF -#define EXTMEM_DCACHE_PRELOAD_SIZE_M ((EXTMEM_DCACHE_PRELOAD_SIZE_V)<<(EXTMEM_DCACHE_PRELOAD_SIZE_S)) -#define EXTMEM_DCACHE_PRELOAD_SIZE_V 0x3FFF -#define EXTMEM_DCACHE_PRELOAD_SIZE_S 0 +Cache, which should be used together with L1_CACHE_PRELOAD_ADDR_REG.*/ +#define EXTMEM_L1_CACHE_PRELOAD_SIZE 0x00003FFF +#define EXTMEM_L1_CACHE_PRELOAD_SIZE_M ((EXTMEM_L1_CACHE_PRELOAD_SIZE_V)<<(EXTMEM_L1_CACHE_PRELOAD_SIZE_S)) +#define EXTMEM_L1_CACHE_PRELOAD_SIZE_V 0x3FFF +#define EXTMEM_L1_CACHE_PRELOAD_SIZE_S 0 -#define EXTMEM_DCACHE_AUTOLOAD_CTRL_REG (DR_REG_EXTMEM_BASE + 0x134) -/* EXTMEM_DCACHE_AUTOLOAD_SCT1_ENA : R/W ;bitpos:[9] ;default: 1'h0 ; */ -/*description: The bit is used to enable the second section for autoload operation on L1-DCache -..*/ -#define EXTMEM_DCACHE_AUTOLOAD_SCT1_ENA (BIT(9)) -#define EXTMEM_DCACHE_AUTOLOAD_SCT1_ENA_M (BIT(9)) -#define EXTMEM_DCACHE_AUTOLOAD_SCT1_ENA_V 0x1 -#define EXTMEM_DCACHE_AUTOLOAD_SCT1_ENA_S 9 -/* EXTMEM_DCACHE_AUTOLOAD_SCT0_ENA : R/W ;bitpos:[8] ;default: 1'h0 ; */ -/*description: The bit is used to enable the first section for autoload operation on L1-DCache..*/ -#define EXTMEM_DCACHE_AUTOLOAD_SCT0_ENA (BIT(8)) -#define EXTMEM_DCACHE_AUTOLOAD_SCT0_ENA_M (BIT(8)) -#define EXTMEM_DCACHE_AUTOLOAD_SCT0_ENA_V 0x1 -#define EXTMEM_DCACHE_AUTOLOAD_SCT0_ENA_S 8 -/* EXTMEM_DCACHE_AUTOLOAD_TRIGGER_MODE : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ -/*description: The field is used to configure trigger mode of autoload operation on L1-DCache. -0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger..*/ -#define EXTMEM_DCACHE_AUTOLOAD_TRIGGER_MODE 0x00000003 -#define EXTMEM_DCACHE_AUTOLOAD_TRIGGER_MODE_M ((EXTMEM_DCACHE_AUTOLOAD_TRIGGER_MODE_V)<<(EXTMEM_DCACHE_AUTOLOAD_TRIGGER_MODE_S)) -#define EXTMEM_DCACHE_AUTOLOAD_TRIGGER_MODE_V 0x3 -#define EXTMEM_DCACHE_AUTOLOAD_TRIGGER_MODE_S 3 -/* EXTMEM_DCACHE_AUTOLOAD_ORDER : R/W ;bitpos:[2] ;default: 1'h0 ; */ -/*description: The bit is used to configure the direction of autoload operation on L1-DCache. 0 -: ascending. 1: descending..*/ -#define EXTMEM_DCACHE_AUTOLOAD_ORDER (BIT(2)) -#define EXTMEM_DCACHE_AUTOLOAD_ORDER_M (BIT(2)) -#define EXTMEM_DCACHE_AUTOLOAD_ORDER_V 0x1 -#define EXTMEM_DCACHE_AUTOLOAD_ORDER_S 2 -/* EXTMEM_DCACHE_AUTOLOAD_DONE : RO ;bitpos:[1] ;default: 1'h1 ; */ -/*description: The bit is used to indicate whether autoload operation on L1-DCache is finished -or not. 0: not finished. 1: finished..*/ -#define EXTMEM_DCACHE_AUTOLOAD_DONE (BIT(1)) -#define EXTMEM_DCACHE_AUTOLOAD_DONE_M (BIT(1)) -#define EXTMEM_DCACHE_AUTOLOAD_DONE_V 0x1 -#define EXTMEM_DCACHE_AUTOLOAD_DONE_S 1 -/* EXTMEM_DCACHE_AUTOLOAD_ENA : R/W ;bitpos:[0] ;default: 1'h0 ; */ -/*description: The bit is used to enable and disable autoload operation on L1-DCache. 1: enabl -e, 0: disable..*/ -#define EXTMEM_DCACHE_AUTOLOAD_ENA (BIT(0)) -#define EXTMEM_DCACHE_AUTOLOAD_ENA_M (BIT(0)) -#define EXTMEM_DCACHE_AUTOLOAD_ENA_V 0x1 -#define EXTMEM_DCACHE_AUTOLOAD_ENA_S 0 +#define EXTMEM_L1_CACHE_AUTOLOAD_CTRL_REG (DR_REG_EXTMEM_BASE + 0x134) +/* EXTMEM_L1_CACHE_AUTOLOAD_SCT1_ENA : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: The bit is used to enable the second section for autoload operation on L1-Cache..*/ +#define EXTMEM_L1_CACHE_AUTOLOAD_SCT1_ENA (BIT(9)) +#define EXTMEM_L1_CACHE_AUTOLOAD_SCT1_ENA_M (BIT(9)) +#define EXTMEM_L1_CACHE_AUTOLOAD_SCT1_ENA_V 0x1 +#define EXTMEM_L1_CACHE_AUTOLOAD_SCT1_ENA_S 9 +/* EXTMEM_L1_CACHE_AUTOLOAD_SCT0_ENA : R/W ;bitpos:[8] ;default: 1'h0 ; */ +/*description: The bit is used to enable the first section for autoload operation on L1-Cache..*/ +#define EXTMEM_L1_CACHE_AUTOLOAD_SCT0_ENA (BIT(8)) +#define EXTMEM_L1_CACHE_AUTOLOAD_SCT0_ENA_M (BIT(8)) +#define EXTMEM_L1_CACHE_AUTOLOAD_SCT0_ENA_V 0x1 +#define EXTMEM_L1_CACHE_AUTOLOAD_SCT0_ENA_S 8 +/* EXTMEM_L1_CACHE_AUTOLOAD_TRIGGER_MODE : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: The field is used to configure trigger mode of autoload operation on L1-Cache. 0 +/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger..*/ +#define EXTMEM_L1_CACHE_AUTOLOAD_TRIGGER_MODE 0x00000003 +#define EXTMEM_L1_CACHE_AUTOLOAD_TRIGGER_MODE_M ((EXTMEM_L1_CACHE_AUTOLOAD_TRIGGER_MODE_V)<<(EXTMEM_L1_CACHE_AUTOLOAD_TRIGGER_MODE_S)) +#define EXTMEM_L1_CACHE_AUTOLOAD_TRIGGER_MODE_V 0x3 +#define EXTMEM_L1_CACHE_AUTOLOAD_TRIGGER_MODE_S 3 +/* EXTMEM_L1_CACHE_AUTOLOAD_ORDER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: The bit is used to configure the direction of autoload operation on L1-Cache. 0: + ascending. 1: descending..*/ +#define EXTMEM_L1_CACHE_AUTOLOAD_ORDER (BIT(2)) +#define EXTMEM_L1_CACHE_AUTOLOAD_ORDER_M (BIT(2)) +#define EXTMEM_L1_CACHE_AUTOLOAD_ORDER_V 0x1 +#define EXTMEM_L1_CACHE_AUTOLOAD_ORDER_S 2 +/* EXTMEM_L1_CACHE_AUTOLOAD_DONE : RO ;bitpos:[1] ;default: 1'h1 ; */ +/*description: The bit is used to indicate whether autoload operation on L1-Cache is finished o +r not. 0: not finished. 1: finished..*/ +#define EXTMEM_L1_CACHE_AUTOLOAD_DONE (BIT(1)) +#define EXTMEM_L1_CACHE_AUTOLOAD_DONE_M (BIT(1)) +#define EXTMEM_L1_CACHE_AUTOLOAD_DONE_V 0x1 +#define EXTMEM_L1_CACHE_AUTOLOAD_DONE_S 1 +/* EXTMEM_L1_CACHE_AUTOLOAD_ENA : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: The bit is used to enable and disable autoload operation on L1-Cache. 1: enable +, 0: disable..*/ +#define EXTMEM_L1_CACHE_AUTOLOAD_ENA (BIT(0)) +#define EXTMEM_L1_CACHE_AUTOLOAD_ENA_M (BIT(0)) +#define EXTMEM_L1_CACHE_AUTOLOAD_ENA_V 0x1 +#define EXTMEM_L1_CACHE_AUTOLOAD_ENA_S 0 -#define EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR_REG (DR_REG_EXTMEM_BASE + 0x138) -/* EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +#define EXTMEM_L1_CACHE_AUTOLOAD_SCT0_ADDR_REG (DR_REG_EXTMEM_BASE + 0x138) +/* EXTMEM_L1_CACHE_AUTOLOAD_SCT0_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ /*description: Those bits are used to configure the start virtual address of the first section -for autoload operation on L1-DCache. Note that it should be used together with L -1_DCACHE_AUTOLOAD_SCT0_SIZE and L1_DCACHE_AUTOLOAD_SCT0_ENA..*/ -#define EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR 0xFFFFFFFF -#define EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR_M ((EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR_V)<<(EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR_S)) -#define EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR_V 0xFFFFFFFF -#define EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR_S 0 +for autoload operation on L1-Cache. Note that it should be used together with L1 +_CACHE_AUTOLOAD_SCT0_SIZE and L1_CACHE_AUTOLOAD_SCT0_ENA..*/ +#define EXTMEM_L1_CACHE_AUTOLOAD_SCT0_ADDR 0xFFFFFFFF +#define EXTMEM_L1_CACHE_AUTOLOAD_SCT0_ADDR_M ((EXTMEM_L1_CACHE_AUTOLOAD_SCT0_ADDR_V)<<(EXTMEM_L1_CACHE_AUTOLOAD_SCT0_ADDR_S)) +#define EXTMEM_L1_CACHE_AUTOLOAD_SCT0_ADDR_V 0xFFFFFFFF +#define EXTMEM_L1_CACHE_AUTOLOAD_SCT0_ADDR_S 0 -#define EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE_REG (DR_REG_EXTMEM_BASE + 0x13C) -/* EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE : R/W ;bitpos:[27:0] ;default: 28'h0 ; */ +#define EXTMEM_L1_CACHE_AUTOLOAD_SCT0_SIZE_REG (DR_REG_EXTMEM_BASE + 0x13C) +/* EXTMEM_L1_CACHE_AUTOLOAD_SCT0_SIZE : R/W ;bitpos:[27:0] ;default: 28'h0 ; */ /*description: Those bits are used to configure the size of the first section for autoload oper -ation on L1-DCache. Note that it should be used together with L1_DCACHE_AUTOLOAD -_SCT0_ADDR and L1_DCACHE_AUTOLOAD_SCT0_ENA..*/ -#define EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE 0x0FFFFFFF -#define EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE_M ((EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE_V)<<(EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE_S)) -#define EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE_V 0xFFFFFFF -#define EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE_S 0 +ation on L1-Cache. Note that it should be used together with L1_CACHE_AUTOLOAD_S +CT0_ADDR and L1_CACHE_AUTOLOAD_SCT0_ENA..*/ +#define EXTMEM_L1_CACHE_AUTOLOAD_SCT0_SIZE 0x0FFFFFFF +#define EXTMEM_L1_CACHE_AUTOLOAD_SCT0_SIZE_M ((EXTMEM_L1_CACHE_AUTOLOAD_SCT0_SIZE_V)<<(EXTMEM_L1_CACHE_AUTOLOAD_SCT0_SIZE_S)) +#define EXTMEM_L1_CACHE_AUTOLOAD_SCT0_SIZE_V 0xFFFFFFF +#define EXTMEM_L1_CACHE_AUTOLOAD_SCT0_SIZE_S 0 -#define EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR_REG (DR_REG_EXTMEM_BASE + 0x140) -/* EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +#define EXTMEM_L1_CACHE_AUTOLOAD_SCT1_ADDR_REG (DR_REG_EXTMEM_BASE + 0x140) +/* EXTMEM_L1_CACHE_AUTOLOAD_SCT1_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ /*description: Those bits are used to configure the start virtual address of the second section - for autoload operation on L1-DCache. Note that it should be used together with -L1_DCACHE_AUTOLOAD_SCT1_SIZE and L1_DCACHE_AUTOLOAD_SCT1_ENA..*/ -#define EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR 0xFFFFFFFF -#define EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR_M ((EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR_V)<<(EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR_S)) -#define EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR_V 0xFFFFFFFF -#define EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR_S 0 + for autoload operation on L1-Cache. Note that it should be used together with L +1_CACHE_AUTOLOAD_SCT1_SIZE and L1_CACHE_AUTOLOAD_SCT1_ENA..*/ +#define EXTMEM_L1_CACHE_AUTOLOAD_SCT1_ADDR 0xFFFFFFFF +#define EXTMEM_L1_CACHE_AUTOLOAD_SCT1_ADDR_M ((EXTMEM_L1_CACHE_AUTOLOAD_SCT1_ADDR_V)<<(EXTMEM_L1_CACHE_AUTOLOAD_SCT1_ADDR_S)) +#define EXTMEM_L1_CACHE_AUTOLOAD_SCT1_ADDR_V 0xFFFFFFFF +#define EXTMEM_L1_CACHE_AUTOLOAD_SCT1_ADDR_S 0 -#define EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE_REG (DR_REG_EXTMEM_BASE + 0x144) -/* EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE : R/W ;bitpos:[27:0] ;default: 28'h0 ; */ +#define EXTMEM_L1_CACHE_AUTOLOAD_SCT1_SIZE_REG (DR_REG_EXTMEM_BASE + 0x144) +/* EXTMEM_L1_CACHE_AUTOLOAD_SCT1_SIZE : R/W ;bitpos:[27:0] ;default: 28'h0 ; */ /*description: Those bits are used to configure the size of the second section for autoload ope -ration on L1-DCache. Note that it should be used together with L1_DCACHE_AUTOLOA -D_SCT1_ADDR and L1_DCACHE_AUTOLOAD_SCT1_ENA..*/ -#define EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE 0x0FFFFFFF -#define EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE_M ((EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE_V)<<(EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE_S)) -#define EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE_V 0xFFFFFFF -#define EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE_S 0 +ration on L1-Cache. Note that it should be used together with L1_CACHE_AUTOLOAD_ +SCT1_ADDR and L1_CACHE_AUTOLOAD_SCT1_ENA..*/ +#define EXTMEM_L1_CACHE_AUTOLOAD_SCT1_SIZE 0x0FFFFFFF +#define EXTMEM_L1_CACHE_AUTOLOAD_SCT1_SIZE_M ((EXTMEM_L1_CACHE_AUTOLOAD_SCT1_SIZE_V)<<(EXTMEM_L1_CACHE_AUTOLOAD_SCT1_SIZE_S)) +#define EXTMEM_L1_CACHE_AUTOLOAD_SCT1_SIZE_V 0xFFFFFFF +#define EXTMEM_L1_CACHE_AUTOLOAD_SCT1_SIZE_S 0 -#define EXTMEM_CACHE_ACS_CNT_INT_ENA_REG (DR_REG_EXTMEM_BASE + 0x158) -/* EXTMEM_DBUS1_OVF_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ +#define EXTMEM_L1_CACHE_ACS_CNT_INT_ENA_REG (DR_REG_EXTMEM_BASE + 0x158) +/* EXTMEM_L1_DBUS_OVF_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ /*description: The bit is used to enable interrupt of one of counters overflow that occurs in L 1-DCache due to bus1 accesses L1-DCache..*/ -#define EXTMEM_DBUS1_OVF_INT_ENA (BIT(5)) -#define EXTMEM_DBUS1_OVF_INT_ENA_M (BIT(5)) -#define EXTMEM_DBUS1_OVF_INT_ENA_V 0x1 -#define EXTMEM_DBUS1_OVF_INT_ENA_S 5 -/* EXTMEM_DBUS0_OVF_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +#define EXTMEM_L1_DBUS_OVF_INT_ENA (BIT(5)) +#define EXTMEM_L1_DBUS_OVF_INT_ENA_M (BIT(5)) +#define EXTMEM_L1_DBUS_OVF_INT_ENA_V 0x1 +#define EXTMEM_L1_DBUS_OVF_INT_ENA_S 5 +/* EXTMEM_L1_IBUS_OVF_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ /*description: The bit is used to enable interrupt of one of counters overflow that occurs in L 1-DCache due to bus0 accesses L1-DCache..*/ -#define EXTMEM_DBUS0_OVF_INT_ENA (BIT(4)) -#define EXTMEM_DBUS0_OVF_INT_ENA_M (BIT(4)) -#define EXTMEM_DBUS0_OVF_INT_ENA_V 0x1 -#define EXTMEM_DBUS0_OVF_INT_ENA_S 4 +#define EXTMEM_L1_IBUS_OVF_INT_ENA (BIT(4)) +#define EXTMEM_L1_IBUS_OVF_INT_ENA_M (BIT(4)) +#define EXTMEM_L1_IBUS_OVF_INT_ENA_V 0x1 +#define EXTMEM_L1_IBUS_OVF_INT_ENA_S 4 -#define EXTMEM_CACHE_ACS_CNT_INT_CLR_REG (DR_REG_EXTMEM_BASE + 0x15C) -/* EXTMEM_DBUS1_OVF_INT_CLR : WT ;bitpos:[5] ;default: 1'b0 ; */ +#define EXTMEM_L1_CACHE_ACS_CNT_INT_CLR_REG (DR_REG_EXTMEM_BASE + 0x15C) +/* EXTMEM_L1_DBUS_OVF_INT_CLR : WT ;bitpos:[5] ;default: 1'b0 ; */ /*description: The bit is used to clear counters overflow interrupt and counters in L1-DCache d ue to bus1 accesses L1-DCache..*/ -#define EXTMEM_DBUS1_OVF_INT_CLR (BIT(5)) -#define EXTMEM_DBUS1_OVF_INT_CLR_M (BIT(5)) -#define EXTMEM_DBUS1_OVF_INT_CLR_V 0x1 -#define EXTMEM_DBUS1_OVF_INT_CLR_S 5 -/* EXTMEM_DBUS0_OVF_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */ +#define EXTMEM_L1_DBUS_OVF_INT_CLR (BIT(5)) +#define EXTMEM_L1_DBUS_OVF_INT_CLR_M (BIT(5)) +#define EXTMEM_L1_DBUS_OVF_INT_CLR_V 0x1 +#define EXTMEM_L1_DBUS_OVF_INT_CLR_S 5 +/* EXTMEM_L1_IBUS_OVF_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */ /*description: The bit is used to clear counters overflow interrupt and counters in L1-DCache d ue to bus0 accesses L1-DCache..*/ -#define EXTMEM_DBUS0_OVF_INT_CLR (BIT(4)) -#define EXTMEM_DBUS0_OVF_INT_CLR_M (BIT(4)) -#define EXTMEM_DBUS0_OVF_INT_CLR_V 0x1 -#define EXTMEM_DBUS0_OVF_INT_CLR_S 4 +#define EXTMEM_L1_IBUS_OVF_INT_CLR (BIT(4)) +#define EXTMEM_L1_IBUS_OVF_INT_CLR_M (BIT(4)) +#define EXTMEM_L1_IBUS_OVF_INT_CLR_V 0x1 +#define EXTMEM_L1_IBUS_OVF_INT_CLR_S 4 -#define EXTMEM_CACHE_ACS_CNT_INT_RAW_REG (DR_REG_EXTMEM_BASE + 0x160) -/* EXTMEM_DBUS1_OVF_INT_RAW : R/WTC/SS ;bitpos:[5] ;default: 1'b0 ; */ +#define EXTMEM_L1_CACHE_ACS_CNT_INT_RAW_REG (DR_REG_EXTMEM_BASE + 0x160) +/* EXTMEM_L1_DBUS_OVF_INT_RAW : R/WTC/SS ;bitpos:[5] ;default: 1'b0 ; */ /*description: The raw bit of the interrupt of one of counters overflow that occurs in L1-DCach e due to bus1 accesses L1-DCache..*/ -#define EXTMEM_DBUS1_OVF_INT_RAW (BIT(5)) -#define EXTMEM_DBUS1_OVF_INT_RAW_M (BIT(5)) -#define EXTMEM_DBUS1_OVF_INT_RAW_V 0x1 -#define EXTMEM_DBUS1_OVF_INT_RAW_S 5 -/* EXTMEM_DBUS0_OVF_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */ +#define EXTMEM_L1_DBUS_OVF_INT_RAW (BIT(5)) +#define EXTMEM_L1_DBUS_OVF_INT_RAW_M (BIT(5)) +#define EXTMEM_L1_DBUS_OVF_INT_RAW_V 0x1 +#define EXTMEM_L1_DBUS_OVF_INT_RAW_S 5 +/* EXTMEM_L1_IBUS_OVF_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */ /*description: The raw bit of the interrupt of one of counters overflow that occurs in L1-DCach e due to bus0 accesses L1-DCache..*/ -#define EXTMEM_DBUS0_OVF_INT_RAW (BIT(4)) -#define EXTMEM_DBUS0_OVF_INT_RAW_M (BIT(4)) -#define EXTMEM_DBUS0_OVF_INT_RAW_V 0x1 -#define EXTMEM_DBUS0_OVF_INT_RAW_S 4 +#define EXTMEM_L1_IBUS_OVF_INT_RAW (BIT(4)) +#define EXTMEM_L1_IBUS_OVF_INT_RAW_M (BIT(4)) +#define EXTMEM_L1_IBUS_OVF_INT_RAW_V 0x1 +#define EXTMEM_L1_IBUS_OVF_INT_RAW_S 4 -#define EXTMEM_CACHE_ACS_CNT_INT_ST_REG (DR_REG_EXTMEM_BASE + 0x164) -/* EXTMEM_DBUS1_OVF_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ +#define EXTMEM_L1_CACHE_ACS_CNT_INT_ST_REG (DR_REG_EXTMEM_BASE + 0x164) +/* EXTMEM_L1_DBUS_OVF_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ /*description: The bit indicates the interrupt status of one of counters overflow that occurs i n L1-DCache due to bus1 accesses L1-DCache..*/ -#define EXTMEM_DBUS1_OVF_INT_ST (BIT(5)) -#define EXTMEM_DBUS1_OVF_INT_ST_M (BIT(5)) -#define EXTMEM_DBUS1_OVF_INT_ST_V 0x1 -#define EXTMEM_DBUS1_OVF_INT_ST_S 5 -/* EXTMEM_DBUS0_OVF_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ +#define EXTMEM_L1_DBUS_OVF_INT_ST (BIT(5)) +#define EXTMEM_L1_DBUS_OVF_INT_ST_M (BIT(5)) +#define EXTMEM_L1_DBUS_OVF_INT_ST_V 0x1 +#define EXTMEM_L1_DBUS_OVF_INT_ST_S 5 +/* EXTMEM_L1_IBUS_OVF_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ /*description: The bit indicates the interrupt status of one of counters overflow that occurs i n L1-DCache due to bus0 accesses L1-DCache..*/ -#define EXTMEM_DBUS0_OVF_INT_ST (BIT(4)) -#define EXTMEM_DBUS0_OVF_INT_ST_M (BIT(4)) -#define EXTMEM_DBUS0_OVF_INT_ST_V 0x1 -#define EXTMEM_DBUS0_OVF_INT_ST_S 4 +#define EXTMEM_L1_IBUS_OVF_INT_ST (BIT(4)) +#define EXTMEM_L1_IBUS_OVF_INT_ST_M (BIT(4)) +#define EXTMEM_L1_IBUS_OVF_INT_ST_V 0x1 +#define EXTMEM_L1_IBUS_OVF_INT_ST_S 4 -#define EXTMEM_CACHE_ACS_FAIL_INT_ENA_REG (DR_REG_EXTMEM_BASE + 0x168) -/* EXTMEM_DCACHE_FAIL_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +#define EXTMEM_L1_CACHE_ACS_FAIL_INT_ENA_REG (DR_REG_EXTMEM_BASE + 0x168) +/* EXTMEM_L1_CACHE_FAIL_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ /*description: The bit is used to enable interrupt of access fail that occurs in L1-DCache due to cpu accesses L1-DCache..*/ -#define EXTMEM_DCACHE_FAIL_INT_ENA (BIT(4)) -#define EXTMEM_DCACHE_FAIL_INT_ENA_M (BIT(4)) -#define EXTMEM_DCACHE_FAIL_INT_ENA_V 0x1 -#define EXTMEM_DCACHE_FAIL_INT_ENA_S 4 +#define EXTMEM_L1_CACHE_FAIL_INT_ENA (BIT(4)) +#define EXTMEM_L1_CACHE_FAIL_INT_ENA_M (BIT(4)) +#define EXTMEM_L1_CACHE_FAIL_INT_ENA_V 0x1 +#define EXTMEM_L1_CACHE_FAIL_INT_ENA_S 4 -#define EXTMEM_CACHE_ACS_FAIL_INT_CLR_REG (DR_REG_EXTMEM_BASE + 0x16C) -/* EXTMEM_DCACHE_FAIL_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */ +#define EXTMEM_L1_CACHE_ACS_FAIL_INT_CLR_REG (DR_REG_EXTMEM_BASE + 0x16C) +/* EXTMEM_L1_CACHE_FAIL_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */ /*description: The bit is used to clear interrupt of access fail that occurs in L1-DCache due t o cpu accesses L1-DCache..*/ -#define EXTMEM_DCACHE_FAIL_INT_CLR (BIT(4)) -#define EXTMEM_DCACHE_FAIL_INT_CLR_M (BIT(4)) -#define EXTMEM_DCACHE_FAIL_INT_CLR_V 0x1 -#define EXTMEM_DCACHE_FAIL_INT_CLR_S 4 +#define EXTMEM_L1_CACHE_FAIL_INT_CLR (BIT(4)) +#define EXTMEM_L1_CACHE_FAIL_INT_CLR_M (BIT(4)) +#define EXTMEM_L1_CACHE_FAIL_INT_CLR_V 0x1 +#define EXTMEM_L1_CACHE_FAIL_INT_CLR_S 4 -#define EXTMEM_CACHE_ACS_FAIL_INT_RAW_REG (DR_REG_EXTMEM_BASE + 0x170) -/* EXTMEM_DCACHE_FAIL_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */ +#define EXTMEM_L1_CACHE_ACS_FAIL_INT_RAW_REG (DR_REG_EXTMEM_BASE + 0x170) +/* EXTMEM_L1_CACHE_FAIL_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */ /*description: The raw bit of the interrupt of access fail that occurs in L1-DCache..*/ -#define EXTMEM_DCACHE_FAIL_INT_RAW (BIT(4)) -#define EXTMEM_DCACHE_FAIL_INT_RAW_M (BIT(4)) -#define EXTMEM_DCACHE_FAIL_INT_RAW_V 0x1 -#define EXTMEM_DCACHE_FAIL_INT_RAW_S 4 +#define EXTMEM_L1_CACHE_FAIL_INT_RAW (BIT(4)) +#define EXTMEM_L1_CACHE_FAIL_INT_RAW_M (BIT(4)) +#define EXTMEM_L1_CACHE_FAIL_INT_RAW_V 0x1 +#define EXTMEM_L1_CACHE_FAIL_INT_RAW_S 4 -#define EXTMEM_CACHE_ACS_FAIL_INT_ST_REG (DR_REG_EXTMEM_BASE + 0x174) -/* EXTMEM_DCACHE_FAIL_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ +#define EXTMEM_L1_CACHE_ACS_FAIL_INT_ST_REG (DR_REG_EXTMEM_BASE + 0x174) +/* EXTMEM_L1_CACHE_FAIL_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ /*description: The bit indicates the interrupt status of access fail that occurs in L1-DCache d ue to cpu accesses L1-DCache..*/ -#define EXTMEM_DCACHE_FAIL_INT_ST (BIT(4)) -#define EXTMEM_DCACHE_FAIL_INT_ST_M (BIT(4)) -#define EXTMEM_DCACHE_FAIL_INT_ST_V 0x1 -#define EXTMEM_DCACHE_FAIL_INT_ST_S 4 +#define EXTMEM_L1_CACHE_FAIL_INT_ST (BIT(4)) +#define EXTMEM_L1_CACHE_FAIL_INT_ST_M (BIT(4)) +#define EXTMEM_L1_CACHE_FAIL_INT_ST_V 0x1 +#define EXTMEM_L1_CACHE_FAIL_INT_ST_S 4 -#define EXTMEM_CACHE_ACS_CNT_CTRL_REG (DR_REG_EXTMEM_BASE + 0x178) -/* EXTMEM_DBUS1_CNT_CLR : WT ;bitpos:[21] ;default: 1'b0 ; */ +#define EXTMEM_L1_CACHE_ACS_CNT_CTRL_REG (DR_REG_EXTMEM_BASE + 0x178) +/* EXTMEM_L1_DBUS_CNT_CLR : WT ;bitpos:[21] ;default: 1'b0 ; */ /*description: The bit is used to clear dbus1 counter in L1-DCache..*/ -#define EXTMEM_DBUS1_CNT_CLR (BIT(21)) -#define EXTMEM_DBUS1_CNT_CLR_M (BIT(21)) -#define EXTMEM_DBUS1_CNT_CLR_V 0x1 -#define EXTMEM_DBUS1_CNT_CLR_S 21 -/* EXTMEM_DBUS0_CNT_CLR : WT ;bitpos:[20] ;default: 1'b0 ; */ +#define EXTMEM_L1_DBUS_CNT_CLR (BIT(21)) +#define EXTMEM_L1_DBUS_CNT_CLR_M (BIT(21)) +#define EXTMEM_L1_DBUS_CNT_CLR_V 0x1 +#define EXTMEM_L1_DBUS_CNT_CLR_S 21 +/* EXTMEM_L1_IBUS_CNT_CLR : WT ;bitpos:[20] ;default: 1'b0 ; */ /*description: The bit is used to clear dbus0 counter in L1-DCache..*/ -#define EXTMEM_DBUS0_CNT_CLR (BIT(20)) -#define EXTMEM_DBUS0_CNT_CLR_M (BIT(20)) -#define EXTMEM_DBUS0_CNT_CLR_V 0x1 -#define EXTMEM_DBUS0_CNT_CLR_S 20 -/* EXTMEM_DBUS1_CNT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ +#define EXTMEM_L1_IBUS_CNT_CLR (BIT(20)) +#define EXTMEM_L1_IBUS_CNT_CLR_M (BIT(20)) +#define EXTMEM_L1_IBUS_CNT_CLR_V 0x1 +#define EXTMEM_L1_IBUS_CNT_CLR_S 20 +/* EXTMEM_L1_DBUS_CNT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ /*description: The bit is used to enable dbus1 counter in L1-DCache..*/ -#define EXTMEM_DBUS1_CNT_ENA (BIT(5)) -#define EXTMEM_DBUS1_CNT_ENA_M (BIT(5)) -#define EXTMEM_DBUS1_CNT_ENA_V 0x1 -#define EXTMEM_DBUS1_CNT_ENA_S 5 -/* EXTMEM_DBUS0_CNT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +#define EXTMEM_L1_DBUS_CNT_ENA (BIT(5)) +#define EXTMEM_L1_DBUS_CNT_ENA_M (BIT(5)) +#define EXTMEM_L1_DBUS_CNT_ENA_V 0x1 +#define EXTMEM_L1_DBUS_CNT_ENA_S 5 +/* EXTMEM_L1_IBUS_CNT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ /*description: The bit is used to enable dbus0 counter in L1-DCache..*/ -#define EXTMEM_DBUS0_CNT_ENA (BIT(4)) -#define EXTMEM_DBUS0_CNT_ENA_M (BIT(4)) -#define EXTMEM_DBUS0_CNT_ENA_V 0x1 -#define EXTMEM_DBUS0_CNT_ENA_S 4 +#define EXTMEM_L1_IBUS_CNT_ENA (BIT(4)) +#define EXTMEM_L1_IBUS_CNT_ENA_M (BIT(4)) +#define EXTMEM_L1_IBUS_CNT_ENA_V 0x1 +#define EXTMEM_L1_IBUS_CNT_ENA_S 4 -#define EXTMEM_DBUS0_ACS_HIT_CNT_REG (DR_REG_EXTMEM_BASE + 0x1BC) -/* EXTMEM_DBUS0_HIT_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The register records the number of hits when bus0 accesses L1-DCache..*/ -#define EXTMEM_DBUS0_HIT_CNT 0xFFFFFFFF -#define EXTMEM_DBUS0_HIT_CNT_M ((EXTMEM_DBUS0_HIT_CNT_V)<<(EXTMEM_DBUS0_HIT_CNT_S)) -#define EXTMEM_DBUS0_HIT_CNT_V 0xFFFFFFFF -#define EXTMEM_DBUS0_HIT_CNT_S 0 +#define EXTMEM_L1_IBUS_ACS_HIT_CNT_REG (DR_REG_EXTMEM_BASE + 0x1BC) +/* EXTMEM_L1_IBUS_HIT_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The register records the number of hits when bus0 accesses L1-Cache..*/ +#define EXTMEM_L1_IBUS_HIT_CNT 0xFFFFFFFF +#define EXTMEM_L1_IBUS_HIT_CNT_M ((EXTMEM_L1_IBUS_HIT_CNT_V)<<(EXTMEM_L1_IBUS_HIT_CNT_S)) +#define EXTMEM_L1_IBUS_HIT_CNT_V 0xFFFFFFFF +#define EXTMEM_L1_IBUS_HIT_CNT_S 0 -#define EXTMEM_DBUS0_ACS_MISS_CNT_REG (DR_REG_EXTMEM_BASE + 0x1C0) -/* EXTMEM_DBUS0_MISS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The register records the number of missing when bus0 accesses L1-DCache..*/ -#define EXTMEM_DBUS0_MISS_CNT 0xFFFFFFFF -#define EXTMEM_DBUS0_MISS_CNT_M ((EXTMEM_DBUS0_MISS_CNT_V)<<(EXTMEM_DBUS0_MISS_CNT_S)) -#define EXTMEM_DBUS0_MISS_CNT_V 0xFFFFFFFF -#define EXTMEM_DBUS0_MISS_CNT_S 0 +#define EXTMEM_L1_IBUS_ACS_MISS_CNT_REG (DR_REG_EXTMEM_BASE + 0x1C0) +/* EXTMEM_L1_IBUS_MISS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The register records the number of missing when bus0 accesses L1-Cache..*/ +#define EXTMEM_L1_IBUS_MISS_CNT 0xFFFFFFFF +#define EXTMEM_L1_IBUS_MISS_CNT_M ((EXTMEM_L1_IBUS_MISS_CNT_V)<<(EXTMEM_L1_IBUS_MISS_CNT_S)) +#define EXTMEM_L1_IBUS_MISS_CNT_V 0xFFFFFFFF +#define EXTMEM_L1_IBUS_MISS_CNT_S 0 -#define EXTMEM_DBUS0_ACS_CONFLICT_CNT_REG (DR_REG_EXTMEM_BASE + 0x1C4) -/* EXTMEM_DBUS0_CONFLICT_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The register records the number of access-conflicts when bus0 accesses L1-DCache +#define EXTMEM_L1_IBUS_ACS_CONFLICT_CNT_REG (DR_REG_EXTMEM_BASE + 0x1C4) +/* EXTMEM_L1_IBUS_CONFLICT_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The register records the number of access-conflicts when bus0 accesses L1-Cache..*/ +#define EXTMEM_L1_IBUS_CONFLICT_CNT 0xFFFFFFFF +#define EXTMEM_L1_IBUS_CONFLICT_CNT_M ((EXTMEM_L1_IBUS_CONFLICT_CNT_V)<<(EXTMEM_L1_IBUS_CONFLICT_CNT_S)) +#define EXTMEM_L1_IBUS_CONFLICT_CNT_V 0xFFFFFFFF +#define EXTMEM_L1_IBUS_CONFLICT_CNT_S 0 + +#define EXTMEM_L1_IBUS_ACS_NXTLVL_CNT_REG (DR_REG_EXTMEM_BASE + 0x1C8) +/* EXTMEM_L1_IBUS_NXTLVL_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The register records the number of times that L1-Cache accesses L2-Cache due to +bus0 accessing L1-Cache..*/ +#define EXTMEM_L1_IBUS_NXTLVL_CNT 0xFFFFFFFF +#define EXTMEM_L1_IBUS_NXTLVL_CNT_M ((EXTMEM_L1_IBUS_NXTLVL_CNT_V)<<(EXTMEM_L1_IBUS_NXTLVL_CNT_S)) +#define EXTMEM_L1_IBUS_NXTLVL_CNT_V 0xFFFFFFFF +#define EXTMEM_L1_IBUS_NXTLVL_CNT_S 0 + +#define EXTMEM_L1_DBUS_ACS_HIT_CNT_REG (DR_REG_EXTMEM_BASE + 0x1CC) +/* EXTMEM_L1_DBUS_HIT_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The register records the number of hits when bus1 accesses L1-Cache..*/ +#define EXTMEM_L1_DBUS_HIT_CNT 0xFFFFFFFF +#define EXTMEM_L1_DBUS_HIT_CNT_M ((EXTMEM_L1_DBUS_HIT_CNT_V)<<(EXTMEM_L1_DBUS_HIT_CNT_S)) +#define EXTMEM_L1_DBUS_HIT_CNT_V 0xFFFFFFFF +#define EXTMEM_L1_DBUS_HIT_CNT_S 0 + +#define EXTMEM_L1_DBUS_ACS_MISS_CNT_REG (DR_REG_EXTMEM_BASE + 0x1D0) +/* EXTMEM_L1_DBUS_MISS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The register records the number of missing when bus1 accesses L1-Cache..*/ +#define EXTMEM_L1_DBUS_MISS_CNT 0xFFFFFFFF +#define EXTMEM_L1_DBUS_MISS_CNT_M ((EXTMEM_L1_DBUS_MISS_CNT_V)<<(EXTMEM_L1_DBUS_MISS_CNT_S)) +#define EXTMEM_L1_DBUS_MISS_CNT_V 0xFFFFFFFF +#define EXTMEM_L1_DBUS_MISS_CNT_S 0 + +#define EXTMEM_L1_DBUS_ACS_CONFLICT_CNT_REG (DR_REG_EXTMEM_BASE + 0x1D4) +/* EXTMEM_L1_DBUS_CONFLICT_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The register records the number of access-conflicts when bus1 accesses L1-Cache..*/ +#define EXTMEM_L1_DBUS_CONFLICT_CNT 0xFFFFFFFF +#define EXTMEM_L1_DBUS_CONFLICT_CNT_M ((EXTMEM_L1_DBUS_CONFLICT_CNT_V)<<(EXTMEM_L1_DBUS_CONFLICT_CNT_S)) +#define EXTMEM_L1_DBUS_CONFLICT_CNT_V 0xFFFFFFFF +#define EXTMEM_L1_DBUS_CONFLICT_CNT_S 0 + +#define EXTMEM_L1_DBUS_ACS_NXTLVL_CNT_REG (DR_REG_EXTMEM_BASE + 0x1D8) +/* EXTMEM_L1_DBUS_NXTLVL_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The register records the number of times that L1-Cache accesses L2-Cache due to +bus1 accessing L1-Cache..*/ +#define EXTMEM_L1_DBUS_NXTLVL_CNT 0xFFFFFFFF +#define EXTMEM_L1_DBUS_NXTLVL_CNT_M ((EXTMEM_L1_DBUS_NXTLVL_CNT_V)<<(EXTMEM_L1_DBUS_NXTLVL_CNT_S)) +#define EXTMEM_L1_DBUS_NXTLVL_CNT_V 0xFFFFFFFF +#define EXTMEM_L1_DBUS_NXTLVL_CNT_S 0 + +#define EXTMEM_L1_CACHE_ACS_FAIL_ID_ATTR_REG (DR_REG_EXTMEM_BASE + 0x21C) +/* EXTMEM_L1_CACHE_FAIL_ATTR : RO ;bitpos:[31:16] ;default: 16'h0 ; */ +/*description: The register records the attribution of fail-access when cache accesses L1-Cache ..*/ -#define EXTMEM_DBUS0_CONFLICT_CNT 0xFFFFFFFF -#define EXTMEM_DBUS0_CONFLICT_CNT_M ((EXTMEM_DBUS0_CONFLICT_CNT_V)<<(EXTMEM_DBUS0_CONFLICT_CNT_S)) -#define EXTMEM_DBUS0_CONFLICT_CNT_V 0xFFFFFFFF -#define EXTMEM_DBUS0_CONFLICT_CNT_S 0 +#define EXTMEM_L1_CACHE_FAIL_ATTR 0x0000FFFF +#define EXTMEM_L1_CACHE_FAIL_ATTR_M ((EXTMEM_L1_CACHE_FAIL_ATTR_V)<<(EXTMEM_L1_CACHE_FAIL_ATTR_S)) +#define EXTMEM_L1_CACHE_FAIL_ATTR_V 0xFFFF +#define EXTMEM_L1_CACHE_FAIL_ATTR_S 16 +/* EXTMEM_L1_CACHE_FAIL_ID : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: The register records the ID of fail-access when cache accesses L1-Cache..*/ +#define EXTMEM_L1_CACHE_FAIL_ID 0x0000FFFF +#define EXTMEM_L1_CACHE_FAIL_ID_M ((EXTMEM_L1_CACHE_FAIL_ID_V)<<(EXTMEM_L1_CACHE_FAIL_ID_S)) +#define EXTMEM_L1_CACHE_FAIL_ID_V 0xFFFF +#define EXTMEM_L1_CACHE_FAIL_ID_S 0 -#define EXTMEM_DBUS0_ACS_NXTLVL_CNT_REG (DR_REG_EXTMEM_BASE + 0x1C8) -/* EXTMEM_DBUS0_NXTLVL_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The register records the number of times that L1-DCache accesses L2-Cache due to - bus0 accessing L1-DCache..*/ -#define EXTMEM_DBUS0_NXTLVL_CNT 0xFFFFFFFF -#define EXTMEM_DBUS0_NXTLVL_CNT_M ((EXTMEM_DBUS0_NXTLVL_CNT_V)<<(EXTMEM_DBUS0_NXTLVL_CNT_S)) -#define EXTMEM_DBUS0_NXTLVL_CNT_V 0xFFFFFFFF -#define EXTMEM_DBUS0_NXTLVL_CNT_S 0 +#define EXTMEM_L1_CACHE_ACS_FAIL_ADDR_REG (DR_REG_EXTMEM_BASE + 0x220) +/* EXTMEM_L1_CACHE_FAIL_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The register records the address of fail-access when cache accesses L1-Cache..*/ +#define EXTMEM_L1_CACHE_FAIL_ADDR 0xFFFFFFFF +#define EXTMEM_L1_CACHE_FAIL_ADDR_M ((EXTMEM_L1_CACHE_FAIL_ADDR_V)<<(EXTMEM_L1_CACHE_FAIL_ADDR_S)) +#define EXTMEM_L1_CACHE_FAIL_ADDR_V 0xFFFFFFFF +#define EXTMEM_L1_CACHE_FAIL_ADDR_S 0 -#define EXTMEM_DBUS1_ACS_HIT_CNT_REG (DR_REG_EXTMEM_BASE + 0x1CC) -/* EXTMEM_DBUS1_HIT_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The register records the number of hits when bus1 accesses L1-DCache..*/ -#define EXTMEM_DBUS1_HIT_CNT 0xFFFFFFFF -#define EXTMEM_DBUS1_HIT_CNT_M ((EXTMEM_DBUS1_HIT_CNT_V)<<(EXTMEM_DBUS1_HIT_CNT_S)) -#define EXTMEM_DBUS1_HIT_CNT_V 0xFFFFFFFF -#define EXTMEM_DBUS1_HIT_CNT_S 0 - -#define EXTMEM_DBUS1_ACS_MISS_CNT_REG (DR_REG_EXTMEM_BASE + 0x1D0) -/* EXTMEM_DBUS1_MISS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The register records the number of missing when bus1 accesses L1-DCache..*/ -#define EXTMEM_DBUS1_MISS_CNT 0xFFFFFFFF -#define EXTMEM_DBUS1_MISS_CNT_M ((EXTMEM_DBUS1_MISS_CNT_V)<<(EXTMEM_DBUS1_MISS_CNT_S)) -#define EXTMEM_DBUS1_MISS_CNT_V 0xFFFFFFFF -#define EXTMEM_DBUS1_MISS_CNT_S 0 - -#define EXTMEM_DBUS1_ACS_CONFLICT_CNT_REG (DR_REG_EXTMEM_BASE + 0x1D4) -/* EXTMEM_DBUS1_CONFLICT_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The register records the number of access-conflicts when bus1 accesses L1-DCache -..*/ -#define EXTMEM_DBUS1_CONFLICT_CNT 0xFFFFFFFF -#define EXTMEM_DBUS1_CONFLICT_CNT_M ((EXTMEM_DBUS1_CONFLICT_CNT_V)<<(EXTMEM_DBUS1_CONFLICT_CNT_S)) -#define EXTMEM_DBUS1_CONFLICT_CNT_V 0xFFFFFFFF -#define EXTMEM_DBUS1_CONFLICT_CNT_S 0 - -#define EXTMEM_DBUS1_ACS_NXTLVL_CNT_REG (DR_REG_EXTMEM_BASE + 0x1D8) -/* EXTMEM_DBUS1_NXTLVL_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The register records the number of times that L1-DCache accesses L2-Cache due to - bus1 accessing L1-DCache..*/ -#define EXTMEM_DBUS1_NXTLVL_CNT 0xFFFFFFFF -#define EXTMEM_DBUS1_NXTLVL_CNT_M ((EXTMEM_DBUS1_NXTLVL_CNT_V)<<(EXTMEM_DBUS1_NXTLVL_CNT_S)) -#define EXTMEM_DBUS1_NXTLVL_CNT_V 0xFFFFFFFF -#define EXTMEM_DBUS1_NXTLVL_CNT_S 0 - -#define EXTMEM_ICACHE0_ACS_FAIL_ID_ATTR_REG (DR_REG_EXTMEM_BASE + 0x1FC) -/* EXTMEM_ICACHE0_FAIL_ATTR : RO ;bitpos:[31:16] ;default: 16'h0 ; */ -/*description: The register records the attribution of fail-access when cache0 accesses L1-ICac -he..*/ -#define EXTMEM_ICACHE0_FAIL_ATTR 0x0000FFFF -#define EXTMEM_ICACHE0_FAIL_ATTR_M ((EXTMEM_ICACHE0_FAIL_ATTR_V)<<(EXTMEM_ICACHE0_FAIL_ATTR_S)) -#define EXTMEM_ICACHE0_FAIL_ATTR_V 0xFFFF -#define EXTMEM_ICACHE0_FAIL_ATTR_S 16 -/* EXTMEM_ICACHE0_FAIL_ID : RO ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: The register records the ID of fail-access when cache0 accesses L1-ICache..*/ -#define EXTMEM_ICACHE0_FAIL_ID 0x0000FFFF -#define EXTMEM_ICACHE0_FAIL_ID_M ((EXTMEM_ICACHE0_FAIL_ID_V)<<(EXTMEM_ICACHE0_FAIL_ID_S)) -#define EXTMEM_ICACHE0_FAIL_ID_V 0xFFFF -#define EXTMEM_ICACHE0_FAIL_ID_S 0 - -#define EXTMEM_ICACHE0_ACS_FAIL_ADDR_REG (DR_REG_EXTMEM_BASE + 0x200) -/* EXTMEM_ICACHE0_FAIL_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The register records the address of fail-access when cache0 accesses L1-ICache..*/ -#define EXTMEM_ICACHE0_FAIL_ADDR 0xFFFFFFFF -#define EXTMEM_ICACHE0_FAIL_ADDR_M ((EXTMEM_ICACHE0_FAIL_ADDR_V)<<(EXTMEM_ICACHE0_FAIL_ADDR_S)) -#define EXTMEM_ICACHE0_FAIL_ADDR_V 0xFFFFFFFF -#define EXTMEM_ICACHE0_FAIL_ADDR_S 0 - -#define EXTMEM_ICACHE1_ACS_FAIL_ID_ATTR_REG (DR_REG_EXTMEM_BASE + 0x204) -/* EXTMEM_ICACHE1_FAIL_ATTR : RO ;bitpos:[31:16] ;default: 16'h0 ; */ -/*description: The register records the attribution of fail-access when cache1 accesses L1-ICac -he..*/ -#define EXTMEM_ICACHE1_FAIL_ATTR 0x0000FFFF -#define EXTMEM_ICACHE1_FAIL_ATTR_M ((EXTMEM_ICACHE1_FAIL_ATTR_V)<<(EXTMEM_ICACHE1_FAIL_ATTR_S)) -#define EXTMEM_ICACHE1_FAIL_ATTR_V 0xFFFF -#define EXTMEM_ICACHE1_FAIL_ATTR_S 16 -/* EXTMEM_ICACHE1_FAIL_ID : RO ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: The register records the ID of fail-access when cache1 accesses L1-ICache..*/ -#define EXTMEM_ICACHE1_FAIL_ID 0x0000FFFF -#define EXTMEM_ICACHE1_FAIL_ID_M ((EXTMEM_ICACHE1_FAIL_ID_V)<<(EXTMEM_ICACHE1_FAIL_ID_S)) -#define EXTMEM_ICACHE1_FAIL_ID_V 0xFFFF -#define EXTMEM_ICACHE1_FAIL_ID_S 0 - -#define EXTMEM_ICACHE1_ACS_FAIL_ADDR_REG (DR_REG_EXTMEM_BASE + 0x208) -/* EXTMEM_ICACHE1_FAIL_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The register records the address of fail-access when cache1 accesses L1-ICache..*/ -#define EXTMEM_ICACHE1_FAIL_ADDR 0xFFFFFFFF -#define EXTMEM_ICACHE1_FAIL_ADDR_M ((EXTMEM_ICACHE1_FAIL_ADDR_V)<<(EXTMEM_ICACHE1_FAIL_ADDR_S)) -#define EXTMEM_ICACHE1_FAIL_ADDR_V 0xFFFFFFFF -#define EXTMEM_ICACHE1_FAIL_ADDR_S 0 - -#define EXTMEM_DCACHE_ACS_FAIL_ID_ATTR_REG (DR_REG_EXTMEM_BASE + 0x21C) -/* EXTMEM_DCACHE_FAIL_ATTR : RO ;bitpos:[31:16] ;default: 16'h0 ; */ -/*description: The register records the attribution of fail-access when cache accesses L1-DCach -e..*/ -#define EXTMEM_DCACHE_FAIL_ATTR 0x0000FFFF -#define EXTMEM_DCACHE_FAIL_ATTR_M ((EXTMEM_DCACHE_FAIL_ATTR_V)<<(EXTMEM_DCACHE_FAIL_ATTR_S)) -#define EXTMEM_DCACHE_FAIL_ATTR_V 0xFFFF -#define EXTMEM_DCACHE_FAIL_ATTR_S 16 -/* EXTMEM_DCACHE_FAIL_ID : RO ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: The register records the ID of fail-access when cache accesses L1-DCache..*/ -#define EXTMEM_DCACHE_FAIL_ID 0x0000FFFF -#define EXTMEM_DCACHE_FAIL_ID_M ((EXTMEM_DCACHE_FAIL_ID_V)<<(EXTMEM_DCACHE_FAIL_ID_S)) -#define EXTMEM_DCACHE_FAIL_ID_V 0xFFFF -#define EXTMEM_DCACHE_FAIL_ID_S 0 - -#define EXTMEM_DCACHE_ACS_FAIL_ADDR_REG (DR_REG_EXTMEM_BASE + 0x220) -/* EXTMEM_DCACHE_FAIL_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The register records the address of fail-access when cache accesses L1-DCache..*/ -#define EXTMEM_DCACHE_FAIL_ADDR 0xFFFFFFFF -#define EXTMEM_DCACHE_FAIL_ADDR_M ((EXTMEM_DCACHE_FAIL_ADDR_V)<<(EXTMEM_DCACHE_FAIL_ADDR_S)) -#define EXTMEM_DCACHE_FAIL_ADDR_V 0xFFFFFFFF -#define EXTMEM_DCACHE_FAIL_ADDR_S 0 - -#define EXTMEM_CACHE_SYNC_PRELOAD_INT_ENA_REG (DR_REG_EXTMEM_BASE + 0x224) -/* EXTMEM_CACHE_SYNC_ERR_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */ +#define EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_ENA_REG (DR_REG_EXTMEM_BASE + 0x224) +/* EXTMEM_L1_CACHE_SYNC_ERR_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */ /*description: The bit is used to enable interrupt of Cache sync-operation error..*/ -#define EXTMEM_CACHE_SYNC_ERR_INT_ENA (BIT(13)) -#define EXTMEM_CACHE_SYNC_ERR_INT_ENA_M (BIT(13)) -#define EXTMEM_CACHE_SYNC_ERR_INT_ENA_V 0x1 -#define EXTMEM_CACHE_SYNC_ERR_INT_ENA_S 13 -/* EXTMEM_DCACHE_PLD_ERR_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: The bit is used to enable interrupt of L1-DCache preload-operation error..*/ -#define EXTMEM_DCACHE_PLD_ERR_INT_ENA (BIT(11)) -#define EXTMEM_DCACHE_PLD_ERR_INT_ENA_M (BIT(11)) -#define EXTMEM_DCACHE_PLD_ERR_INT_ENA_V 0x1 -#define EXTMEM_DCACHE_PLD_ERR_INT_ENA_S 11 -/* EXTMEM_CACHE_SYNC_DONE_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ +#define EXTMEM_L1_CACHE_SYNC_ERR_INT_ENA (BIT(13)) +#define EXTMEM_L1_CACHE_SYNC_ERR_INT_ENA_M (BIT(13)) +#define EXTMEM_L1_CACHE_SYNC_ERR_INT_ENA_V 0x1 +#define EXTMEM_L1_CACHE_SYNC_ERR_INT_ENA_S 13 +/* EXTMEM_L1_CACHE_PLD_ERR_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: The bit is used to enable interrupt of L1-Cache preload-operation error..*/ +#define EXTMEM_L1_CACHE_PLD_ERR_INT_ENA (BIT(11)) +#define EXTMEM_L1_CACHE_PLD_ERR_INT_ENA_M (BIT(11)) +#define EXTMEM_L1_CACHE_PLD_ERR_INT_ENA_V 0x1 +#define EXTMEM_L1_CACHE_PLD_ERR_INT_ENA_S 11 +/* EXTMEM_L1_CACHE_SYNC_DONE_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ /*description: The bit is used to enable interrupt of Cache sync-operation done..*/ -#define EXTMEM_CACHE_SYNC_DONE_INT_ENA (BIT(6)) -#define EXTMEM_CACHE_SYNC_DONE_INT_ENA_M (BIT(6)) -#define EXTMEM_CACHE_SYNC_DONE_INT_ENA_V 0x1 -#define EXTMEM_CACHE_SYNC_DONE_INT_ENA_S 6 -/* EXTMEM_DCACHE_PLD_DONE_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The bit is used to enable interrupt of L1-DCache preload-operation. If preload o -peration is done, interrupt occurs..*/ -#define EXTMEM_DCACHE_PLD_DONE_INT_ENA (BIT(4)) -#define EXTMEM_DCACHE_PLD_DONE_INT_ENA_M (BIT(4)) -#define EXTMEM_DCACHE_PLD_DONE_INT_ENA_V 0x1 -#define EXTMEM_DCACHE_PLD_DONE_INT_ENA_S 4 +#define EXTMEM_L1_CACHE_SYNC_DONE_INT_ENA (BIT(6)) +#define EXTMEM_L1_CACHE_SYNC_DONE_INT_ENA_M (BIT(6)) +#define EXTMEM_L1_CACHE_SYNC_DONE_INT_ENA_V 0x1 +#define EXTMEM_L1_CACHE_SYNC_DONE_INT_ENA_S 6 +/* EXTMEM_L1_CACHE_PLD_DONE_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The bit is used to enable interrupt of L1-Cache preload-operation. If preload op +eration is done, interrupt occurs..*/ +#define EXTMEM_L1_CACHE_PLD_DONE_INT_ENA (BIT(4)) +#define EXTMEM_L1_CACHE_PLD_DONE_INT_ENA_M (BIT(4)) +#define EXTMEM_L1_CACHE_PLD_DONE_INT_ENA_V 0x1 +#define EXTMEM_L1_CACHE_PLD_DONE_INT_ENA_S 4 -#define EXTMEM_CACHE_SYNC_PRELOAD_INT_CLR_REG (DR_REG_EXTMEM_BASE + 0x228) -/* EXTMEM_CACHE_SYNC_ERR_INT_CLR : WT ;bitpos:[13] ;default: 1'b0 ; */ +#define EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_CLR_REG (DR_REG_EXTMEM_BASE + 0x228) +/* EXTMEM_L1_CACHE_SYNC_ERR_INT_CLR : WT ;bitpos:[13] ;default: 1'b0 ; */ /*description: The bit is used to clear interrupt of Cache sync-operation error..*/ -#define EXTMEM_CACHE_SYNC_ERR_INT_CLR (BIT(13)) -#define EXTMEM_CACHE_SYNC_ERR_INT_CLR_M (BIT(13)) -#define EXTMEM_CACHE_SYNC_ERR_INT_CLR_V 0x1 -#define EXTMEM_CACHE_SYNC_ERR_INT_CLR_S 13 -/* EXTMEM_DCACHE_PLD_ERR_INT_CLR : WT ;bitpos:[11] ;default: 1'b0 ; */ -/*description: The bit is used to clear interrupt of L1-DCache preload-operation error..*/ -#define EXTMEM_DCACHE_PLD_ERR_INT_CLR (BIT(11)) -#define EXTMEM_DCACHE_PLD_ERR_INT_CLR_M (BIT(11)) -#define EXTMEM_DCACHE_PLD_ERR_INT_CLR_V 0x1 -#define EXTMEM_DCACHE_PLD_ERR_INT_CLR_S 11 -/* EXTMEM_CACHE_SYNC_DONE_INT_CLR : WT ;bitpos:[6] ;default: 1'b0 ; */ +#define EXTMEM_L1_CACHE_SYNC_ERR_INT_CLR (BIT(13)) +#define EXTMEM_L1_CACHE_SYNC_ERR_INT_CLR_M (BIT(13)) +#define EXTMEM_L1_CACHE_SYNC_ERR_INT_CLR_V 0x1 +#define EXTMEM_L1_CACHE_SYNC_ERR_INT_CLR_S 13 +/* EXTMEM_L1_CACHE_PLD_ERR_INT_CLR : WT ;bitpos:[11] ;default: 1'b0 ; */ +/*description: The bit is used to clear interrupt of L1-Cache preload-operation error..*/ +#define EXTMEM_L1_CACHE_PLD_ERR_INT_CLR (BIT(11)) +#define EXTMEM_L1_CACHE_PLD_ERR_INT_CLR_M (BIT(11)) +#define EXTMEM_L1_CACHE_PLD_ERR_INT_CLR_V 0x1 +#define EXTMEM_L1_CACHE_PLD_ERR_INT_CLR_S 11 +/* EXTMEM_L1_CACHE_SYNC_DONE_INT_CLR : WT ;bitpos:[6] ;default: 1'b0 ; */ /*description: The bit is used to clear interrupt that occurs only when Cache sync-operation is done..*/ -#define EXTMEM_CACHE_SYNC_DONE_INT_CLR (BIT(6)) -#define EXTMEM_CACHE_SYNC_DONE_INT_CLR_M (BIT(6)) -#define EXTMEM_CACHE_SYNC_DONE_INT_CLR_V 0x1 -#define EXTMEM_CACHE_SYNC_DONE_INT_CLR_S 6 -/* EXTMEM_DCACHE_PLD_DONE_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The bit is used to clear interrupt that occurs only when L1-DCache preload-opera -tion is done..*/ -#define EXTMEM_DCACHE_PLD_DONE_INT_CLR (BIT(4)) -#define EXTMEM_DCACHE_PLD_DONE_INT_CLR_M (BIT(4)) -#define EXTMEM_DCACHE_PLD_DONE_INT_CLR_V 0x1 -#define EXTMEM_DCACHE_PLD_DONE_INT_CLR_S 4 +#define EXTMEM_L1_CACHE_SYNC_DONE_INT_CLR (BIT(6)) +#define EXTMEM_L1_CACHE_SYNC_DONE_INT_CLR_M (BIT(6)) +#define EXTMEM_L1_CACHE_SYNC_DONE_INT_CLR_V 0x1 +#define EXTMEM_L1_CACHE_SYNC_DONE_INT_CLR_S 6 +/* EXTMEM_L1_CACHE_PLD_DONE_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The bit is used to clear interrupt that occurs only when L1-Cache preload-operat +ion is done..*/ +#define EXTMEM_L1_CACHE_PLD_DONE_INT_CLR (BIT(4)) +#define EXTMEM_L1_CACHE_PLD_DONE_INT_CLR_M (BIT(4)) +#define EXTMEM_L1_CACHE_PLD_DONE_INT_CLR_V 0x1 +#define EXTMEM_L1_CACHE_PLD_DONE_INT_CLR_S 4 -#define EXTMEM_CACHE_SYNC_PRELOAD_INT_RAW_REG (DR_REG_EXTMEM_BASE + 0x22C) -/* EXTMEM_CACHE_SYNC_ERR_INT_RAW : R/WTC/SS ;bitpos:[13] ;default: 1'b0 ; */ +#define EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_RAW_REG (DR_REG_EXTMEM_BASE + 0x22C) +/* EXTMEM_L1_CACHE_SYNC_ERR_INT_RAW : R/WTC/SS ;bitpos:[13] ;default: 1'b0 ; */ /*description: The raw bit of the interrupt that occurs only when Cache sync-operation error oc curs..*/ -#define EXTMEM_CACHE_SYNC_ERR_INT_RAW (BIT(13)) -#define EXTMEM_CACHE_SYNC_ERR_INT_RAW_M (BIT(13)) -#define EXTMEM_CACHE_SYNC_ERR_INT_RAW_V 0x1 -#define EXTMEM_CACHE_SYNC_ERR_INT_RAW_S 13 -/* EXTMEM_DCACHE_PLD_ERR_INT_RAW : R/WTC/SS ;bitpos:[11] ;default: 1'b0 ; */ -/*description: The raw bit of the interrupt that occurs only when L1-DCache preload-operation e -rror occurs..*/ -#define EXTMEM_DCACHE_PLD_ERR_INT_RAW (BIT(11)) -#define EXTMEM_DCACHE_PLD_ERR_INT_RAW_M (BIT(11)) -#define EXTMEM_DCACHE_PLD_ERR_INT_RAW_V 0x1 -#define EXTMEM_DCACHE_PLD_ERR_INT_RAW_S 11 -/* EXTMEM_CACHE_SYNC_DONE_INT_RAW : R/WTC/SS ;bitpos:[6] ;default: 1'b0 ; */ +#define EXTMEM_L1_CACHE_SYNC_ERR_INT_RAW (BIT(13)) +#define EXTMEM_L1_CACHE_SYNC_ERR_INT_RAW_M (BIT(13)) +#define EXTMEM_L1_CACHE_SYNC_ERR_INT_RAW_V 0x1 +#define EXTMEM_L1_CACHE_SYNC_ERR_INT_RAW_S 13 +/* EXTMEM_L1_CACHE_PLD_ERR_INT_RAW : R/WTC/SS ;bitpos:[11] ;default: 1'b0 ; */ +/*description: The raw bit of the interrupt that occurs only when L1-Cache preload-operation er +ror occurs..*/ +#define EXTMEM_L1_CACHE_PLD_ERR_INT_RAW (BIT(11)) +#define EXTMEM_L1_CACHE_PLD_ERR_INT_RAW_M (BIT(11)) +#define EXTMEM_L1_CACHE_PLD_ERR_INT_RAW_V 0x1 +#define EXTMEM_L1_CACHE_PLD_ERR_INT_RAW_S 11 +/* EXTMEM_L1_CACHE_SYNC_DONE_INT_RAW : R/WTC/SS ;bitpos:[6] ;default: 1'b0 ; */ /*description: The raw bit of the interrupt that occurs only when Cache sync-operation is done..*/ -#define EXTMEM_CACHE_SYNC_DONE_INT_RAW (BIT(6)) -#define EXTMEM_CACHE_SYNC_DONE_INT_RAW_M (BIT(6)) -#define EXTMEM_CACHE_SYNC_DONE_INT_RAW_V 0x1 -#define EXTMEM_CACHE_SYNC_DONE_INT_RAW_S 6 -/* EXTMEM_DCACHE_PLD_DONE_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The raw bit of the interrupt that occurs only when L1-DCache preload-operation i -s done..*/ -#define EXTMEM_DCACHE_PLD_DONE_INT_RAW (BIT(4)) -#define EXTMEM_DCACHE_PLD_DONE_INT_RAW_M (BIT(4)) -#define EXTMEM_DCACHE_PLD_DONE_INT_RAW_V 0x1 -#define EXTMEM_DCACHE_PLD_DONE_INT_RAW_S 4 +#define EXTMEM_L1_CACHE_SYNC_DONE_INT_RAW (BIT(6)) +#define EXTMEM_L1_CACHE_SYNC_DONE_INT_RAW_M (BIT(6)) +#define EXTMEM_L1_CACHE_SYNC_DONE_INT_RAW_V 0x1 +#define EXTMEM_L1_CACHE_SYNC_DONE_INT_RAW_S 6 +/* EXTMEM_L1_CACHE_PLD_DONE_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The raw bit of the interrupt that occurs only when L1-Cache preload-operation is + done..*/ +#define EXTMEM_L1_CACHE_PLD_DONE_INT_RAW (BIT(4)) +#define EXTMEM_L1_CACHE_PLD_DONE_INT_RAW_M (BIT(4)) +#define EXTMEM_L1_CACHE_PLD_DONE_INT_RAW_V 0x1 +#define EXTMEM_L1_CACHE_PLD_DONE_INT_RAW_S 4 -#define EXTMEM_CACHE_SYNC_PRELOAD_INT_ST_REG (DR_REG_EXTMEM_BASE + 0x230) -/* EXTMEM_CACHE_SYNC_ERR_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */ +#define EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_ST_REG (DR_REG_EXTMEM_BASE + 0x230) +/* EXTMEM_L1_CACHE_SYNC_ERR_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */ /*description: The bit indicates the status of the interrupt of Cache sync-operation error..*/ -#define EXTMEM_CACHE_SYNC_ERR_INT_ST (BIT(13)) -#define EXTMEM_CACHE_SYNC_ERR_INT_ST_M (BIT(13)) -#define EXTMEM_CACHE_SYNC_ERR_INT_ST_V 0x1 -#define EXTMEM_CACHE_SYNC_ERR_INT_ST_S 13 -/* EXTMEM_DCACHE_PLD_ERR_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: The bit indicates the status of the interrupt of L1-DCache preload-operation err -or..*/ -#define EXTMEM_DCACHE_PLD_ERR_INT_ST (BIT(11)) -#define EXTMEM_DCACHE_PLD_ERR_INT_ST_M (BIT(11)) -#define EXTMEM_DCACHE_PLD_ERR_INT_ST_V 0x1 -#define EXTMEM_DCACHE_PLD_ERR_INT_ST_S 11 -/* EXTMEM_CACHE_SYNC_DONE_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ +#define EXTMEM_L1_CACHE_SYNC_ERR_INT_ST (BIT(13)) +#define EXTMEM_L1_CACHE_SYNC_ERR_INT_ST_M (BIT(13)) +#define EXTMEM_L1_CACHE_SYNC_ERR_INT_ST_V 0x1 +#define EXTMEM_L1_CACHE_SYNC_ERR_INT_ST_S 13 +/* EXTMEM_L1_CACHE_PLD_ERR_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: The bit indicates the status of the interrupt of L1-Cache preload-operation erro +r..*/ +#define EXTMEM_L1_CACHE_PLD_ERR_INT_ST (BIT(11)) +#define EXTMEM_L1_CACHE_PLD_ERR_INT_ST_M (BIT(11)) +#define EXTMEM_L1_CACHE_PLD_ERR_INT_ST_V 0x1 +#define EXTMEM_L1_CACHE_PLD_ERR_INT_ST_S 11 +/* EXTMEM_L1_CACHE_SYNC_DONE_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ /*description: The bit indicates the status of the interrupt that occurs only when Cache sync-o peration is done..*/ -#define EXTMEM_CACHE_SYNC_DONE_INT_ST (BIT(6)) -#define EXTMEM_CACHE_SYNC_DONE_INT_ST_M (BIT(6)) -#define EXTMEM_CACHE_SYNC_DONE_INT_ST_V 0x1 -#define EXTMEM_CACHE_SYNC_DONE_INT_ST_S 6 -/* EXTMEM_DCACHE_PLD_DONE_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The bit indicates the status of the interrupt that occurs only when L1-DCache pr -eload-operation is done..*/ -#define EXTMEM_DCACHE_PLD_DONE_INT_ST (BIT(4)) -#define EXTMEM_DCACHE_PLD_DONE_INT_ST_M (BIT(4)) -#define EXTMEM_DCACHE_PLD_DONE_INT_ST_V 0x1 -#define EXTMEM_DCACHE_PLD_DONE_INT_ST_S 4 +#define EXTMEM_L1_CACHE_SYNC_DONE_INT_ST (BIT(6)) +#define EXTMEM_L1_CACHE_SYNC_DONE_INT_ST_M (BIT(6)) +#define EXTMEM_L1_CACHE_SYNC_DONE_INT_ST_V 0x1 +#define EXTMEM_L1_CACHE_SYNC_DONE_INT_ST_S 6 +/* EXTMEM_L1_CACHE_PLD_DONE_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The bit indicates the status of the interrupt that occurs only when L1-Cache pre +load-operation is done..*/ +#define EXTMEM_L1_CACHE_PLD_DONE_INT_ST (BIT(4)) +#define EXTMEM_L1_CACHE_PLD_DONE_INT_ST_M (BIT(4)) +#define EXTMEM_L1_CACHE_PLD_DONE_INT_ST_V 0x1 +#define EXTMEM_L1_CACHE_PLD_DONE_INT_ST_S 4 -#define EXTMEM_CACHE_SYNC_PRELOAD_EXCEPTION_REG (DR_REG_EXTMEM_BASE + 0x234) -/* EXTMEM_CACHE_SYNC_ERR_CODE : RO ;bitpos:[13:12] ;default: 2'h0 ; */ +#define EXTMEM_L1_CACHE_SYNC_PRELOAD_EXCEPTION_REG (DR_REG_EXTMEM_BASE + 0x234) +/* EXTMEM_L1_CACHE_SYNC_ERR_CODE : RO ;bitpos:[13:12] ;default: 2'h0 ; */ /*description: The values 0-2 are available which means sync map, command conflict and size are error in Cache System..*/ -#define EXTMEM_CACHE_SYNC_ERR_CODE 0x00000003 -#define EXTMEM_CACHE_SYNC_ERR_CODE_M ((EXTMEM_CACHE_SYNC_ERR_CODE_V)<<(EXTMEM_CACHE_SYNC_ERR_CODE_S)) -#define EXTMEM_CACHE_SYNC_ERR_CODE_V 0x3 -#define EXTMEM_CACHE_SYNC_ERR_CODE_S 12 -/* EXTMEM_DCACHE_PLD_ERR_CODE : RO ;bitpos:[9:8] ;default: 2'h0 ; */ -/*description: The value 2 is Only available which means preload size is error in L1-DCache..*/ -#define EXTMEM_DCACHE_PLD_ERR_CODE 0x00000003 -#define EXTMEM_DCACHE_PLD_ERR_CODE_M ((EXTMEM_DCACHE_PLD_ERR_CODE_V)<<(EXTMEM_DCACHE_PLD_ERR_CODE_S)) -#define EXTMEM_DCACHE_PLD_ERR_CODE_V 0x3 -#define EXTMEM_DCACHE_PLD_ERR_CODE_S 8 +#define EXTMEM_L1_CACHE_SYNC_ERR_CODE 0x00000003 +#define EXTMEM_L1_CACHE_SYNC_ERR_CODE_M ((EXTMEM_L1_CACHE_SYNC_ERR_CODE_V)<<(EXTMEM_L1_CACHE_SYNC_ERR_CODE_S)) +#define EXTMEM_L1_CACHE_SYNC_ERR_CODE_V 0x3 +#define EXTMEM_L1_CACHE_SYNC_ERR_CODE_S 12 +/* EXTMEM_L1_CACHE_PLD_ERR_CODE : RO ;bitpos:[9:8] ;default: 2'h0 ; */ +/*description: The value 2 is Only available which means preload size is error in L1-Cache..*/ +#define EXTMEM_L1_CACHE_PLD_ERR_CODE 0x00000003 +#define EXTMEM_L1_CACHE_PLD_ERR_CODE_M ((EXTMEM_L1_CACHE_PLD_ERR_CODE_V)<<(EXTMEM_L1_CACHE_PLD_ERR_CODE_S)) +#define EXTMEM_L1_CACHE_PLD_ERR_CODE_V 0x3 +#define EXTMEM_L1_CACHE_PLD_ERR_CODE_S 8 -#define EXTMEM_CACHE_SYNC_RST_CTRL_REG (DR_REG_EXTMEM_BASE + 0x238) -/* EXTMEM_DCACHE_SYNC_RST : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: set this bit to reset sync-logic inside L1-DCache. Recommend that this should on -ly be used to initialize sync-logic when some fatal error of sync-logic occurs..*/ -#define EXTMEM_DCACHE_SYNC_RST (BIT(4)) -#define EXTMEM_DCACHE_SYNC_RST_M (BIT(4)) -#define EXTMEM_DCACHE_SYNC_RST_V 0x1 -#define EXTMEM_DCACHE_SYNC_RST_S 4 +#define EXTMEM_L1_CACHE_SYNC_RST_CTRL_REG (DR_REG_EXTMEM_BASE + 0x238) +/* EXTMEM_L1_CACHE_SYNC_RST : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: set this bit to reset sync-logic inside L1-Cache. Recommend that this should onl +y be used to initialize sync-logic when some fatal error of sync-logic occurs..*/ +#define EXTMEM_L1_CACHE_SYNC_RST (BIT(4)) +#define EXTMEM_L1_CACHE_SYNC_RST_M (BIT(4)) +#define EXTMEM_L1_CACHE_SYNC_RST_V 0x1 +#define EXTMEM_L1_CACHE_SYNC_RST_S 4 -#define EXTMEM_CACHE_PRELOAD_RST_CTRL_REG (DR_REG_EXTMEM_BASE + 0x23C) -/* EXTMEM_DCACHE_PLD_RST : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: set this bit to reset preload-logic inside L1-DCache. Recommend that this should - only be used to initialize preload-logic when some fatal error of preload-logic - occurs..*/ -#define EXTMEM_DCACHE_PLD_RST (BIT(4)) -#define EXTMEM_DCACHE_PLD_RST_M (BIT(4)) -#define EXTMEM_DCACHE_PLD_RST_V 0x1 -#define EXTMEM_DCACHE_PLD_RST_S 4 +#define EXTMEM_L1_CACHE_PRELOAD_RST_CTRL_REG (DR_REG_EXTMEM_BASE + 0x23C) +/* EXTMEM_L1_CACHE_PLD_RST : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: set this bit to reset preload-logic inside L1-Cache. Recommend that this should +only be used to initialize preload-logic when some fatal error of preload-logic +occurs..*/ +#define EXTMEM_L1_CACHE_PLD_RST (BIT(4)) +#define EXTMEM_L1_CACHE_PLD_RST_M (BIT(4)) +#define EXTMEM_L1_CACHE_PLD_RST_V 0x1 +#define EXTMEM_L1_CACHE_PLD_RST_S 4 -#define EXTMEM_CACHE_AUTOLOAD_BUF_CLR_CTRL_REG (DR_REG_EXTMEM_BASE + 0x240) -/* EXTMEM_DCACHE_ALD_BUF_CLR : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: set this bit to clear autoload-buffer inside L1-DCache. If this bit is active, a -utoload will not work in L1-DCache. This bit should not be active when autoload -works in L1-DCache..*/ -#define EXTMEM_DCACHE_ALD_BUF_CLR (BIT(4)) -#define EXTMEM_DCACHE_ALD_BUF_CLR_M (BIT(4)) -#define EXTMEM_DCACHE_ALD_BUF_CLR_V 0x1 -#define EXTMEM_DCACHE_ALD_BUF_CLR_S 4 +#define EXTMEM_L1_CACHE_AUTOLOAD_BUF_CLR_CTRL_REG (DR_REG_EXTMEM_BASE + 0x240) +/* EXTMEM_L1_CACHE_ALD_BUF_CLR : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: set this bit to clear autoload-buffer inside L1-Cache. If this bit is active, au +toload will not work in L1-Cache. This bit should not be active when autoload wo +rks in L1-Cache..*/ +#define EXTMEM_L1_CACHE_ALD_BUF_CLR (BIT(4)) +#define EXTMEM_L1_CACHE_ALD_BUF_CLR_M (BIT(4)) +#define EXTMEM_L1_CACHE_ALD_BUF_CLR_V 0x1 +#define EXTMEM_L1_CACHE_ALD_BUF_CLR_S 4 -#define EXTMEM_UNALLOCATE_BUFFER_CLEAR_REG (DR_REG_EXTMEM_BASE + 0x244) -/* EXTMEM_DCACHE_UNALLOC_CLR : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The bit is used to clear the unallocate request buffer of l1 dcache where the un -allocate request is responsed but not completed..*/ -#define EXTMEM_DCACHE_UNALLOC_CLR (BIT(4)) -#define EXTMEM_DCACHE_UNALLOC_CLR_M (BIT(4)) -#define EXTMEM_DCACHE_UNALLOC_CLR_V 0x1 -#define EXTMEM_DCACHE_UNALLOC_CLR_S 4 +#define EXTMEM_L1_UNALLOCATE_BUFFER_CLEAR_REG (DR_REG_EXTMEM_BASE + 0x244) +/* EXTMEM_L1_CACHE_UNALLOC_CLR : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The bit is used to clear the unallocate request buffer of l1 cache where the una +llocate request is responsed but not completed..*/ +#define EXTMEM_L1_CACHE_UNALLOC_CLR (BIT(4)) +#define EXTMEM_L1_CACHE_UNALLOC_CLR_M (BIT(4)) +#define EXTMEM_L1_CACHE_UNALLOC_CLR_V 0x1 +#define EXTMEM_L1_CACHE_UNALLOC_CLR_S 4 -#define EXTMEM_CACHE_OBJECT_CTRL_REG (DR_REG_EXTMEM_BASE + 0x248) -/* EXTMEM_DCACHE_MEM_OBJECT : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: Set this bit to set L1-DCache data memory as object. This bit should be onehot w -ith the others fields inside this register..*/ -#define EXTMEM_DCACHE_MEM_OBJECT (BIT(10)) -#define EXTMEM_DCACHE_MEM_OBJECT_M (BIT(10)) -#define EXTMEM_DCACHE_MEM_OBJECT_V 0x1 -#define EXTMEM_DCACHE_MEM_OBJECT_S 10 -/* EXTMEM_DCACHE_TAG_OBJECT : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: Set this bit to set L1-DCache tag memory as object. This bit should be onehot wi +#define EXTMEM_L1_CACHE_OBJECT_CTRL_REG (DR_REG_EXTMEM_BASE + 0x248) +/* EXTMEM_L1_CACHE_MEM_OBJECT : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: Set this bit to set L1-Cache data memory as object. This bit should be onehot wi th the others fields inside this register..*/ -#define EXTMEM_DCACHE_TAG_OBJECT (BIT(4)) -#define EXTMEM_DCACHE_TAG_OBJECT_M (BIT(4)) -#define EXTMEM_DCACHE_TAG_OBJECT_V 0x1 -#define EXTMEM_DCACHE_TAG_OBJECT_S 4 +#define EXTMEM_L1_CACHE_MEM_OBJECT (BIT(10)) +#define EXTMEM_L1_CACHE_MEM_OBJECT_M (BIT(10)) +#define EXTMEM_L1_CACHE_MEM_OBJECT_V 0x1 +#define EXTMEM_L1_CACHE_MEM_OBJECT_S 10 +/* EXTMEM_L1_CACHE_TAG_OBJECT : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit to set L1-Cache tag memory as object. This bit should be onehot wit +h the others fields inside this register..*/ +#define EXTMEM_L1_CACHE_TAG_OBJECT (BIT(4)) +#define EXTMEM_L1_CACHE_TAG_OBJECT_M (BIT(4)) +#define EXTMEM_L1_CACHE_TAG_OBJECT_V 0x1 +#define EXTMEM_L1_CACHE_TAG_OBJECT_S 4 -#define EXTMEM_CACHE_WAY_OBJECT_REG (DR_REG_EXTMEM_BASE + 0x24C) -/* EXTMEM_CACHE_WAY_OBJECT : R/W ;bitpos:[2:0] ;default: 3'h0 ; */ +#define EXTMEM_L1_CACHE_WAY_OBJECT_REG (DR_REG_EXTMEM_BASE + 0x24C) +/* EXTMEM_L1_CACHE_WAY_OBJECT : R/W ;bitpos:[2:0] ;default: 3'h0 ; */ /*description: Set this bits to select which way of the tag-object will be accessed. 0: way0, 1 : way1, 2: way2, 3: way3, ?, 7: way7..*/ -#define EXTMEM_CACHE_WAY_OBJECT 0x00000007 -#define EXTMEM_CACHE_WAY_OBJECT_M ((EXTMEM_CACHE_WAY_OBJECT_V)<<(EXTMEM_CACHE_WAY_OBJECT_S)) -#define EXTMEM_CACHE_WAY_OBJECT_V 0x7 -#define EXTMEM_CACHE_WAY_OBJECT_S 0 +#define EXTMEM_L1_CACHE_WAY_OBJECT 0x00000007 +#define EXTMEM_L1_CACHE_WAY_OBJECT_M ((EXTMEM_L1_CACHE_WAY_OBJECT_V)<<(EXTMEM_L1_CACHE_WAY_OBJECT_S)) +#define EXTMEM_L1_CACHE_WAY_OBJECT_V 0x7 +#define EXTMEM_L1_CACHE_WAY_OBJECT_S 0 -#define EXTMEM_CACHE_VADDR_REG (DR_REG_EXTMEM_BASE + 0x250) -/* EXTMEM_CACHE_VADDR : R/W ;bitpos:[31:0] ;default: 32'h40000000 ; */ +#define EXTMEM_L1_CACHE_VADDR_REG (DR_REG_EXTMEM_BASE + 0x250) +/* EXTMEM_L1_CACHE_VADDR : R/W ;bitpos:[31:0] ;default: 32'h40000000 ; */ /*description: Those bits stores the virtual address which will decide where inside the specifi ed tag memory object will be accessed..*/ -#define EXTMEM_CACHE_VADDR 0xFFFFFFFF -#define EXTMEM_CACHE_VADDR_M ((EXTMEM_CACHE_VADDR_V)<<(EXTMEM_CACHE_VADDR_S)) -#define EXTMEM_CACHE_VADDR_V 0xFFFFFFFF -#define EXTMEM_CACHE_VADDR_S 0 +#define EXTMEM_L1_CACHE_VADDR 0xFFFFFFFF +#define EXTMEM_L1_CACHE_VADDR_M ((EXTMEM_L1_CACHE_VADDR_V)<<(EXTMEM_L1_CACHE_VADDR_S)) +#define EXTMEM_L1_CACHE_VADDR_V 0xFFFFFFFF +#define EXTMEM_L1_CACHE_VADDR_S 0 -#define EXTMEM_CACHE_DEBUG_BUS_REG (DR_REG_EXTMEM_BASE + 0x254) -/* EXTMEM_CACHE_DEBUG_BUS : R/W ;bitpos:[31:0] ;default: 32'h254 ; */ +#define EXTMEM_L1_CACHE_DEBUG_BUS_REG (DR_REG_EXTMEM_BASE + 0x254) +/* EXTMEM_L1_CACHE_DEBUG_BUS : R/W ;bitpos:[31:0] ;default: 32'h254 ; */ /*description: This is a constant place where we can write data to or read data from the tag/da ta memory on the specified cache..*/ -#define EXTMEM_CACHE_DEBUG_BUS 0xFFFFFFFF -#define EXTMEM_CACHE_DEBUG_BUS_M ((EXTMEM_CACHE_DEBUG_BUS_V)<<(EXTMEM_CACHE_DEBUG_BUS_S)) -#define EXTMEM_CACHE_DEBUG_BUS_V 0xFFFFFFFF -#define EXTMEM_CACHE_DEBUG_BUS_S 0 +#define EXTMEM_L1_CACHE_DEBUG_BUS 0xFFFFFFFF +#define EXTMEM_L1_CACHE_DEBUG_BUS_M ((EXTMEM_L1_CACHE_DEBUG_BUS_V)<<(EXTMEM_L1_CACHE_DEBUG_BUS_S)) +#define EXTMEM_L1_CACHE_DEBUG_BUS_V 0xFFFFFFFF +#define EXTMEM_L1_CACHE_DEBUG_BUS_S 0 #define EXTMEM_DATE_REG (DR_REG_EXTMEM_BASE + 0x3FC) /* EXTMEM_DATE : R/W ;bitpos:[27:0] ;default: 28'h2202080 ; */ @@ -945,7 +866,6 @@ ta memory on the specified cache..*/ #define EXTMEM_DATE_V 0xFFFFFFF #define EXTMEM_DATE_S 0 - #ifdef __cplusplus } #endif diff --git a/components/soc/esp32h2/include/soc/extmem_reg.h b/components/soc/esp32h2/include/soc/extmem_reg.h index 42cea3bdb3..b53ab46731 100644 --- a/components/soc/esp32h2/include/soc/extmem_reg.h +++ b/components/soc/esp32h2/include/soc/extmem_reg.h @@ -1,951 +1,971 @@ /* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ -#pragma once +#ifndef _SOC_CACHE_REG_H_ +#define _SOC_CACHE_REG_H_ + -#include -#include "soc/soc.h" #ifdef __cplusplus extern "C" { #endif +#include "soc.h" -// TODO: IDF-5797 +#define CACHE_L1_CACHE_CTRL_REG (DR_REG_CACHE_BASE + 0x4) +/* CACHE_L1_CACHE_SHUT_BUS1 : R/W ;bitpos:[1] ;default: 1'h0 ; */ +/*description: The bit is used to disable core1 dbus access L1-Cache, 0: enable, 1: disable.*/ +#define CACHE_L1_CACHE_SHUT_BUS1 (BIT(1)) +#define CACHE_L1_CACHE_SHUT_BUS1_M (BIT(1)) +#define CACHE_L1_CACHE_SHUT_BUS1_V 0x1 +#define CACHE_L1_CACHE_SHUT_BUS1_S 1 +/* CACHE_L1_CACHE_SHUT_BUS0 : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: The bit is used to disable core0 dbus access L1-Cache, 0: enable, 1: disable.*/ +#define CACHE_L1_CACHE_SHUT_BUS0 (BIT(0)) +#define CACHE_L1_CACHE_SHUT_BUS0_M (BIT(0)) +#define CACHE_L1_CACHE_SHUT_BUS0_V 0x1 +#define CACHE_L1_CACHE_SHUT_BUS0_S 0 -#define EXTMEM_ICACHE_CTRL_REG (DR_REG_EXTMEM_BASE + 0x0) - -#define EXTMEM_DCACHE_CTRL_REG (DR_REG_EXTMEM_BASE + 0x4) -/* EXTMEM_DCACHE_SHUT_DBUS1 : R/W ;bitpos:[1] ;default: 1'h0 ; */ -/*description: The bit is used to disable core1 dbus access L1-DCache, 0: enable, 1: disable.*/ -#define EXTMEM_DCACHE_SHUT_DBUS1 (BIT(1)) -#define EXTMEM_DCACHE_SHUT_DBUS1_M (BIT(1)) -#define EXTMEM_DCACHE_SHUT_DBUS1_V 0x1 -#define EXTMEM_DCACHE_SHUT_DBUS1_S 1 -/* EXTMEM_DCACHE_SHUT_DBUS0 : R/W ;bitpos:[0] ;default: 1'h0 ; */ -/*description: The bit is used to disable core0 dbus access L1-DCache, 0: enable, 1: disable.*/ -#define EXTMEM_DCACHE_SHUT_DBUS0 (BIT(0)) -#define EXTMEM_DCACHE_SHUT_DBUS0_M (BIT(0)) -#define EXTMEM_DCACHE_SHUT_DBUS0_V 0x1 -#define EXTMEM_DCACHE_SHUT_DBUS0_S 0 - -#define EXTMEM_CACHE_WRAP_AROUND_CTRL_REG (DR_REG_EXTMEM_BASE + 0x20) -/* EXTMEM_DCACHE_WRAP : R/W ;bitpos:[4] ;default: 1'h0 ; */ +#define CACHE_L1_CACHE_WRAP_AROUND_CTRL_REG (DR_REG_CACHE_BASE + 0x20) +/* CACHE_L1_CACHE_WRAP : R/W ;bitpos:[4] ;default: 1'h0 ; */ /*description: Set this bit as 1 to enable L1-DCache wrap around mode..*/ -#define EXTMEM_CACHE_FLASH_WRAP_AROUND (BIT(4)) -#define EXTMEM_CACHE_FLASH_WRAP_AROUND_M (BIT(4)) -#define EXTMEM_CACHE_FLASH_WRAP_AROUND_V 0x1 -#define EXTMEM_CACHE_FLASH_WRAP_AROUND_S 4 +#define CACHE_L1_CACHE_WRAP (BIT(4)) +#define CACHE_L1_CACHE_WRAP_M (BIT(4)) +#define CACHE_L1_CACHE_WRAP_V 0x1 +#define CACHE_L1_CACHE_WRAP_S 4 -#define EXTMEM_CACHE_TAG_MEM_POWER_CTRL_REG (DR_REG_EXTMEM_BASE + 0x24) -/* EXTMEM_DCACHE_TAG_MEM_FORCE_PU : R/W ;bitpos:[18] ;default: 1'h1 ; */ -/*description: The bit is used to power L1-DCache tag memory up. 0: follow rtc_lslp, 1: power u +#define CACHE_L1_CACHE_TAG_MEM_POWER_CTRL_REG (DR_REG_CACHE_BASE + 0x24) +/* CACHE_L1_CACHE_TAG_MEM_FORCE_PU : R/W ;bitpos:[18] ;default: 1'h1 ; */ +/*description: The bit is used to power L1-Cache tag memory up. 0: follow rtc_lslp, 1: power up.*/ +#define CACHE_L1_CACHE_TAG_MEM_FORCE_PU (BIT(18)) +#define CACHE_L1_CACHE_TAG_MEM_FORCE_PU_M (BIT(18)) +#define CACHE_L1_CACHE_TAG_MEM_FORCE_PU_V 0x1 +#define CACHE_L1_CACHE_TAG_MEM_FORCE_PU_S 18 +/* CACHE_L1_CACHE_TAG_MEM_FORCE_PD : R/W ;bitpos:[17] ;default: 1'h0 ; */ +/*description: The bit is used to power L1-Cache tag memory down. 0: follow rtc_lslp, 1: power +down.*/ +#define CACHE_L1_CACHE_TAG_MEM_FORCE_PD (BIT(17)) +#define CACHE_L1_CACHE_TAG_MEM_FORCE_PD_M (BIT(17)) +#define CACHE_L1_CACHE_TAG_MEM_FORCE_PD_V 0x1 +#define CACHE_L1_CACHE_TAG_MEM_FORCE_PD_S 17 +/* CACHE_L1_CACHE_TAG_MEM_FORCE_ON : R/W ;bitpos:[16] ;default: 1'h1 ; */ +/*description: The bit is used to close clock gating of L1-Cache tag memory. 1: close gating, +0: open clock gating..*/ +#define CACHE_L1_CACHE_TAG_MEM_FORCE_ON (BIT(16)) +#define CACHE_L1_CACHE_TAG_MEM_FORCE_ON_M (BIT(16)) +#define CACHE_L1_CACHE_TAG_MEM_FORCE_ON_V 0x1 +#define CACHE_L1_CACHE_TAG_MEM_FORCE_ON_S 16 + +#define CACHE_L1_CACHE_DATA_MEM_POWER_CTRL_REG (DR_REG_CACHE_BASE + 0x28) +/* CACHE_L1_CACHE_DATA_MEM_FORCE_PU : R/W ;bitpos:[18] ;default: 1'h1 ; */ +/*description: The bit is used to power L1-Cache data memory up. 0: follow rtc_lslp, 1: power u p.*/ -#define EXTMEM_DCACHE_TAG_MEM_FORCE_PU (BIT(18)) -#define EXTMEM_DCACHE_TAG_MEM_FORCE_PU_M (BIT(18)) -#define EXTMEM_DCACHE_TAG_MEM_FORCE_PU_V 0x1 -#define EXTMEM_DCACHE_TAG_MEM_FORCE_PU_S 18 -/* EXTMEM_DCACHE_TAG_MEM_FORCE_PD : R/W ;bitpos:[17] ;default: 1'h0 ; */ -/*description: The bit is used to power L1-DCache tag memory down. 0: follow rtc_lslp, 1: power +#define CACHE_L1_CACHE_DATA_MEM_FORCE_PU (BIT(18)) +#define CACHE_L1_CACHE_DATA_MEM_FORCE_PU_M (BIT(18)) +#define CACHE_L1_CACHE_DATA_MEM_FORCE_PU_V 0x1 +#define CACHE_L1_CACHE_DATA_MEM_FORCE_PU_S 18 +/* CACHE_L1_CACHE_DATA_MEM_FORCE_PD : R/W ;bitpos:[17] ;default: 1'h0 ; */ +/*description: The bit is used to power L1-Cache data memory down. 0: follow rtc_lslp, 1: power down.*/ -#define EXTMEM_DCACHE_TAG_MEM_FORCE_PD (BIT(17)) -#define EXTMEM_DCACHE_TAG_MEM_FORCE_PD_M (BIT(17)) -#define EXTMEM_DCACHE_TAG_MEM_FORCE_PD_V 0x1 -#define EXTMEM_DCACHE_TAG_MEM_FORCE_PD_S 17 -/* EXTMEM_DCACHE_TAG_MEM_FORCE_ON : R/W ;bitpos:[16] ;default: 1'h1 ; */ -/*description: The bit is used to close clock gating of L1-DCache tag memory. 1: close gating, +#define CACHE_L1_CACHE_DATA_MEM_FORCE_PD (BIT(17)) +#define CACHE_L1_CACHE_DATA_MEM_FORCE_PD_M (BIT(17)) +#define CACHE_L1_CACHE_DATA_MEM_FORCE_PD_V 0x1 +#define CACHE_L1_CACHE_DATA_MEM_FORCE_PD_S 17 +/* CACHE_L1_CACHE_DATA_MEM_FORCE_ON : R/W ;bitpos:[16] ;default: 1'h1 ; */ +/*description: The bit is used to close clock gating of L1-Cache data memory. 1: close gating, 0: open clock gating..*/ -#define EXTMEM_DCACHE_TAG_MEM_FORCE_ON (BIT(16)) -#define EXTMEM_DCACHE_TAG_MEM_FORCE_ON_M (BIT(16)) -#define EXTMEM_DCACHE_TAG_MEM_FORCE_ON_V 0x1 -#define EXTMEM_DCACHE_TAG_MEM_FORCE_ON_S 16 +#define CACHE_L1_CACHE_DATA_MEM_FORCE_ON (BIT(16)) +#define CACHE_L1_CACHE_DATA_MEM_FORCE_ON_M (BIT(16)) +#define CACHE_L1_CACHE_DATA_MEM_FORCE_ON_V 0x1 +#define CACHE_L1_CACHE_DATA_MEM_FORCE_ON_S 16 -#define EXTMEM_CACHE_DATA_MEM_POWER_CTRL_REG (DR_REG_EXTMEM_BASE + 0x28) -/* EXTMEM_DCACHE_DATA_MEM_FORCE_PU : R/W ;bitpos:[18] ;default: 1'h1 ; */ -/*description: The bit is used to power L1-DCache data memory up. 0: follow rtc_lslp, 1: power -up.*/ -#define EXTMEM_DCACHE_DATA_MEM_FORCE_PU (BIT(18)) -#define EXTMEM_DCACHE_DATA_MEM_FORCE_PU_M (BIT(18)) -#define EXTMEM_DCACHE_DATA_MEM_FORCE_PU_V 0x1 -#define EXTMEM_DCACHE_DATA_MEM_FORCE_PU_S 18 -/* EXTMEM_DCACHE_DATA_MEM_FORCE_PD : R/W ;bitpos:[17] ;default: 1'h0 ; */ -/*description: The bit is used to power L1-DCache data memory down. 0: follow rtc_lslp, 1: powe -r down.*/ -#define EXTMEM_DCACHE_DATA_MEM_FORCE_PD (BIT(17)) -#define EXTMEM_DCACHE_DATA_MEM_FORCE_PD_M (BIT(17)) -#define EXTMEM_DCACHE_DATA_MEM_FORCE_PD_V 0x1 -#define EXTMEM_DCACHE_DATA_MEM_FORCE_PD_S 17 -/* EXTMEM_DCACHE_DATA_MEM_FORCE_ON : R/W ;bitpos:[16] ;default: 1'h1 ; */ -/*description: The bit is used to close clock gating of L1-DCache data memory. 1: close gating -, 0: open clock gating..*/ -#define EXTMEM_DCACHE_DATA_MEM_FORCE_ON (BIT(16)) -#define EXTMEM_DCACHE_DATA_MEM_FORCE_ON_M (BIT(16)) -#define EXTMEM_DCACHE_DATA_MEM_FORCE_ON_V 0x1 -#define EXTMEM_DCACHE_DATA_MEM_FORCE_ON_S 16 +#define CACHE_L1_CACHE_FREEZE_CTRL_REG (DR_REG_CACHE_BASE + 0x2C) +/* CACHE_L1_CACHE_FREEZE_DONE : RO ;bitpos:[18] ;default: 1'h0 ; */ +/*description: The bit is used to indicate whether freeze operation on L1-Cache is finished or +not. 0: not finished. 1: finished..*/ +#define CACHE_L1_CACHE_FREEZE_DONE (BIT(18)) +#define CACHE_L1_CACHE_FREEZE_DONE_M (BIT(18)) +#define CACHE_L1_CACHE_FREEZE_DONE_V 0x1 +#define CACHE_L1_CACHE_FREEZE_DONE_S 18 +/* CACHE_L1_CACHE_FREEZE_MODE : R/W ;bitpos:[17] ;default: 1'h0 ; */ +/*description: The bit is used to configure mode of freeze operation L1-Cache. 0: a miss-access + will not stuck. 1: a miss-access will stuck..*/ +#define CACHE_L1_CACHE_FREEZE_MODE (BIT(17)) +#define CACHE_L1_CACHE_FREEZE_MODE_M (BIT(17)) +#define CACHE_L1_CACHE_FREEZE_MODE_V 0x1 +#define CACHE_L1_CACHE_FREEZE_MODE_S 17 +/* CACHE_L1_CACHE_FREEZE_EN : R/W ;bitpos:[16] ;default: 1'h0 ; */ +/*description: The bit is used to enable freeze operation on L1-Cache. It can be cleared by sof +tware..*/ +#define CACHE_L1_CACHE_FREEZE_EN (BIT(16)) +#define CACHE_L1_CACHE_FREEZE_EN_M (BIT(16)) +#define CACHE_L1_CACHE_FREEZE_EN_V 0x1 +#define CACHE_L1_CACHE_FREEZE_EN_S 16 -#define EXTMEM_CACHE_FREEZE_CTRL_REG (DR_REG_EXTMEM_BASE + 0x2C) -/* EXTMEM_DCACHE_FREEZE_DONE : RO ;bitpos:[18] ;default: 1'h0 ; */ -/*description: The bit is used to indicate whether freeze operation on L1-DCache is finished or - not. 0: not finished. 1: finished..*/ -#define EXTMEM_DCACHE_FREEZE_DONE (BIT(18)) -#define EXTMEM_DCACHE_FREEZE_DONE_M (BIT(18)) -#define EXTMEM_DCACHE_FREEZE_DONE_V 0x1 -#define EXTMEM_DCACHE_FREEZE_DONE_S 18 -/* EXTMEM_DCACHE_FREEZE_MODE : R/W ;bitpos:[17] ;default: 1'h0 ; */ -/*description: The bit is used to configure mode of freeze operation L1-DCache. 0: a miss-acces -s will not stuck. 1: a miss-access will stuck..*/ -#define EXTMEM_DCACHE_FREEZE_MODE (BIT(17)) -#define EXTMEM_DCACHE_FREEZE_MODE_M (BIT(17)) -#define EXTMEM_DCACHE_FREEZE_MODE_V 0x1 -#define EXTMEM_DCACHE_FREEZE_MODE_S 17 -/* EXTMEM_DCACHE_FREEZE_EN : R/W ;bitpos:[16] ;default: 1'h0 ; */ -/*description: The bit is used to enable freeze operation on L1-DCache. It can be cleared by so -ftware..*/ -#define EXTMEM_DCACHE_FREEZE_EN (BIT(16)) -#define EXTMEM_DCACHE_FREEZE_EN_M (BIT(16)) -#define EXTMEM_DCACHE_FREEZE_EN_V 0x1 -#define EXTMEM_DCACHE_FREEZE_EN_S 16 - -#define EXTMEM_CACHE_DATA_MEM_ACS_CONF_REG (DR_REG_EXTMEM_BASE + 0x30) -/* EXTMEM_DCACHE_DATA_MEM_WR_EN : R/W ;bitpos:[17] ;default: 1'h1 ; */ -/*description: The bit is used to enable config-bus write L1-DCache data memoryory. 0: disable, - 1: enable..*/ -#define EXTMEM_DCACHE_DATA_MEM_WR_EN (BIT(17)) -#define EXTMEM_DCACHE_DATA_MEM_WR_EN_M (BIT(17)) -#define EXTMEM_DCACHE_DATA_MEM_WR_EN_V 0x1 -#define EXTMEM_DCACHE_DATA_MEM_WR_EN_S 17 -/* EXTMEM_DCACHE_DATA_MEM_RD_EN : R/W ;bitpos:[16] ;default: 1'h1 ; */ -/*description: The bit is used to enable config-bus read L1-DCache data memoryory. 0: disable, +#define CACHE_L1_CACHE_DATA_MEM_ACS_CONF_REG (DR_REG_CACHE_BASE + 0x30) +/* CACHE_L1_CACHE_DATA_MEM_WR_EN : R/W ;bitpos:[17] ;default: 1'h1 ; */ +/*description: The bit is used to enable config-bus write L1-Cache data memoryory. 0: disable, 1: enable..*/ -#define EXTMEM_DCACHE_DATA_MEM_RD_EN (BIT(16)) -#define EXTMEM_DCACHE_DATA_MEM_RD_EN_M (BIT(16)) -#define EXTMEM_DCACHE_DATA_MEM_RD_EN_V 0x1 -#define EXTMEM_DCACHE_DATA_MEM_RD_EN_S 16 - -#define EXTMEM_CACHE_TAG_MEM_ACS_CONF_REG (DR_REG_EXTMEM_BASE + 0x34) -/* EXTMEM_DCACHE_TAG_MEM_WR_EN : R/W ;bitpos:[17] ;default: 1'h1 ; */ -/*description: The bit is used to enable config-bus write L1-DCache tag memoryory. 0: disable, -1: enable..*/ -#define EXTMEM_DCACHE_TAG_MEM_WR_EN (BIT(17)) -#define EXTMEM_DCACHE_TAG_MEM_WR_EN_M (BIT(17)) -#define EXTMEM_DCACHE_TAG_MEM_WR_EN_V 0x1 -#define EXTMEM_DCACHE_TAG_MEM_WR_EN_S 17 -/* EXTMEM_DCACHE_TAG_MEM_RD_EN : R/W ;bitpos:[16] ;default: 1'h1 ; */ -/*description: The bit is used to enable config-bus read L1-DCache tag memoryory. 0: disable, 1 +#define CACHE_L1_CACHE_DATA_MEM_WR_EN (BIT(17)) +#define CACHE_L1_CACHE_DATA_MEM_WR_EN_M (BIT(17)) +#define CACHE_L1_CACHE_DATA_MEM_WR_EN_V 0x1 +#define CACHE_L1_CACHE_DATA_MEM_WR_EN_S 17 +/* CACHE_L1_CACHE_DATA_MEM_RD_EN : R/W ;bitpos:[16] ;default: 1'h1 ; */ +/*description: The bit is used to enable config-bus read L1-Cache data memoryory. 0: disable, 1 : enable..*/ -#define EXTMEM_DCACHE_TAG_MEM_RD_EN (BIT(16)) -#define EXTMEM_DCACHE_TAG_MEM_RD_EN_M (BIT(16)) -#define EXTMEM_DCACHE_TAG_MEM_RD_EN_V 0x1 -#define EXTMEM_DCACHE_TAG_MEM_RD_EN_S 16 +#define CACHE_L1_CACHE_DATA_MEM_RD_EN (BIT(16)) +#define CACHE_L1_CACHE_DATA_MEM_RD_EN_M (BIT(16)) +#define CACHE_L1_CACHE_DATA_MEM_RD_EN_V 0x1 +#define CACHE_L1_CACHE_DATA_MEM_RD_EN_S 16 -#define EXTMEM_DCACHE_PRELOCK_CONF_REG (DR_REG_EXTMEM_BASE + 0x78) -/* EXTMEM_DCACHE_PRELOCK_RGID : HRO ;bitpos:[5:2] ;default: 4'h0 ; */ -/*description: The bit is used to set the gid of l1 dcache prelock..*/ -#define EXTMEM_DCACHE_PRELOCK_RGID 0x0000000F -#define EXTMEM_DCACHE_PRELOCK_RGID_M ((EXTMEM_DCACHE_PRELOCK_RGID_V)<<(EXTMEM_DCACHE_PRELOCK_RGID_S)) -#define EXTMEM_DCACHE_PRELOCK_RGID_V 0xF -#define EXTMEM_DCACHE_PRELOCK_RGID_S 2 -/* EXTMEM_DCACHE_PRELOCK_SCT1_EN : R/W ;bitpos:[1] ;default: 1'h0 ; */ -/*description: The bit is used to enable the second section of prelock function on L1-DCache..*/ -#define EXTMEM_DCACHE_PRELOCK_SCT1_EN (BIT(1)) -#define EXTMEM_DCACHE_PRELOCK_SCT1_EN_M (BIT(1)) -#define EXTMEM_DCACHE_PRELOCK_SCT1_EN_V 0x1 -#define EXTMEM_DCACHE_PRELOCK_SCT1_EN_S 1 -/* EXTMEM_DCACHE_PRELOCK_SCT0_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */ -/*description: The bit is used to enable the first section of prelock function on L1-DCache..*/ -#define EXTMEM_DCACHE_PRELOCK_SCT0_EN (BIT(0)) -#define EXTMEM_DCACHE_PRELOCK_SCT0_EN_M (BIT(0)) -#define EXTMEM_DCACHE_PRELOCK_SCT0_EN_V 0x1 -#define EXTMEM_DCACHE_PRELOCK_SCT0_EN_S 0 +#define CACHE_L1_CACHE_TAG_MEM_ACS_CONF_REG (DR_REG_CACHE_BASE + 0x34) +/* CACHE_L1_CACHE_TAG_MEM_WR_EN : R/W ;bitpos:[17] ;default: 1'h1 ; */ +/*description: The bit is used to enable config-bus write L1-Cache tag memoryory. 0: disable, 1 +: enable..*/ +#define CACHE_L1_CACHE_TAG_MEM_WR_EN (BIT(17)) +#define CACHE_L1_CACHE_TAG_MEM_WR_EN_M (BIT(17)) +#define CACHE_L1_CACHE_TAG_MEM_WR_EN_V 0x1 +#define CACHE_L1_CACHE_TAG_MEM_WR_EN_S 17 +/* CACHE_L1_CACHE_TAG_MEM_RD_EN : R/W ;bitpos:[16] ;default: 1'h1 ; */ +/*description: The bit is used to enable config-bus read L1-Cache tag memoryory. 0: disable, 1: + enable..*/ +#define CACHE_L1_CACHE_TAG_MEM_RD_EN (BIT(16)) +#define CACHE_L1_CACHE_TAG_MEM_RD_EN_M (BIT(16)) +#define CACHE_L1_CACHE_TAG_MEM_RD_EN_V 0x1 +#define CACHE_L1_CACHE_TAG_MEM_RD_EN_S 16 -#define EXTMEM_DCACHE_PRELOCK_SCT0_ADDR_REG (DR_REG_EXTMEM_BASE + 0x7C) -/* EXTMEM_DCACHE_PRELOCK_SCT0_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +#define CACHE_L1_CACHE_PRELOCK_CONF_REG (DR_REG_CACHE_BASE + 0x78) +/* CACHE_L1_CACHE_PRELOCK_RGID : HRO ;bitpos:[5:2] ;default: 4'h0 ; */ +/*description: The bit is used to set the gid of l1 cache prelock..*/ +#define CACHE_L1_CACHE_PRELOCK_RGID 0x0000000F +#define CACHE_L1_CACHE_PRELOCK_RGID_M ((CACHE_L1_CACHE_PRELOCK_RGID_V)<<(CACHE_L1_CACHE_PRELOCK_RGID_S)) +#define CACHE_L1_CACHE_PRELOCK_RGID_V 0xF +#define CACHE_L1_CACHE_PRELOCK_RGID_S 2 +/* CACHE_L1_CACHE_PRELOCK_SCT1_EN : R/W ;bitpos:[1] ;default: 1'h0 ; */ +/*description: The bit is used to enable the second section of prelock function on L1-Cache..*/ +#define CACHE_L1_CACHE_PRELOCK_SCT1_EN (BIT(1)) +#define CACHE_L1_CACHE_PRELOCK_SCT1_EN_M (BIT(1)) +#define CACHE_L1_CACHE_PRELOCK_SCT1_EN_V 0x1 +#define CACHE_L1_CACHE_PRELOCK_SCT1_EN_S 1 +/* CACHE_L1_CACHE_PRELOCK_SCT0_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: The bit is used to enable the first section of prelock function on L1-Cache..*/ +#define CACHE_L1_CACHE_PRELOCK_SCT0_EN (BIT(0)) +#define CACHE_L1_CACHE_PRELOCK_SCT0_EN_M (BIT(0)) +#define CACHE_L1_CACHE_PRELOCK_SCT0_EN_V 0x1 +#define CACHE_L1_CACHE_PRELOCK_SCT0_EN_S 0 + +#define CACHE_L1_CACHE_PRELOCK_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x7C) +/* CACHE_L1_CACHE_PRELOCK_SCT0_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ /*description: Those bits are used to configure the start virtual address of the first section -of prelock on L1-DCache, which should be used together with L1_DCACHE_PRELOCK_SC -T0_SIZE_REG.*/ -#define EXTMEM_DCACHE_PRELOCK_SCT0_ADDR 0xFFFFFFFF -#define EXTMEM_DCACHE_PRELOCK_SCT0_ADDR_M ((EXTMEM_DCACHE_PRELOCK_SCT0_ADDR_V)<<(EXTMEM_DCACHE_PRELOCK_SCT0_ADDR_S)) -#define EXTMEM_DCACHE_PRELOCK_SCT0_ADDR_V 0xFFFFFFFF -#define EXTMEM_DCACHE_PRELOCK_SCT0_ADDR_S 0 +of prelock on L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT0 +_SIZE_REG.*/ +#define CACHE_L1_CACHE_PRELOCK_SCT0_ADDR 0xFFFFFFFF +#define CACHE_L1_CACHE_PRELOCK_SCT0_ADDR_M ((CACHE_L1_CACHE_PRELOCK_SCT0_ADDR_V)<<(CACHE_L1_CACHE_PRELOCK_SCT0_ADDR_S)) +#define CACHE_L1_CACHE_PRELOCK_SCT0_ADDR_V 0xFFFFFFFF +#define CACHE_L1_CACHE_PRELOCK_SCT0_ADDR_S 0 -#define EXTMEM_DCACHE_PRELOCK_SCT1_ADDR_REG (DR_REG_EXTMEM_BASE + 0x80) -/* EXTMEM_DCACHE_PRELOCK_SCT1_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +#define CACHE_L1_CACHE_PRELOCK_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x80) +/* CACHE_L1_CACHE_PRELOCK_SCT1_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ /*description: Those bits are used to configure the start virtual address of the second section - of prelock on L1-DCache, which should be used together with L1_DCACHE_PRELOCK_S -CT1_SIZE_REG.*/ -#define EXTMEM_DCACHE_PRELOCK_SCT1_ADDR 0xFFFFFFFF -#define EXTMEM_DCACHE_PRELOCK_SCT1_ADDR_M ((EXTMEM_DCACHE_PRELOCK_SCT1_ADDR_V)<<(EXTMEM_DCACHE_PRELOCK_SCT1_ADDR_S)) -#define EXTMEM_DCACHE_PRELOCK_SCT1_ADDR_V 0xFFFFFFFF -#define EXTMEM_DCACHE_PRELOCK_SCT1_ADDR_S 0 + of prelock on L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT +1_SIZE_REG.*/ +#define CACHE_L1_CACHE_PRELOCK_SCT1_ADDR 0xFFFFFFFF +#define CACHE_L1_CACHE_PRELOCK_SCT1_ADDR_M ((CACHE_L1_CACHE_PRELOCK_SCT1_ADDR_V)<<(CACHE_L1_CACHE_PRELOCK_SCT1_ADDR_S)) +#define CACHE_L1_CACHE_PRELOCK_SCT1_ADDR_V 0xFFFFFFFF +#define CACHE_L1_CACHE_PRELOCK_SCT1_ADDR_S 0 -#define EXTMEM_DCACHE_PRELOCK_SCT_SIZE_REG (DR_REG_EXTMEM_BASE + 0x84) -/* EXTMEM_DCACHE_PRELOCK_SCT1_SIZE : R/W ;bitpos:[29:16] ;default: 14'h3fff ; */ +#define CACHE_L1_CACHE_PRELOCK_SCT_SIZE_REG (DR_REG_CACHE_BASE + 0x84) +/* CACHE_L1_CACHE_PRELOCK_SCT1_SIZE : R/W ;bitpos:[29:16] ;default: 14'h3fff ; */ /*description: Those bits are used to configure the size of the second section of prelock on L1 --DCache, which should be used together with L1_DCACHE_PRELOCK_SCT1_ADDR_REG.*/ -#define EXTMEM_DCACHE_PRELOCK_SCT1_SIZE 0x00003FFF -#define EXTMEM_DCACHE_PRELOCK_SCT1_SIZE_M ((EXTMEM_DCACHE_PRELOCK_SCT1_SIZE_V)<<(EXTMEM_DCACHE_PRELOCK_SCT1_SIZE_S)) -#define EXTMEM_DCACHE_PRELOCK_SCT1_SIZE_V 0x3FFF -#define EXTMEM_DCACHE_PRELOCK_SCT1_SIZE_S 16 -/* EXTMEM_DCACHE_PRELOCK_SCT0_SIZE : R/W ;bitpos:[13:0] ;default: 14'h3fff ; */ +-Cache, which should be used together with L1_CACHE_PRELOCK_SCT1_ADDR_REG.*/ +#define CACHE_L1_CACHE_PRELOCK_SCT1_SIZE 0x00003FFF +#define CACHE_L1_CACHE_PRELOCK_SCT1_SIZE_M ((CACHE_L1_CACHE_PRELOCK_SCT1_SIZE_V)<<(CACHE_L1_CACHE_PRELOCK_SCT1_SIZE_S)) +#define CACHE_L1_CACHE_PRELOCK_SCT1_SIZE_V 0x3FFF +#define CACHE_L1_CACHE_PRELOCK_SCT1_SIZE_S 16 +/* CACHE_L1_CACHE_PRELOCK_SCT0_SIZE : R/W ;bitpos:[13:0] ;default: 14'h3fff ; */ /*description: Those bits are used to configure the size of the first section of prelock on L1- -DCache, which should be used together with L1_DCACHE_PRELOCK_SCT0_ADDR_REG.*/ -#define EXTMEM_DCACHE_PRELOCK_SCT0_SIZE 0x00003FFF -#define EXTMEM_DCACHE_PRELOCK_SCT0_SIZE_M ((EXTMEM_DCACHE_PRELOCK_SCT0_SIZE_V)<<(EXTMEM_DCACHE_PRELOCK_SCT0_SIZE_S)) -#define EXTMEM_DCACHE_PRELOCK_SCT0_SIZE_V 0x3FFF -#define EXTMEM_DCACHE_PRELOCK_SCT0_SIZE_S 0 +Cache, which should be used together with L1_CACHE_PRELOCK_SCT0_ADDR_REG.*/ +#define CACHE_L1_CACHE_PRELOCK_SCT0_SIZE 0x00003FFF +#define CACHE_L1_CACHE_PRELOCK_SCT0_SIZE_M ((CACHE_L1_CACHE_PRELOCK_SCT0_SIZE_V)<<(CACHE_L1_CACHE_PRELOCK_SCT0_SIZE_S)) +#define CACHE_L1_CACHE_PRELOCK_SCT0_SIZE_V 0x3FFF +#define CACHE_L1_CACHE_PRELOCK_SCT0_SIZE_S 0 -#define EXTMEM_CACHE_LOCK_CTRL_REG (DR_REG_EXTMEM_BASE + 0x88) -/* EXTMEM_CACHE_LOCK_RGID : HRO ;bitpos:[6:3] ;default: 4'h0 ; */ -/*description: The bit is used to set the gid of cache lock/unlock..*/ -#define EXTMEM_CACHE_LOCK_RGID 0x0000000F -#define EXTMEM_CACHE_LOCK_RGID_M ((EXTMEM_CACHE_LOCK_RGID_V)<<(EXTMEM_CACHE_LOCK_RGID_S)) -#define EXTMEM_CACHE_LOCK_RGID_V 0xF -#define EXTMEM_CACHE_LOCK_RGID_S 3 -/* EXTMEM_CACHE_LOCK_DONE : RO ;bitpos:[2] ;default: 1'h1 ; */ +#define CACHE_LOCK_CTRL_REG (DR_REG_CACHE_BASE + 0x88) +/* CACHE_LOCK_DONE : RO ;bitpos:[2] ;default: 1'h1 ; */ /*description: The bit is used to indicate whether unlock/lock operation is finished or not. 0: not finished. 1: finished..*/ -#define EXTMEM_CACHE_LOCK_DONE (BIT(2)) -#define EXTMEM_CACHE_LOCK_DONE_M (BIT(2)) -#define EXTMEM_CACHE_LOCK_DONE_V 0x1 -#define EXTMEM_CACHE_LOCK_DONE_S 2 -/* EXTMEM_CACHE_UNLOCK_ENA : R/W/SC ;bitpos:[1] ;default: 1'h0 ; */ +#define CACHE_LOCK_DONE (BIT(2)) +#define CACHE_LOCK_DONE_M (BIT(2)) +#define CACHE_LOCK_DONE_V 0x1 +#define CACHE_LOCK_DONE_S 2 +/* CACHE_UNLOCK_ENA : R/W/SC ;bitpos:[1] ;default: 1'h0 ; */ /*description: The bit is used to enable unlock operation. It will be cleared by hardware after - unlock operation done. Note that (1) this bit and lock_ena bit are mutually exc -lusive, that is, those bits can not be set to 1 at the same time. (2) unlock ope -ration can be applied on L1-ICache, L1-DCache and L2-Cache..*/ -#define EXTMEM_CACHE_UNLOCK_ENA (BIT(1)) -#define EXTMEM_CACHE_UNLOCK_ENA_M (BIT(1)) -#define EXTMEM_CACHE_UNLOCK_ENA_V 0x1 -#define EXTMEM_CACHE_UNLOCK_ENA_S 1 -/* EXTMEM_CACHE_LOCK_ENA : R/W/SC ;bitpos:[0] ;default: 1'h0 ; */ + unlock operation done.*/ +#define CACHE_UNLOCK_ENA (BIT(1)) +#define CACHE_UNLOCK_ENA_M (BIT(1)) +#define CACHE_UNLOCK_ENA_V 0x1 +#define CACHE_UNLOCK_ENA_S 1 +/* CACHE_LOCK_ENA : R/W/SC ;bitpos:[0] ;default: 1'h0 ; */ /*description: The bit is used to enable lock operation. It will be cleared by hardware after l -ock operation done. Note that (1) this bit and unlock_ena bit are mutually exclu -sive, that is, those bits can not be set to 1 at the same time. (2) lock operati -on can be applied on LL1-ICache, L1-DCache and L2-Cache..*/ -#define EXTMEM_CACHE_LOCK_ENA (BIT(0)) -#define EXTMEM_CACHE_LOCK_ENA_M (BIT(0)) -#define EXTMEM_CACHE_LOCK_ENA_V 0x1 -#define EXTMEM_CACHE_LOCK_ENA_S 0 +ock operation done.*/ +#define CACHE_LOCK_ENA (BIT(0)) +#define CACHE_LOCK_ENA_M (BIT(0)) +#define CACHE_LOCK_ENA_V 0x1 +#define CACHE_LOCK_ENA_S 0 -#define EXTMEM_CACHE_LOCK_MAP_REG (DR_REG_EXTMEM_BASE + 0x8C) -/* EXTMEM_CACHE_LOCK_MAP : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +#define CACHE_LOCK_MAP_REG (DR_REG_CACHE_BASE + 0x8C) +/* CACHE_LOCK_MAP : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ /*description: Those bits are used to indicate which caches in the two-level cache structure wi -ll apply this lock/unlock operation. [0]: L1-ICache0, [1]: L1-ICache1, [2]: L1-I -Cache2, [3]: L1-ICache3, [4]: L1-DCache, [5]: L2-Cache..*/ -#define EXTMEM_CACHE_LOCK_MAP 0x0000003F -#define EXTMEM_CACHE_LOCK_MAP_M ((EXTMEM_CACHE_LOCK_MAP_V)<<(EXTMEM_CACHE_LOCK_MAP_S)) -#define EXTMEM_CACHE_LOCK_MAP_V 0x3F -#define EXTMEM_CACHE_LOCK_MAP_S 0 +ll apply this lock/unlock operation. [4]: L1-Cache.*/ +#define CACHE_LOCK_MAP 0x0000003F +#define CACHE_LOCK_MAP_M ((CACHE_LOCK_MAP_V)<<(CACHE_LOCK_MAP_S)) +#define CACHE_LOCK_MAP_V 0x3F +#define CACHE_LOCK_MAP_S 0 -#define EXTMEM_CACHE_LOCK_ADDR_REG (DR_REG_EXTMEM_BASE + 0x90) -/* EXTMEM_CACHE_LOCK_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +#define CACHE_LOCK_ADDR_REG (DR_REG_CACHE_BASE + 0x90) +/* CACHE_LOCK_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ /*description: Those bits are used to configure the start virtual address of the lock/unlock op eration, which should be used together with CACHE_LOCK_SIZE_REG.*/ -#define EXTMEM_CACHE_LOCK_ADDR 0xFFFFFFFF -#define EXTMEM_CACHE_LOCK_ADDR_M ((EXTMEM_CACHE_LOCK_ADDR_V)<<(EXTMEM_CACHE_LOCK_ADDR_S)) -#define EXTMEM_CACHE_LOCK_ADDR_V 0xFFFFFFFF -#define EXTMEM_CACHE_LOCK_ADDR_S 0 +#define CACHE_LOCK_ADDR 0xFFFFFFFF +#define CACHE_LOCK_ADDR_M ((CACHE_LOCK_ADDR_V)<<(CACHE_LOCK_ADDR_S)) +#define CACHE_LOCK_ADDR_V 0xFFFFFFFF +#define CACHE_LOCK_ADDR_S 0 -#define EXTMEM_CACHE_LOCK_SIZE_REG (DR_REG_EXTMEM_BASE + 0x94) -/* EXTMEM_CACHE_LOCK_SIZE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ +#define CACHE_LOCK_SIZE_REG (DR_REG_CACHE_BASE + 0x94) +/* CACHE_LOCK_SIZE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ /*description: Those bits are used to configure the size of the lock/unlock operation, which sh ould be used together with CACHE_LOCK_ADDR_REG.*/ -#define EXTMEM_CACHE_LOCK_SIZE 0x0000FFFF -#define EXTMEM_CACHE_LOCK_SIZE_M ((EXTMEM_CACHE_LOCK_SIZE_V)<<(EXTMEM_CACHE_LOCK_SIZE_S)) -#define EXTMEM_CACHE_LOCK_SIZE_V 0xFFFF -#define EXTMEM_CACHE_LOCK_SIZE_S 0 +#define CACHE_LOCK_SIZE 0x0000FFFF +#define CACHE_LOCK_SIZE_M ((CACHE_LOCK_SIZE_V)<<(CACHE_LOCK_SIZE_S)) +#define CACHE_LOCK_SIZE_V 0xFFFF +#define CACHE_LOCK_SIZE_S 0 -#define EXTMEM_CACHE_SYNC_CTRL_REG (DR_REG_EXTMEM_BASE + 0x98) -/* EXTMEM_CACHE_SYNC_RGID : HRO ;bitpos:[8:5] ;default: 4'h0 ; */ -/*description: The bit is used to set the gid of cache sync operation (invalidate, clean, writ -eback, writeback_invalidate).*/ -#define EXTMEM_CACHE_SYNC_RGID 0x0000000F -#define EXTMEM_CACHE_SYNC_RGID_M ((EXTMEM_CACHE_SYNC_RGID_V)<<(EXTMEM_CACHE_SYNC_RGID_S)) -#define EXTMEM_CACHE_SYNC_RGID_V 0xF -#define EXTMEM_CACHE_SYNC_RGID_S 5 -/* EXTMEM_CACHE_SYNC_DONE : RO ;bitpos:[4] ;default: 1'h0 ; */ +#define CACHE_SYNC_CTRL_REG (DR_REG_CACHE_BASE + 0x98) +/* CACHE_SYNC_DONE : RO ;bitpos:[4] ;default: 1'h0 ; */ /*description: The bit is used to indicate whether sync operation (invalidate, clean, writeback , writeback_invalidate) is finished or not. 0: not finished. 1: finished..*/ -#define EXTMEM_CACHE_SYNC_DONE (BIT(4)) -#define EXTMEM_CACHE_SYNC_DONE_M (BIT(4)) -#define EXTMEM_CACHE_SYNC_DONE_V 0x1 -#define EXTMEM_CACHE_SYNC_DONE_S 4 -/* EXTMEM_CACHE_WRITEBACK_INVALIDATE_ENA : R/W/SC ;bitpos:[3] ;default: 1'h0 ; */ +#define CACHE_SYNC_DONE (BIT(4)) +#define CACHE_SYNC_DONE_M (BIT(4)) +#define CACHE_SYNC_DONE_V 0x1 +#define CACHE_SYNC_DONE_S 4 +/* CACHE_WRITEBACK_INVALIDATE_ENA : R/W/SC ;bitpos:[3] ;default: 1'h0 ; */ /*description: The bit is used to enable writeback-invalidate operation. It will be cleared by hardware after writeback-invalidate operation done. Note that this bit and the o ther sync-bits (invalidate_ena, clean_ena, writeback_ena) are mutually exclusive , that is, those bits can not be set to 1 at the same time..*/ -#define EXTMEM_CACHE_WRITEBACK_INVALIDATE_ENA (BIT(3)) -#define EXTMEM_CACHE_WRITEBACK_INVALIDATE_ENA_M (BIT(3)) -#define EXTMEM_CACHE_WRITEBACK_INVALIDATE_ENA_V 0x1 -#define EXTMEM_CACHE_WRITEBACK_INVALIDATE_ENA_S 3 -/* EXTMEM_CACHE_WRITEBACK_ENA : R/W/SC ;bitpos:[2] ;default: 1'h0 ; */ +#define CACHE_WRITEBACK_INVALIDATE_ENA (BIT(3)) +#define CACHE_WRITEBACK_INVALIDATE_ENA_M (BIT(3)) +#define CACHE_WRITEBACK_INVALIDATE_ENA_V 0x1 +#define CACHE_WRITEBACK_INVALIDATE_ENA_S 3 +/* CACHE_WRITEBACK_ENA : R/W/SC ;bitpos:[2] ;default: 1'h0 ; */ /*description: The bit is used to enable writeback operation. It will be cleared by hardware af ter writeback operation done. Note that this bit and the other sync-bits (invali date_ena, clean_ena, writeback_invalidate_ena) are mutually exclusive, that is, those bits can not be set to 1 at the same time..*/ -#define EXTMEM_CACHE_WRITEBACK_ENA (BIT(2)) -#define EXTMEM_CACHE_WRITEBACK_ENA_M (BIT(2)) -#define EXTMEM_CACHE_WRITEBACK_ENA_V 0x1 -#define EXTMEM_CACHE_WRITEBACK_ENA_S 2 -/* EXTMEM_CACHE_CLEAN_ENA : R/W/SC ;bitpos:[1] ;default: 1'h0 ; */ +#define CACHE_WRITEBACK_ENA (BIT(2)) +#define CACHE_WRITEBACK_ENA_M (BIT(2)) +#define CACHE_WRITEBACK_ENA_V 0x1 +#define CACHE_WRITEBACK_ENA_S 2 +/* CACHE_CLEAN_ENA : R/W/SC ;bitpos:[1] ;default: 1'h0 ; */ /*description: The bit is used to enable clean operation. It will be cleared by hardware after clean operation done. Note that this bit and the other sync-bits (invalidate_ena , writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is, thos e bits can not be set to 1 at the same time..*/ -#define EXTMEM_CACHE_CLEAN_ENA (BIT(1)) -#define EXTMEM_CACHE_CLEAN_ENA_M (BIT(1)) -#define EXTMEM_CACHE_CLEAN_ENA_V 0x1 -#define EXTMEM_CACHE_CLEAN_ENA_S 1 -/* EXTMEM_CACHE_INVALIDATE_ENA : R/W/SC ;bitpos:[0] ;default: 1'h1 ; */ +#define CACHE_CLEAN_ENA (BIT(1)) +#define CACHE_CLEAN_ENA_M (BIT(1)) +#define CACHE_CLEAN_ENA_V 0x1 +#define CACHE_CLEAN_ENA_S 1 +/* CACHE_INVALIDATE_ENA : R/W/SC ;bitpos:[0] ;default: 1'h1 ; */ /*description: The bit is used to enable invalidate operation. It will be cleared by hardware a fter invalidate operation done. Note that this bit and the other sync-bits (clea n_ena, writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is, those bits can not be set to 1 at the same time..*/ -#define EXTMEM_CACHE_INVALIDATE_ENA (BIT(0)) -#define EXTMEM_CACHE_INVALIDATE_ENA_M (BIT(0)) -#define EXTMEM_CACHE_INVALIDATE_ENA_V 0x1 -#define EXTMEM_CACHE_INVALIDATE_ENA_S 0 +#define CACHE_INVALIDATE_ENA (BIT(0)) +#define CACHE_INVALIDATE_ENA_M (BIT(0)) +#define CACHE_INVALIDATE_ENA_V 0x1 +#define CACHE_INVALIDATE_ENA_S 0 -#define EXTMEM_CACHE_SYNC_MAP_REG (DR_REG_EXTMEM_BASE + 0x9C) -/* EXTMEM_CACHE_SYNC_MAP : R/W ;bitpos:[5:0] ;default: 6'h3f ; */ +#define CACHE_SYNC_MAP_REG (DR_REG_CACHE_BASE + 0x9C) +/* CACHE_SYNC_MAP : R/W ;bitpos:[5:0] ;default: 6'h3f ; */ /*description: Those bits are used to indicate which caches in the two-level cache structure wi -ll apply the sync operation. [0]: L1-ICache0, [1]: L1-ICache1, [2]: L1-ICache2, -[3]: L1-ICache3, [4]: L1-DCache, [5]: L2-Cache..*/ -#define EXTMEM_CACHE_SYNC_MAP 0x0000003F -#define EXTMEM_CACHE_SYNC_MAP_M ((EXTMEM_CACHE_SYNC_MAP_V)<<(EXTMEM_CACHE_SYNC_MAP_S)) -#define EXTMEM_CACHE_SYNC_MAP_V 0x3F -#define EXTMEM_CACHE_SYNC_MAP_S 0 +ll apply the sync operation. [4]: L1-Cache.*/ +#define CACHE_SYNC_MAP 0x0000003F +#define CACHE_SYNC_MAP_M ((CACHE_SYNC_MAP_V)<<(CACHE_SYNC_MAP_S)) +#define CACHE_SYNC_MAP_V 0x3F +#define CACHE_SYNC_MAP_S 0 -#define EXTMEM_CACHE_SYNC_ADDR_REG (DR_REG_EXTMEM_BASE + 0xA0) -/* EXTMEM_CACHE_SYNC_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +#define CACHE_SYNC_ADDR_REG (DR_REG_CACHE_BASE + 0xA0) +/* CACHE_SYNC_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ /*description: Those bits are used to configure the start virtual address of the sync operation , which should be used together with CACHE_SYNC_SIZE_REG.*/ -#define EXTMEM_CACHE_SYNC_ADDR 0xFFFFFFFF -#define EXTMEM_CACHE_SYNC_ADDR_M ((EXTMEM_CACHE_SYNC_ADDR_V)<<(EXTMEM_CACHE_SYNC_ADDR_S)) -#define EXTMEM_CACHE_SYNC_ADDR_V 0xFFFFFFFF -#define EXTMEM_CACHE_SYNC_ADDR_S 0 +#define CACHE_SYNC_ADDR 0xFFFFFFFF +#define CACHE_SYNC_ADDR_M ((CACHE_SYNC_ADDR_V)<<(CACHE_SYNC_ADDR_S)) +#define CACHE_SYNC_ADDR_V 0xFFFFFFFF +#define CACHE_SYNC_ADDR_S 0 -#define EXTMEM_CACHE_SYNC_SIZE_REG (DR_REG_EXTMEM_BASE + 0xA4) -/* EXTMEM_CACHE_SYNC_SIZE : R/W ;bitpos:[23:0] ;default: 24'h0 ; */ +#define CACHE_SYNC_SIZE_REG (DR_REG_CACHE_BASE + 0xA4) +/* CACHE_SYNC_SIZE : R/W ;bitpos:[23:0] ;default: 24'h0 ; */ /*description: Those bits are used to configure the size of the sync operation, which should be used together with CACHE_SYNC_ADDR_REG.*/ -#define EXTMEM_CACHE_SYNC_SIZE 0x00FFFFFF -#define EXTMEM_CACHE_SYNC_SIZE_M ((EXTMEM_CACHE_SYNC_SIZE_V)<<(EXTMEM_CACHE_SYNC_SIZE_S)) -#define EXTMEM_CACHE_SYNC_SIZE_V 0xFFFFFF -#define EXTMEM_CACHE_SYNC_SIZE_S 0 +#define CACHE_SYNC_SIZE 0x00FFFFFF +#define CACHE_SYNC_SIZE_M ((CACHE_SYNC_SIZE_V)<<(CACHE_SYNC_SIZE_S)) +#define CACHE_SYNC_SIZE_V 0xFFFFFF +#define CACHE_SYNC_SIZE_S 0 -#define EXTMEM_DCACHE_PRELOAD_CTRL_REG (DR_REG_EXTMEM_BASE + 0xD8) -/* EXTMEM_DCACHE_PRELOAD_RGID : HRO ;bitpos:[6:3] ;default: 4'h0 ; */ -/*description: The bit is used to set the gid of l1 dcache preload..*/ -#define EXTMEM_DCACHE_PRELOAD_RGID 0x0000000F -#define EXTMEM_DCACHE_PRELOAD_RGID_M ((EXTMEM_DCACHE_PRELOAD_RGID_V)<<(EXTMEM_DCACHE_PRELOAD_RGID_S)) -#define EXTMEM_DCACHE_PRELOAD_RGID_V 0xF -#define EXTMEM_DCACHE_PRELOAD_RGID_S 3 -/* EXTMEM_DCACHE_PRELOAD_ORDER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +#define CACHE_L1_CACHE_PRELOAD_CTRL_REG (DR_REG_CACHE_BASE + 0xD8) +/* CACHE_L1_CACHE_PRELOAD_RGID : HRO ;bitpos:[6:3] ;default: 4'h0 ; */ +/*description: The bit is used to set the gid of l1 cache preload..*/ +#define CACHE_L1_CACHE_PRELOAD_RGID 0x0000000F +#define CACHE_L1_CACHE_PRELOAD_RGID_M ((CACHE_L1_CACHE_PRELOAD_RGID_V)<<(CACHE_L1_CACHE_PRELOAD_RGID_S)) +#define CACHE_L1_CACHE_PRELOAD_RGID_V 0xF +#define CACHE_L1_CACHE_PRELOAD_RGID_S 3 +/* CACHE_L1_CACHE_PRELOAD_ORDER : R/W ;bitpos:[2] ;default: 1'h0 ; */ /*description: The bit is used to configure the direction of preload operation. 0: ascending, 1 : descending..*/ -#define EXTMEM_DCACHE_PRELOAD_ORDER (BIT(2)) -#define EXTMEM_DCACHE_PRELOAD_ORDER_M (BIT(2)) -#define EXTMEM_DCACHE_PRELOAD_ORDER_V 0x1 -#define EXTMEM_DCACHE_PRELOAD_ORDER_S 2 -/* EXTMEM_DCACHE_PRELOAD_DONE : RO ;bitpos:[1] ;default: 1'h1 ; */ +#define CACHE_L1_CACHE_PRELOAD_ORDER (BIT(2)) +#define CACHE_L1_CACHE_PRELOAD_ORDER_M (BIT(2)) +#define CACHE_L1_CACHE_PRELOAD_ORDER_V 0x1 +#define CACHE_L1_CACHE_PRELOAD_ORDER_S 2 +/* CACHE_L1_CACHE_PRELOAD_DONE : RO ;bitpos:[1] ;default: 1'h1 ; */ /*description: The bit is used to indicate whether preload operation is finished or not. 0: not finished. 1: finished..*/ -#define EXTMEM_DCACHE_PRELOAD_DONE (BIT(1)) -#define EXTMEM_DCACHE_PRELOAD_DONE_M (BIT(1)) -#define EXTMEM_DCACHE_PRELOAD_DONE_V 0x1 -#define EXTMEM_DCACHE_PRELOAD_DONE_S 1 -/* EXTMEM_DCACHE_PRELOAD_ENA : R/W/SC ;bitpos:[0] ;default: 1'h0 ; */ -/*description: The bit is used to enable preload operation on L1-DCache. It will be cleared by -hardware automatically after preload operation is done..*/ -#define EXTMEM_DCACHE_PRELOAD_ENA (BIT(0)) -#define EXTMEM_DCACHE_PRELOAD_ENA_M (BIT(0)) -#define EXTMEM_DCACHE_PRELOAD_ENA_V 0x1 -#define EXTMEM_DCACHE_PRELOAD_ENA_S 0 +#define CACHE_L1_CACHE_PRELOAD_DONE (BIT(1)) +#define CACHE_L1_CACHE_PRELOAD_DONE_M (BIT(1)) +#define CACHE_L1_CACHE_PRELOAD_DONE_V 0x1 +#define CACHE_L1_CACHE_PRELOAD_DONE_S 1 +/* CACHE_L1_CACHE_PRELOAD_ENA : R/W/SC ;bitpos:[0] ;default: 1'h0 ; */ +/*description: The bit is used to enable preload operation on L1-Cache. It will be cleared by h +ardware automatically after preload operation is done..*/ +#define CACHE_L1_CACHE_PRELOAD_ENA (BIT(0)) +#define CACHE_L1_CACHE_PRELOAD_ENA_M (BIT(0)) +#define CACHE_L1_CACHE_PRELOAD_ENA_V 0x1 +#define CACHE_L1_CACHE_PRELOAD_ENA_S 0 -#define EXTMEM_DCACHE_PRELOAD_ADDR_REG (DR_REG_EXTMEM_BASE + 0xDC) -/* EXTMEM_DCACHE_PRELOAD_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Those bits are used to configure the start virtual address of preload on L1-DCac -he, which should be used together with L1_DCACHE_PRELOAD_SIZE_REG.*/ -#define EXTMEM_DCACHE_PRELOAD_ADDR 0xFFFFFFFF -#define EXTMEM_DCACHE_PRELOAD_ADDR_M ((EXTMEM_DCACHE_PRELOAD_ADDR_V)<<(EXTMEM_DCACHE_PRELOAD_ADDR_S)) -#define EXTMEM_DCACHE_PRELOAD_ADDR_V 0xFFFFFFFF -#define EXTMEM_DCACHE_PRELOAD_ADDR_S 0 +#define CACHE_L1_CACHE_PRELOAD_ADDR_REG (DR_REG_CACHE_BASE + 0xDC) +/* CACHE_L1_CACHE_PRELOAD_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Those bits are used to configure the start virtual address of preload on L1-Cach +e, which should be used together with L1_CACHE_PRELOAD_SIZE_REG.*/ +#define CACHE_L1_CACHE_PRELOAD_ADDR 0xFFFFFFFF +#define CACHE_L1_CACHE_PRELOAD_ADDR_M ((CACHE_L1_CACHE_PRELOAD_ADDR_V)<<(CACHE_L1_CACHE_PRELOAD_ADDR_S)) +#define CACHE_L1_CACHE_PRELOAD_ADDR_V 0xFFFFFFFF +#define CACHE_L1_CACHE_PRELOAD_ADDR_S 0 -#define EXTMEM_DCACHE_PRELOAD_SIZE_REG (DR_REG_EXTMEM_BASE + 0xE0) -/* EXTMEM_DCACHE_PRELOAD_SIZE : R/W ;bitpos:[13:0] ;default: 14'h0 ; */ +#define CACHE_L1_CACHE_PRELOAD_SIZE_REG (DR_REG_CACHE_BASE + 0xE0) +/* CACHE_L1_CACHE_PRELOAD_SIZE : R/W ;bitpos:[13:0] ;default: 14'h0 ; */ /*description: Those bits are used to configure the size of the first section of prelock on L1- -DCache, which should be used together with L1_DCACHE_PRELOAD_ADDR_REG.*/ -#define EXTMEM_DCACHE_PRELOAD_SIZE 0x00003FFF -#define EXTMEM_DCACHE_PRELOAD_SIZE_M ((EXTMEM_DCACHE_PRELOAD_SIZE_V)<<(EXTMEM_DCACHE_PRELOAD_SIZE_S)) -#define EXTMEM_DCACHE_PRELOAD_SIZE_V 0x3FFF -#define EXTMEM_DCACHE_PRELOAD_SIZE_S 0 +Cache, which should be used together with L1_CACHE_PRELOAD_ADDR_REG.*/ +#define CACHE_L1_CACHE_PRELOAD_SIZE 0x00003FFF +#define CACHE_L1_CACHE_PRELOAD_SIZE_M ((CACHE_L1_CACHE_PRELOAD_SIZE_V)<<(CACHE_L1_CACHE_PRELOAD_SIZE_S)) +#define CACHE_L1_CACHE_PRELOAD_SIZE_V 0x3FFF +#define CACHE_L1_CACHE_PRELOAD_SIZE_S 0 -#define EXTMEM_DCACHE_AUTOLOAD_CTRL_REG (DR_REG_EXTMEM_BASE + 0x134) -/* EXTMEM_DCACHE_AUTOLOAD_SCT1_ENA : R/W ;bitpos:[9] ;default: 1'h0 ; */ -/*description: The bit is used to enable the second section for autoload operation on L1-DCache -..*/ -#define EXTMEM_DCACHE_AUTOLOAD_SCT1_ENA (BIT(9)) -#define EXTMEM_DCACHE_AUTOLOAD_SCT1_ENA_M (BIT(9)) -#define EXTMEM_DCACHE_AUTOLOAD_SCT1_ENA_V 0x1 -#define EXTMEM_DCACHE_AUTOLOAD_SCT1_ENA_S 9 -/* EXTMEM_DCACHE_AUTOLOAD_SCT0_ENA : R/W ;bitpos:[8] ;default: 1'h0 ; */ -/*description: The bit is used to enable the first section for autoload operation on L1-DCache..*/ -#define EXTMEM_DCACHE_AUTOLOAD_SCT0_ENA (BIT(8)) -#define EXTMEM_DCACHE_AUTOLOAD_SCT0_ENA_M (BIT(8)) -#define EXTMEM_DCACHE_AUTOLOAD_SCT0_ENA_V 0x1 -#define EXTMEM_DCACHE_AUTOLOAD_SCT0_ENA_S 8 -/* EXTMEM_DCACHE_AUTOLOAD_TRIGGER_MODE : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ -/*description: The field is used to configure trigger mode of autoload operation on L1-DCache. -0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger..*/ -#define EXTMEM_DCACHE_AUTOLOAD_TRIGGER_MODE 0x00000003 -#define EXTMEM_DCACHE_AUTOLOAD_TRIGGER_MODE_M ((EXTMEM_DCACHE_AUTOLOAD_TRIGGER_MODE_V)<<(EXTMEM_DCACHE_AUTOLOAD_TRIGGER_MODE_S)) -#define EXTMEM_DCACHE_AUTOLOAD_TRIGGER_MODE_V 0x3 -#define EXTMEM_DCACHE_AUTOLOAD_TRIGGER_MODE_S 3 -/* EXTMEM_DCACHE_AUTOLOAD_ORDER : R/W ;bitpos:[2] ;default: 1'h0 ; */ -/*description: The bit is used to configure the direction of autoload operation on L1-DCache. 0 -: ascending. 1: descending..*/ -#define EXTMEM_DCACHE_AUTOLOAD_ORDER (BIT(2)) -#define EXTMEM_DCACHE_AUTOLOAD_ORDER_M (BIT(2)) -#define EXTMEM_DCACHE_AUTOLOAD_ORDER_V 0x1 -#define EXTMEM_DCACHE_AUTOLOAD_ORDER_S 2 -/* EXTMEM_DCACHE_AUTOLOAD_DONE : RO ;bitpos:[1] ;default: 1'h1 ; */ -/*description: The bit is used to indicate whether autoload operation on L1-DCache is finished -or not. 0: not finished. 1: finished..*/ -#define EXTMEM_DCACHE_AUTOLOAD_DONE (BIT(1)) -#define EXTMEM_DCACHE_AUTOLOAD_DONE_M (BIT(1)) -#define EXTMEM_DCACHE_AUTOLOAD_DONE_V 0x1 -#define EXTMEM_DCACHE_AUTOLOAD_DONE_S 1 -/* EXTMEM_DCACHE_AUTOLOAD_ENA : R/W ;bitpos:[0] ;default: 1'h0 ; */ -/*description: The bit is used to enable and disable autoload operation on L1-DCache. 1: enabl -e, 0: disable..*/ -#define EXTMEM_DCACHE_AUTOLOAD_ENA (BIT(0)) -#define EXTMEM_DCACHE_AUTOLOAD_ENA_M (BIT(0)) -#define EXTMEM_DCACHE_AUTOLOAD_ENA_V 0x1 -#define EXTMEM_DCACHE_AUTOLOAD_ENA_S 0 +#define CACHE_L1_CACHE_AUTOLOAD_CTRL_REG (DR_REG_CACHE_BASE + 0x134) +/* CACHE_L1_CACHE_AUTOLOAD_SCT1_ENA : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: The bit is used to enable the second section for autoload operation on L1-Cache..*/ +#define CACHE_L1_CACHE_AUTOLOAD_SCT1_ENA (BIT(9)) +#define CACHE_L1_CACHE_AUTOLOAD_SCT1_ENA_M (BIT(9)) +#define CACHE_L1_CACHE_AUTOLOAD_SCT1_ENA_V 0x1 +#define CACHE_L1_CACHE_AUTOLOAD_SCT1_ENA_S 9 +/* CACHE_L1_CACHE_AUTOLOAD_SCT0_ENA : R/W ;bitpos:[8] ;default: 1'h0 ; */ +/*description: The bit is used to enable the first section for autoload operation on L1-Cache..*/ +#define CACHE_L1_CACHE_AUTOLOAD_SCT0_ENA (BIT(8)) +#define CACHE_L1_CACHE_AUTOLOAD_SCT0_ENA_M (BIT(8)) +#define CACHE_L1_CACHE_AUTOLOAD_SCT0_ENA_V 0x1 +#define CACHE_L1_CACHE_AUTOLOAD_SCT0_ENA_S 8 +/* CACHE_L1_CACHE_AUTOLOAD_TRIGGER_MODE : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: The field is used to configure trigger mode of autoload operation on L1-Cache. 0 +/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger..*/ +#define CACHE_L1_CACHE_AUTOLOAD_TRIGGER_MODE 0x00000003 +#define CACHE_L1_CACHE_AUTOLOAD_TRIGGER_MODE_M ((CACHE_L1_CACHE_AUTOLOAD_TRIGGER_MODE_V)<<(CACHE_L1_CACHE_AUTOLOAD_TRIGGER_MODE_S)) +#define CACHE_L1_CACHE_AUTOLOAD_TRIGGER_MODE_V 0x3 +#define CACHE_L1_CACHE_AUTOLOAD_TRIGGER_MODE_S 3 +/* CACHE_L1_CACHE_AUTOLOAD_ORDER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: The bit is used to configure the direction of autoload operation on L1-Cache. 0: + ascending. 1: descending..*/ +#define CACHE_L1_CACHE_AUTOLOAD_ORDER (BIT(2)) +#define CACHE_L1_CACHE_AUTOLOAD_ORDER_M (BIT(2)) +#define CACHE_L1_CACHE_AUTOLOAD_ORDER_V 0x1 +#define CACHE_L1_CACHE_AUTOLOAD_ORDER_S 2 +/* CACHE_L1_CACHE_AUTOLOAD_DONE : RO ;bitpos:[1] ;default: 1'h1 ; */ +/*description: The bit is used to indicate whether autoload operation on L1-Cache is finished o +r not. 0: not finished. 1: finished..*/ +#define CACHE_L1_CACHE_AUTOLOAD_DONE (BIT(1)) +#define CACHE_L1_CACHE_AUTOLOAD_DONE_M (BIT(1)) +#define CACHE_L1_CACHE_AUTOLOAD_DONE_V 0x1 +#define CACHE_L1_CACHE_AUTOLOAD_DONE_S 1 +/* CACHE_L1_CACHE_AUTOLOAD_ENA : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: The bit is used to enable and disable autoload operation on L1-Cache. 1: enable +, 0: disable..*/ +#define CACHE_L1_CACHE_AUTOLOAD_ENA (BIT(0)) +#define CACHE_L1_CACHE_AUTOLOAD_ENA_M (BIT(0)) +#define CACHE_L1_CACHE_AUTOLOAD_ENA_V 0x1 +#define CACHE_L1_CACHE_AUTOLOAD_ENA_S 0 -#define EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR_REG (DR_REG_EXTMEM_BASE + 0x138) -/* EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +#define CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x138) +/* CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ /*description: Those bits are used to configure the start virtual address of the first section -for autoload operation on L1-DCache. Note that it should be used together with L -1_DCACHE_AUTOLOAD_SCT0_SIZE and L1_DCACHE_AUTOLOAD_SCT0_ENA..*/ -#define EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR 0xFFFFFFFF -#define EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR_M ((EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR_V)<<(EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR_S)) -#define EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR_V 0xFFFFFFFF -#define EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR_S 0 +for autoload operation on L1-Cache. Note that it should be used together with L1 +_CACHE_AUTOLOAD_SCT0_SIZE and L1_CACHE_AUTOLOAD_SCT0_ENA..*/ +#define CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR 0xFFFFFFFF +#define CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR_M ((CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR_V)<<(CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR_S)) +#define CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR_V 0xFFFFFFFF +#define CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR_S 0 -#define EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE_REG (DR_REG_EXTMEM_BASE + 0x13C) -/* EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE : R/W ;bitpos:[27:0] ;default: 28'h0 ; */ +#define CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE_REG (DR_REG_CACHE_BASE + 0x13C) +/* CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE : R/W ;bitpos:[23:0] ;default: 24'h0 ; */ /*description: Those bits are used to configure the size of the first section for autoload oper -ation on L1-DCache. Note that it should be used together with L1_DCACHE_AUTOLOAD -_SCT0_ADDR and L1_DCACHE_AUTOLOAD_SCT0_ENA..*/ -#define EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE 0x0FFFFFFF -#define EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE_M ((EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE_V)<<(EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE_S)) -#define EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE_V 0xFFFFFFF -#define EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE_S 0 +ation on L1-Cache. Note that it should be used together with L1_CACHE_AUTOLOAD_S +CT0_ADDR and L1_CACHE_AUTOLOAD_SCT0_ENA..*/ +#define CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE 0x00FFFFFF +#define CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE_M ((CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE_V)<<(CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE_S)) +#define CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE_V 0xFFFFFF +#define CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE_S 0 -#define EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR_REG (DR_REG_EXTMEM_BASE + 0x140) -/* EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +#define CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x140) +/* CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ /*description: Those bits are used to configure the start virtual address of the second section - for autoload operation on L1-DCache. Note that it should be used together with -L1_DCACHE_AUTOLOAD_SCT1_SIZE and L1_DCACHE_AUTOLOAD_SCT1_ENA..*/ -#define EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR 0xFFFFFFFF -#define EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR_M ((EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR_V)<<(EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR_S)) -#define EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR_V 0xFFFFFFFF -#define EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR_S 0 + for autoload operation on L1-Cache. Note that it should be used together with L +1_CACHE_AUTOLOAD_SCT1_SIZE and L1_CACHE_AUTOLOAD_SCT1_ENA..*/ +#define CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR 0xFFFFFFFF +#define CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR_M ((CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR_V)<<(CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR_S)) +#define CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR_V 0xFFFFFFFF +#define CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR_S 0 -#define EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE_REG (DR_REG_EXTMEM_BASE + 0x144) -/* EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE : R/W ;bitpos:[27:0] ;default: 28'h0 ; */ +#define CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE_REG (DR_REG_CACHE_BASE + 0x144) +/* CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE : R/W ;bitpos:[23:0] ;default: 24'h0 ; */ /*description: Those bits are used to configure the size of the second section for autoload ope -ration on L1-DCache. Note that it should be used together with L1_DCACHE_AUTOLOA -D_SCT1_ADDR and L1_DCACHE_AUTOLOAD_SCT1_ENA..*/ -#define EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE 0x0FFFFFFF -#define EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE_M ((EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE_V)<<(EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE_S)) -#define EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE_V 0xFFFFFFF -#define EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE_S 0 +ration on L1-Cache. Note that it should be used together with L1_CACHE_AUTOLOAD_ +SCT1_ADDR and L1_CACHE_AUTOLOAD_SCT1_ENA..*/ +#define CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE 0x00FFFFFF +#define CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE_M ((CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE_V)<<(CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE_S)) +#define CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE_V 0xFFFFFF +#define CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE_S 0 -#define EXTMEM_CACHE_ACS_CNT_INT_ENA_REG (DR_REG_EXTMEM_BASE + 0x158) -/* EXTMEM_DBUS1_OVF_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ +#define CACHE_L1_CACHE_AUTOLOAD_SCT2_ADDR_REG (DR_REG_CACHE_BASE + 0x148) +/* CACHE_L1_CACHE_AUTOLOAD_SCT2_ADDR : HRO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Those bits are used to configure the start virtual address of the third section +for autoload operation on L1-Cache. Note that it should be used together with L1 +_CACHE_AUTOLOAD_SCT2_SIZE and L1_CACHE_AUTOLOAD_SCT2_ENA..*/ +#define CACHE_L1_CACHE_AUTOLOAD_SCT2_ADDR 0xFFFFFFFF +#define CACHE_L1_CACHE_AUTOLOAD_SCT2_ADDR_M ((CACHE_L1_CACHE_AUTOLOAD_SCT2_ADDR_V)<<(CACHE_L1_CACHE_AUTOLOAD_SCT2_ADDR_S)) +#define CACHE_L1_CACHE_AUTOLOAD_SCT2_ADDR_V 0xFFFFFFFF +#define CACHE_L1_CACHE_AUTOLOAD_SCT2_ADDR_S 0 + +#define CACHE_L1_CACHE_AUTOLOAD_SCT2_SIZE_REG (DR_REG_CACHE_BASE + 0x14C) +/* CACHE_L1_CACHE_AUTOLOAD_SCT2_SIZE : HRO ;bitpos:[23:0] ;default: 24'h0 ; */ +/*description: Those bits are used to configure the size of the third section for autoload oper +ation on L1-Cache. Note that it should be used together with L1_CACHE_AUTOLOAD_S +CT2_ADDR and L1_CACHE_AUTOLOAD_SCT2_ENA..*/ +#define CACHE_L1_CACHE_AUTOLOAD_SCT2_SIZE 0x00FFFFFF +#define CACHE_L1_CACHE_AUTOLOAD_SCT2_SIZE_M ((CACHE_L1_CACHE_AUTOLOAD_SCT2_SIZE_V)<<(CACHE_L1_CACHE_AUTOLOAD_SCT2_SIZE_S)) +#define CACHE_L1_CACHE_AUTOLOAD_SCT2_SIZE_V 0xFFFFFF +#define CACHE_L1_CACHE_AUTOLOAD_SCT2_SIZE_S 0 + +#define CACHE_L1_CACHE_AUTOLOAD_SCT3_ADDR_REG (DR_REG_CACHE_BASE + 0x150) +/* CACHE_L1_CACHE_AUTOLOAD_SCT3_ADDR : HRO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Those bits are used to configure the start virtual address of the fourth section + for autoload operation on L1-Cache. Note that it should be used together with L +1_CACHE_AUTOLOAD_SCT3_SIZE and L1_CACHE_AUTOLOAD_SCT3_ENA..*/ +#define CACHE_L1_CACHE_AUTOLOAD_SCT3_ADDR 0xFFFFFFFF +#define CACHE_L1_CACHE_AUTOLOAD_SCT3_ADDR_M ((CACHE_L1_CACHE_AUTOLOAD_SCT3_ADDR_V)<<(CACHE_L1_CACHE_AUTOLOAD_SCT3_ADDR_S)) +#define CACHE_L1_CACHE_AUTOLOAD_SCT3_ADDR_V 0xFFFFFFFF +#define CACHE_L1_CACHE_AUTOLOAD_SCT3_ADDR_S 0 + +#define CACHE_L1_CACHE_AUTOLOAD_SCT3_SIZE_REG (DR_REG_CACHE_BASE + 0x154) +/* CACHE_L1_CACHE_AUTOLOAD_SCT3_SIZE : HRO ;bitpos:[23:0] ;default: 24'h0 ; */ +/*description: Those bits are used to configure the size of the fourth section for autoload ope +ration on L1-Cache. Note that it should be used together with L1_CACHE_AUTOLOAD_ +SCT3_ADDR and L1_CACHE_AUTOLOAD_SCT3_ENA..*/ +#define CACHE_L1_CACHE_AUTOLOAD_SCT3_SIZE 0x00FFFFFF +#define CACHE_L1_CACHE_AUTOLOAD_SCT3_SIZE_M ((CACHE_L1_CACHE_AUTOLOAD_SCT3_SIZE_V)<<(CACHE_L1_CACHE_AUTOLOAD_SCT3_SIZE_S)) +#define CACHE_L1_CACHE_AUTOLOAD_SCT3_SIZE_V 0xFFFFFF +#define CACHE_L1_CACHE_AUTOLOAD_SCT3_SIZE_S 0 + +#define CACHE_L1_CACHE_ACS_CNT_INT_ENA_REG (DR_REG_CACHE_BASE + 0x158) +/* CACHE_L1_BUS1_OVF_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ /*description: The bit is used to enable interrupt of one of counters overflow that occurs in L 1-DCache due to bus1 accesses L1-DCache..*/ -#define EXTMEM_DBUS1_OVF_INT_ENA (BIT(5)) -#define EXTMEM_DBUS1_OVF_INT_ENA_M (BIT(5)) -#define EXTMEM_DBUS1_OVF_INT_ENA_V 0x1 -#define EXTMEM_DBUS1_OVF_INT_ENA_S 5 -/* EXTMEM_DBUS0_OVF_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +#define CACHE_L1_BUS1_OVF_INT_ENA (BIT(5)) +#define CACHE_L1_BUS1_OVF_INT_ENA_M (BIT(5)) +#define CACHE_L1_BUS1_OVF_INT_ENA_V 0x1 +#define CACHE_L1_BUS1_OVF_INT_ENA_S 5 +/* CACHE_L1_BUS0_OVF_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ /*description: The bit is used to enable interrupt of one of counters overflow that occurs in L 1-DCache due to bus0 accesses L1-DCache..*/ -#define EXTMEM_DBUS0_OVF_INT_ENA (BIT(4)) -#define EXTMEM_DBUS0_OVF_INT_ENA_M (BIT(4)) -#define EXTMEM_DBUS0_OVF_INT_ENA_V 0x1 -#define EXTMEM_DBUS0_OVF_INT_ENA_S 4 +#define CACHE_L1_BUS0_OVF_INT_ENA (BIT(4)) +#define CACHE_L1_BUS0_OVF_INT_ENA_M (BIT(4)) +#define CACHE_L1_BUS0_OVF_INT_ENA_V 0x1 +#define CACHE_L1_BUS0_OVF_INT_ENA_S 4 -#define EXTMEM_CACHE_ACS_CNT_INT_CLR_REG (DR_REG_EXTMEM_BASE + 0x15C) -/* EXTMEM_DBUS1_OVF_INT_CLR : WT ;bitpos:[5] ;default: 1'b0 ; */ +#define CACHE_L1_CACHE_ACS_CNT_INT_CLR_REG (DR_REG_CACHE_BASE + 0x15C) +/* CACHE_L1_BUS1_OVF_INT_CLR : WT ;bitpos:[5] ;default: 1'b0 ; */ /*description: The bit is used to clear counters overflow interrupt and counters in L1-DCache d ue to bus1 accesses L1-DCache..*/ -#define EXTMEM_DBUS1_OVF_INT_CLR (BIT(5)) -#define EXTMEM_DBUS1_OVF_INT_CLR_M (BIT(5)) -#define EXTMEM_DBUS1_OVF_INT_CLR_V 0x1 -#define EXTMEM_DBUS1_OVF_INT_CLR_S 5 -/* EXTMEM_DBUS0_OVF_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */ +#define CACHE_L1_BUS1_OVF_INT_CLR (BIT(5)) +#define CACHE_L1_BUS1_OVF_INT_CLR_M (BIT(5)) +#define CACHE_L1_BUS1_OVF_INT_CLR_V 0x1 +#define CACHE_L1_BUS1_OVF_INT_CLR_S 5 +/* CACHE_L1_BUS0_OVF_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */ /*description: The bit is used to clear counters overflow interrupt and counters in L1-DCache d ue to bus0 accesses L1-DCache..*/ -#define EXTMEM_DBUS0_OVF_INT_CLR (BIT(4)) -#define EXTMEM_DBUS0_OVF_INT_CLR_M (BIT(4)) -#define EXTMEM_DBUS0_OVF_INT_CLR_V 0x1 -#define EXTMEM_DBUS0_OVF_INT_CLR_S 4 +#define CACHE_L1_BUS0_OVF_INT_CLR (BIT(4)) +#define CACHE_L1_BUS0_OVF_INT_CLR_M (BIT(4)) +#define CACHE_L1_BUS0_OVF_INT_CLR_V 0x1 +#define CACHE_L1_BUS0_OVF_INT_CLR_S 4 -#define EXTMEM_CACHE_ACS_CNT_INT_RAW_REG (DR_REG_EXTMEM_BASE + 0x160) -/* EXTMEM_DBUS1_OVF_INT_RAW : R/WTC/SS ;bitpos:[5] ;default: 1'b0 ; */ +#define CACHE_L1_CACHE_ACS_CNT_INT_RAW_REG (DR_REG_CACHE_BASE + 0x160) +/* CACHE_L1_BUS1_OVF_INT_RAW : R/WTC/SS ;bitpos:[5] ;default: 1'b0 ; */ /*description: The raw bit of the interrupt of one of counters overflow that occurs in L1-DCach e due to bus1 accesses L1-DCache..*/ -#define EXTMEM_DBUS1_OVF_INT_RAW (BIT(5)) -#define EXTMEM_DBUS1_OVF_INT_RAW_M (BIT(5)) -#define EXTMEM_DBUS1_OVF_INT_RAW_V 0x1 -#define EXTMEM_DBUS1_OVF_INT_RAW_S 5 -/* EXTMEM_DBUS0_OVF_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */ +#define CACHE_L1_BUS1_OVF_INT_RAW (BIT(5)) +#define CACHE_L1_BUS1_OVF_INT_RAW_M (BIT(5)) +#define CACHE_L1_BUS1_OVF_INT_RAW_V 0x1 +#define CACHE_L1_BUS1_OVF_INT_RAW_S 5 +/* CACHE_L1_BUS0_OVF_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */ /*description: The raw bit of the interrupt of one of counters overflow that occurs in L1-DCach e due to bus0 accesses L1-DCache..*/ -#define EXTMEM_DBUS0_OVF_INT_RAW (BIT(4)) -#define EXTMEM_DBUS0_OVF_INT_RAW_M (BIT(4)) -#define EXTMEM_DBUS0_OVF_INT_RAW_V 0x1 -#define EXTMEM_DBUS0_OVF_INT_RAW_S 4 +#define CACHE_L1_BUS0_OVF_INT_RAW (BIT(4)) +#define CACHE_L1_BUS0_OVF_INT_RAW_M (BIT(4)) +#define CACHE_L1_BUS0_OVF_INT_RAW_V 0x1 +#define CACHE_L1_BUS0_OVF_INT_RAW_S 4 -#define EXTMEM_CACHE_ACS_CNT_INT_ST_REG (DR_REG_EXTMEM_BASE + 0x164) -/* EXTMEM_DBUS1_OVF_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ +#define CACHE_L1_CACHE_ACS_CNT_INT_ST_REG (DR_REG_CACHE_BASE + 0x164) +/* CACHE_L1_BUS1_OVF_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ /*description: The bit indicates the interrupt status of one of counters overflow that occurs i n L1-DCache due to bus1 accesses L1-DCache..*/ -#define EXTMEM_DBUS1_OVF_INT_ST (BIT(5)) -#define EXTMEM_DBUS1_OVF_INT_ST_M (BIT(5)) -#define EXTMEM_DBUS1_OVF_INT_ST_V 0x1 -#define EXTMEM_DBUS1_OVF_INT_ST_S 5 -/* EXTMEM_DBUS0_OVF_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ +#define CACHE_L1_BUS1_OVF_INT_ST (BIT(5)) +#define CACHE_L1_BUS1_OVF_INT_ST_M (BIT(5)) +#define CACHE_L1_BUS1_OVF_INT_ST_V 0x1 +#define CACHE_L1_BUS1_OVF_INT_ST_S 5 +/* CACHE_L1_BUS0_OVF_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ /*description: The bit indicates the interrupt status of one of counters overflow that occurs i n L1-DCache due to bus0 accesses L1-DCache..*/ -#define EXTMEM_DBUS0_OVF_INT_ST (BIT(4)) -#define EXTMEM_DBUS0_OVF_INT_ST_M (BIT(4)) -#define EXTMEM_DBUS0_OVF_INT_ST_V 0x1 -#define EXTMEM_DBUS0_OVF_INT_ST_S 4 +#define CACHE_L1_BUS0_OVF_INT_ST (BIT(4)) +#define CACHE_L1_BUS0_OVF_INT_ST_M (BIT(4)) +#define CACHE_L1_BUS0_OVF_INT_ST_V 0x1 +#define CACHE_L1_BUS0_OVF_INT_ST_S 4 -#define EXTMEM_CACHE_ACS_FAIL_INT_ENA_REG (DR_REG_EXTMEM_BASE + 0x168) -/* EXTMEM_DCACHE_FAIL_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +#define CACHE_L1_CACHE_ACS_FAIL_INT_ENA_REG (DR_REG_CACHE_BASE + 0x168) +/* CACHE_L1_CACHE_FAIL_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ /*description: The bit is used to enable interrupt of access fail that occurs in L1-DCache due to cpu accesses L1-DCache..*/ -#define EXTMEM_DCACHE_FAIL_INT_ENA (BIT(4)) -#define EXTMEM_DCACHE_FAIL_INT_ENA_M (BIT(4)) -#define EXTMEM_DCACHE_FAIL_INT_ENA_V 0x1 -#define EXTMEM_DCACHE_FAIL_INT_ENA_S 4 +#define CACHE_L1_CACHE_FAIL_INT_ENA (BIT(4)) +#define CACHE_L1_CACHE_FAIL_INT_ENA_M (BIT(4)) +#define CACHE_L1_CACHE_FAIL_INT_ENA_V 0x1 +#define CACHE_L1_CACHE_FAIL_INT_ENA_S 4 -#define EXTMEM_CACHE_ACS_FAIL_INT_CLR_REG (DR_REG_EXTMEM_BASE + 0x16C) -/* EXTMEM_DCACHE_FAIL_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */ +#define CACHE_L1_CACHE_ACS_FAIL_INT_CLR_REG (DR_REG_CACHE_BASE + 0x16C) +/* CACHE_L1_CACHE_FAIL_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */ /*description: The bit is used to clear interrupt of access fail that occurs in L1-DCache due t o cpu accesses L1-DCache..*/ -#define EXTMEM_DCACHE_FAIL_INT_CLR (BIT(4)) -#define EXTMEM_DCACHE_FAIL_INT_CLR_M (BIT(4)) -#define EXTMEM_DCACHE_FAIL_INT_CLR_V 0x1 -#define EXTMEM_DCACHE_FAIL_INT_CLR_S 4 +#define CACHE_L1_CACHE_FAIL_INT_CLR (BIT(4)) +#define CACHE_L1_CACHE_FAIL_INT_CLR_M (BIT(4)) +#define CACHE_L1_CACHE_FAIL_INT_CLR_V 0x1 +#define CACHE_L1_CACHE_FAIL_INT_CLR_S 4 -#define EXTMEM_CACHE_ACS_FAIL_INT_RAW_REG (DR_REG_EXTMEM_BASE + 0x170) -/* EXTMEM_DCACHE_FAIL_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */ +#define CACHE_L1_CACHE_ACS_FAIL_INT_RAW_REG (DR_REG_CACHE_BASE + 0x170) +/* CACHE_L1_CACHE_FAIL_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */ /*description: The raw bit of the interrupt of access fail that occurs in L1-DCache..*/ -#define EXTMEM_DCACHE_FAIL_INT_RAW (BIT(4)) -#define EXTMEM_DCACHE_FAIL_INT_RAW_M (BIT(4)) -#define EXTMEM_DCACHE_FAIL_INT_RAW_V 0x1 -#define EXTMEM_DCACHE_FAIL_INT_RAW_S 4 +#define CACHE_L1_CACHE_FAIL_INT_RAW (BIT(4)) +#define CACHE_L1_CACHE_FAIL_INT_RAW_M (BIT(4)) +#define CACHE_L1_CACHE_FAIL_INT_RAW_V 0x1 +#define CACHE_L1_CACHE_FAIL_INT_RAW_S 4 -#define EXTMEM_CACHE_ACS_FAIL_INT_ST_REG (DR_REG_EXTMEM_BASE + 0x174) -/* EXTMEM_DCACHE_FAIL_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ +#define CACHE_L1_CACHE_ACS_FAIL_INT_ST_REG (DR_REG_CACHE_BASE + 0x174) +/* CACHE_L1_CACHE_FAIL_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ /*description: The bit indicates the interrupt status of access fail that occurs in L1-DCache d ue to cpu accesses L1-DCache..*/ -#define EXTMEM_DCACHE_FAIL_INT_ST (BIT(4)) -#define EXTMEM_DCACHE_FAIL_INT_ST_M (BIT(4)) -#define EXTMEM_DCACHE_FAIL_INT_ST_V 0x1 -#define EXTMEM_DCACHE_FAIL_INT_ST_S 4 +#define CACHE_L1_CACHE_FAIL_INT_ST (BIT(4)) +#define CACHE_L1_CACHE_FAIL_INT_ST_M (BIT(4)) +#define CACHE_L1_CACHE_FAIL_INT_ST_V 0x1 +#define CACHE_L1_CACHE_FAIL_INT_ST_S 4 -#define EXTMEM_CACHE_ACS_CNT_CTRL_REG (DR_REG_EXTMEM_BASE + 0x178) -/* EXTMEM_DBUS1_CNT_CLR : WT ;bitpos:[21] ;default: 1'b0 ; */ +#define CACHE_L1_CACHE_ACS_CNT_CTRL_REG (DR_REG_CACHE_BASE + 0x178) +/* CACHE_L1_BUS1_CNT_CLR : WT ;bitpos:[21] ;default: 1'b0 ; */ /*description: The bit is used to clear dbus1 counter in L1-DCache..*/ -#define EXTMEM_DBUS1_CNT_CLR (BIT(21)) -#define EXTMEM_DBUS1_CNT_CLR_M (BIT(21)) -#define EXTMEM_DBUS1_CNT_CLR_V 0x1 -#define EXTMEM_DBUS1_CNT_CLR_S 21 -/* EXTMEM_DBUS0_CNT_CLR : WT ;bitpos:[20] ;default: 1'b0 ; */ +#define CACHE_L1_BUS1_CNT_CLR (BIT(21)) +#define CACHE_L1_BUS1_CNT_CLR_M (BIT(21)) +#define CACHE_L1_BUS1_CNT_CLR_V 0x1 +#define CACHE_L1_BUS1_CNT_CLR_S 21 +/* CACHE_L1_BUS0_CNT_CLR : WT ;bitpos:[20] ;default: 1'b0 ; */ /*description: The bit is used to clear dbus0 counter in L1-DCache..*/ -#define EXTMEM_DBUS0_CNT_CLR (BIT(20)) -#define EXTMEM_DBUS0_CNT_CLR_M (BIT(20)) -#define EXTMEM_DBUS0_CNT_CLR_V 0x1 -#define EXTMEM_DBUS0_CNT_CLR_S 20 -/* EXTMEM_DBUS1_CNT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ +#define CACHE_L1_BUS0_CNT_CLR (BIT(20)) +#define CACHE_L1_BUS0_CNT_CLR_M (BIT(20)) +#define CACHE_L1_BUS0_CNT_CLR_V 0x1 +#define CACHE_L1_BUS0_CNT_CLR_S 20 +/* CACHE_L1_BUS1_CNT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ /*description: The bit is used to enable dbus1 counter in L1-DCache..*/ -#define EXTMEM_DBUS1_CNT_ENA (BIT(5)) -#define EXTMEM_DBUS1_CNT_ENA_M (BIT(5)) -#define EXTMEM_DBUS1_CNT_ENA_V 0x1 -#define EXTMEM_DBUS1_CNT_ENA_S 5 -/* EXTMEM_DBUS0_CNT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +#define CACHE_L1_BUS1_CNT_ENA (BIT(5)) +#define CACHE_L1_BUS1_CNT_ENA_M (BIT(5)) +#define CACHE_L1_BUS1_CNT_ENA_V 0x1 +#define CACHE_L1_BUS1_CNT_ENA_S 5 +/* CACHE_L1_BUS0_CNT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ /*description: The bit is used to enable dbus0 counter in L1-DCache..*/ -#define EXTMEM_DBUS0_CNT_ENA (BIT(4)) -#define EXTMEM_DBUS0_CNT_ENA_M (BIT(4)) -#define EXTMEM_DBUS0_CNT_ENA_V 0x1 -#define EXTMEM_DBUS0_CNT_ENA_S 4 +#define CACHE_L1_BUS0_CNT_ENA (BIT(4)) +#define CACHE_L1_BUS0_CNT_ENA_M (BIT(4)) +#define CACHE_L1_BUS0_CNT_ENA_V 0x1 +#define CACHE_L1_BUS0_CNT_ENA_S 4 -#define EXTMEM_DBUS0_ACS_HIT_CNT_REG (DR_REG_EXTMEM_BASE + 0x1BC) -/* EXTMEM_DBUS0_HIT_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The register records the number of hits when bus0 accesses L1-DCache..*/ -#define EXTMEM_DBUS0_HIT_CNT 0xFFFFFFFF -#define EXTMEM_DBUS0_HIT_CNT_M ((EXTMEM_DBUS0_HIT_CNT_V)<<(EXTMEM_DBUS0_HIT_CNT_S)) -#define EXTMEM_DBUS0_HIT_CNT_V 0xFFFFFFFF -#define EXTMEM_DBUS0_HIT_CNT_S 0 +#define CACHE_L1_BUS0_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x1BC) +/* CACHE_L1_BUS0_HIT_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The register records the number of hits when bus0 accesses L1-Cache..*/ +#define CACHE_L1_BUS0_HIT_CNT 0xFFFFFFFF +#define CACHE_L1_BUS0_HIT_CNT_M ((CACHE_L1_BUS0_HIT_CNT_V)<<(CACHE_L1_BUS0_HIT_CNT_S)) +#define CACHE_L1_BUS0_HIT_CNT_V 0xFFFFFFFF +#define CACHE_L1_BUS0_HIT_CNT_S 0 -#define EXTMEM_DBUS0_ACS_MISS_CNT_REG (DR_REG_EXTMEM_BASE + 0x1C0) -/* EXTMEM_DBUS0_MISS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The register records the number of missing when bus0 accesses L1-DCache..*/ -#define EXTMEM_DBUS0_MISS_CNT 0xFFFFFFFF -#define EXTMEM_DBUS0_MISS_CNT_M ((EXTMEM_DBUS0_MISS_CNT_V)<<(EXTMEM_DBUS0_MISS_CNT_S)) -#define EXTMEM_DBUS0_MISS_CNT_V 0xFFFFFFFF -#define EXTMEM_DBUS0_MISS_CNT_S 0 +#define CACHE_L1_BUS0_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x1C0) +/* CACHE_L1_BUS0_MISS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The register records the number of missing when bus0 accesses L1-Cache..*/ +#define CACHE_L1_BUS0_MISS_CNT 0xFFFFFFFF +#define CACHE_L1_BUS0_MISS_CNT_M ((CACHE_L1_BUS0_MISS_CNT_V)<<(CACHE_L1_BUS0_MISS_CNT_S)) +#define CACHE_L1_BUS0_MISS_CNT_V 0xFFFFFFFF +#define CACHE_L1_BUS0_MISS_CNT_S 0 -#define EXTMEM_DBUS0_ACS_CONFLICT_CNT_REG (DR_REG_EXTMEM_BASE + 0x1C4) -/* EXTMEM_DBUS0_CONFLICT_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The register records the number of access-conflicts when bus0 accesses L1-DCache +#define CACHE_L1_BUS0_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x1C4) +/* CACHE_L1_BUS0_CONFLICT_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The register records the number of access-conflicts when bus0 accesses L1-Cache..*/ +#define CACHE_L1_BUS0_CONFLICT_CNT 0xFFFFFFFF +#define CACHE_L1_BUS0_CONFLICT_CNT_M ((CACHE_L1_BUS0_CONFLICT_CNT_V)<<(CACHE_L1_BUS0_CONFLICT_CNT_S)) +#define CACHE_L1_BUS0_CONFLICT_CNT_V 0xFFFFFFFF +#define CACHE_L1_BUS0_CONFLICT_CNT_S 0 + +#define CACHE_L1_BUS0_ACS_NXTLVL_CNT_REG (DR_REG_CACHE_BASE + 0x1C8) +/* CACHE_L1_BUS0_NXTLVL_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The register records the number of times that L1-Cache accesses L2-Cache due to +bus0 accessing L1-Cache..*/ +#define CACHE_L1_BUS0_NXTLVL_CNT 0xFFFFFFFF +#define CACHE_L1_BUS0_NXTLVL_CNT_M ((CACHE_L1_BUS0_NXTLVL_CNT_V)<<(CACHE_L1_BUS0_NXTLVL_CNT_S)) +#define CACHE_L1_BUS0_NXTLVL_CNT_V 0xFFFFFFFF +#define CACHE_L1_BUS0_NXTLVL_CNT_S 0 + +#define CACHE_L1_BUS1_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x1CC) +/* CACHE_L1_BUS1_HIT_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The register records the number of hits when bus1 accesses L1-Cache..*/ +#define CACHE_L1_BUS1_HIT_CNT 0xFFFFFFFF +#define CACHE_L1_BUS1_HIT_CNT_M ((CACHE_L1_BUS1_HIT_CNT_V)<<(CACHE_L1_BUS1_HIT_CNT_S)) +#define CACHE_L1_BUS1_HIT_CNT_V 0xFFFFFFFF +#define CACHE_L1_BUS1_HIT_CNT_S 0 + +#define CACHE_L1_BUS1_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x1D0) +/* CACHE_L1_BUS1_MISS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The register records the number of missing when bus1 accesses L1-Cache..*/ +#define CACHE_L1_BUS1_MISS_CNT 0xFFFFFFFF +#define CACHE_L1_BUS1_MISS_CNT_M ((CACHE_L1_BUS1_MISS_CNT_V)<<(CACHE_L1_BUS1_MISS_CNT_S)) +#define CACHE_L1_BUS1_MISS_CNT_V 0xFFFFFFFF +#define CACHE_L1_BUS1_MISS_CNT_S 0 + +#define CACHE_L1_BUS1_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x1D4) +/* CACHE_L1_BUS1_CONFLICT_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The register records the number of access-conflicts when bus1 accesses L1-Cache..*/ +#define CACHE_L1_BUS1_CONFLICT_CNT 0xFFFFFFFF +#define CACHE_L1_BUS1_CONFLICT_CNT_M ((CACHE_L1_BUS1_CONFLICT_CNT_V)<<(CACHE_L1_BUS1_CONFLICT_CNT_S)) +#define CACHE_L1_BUS1_CONFLICT_CNT_V 0xFFFFFFFF +#define CACHE_L1_BUS1_CONFLICT_CNT_S 0 + +#define CACHE_L1_BUS1_ACS_NXTLVL_CNT_REG (DR_REG_CACHE_BASE + 0x1D8) +/* CACHE_L1_BUS1_NXTLVL_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The register records the number of times that L1-Cache accesses L2-Cache due to +bus1 accessing L1-Cache..*/ +#define CACHE_L1_BUS1_NXTLVL_CNT 0xFFFFFFFF +#define CACHE_L1_BUS1_NXTLVL_CNT_M ((CACHE_L1_BUS1_NXTLVL_CNT_V)<<(CACHE_L1_BUS1_NXTLVL_CNT_S)) +#define CACHE_L1_BUS1_NXTLVL_CNT_V 0xFFFFFFFF +#define CACHE_L1_BUS1_NXTLVL_CNT_S 0 + +#define CACHE_L1_CACHE_ACS_FAIL_ID_ATTR_REG (DR_REG_CACHE_BASE + 0x21C) +/* CACHE_L1_CACHE_FAIL_ATTR : RO ;bitpos:[31:16] ;default: 16'h0 ; */ +/*description: The register records the attribution of fail-access when cache accesses L1-Cache ..*/ -#define EXTMEM_DBUS0_CONFLICT_CNT 0xFFFFFFFF -#define EXTMEM_DBUS0_CONFLICT_CNT_M ((EXTMEM_DBUS0_CONFLICT_CNT_V)<<(EXTMEM_DBUS0_CONFLICT_CNT_S)) -#define EXTMEM_DBUS0_CONFLICT_CNT_V 0xFFFFFFFF -#define EXTMEM_DBUS0_CONFLICT_CNT_S 0 +#define CACHE_L1_CACHE_FAIL_ATTR 0x0000FFFF +#define CACHE_L1_CACHE_FAIL_ATTR_M ((CACHE_L1_CACHE_FAIL_ATTR_V)<<(CACHE_L1_CACHE_FAIL_ATTR_S)) +#define CACHE_L1_CACHE_FAIL_ATTR_V 0xFFFF +#define CACHE_L1_CACHE_FAIL_ATTR_S 16 +/* CACHE_L1_CACHE_FAIL_ID : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: The register records the ID of fail-access when cache accesses L1-Cache..*/ +#define CACHE_L1_CACHE_FAIL_ID 0x0000FFFF +#define CACHE_L1_CACHE_FAIL_ID_M ((CACHE_L1_CACHE_FAIL_ID_V)<<(CACHE_L1_CACHE_FAIL_ID_S)) +#define CACHE_L1_CACHE_FAIL_ID_V 0xFFFF +#define CACHE_L1_CACHE_FAIL_ID_S 0 -#define EXTMEM_DBUS0_ACS_NXTLVL_CNT_REG (DR_REG_EXTMEM_BASE + 0x1C8) -/* EXTMEM_DBUS0_NXTLVL_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The register records the number of times that L1-DCache accesses L2-Cache due to - bus0 accessing L1-DCache..*/ -#define EXTMEM_DBUS0_NXTLVL_CNT 0xFFFFFFFF -#define EXTMEM_DBUS0_NXTLVL_CNT_M ((EXTMEM_DBUS0_NXTLVL_CNT_V)<<(EXTMEM_DBUS0_NXTLVL_CNT_S)) -#define EXTMEM_DBUS0_NXTLVL_CNT_V 0xFFFFFFFF -#define EXTMEM_DBUS0_NXTLVL_CNT_S 0 +#define CACHE_L1_CACHE_ACS_FAIL_ADDR_REG (DR_REG_CACHE_BASE + 0x220) +/* CACHE_L1_CACHE_FAIL_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The register records the address of fail-access when cache accesses L1-Cache..*/ +#define CACHE_L1_CACHE_FAIL_ADDR 0xFFFFFFFF +#define CACHE_L1_CACHE_FAIL_ADDR_M ((CACHE_L1_CACHE_FAIL_ADDR_V)<<(CACHE_L1_CACHE_FAIL_ADDR_S)) +#define CACHE_L1_CACHE_FAIL_ADDR_V 0xFFFFFFFF +#define CACHE_L1_CACHE_FAIL_ADDR_S 0 -#define EXTMEM_DBUS1_ACS_HIT_CNT_REG (DR_REG_EXTMEM_BASE + 0x1CC) -/* EXTMEM_DBUS1_HIT_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The register records the number of hits when bus1 accesses L1-DCache..*/ -#define EXTMEM_DBUS1_HIT_CNT 0xFFFFFFFF -#define EXTMEM_DBUS1_HIT_CNT_M ((EXTMEM_DBUS1_HIT_CNT_V)<<(EXTMEM_DBUS1_HIT_CNT_S)) -#define EXTMEM_DBUS1_HIT_CNT_V 0xFFFFFFFF -#define EXTMEM_DBUS1_HIT_CNT_S 0 - -#define EXTMEM_DBUS1_ACS_MISS_CNT_REG (DR_REG_EXTMEM_BASE + 0x1D0) -/* EXTMEM_DBUS1_MISS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The register records the number of missing when bus1 accesses L1-DCache..*/ -#define EXTMEM_DBUS1_MISS_CNT 0xFFFFFFFF -#define EXTMEM_DBUS1_MISS_CNT_M ((EXTMEM_DBUS1_MISS_CNT_V)<<(EXTMEM_DBUS1_MISS_CNT_S)) -#define EXTMEM_DBUS1_MISS_CNT_V 0xFFFFFFFF -#define EXTMEM_DBUS1_MISS_CNT_S 0 - -#define EXTMEM_DBUS1_ACS_CONFLICT_CNT_REG (DR_REG_EXTMEM_BASE + 0x1D4) -/* EXTMEM_DBUS1_CONFLICT_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The register records the number of access-conflicts when bus1 accesses L1-DCache -..*/ -#define EXTMEM_DBUS1_CONFLICT_CNT 0xFFFFFFFF -#define EXTMEM_DBUS1_CONFLICT_CNT_M ((EXTMEM_DBUS1_CONFLICT_CNT_V)<<(EXTMEM_DBUS1_CONFLICT_CNT_S)) -#define EXTMEM_DBUS1_CONFLICT_CNT_V 0xFFFFFFFF -#define EXTMEM_DBUS1_CONFLICT_CNT_S 0 - -#define EXTMEM_DBUS1_ACS_NXTLVL_CNT_REG (DR_REG_EXTMEM_BASE + 0x1D8) -/* EXTMEM_DBUS1_NXTLVL_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The register records the number of times that L1-DCache accesses L2-Cache due to - bus1 accessing L1-DCache..*/ -#define EXTMEM_DBUS1_NXTLVL_CNT 0xFFFFFFFF -#define EXTMEM_DBUS1_NXTLVL_CNT_M ((EXTMEM_DBUS1_NXTLVL_CNT_V)<<(EXTMEM_DBUS1_NXTLVL_CNT_S)) -#define EXTMEM_DBUS1_NXTLVL_CNT_V 0xFFFFFFFF -#define EXTMEM_DBUS1_NXTLVL_CNT_S 0 - -#define EXTMEM_ICACHE0_ACS_FAIL_ID_ATTR_REG (DR_REG_EXTMEM_BASE + 0x1FC) -/* EXTMEM_ICACHE0_FAIL_ATTR : RO ;bitpos:[31:16] ;default: 16'h0 ; */ -/*description: The register records the attribution of fail-access when cache0 accesses L1-ICac -he..*/ -#define EXTMEM_ICACHE0_FAIL_ATTR 0x0000FFFF -#define EXTMEM_ICACHE0_FAIL_ATTR_M ((EXTMEM_ICACHE0_FAIL_ATTR_V)<<(EXTMEM_ICACHE0_FAIL_ATTR_S)) -#define EXTMEM_ICACHE0_FAIL_ATTR_V 0xFFFF -#define EXTMEM_ICACHE0_FAIL_ATTR_S 16 -/* EXTMEM_ICACHE0_FAIL_ID : RO ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: The register records the ID of fail-access when cache0 accesses L1-ICache..*/ -#define EXTMEM_ICACHE0_FAIL_ID 0x0000FFFF -#define EXTMEM_ICACHE0_FAIL_ID_M ((EXTMEM_ICACHE0_FAIL_ID_V)<<(EXTMEM_ICACHE0_FAIL_ID_S)) -#define EXTMEM_ICACHE0_FAIL_ID_V 0xFFFF -#define EXTMEM_ICACHE0_FAIL_ID_S 0 - -#define EXTMEM_ICACHE0_ACS_FAIL_ADDR_REG (DR_REG_EXTMEM_BASE + 0x200) -/* EXTMEM_ICACHE0_FAIL_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The register records the address of fail-access when cache0 accesses L1-ICache..*/ -#define EXTMEM_ICACHE0_FAIL_ADDR 0xFFFFFFFF -#define EXTMEM_ICACHE0_FAIL_ADDR_M ((EXTMEM_ICACHE0_FAIL_ADDR_V)<<(EXTMEM_ICACHE0_FAIL_ADDR_S)) -#define EXTMEM_ICACHE0_FAIL_ADDR_V 0xFFFFFFFF -#define EXTMEM_ICACHE0_FAIL_ADDR_S 0 - -#define EXTMEM_ICACHE1_ACS_FAIL_ID_ATTR_REG (DR_REG_EXTMEM_BASE + 0x204) -/* EXTMEM_ICACHE1_FAIL_ATTR : RO ;bitpos:[31:16] ;default: 16'h0 ; */ -/*description: The register records the attribution of fail-access when cache1 accesses L1-ICac -he..*/ -#define EXTMEM_ICACHE1_FAIL_ATTR 0x0000FFFF -#define EXTMEM_ICACHE1_FAIL_ATTR_M ((EXTMEM_ICACHE1_FAIL_ATTR_V)<<(EXTMEM_ICACHE1_FAIL_ATTR_S)) -#define EXTMEM_ICACHE1_FAIL_ATTR_V 0xFFFF -#define EXTMEM_ICACHE1_FAIL_ATTR_S 16 -/* EXTMEM_ICACHE1_FAIL_ID : RO ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: The register records the ID of fail-access when cache1 accesses L1-ICache..*/ -#define EXTMEM_ICACHE1_FAIL_ID 0x0000FFFF -#define EXTMEM_ICACHE1_FAIL_ID_M ((EXTMEM_ICACHE1_FAIL_ID_V)<<(EXTMEM_ICACHE1_FAIL_ID_S)) -#define EXTMEM_ICACHE1_FAIL_ID_V 0xFFFF -#define EXTMEM_ICACHE1_FAIL_ID_S 0 - -#define EXTMEM_ICACHE1_ACS_FAIL_ADDR_REG (DR_REG_EXTMEM_BASE + 0x208) -/* EXTMEM_ICACHE1_FAIL_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The register records the address of fail-access when cache1 accesses L1-ICache..*/ -#define EXTMEM_ICACHE1_FAIL_ADDR 0xFFFFFFFF -#define EXTMEM_ICACHE1_FAIL_ADDR_M ((EXTMEM_ICACHE1_FAIL_ADDR_V)<<(EXTMEM_ICACHE1_FAIL_ADDR_S)) -#define EXTMEM_ICACHE1_FAIL_ADDR_V 0xFFFFFFFF -#define EXTMEM_ICACHE1_FAIL_ADDR_S 0 - -#define EXTMEM_DCACHE_ACS_FAIL_ID_ATTR_REG (DR_REG_EXTMEM_BASE + 0x21C) -/* EXTMEM_DCACHE_FAIL_ATTR : RO ;bitpos:[31:16] ;default: 16'h0 ; */ -/*description: The register records the attribution of fail-access when cache accesses L1-DCach -e..*/ -#define EXTMEM_DCACHE_FAIL_ATTR 0x0000FFFF -#define EXTMEM_DCACHE_FAIL_ATTR_M ((EXTMEM_DCACHE_FAIL_ATTR_V)<<(EXTMEM_DCACHE_FAIL_ATTR_S)) -#define EXTMEM_DCACHE_FAIL_ATTR_V 0xFFFF -#define EXTMEM_DCACHE_FAIL_ATTR_S 16 -/* EXTMEM_DCACHE_FAIL_ID : RO ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: The register records the ID of fail-access when cache accesses L1-DCache..*/ -#define EXTMEM_DCACHE_FAIL_ID 0x0000FFFF -#define EXTMEM_DCACHE_FAIL_ID_M ((EXTMEM_DCACHE_FAIL_ID_V)<<(EXTMEM_DCACHE_FAIL_ID_S)) -#define EXTMEM_DCACHE_FAIL_ID_V 0xFFFF -#define EXTMEM_DCACHE_FAIL_ID_S 0 - -#define EXTMEM_DCACHE_ACS_FAIL_ADDR_REG (DR_REG_EXTMEM_BASE + 0x220) -/* EXTMEM_DCACHE_FAIL_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The register records the address of fail-access when cache accesses L1-DCache..*/ -#define EXTMEM_DCACHE_FAIL_ADDR 0xFFFFFFFF -#define EXTMEM_DCACHE_FAIL_ADDR_M ((EXTMEM_DCACHE_FAIL_ADDR_V)<<(EXTMEM_DCACHE_FAIL_ADDR_S)) -#define EXTMEM_DCACHE_FAIL_ADDR_V 0xFFFFFFFF -#define EXTMEM_DCACHE_FAIL_ADDR_S 0 - -#define EXTMEM_CACHE_SYNC_PRELOAD_INT_ENA_REG (DR_REG_EXTMEM_BASE + 0x224) -/* EXTMEM_CACHE_SYNC_ERR_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */ +#define CACHE_L1_CACHE_SYNC_PRELOAD_INT_ENA_REG (DR_REG_CACHE_BASE + 0x224) +/* CACHE_SYNC_ERR_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */ /*description: The bit is used to enable interrupt of Cache sync-operation error..*/ -#define EXTMEM_CACHE_SYNC_ERR_INT_ENA (BIT(13)) -#define EXTMEM_CACHE_SYNC_ERR_INT_ENA_M (BIT(13)) -#define EXTMEM_CACHE_SYNC_ERR_INT_ENA_V 0x1 -#define EXTMEM_CACHE_SYNC_ERR_INT_ENA_S 13 -/* EXTMEM_DCACHE_PLD_ERR_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: The bit is used to enable interrupt of L1-DCache preload-operation error..*/ -#define EXTMEM_DCACHE_PLD_ERR_INT_ENA (BIT(11)) -#define EXTMEM_DCACHE_PLD_ERR_INT_ENA_M (BIT(11)) -#define EXTMEM_DCACHE_PLD_ERR_INT_ENA_V 0x1 -#define EXTMEM_DCACHE_PLD_ERR_INT_ENA_S 11 -/* EXTMEM_CACHE_SYNC_DONE_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ +#define CACHE_SYNC_ERR_INT_ENA (BIT(13)) +#define CACHE_SYNC_ERR_INT_ENA_M (BIT(13)) +#define CACHE_SYNC_ERR_INT_ENA_V 0x1 +#define CACHE_SYNC_ERR_INT_ENA_S 13 +/* CACHE_L1_CACHE_PLD_ERR_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: The bit is used to enable interrupt of L1-Cache preload-operation error..*/ +#define CACHE_L1_CACHE_PLD_ERR_INT_ENA (BIT(11)) +#define CACHE_L1_CACHE_PLD_ERR_INT_ENA_M (BIT(11)) +#define CACHE_L1_CACHE_PLD_ERR_INT_ENA_V 0x1 +#define CACHE_L1_CACHE_PLD_ERR_INT_ENA_S 11 +/* CACHE_SYNC_DONE_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ /*description: The bit is used to enable interrupt of Cache sync-operation done..*/ -#define EXTMEM_CACHE_SYNC_DONE_INT_ENA (BIT(6)) -#define EXTMEM_CACHE_SYNC_DONE_INT_ENA_M (BIT(6)) -#define EXTMEM_CACHE_SYNC_DONE_INT_ENA_V 0x1 -#define EXTMEM_CACHE_SYNC_DONE_INT_ENA_S 6 -/* EXTMEM_DCACHE_PLD_DONE_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The bit is used to enable interrupt of L1-DCache preload-operation. If preload o -peration is done, interrupt occurs..*/ -#define EXTMEM_DCACHE_PLD_DONE_INT_ENA (BIT(4)) -#define EXTMEM_DCACHE_PLD_DONE_INT_ENA_M (BIT(4)) -#define EXTMEM_DCACHE_PLD_DONE_INT_ENA_V 0x1 -#define EXTMEM_DCACHE_PLD_DONE_INT_ENA_S 4 +#define CACHE_SYNC_DONE_INT_ENA (BIT(6)) +#define CACHE_SYNC_DONE_INT_ENA_M (BIT(6)) +#define CACHE_SYNC_DONE_INT_ENA_V 0x1 +#define CACHE_SYNC_DONE_INT_ENA_S 6 +/* CACHE_L1_CACHE_PLD_DONE_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The bit is used to enable interrupt of L1-Cache preload-operation. If preload op +eration is done, interrupt occurs..*/ +#define CACHE_L1_CACHE_PLD_DONE_INT_ENA (BIT(4)) +#define CACHE_L1_CACHE_PLD_DONE_INT_ENA_M (BIT(4)) +#define CACHE_L1_CACHE_PLD_DONE_INT_ENA_V 0x1 +#define CACHE_L1_CACHE_PLD_DONE_INT_ENA_S 4 -#define EXTMEM_CACHE_SYNC_PRELOAD_INT_CLR_REG (DR_REG_EXTMEM_BASE + 0x228) -/* EXTMEM_CACHE_SYNC_ERR_INT_CLR : WT ;bitpos:[13] ;default: 1'b0 ; */ +#define CACHE_L1_CACHE_SYNC_PRELOAD_INT_CLR_REG (DR_REG_CACHE_BASE + 0x228) +/* CACHE_SYNC_ERR_INT_CLR : WT ;bitpos:[13] ;default: 1'b0 ; */ /*description: The bit is used to clear interrupt of Cache sync-operation error..*/ -#define EXTMEM_CACHE_SYNC_ERR_INT_CLR (BIT(13)) -#define EXTMEM_CACHE_SYNC_ERR_INT_CLR_M (BIT(13)) -#define EXTMEM_CACHE_SYNC_ERR_INT_CLR_V 0x1 -#define EXTMEM_CACHE_SYNC_ERR_INT_CLR_S 13 -/* EXTMEM_DCACHE_PLD_ERR_INT_CLR : WT ;bitpos:[11] ;default: 1'b0 ; */ -/*description: The bit is used to clear interrupt of L1-DCache preload-operation error..*/ -#define EXTMEM_DCACHE_PLD_ERR_INT_CLR (BIT(11)) -#define EXTMEM_DCACHE_PLD_ERR_INT_CLR_M (BIT(11)) -#define EXTMEM_DCACHE_PLD_ERR_INT_CLR_V 0x1 -#define EXTMEM_DCACHE_PLD_ERR_INT_CLR_S 11 -/* EXTMEM_CACHE_SYNC_DONE_INT_CLR : WT ;bitpos:[6] ;default: 1'b0 ; */ +#define CACHE_SYNC_ERR_INT_CLR (BIT(13)) +#define CACHE_SYNC_ERR_INT_CLR_M (BIT(13)) +#define CACHE_SYNC_ERR_INT_CLR_V 0x1 +#define CACHE_SYNC_ERR_INT_CLR_S 13 +/* CACHE_L1_CACHE_PLD_ERR_INT_CLR : WT ;bitpos:[11] ;default: 1'b0 ; */ +/*description: The bit is used to clear interrupt of L1-Cache preload-operation error..*/ +#define CACHE_L1_CACHE_PLD_ERR_INT_CLR (BIT(11)) +#define CACHE_L1_CACHE_PLD_ERR_INT_CLR_M (BIT(11)) +#define CACHE_L1_CACHE_PLD_ERR_INT_CLR_V 0x1 +#define CACHE_L1_CACHE_PLD_ERR_INT_CLR_S 11 +/* CACHE_SYNC_DONE_INT_CLR : WT ;bitpos:[6] ;default: 1'b0 ; */ /*description: The bit is used to clear interrupt that occurs only when Cache sync-operation is done..*/ -#define EXTMEM_CACHE_SYNC_DONE_INT_CLR (BIT(6)) -#define EXTMEM_CACHE_SYNC_DONE_INT_CLR_M (BIT(6)) -#define EXTMEM_CACHE_SYNC_DONE_INT_CLR_V 0x1 -#define EXTMEM_CACHE_SYNC_DONE_INT_CLR_S 6 -/* EXTMEM_DCACHE_PLD_DONE_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The bit is used to clear interrupt that occurs only when L1-DCache preload-opera -tion is done..*/ -#define EXTMEM_DCACHE_PLD_DONE_INT_CLR (BIT(4)) -#define EXTMEM_DCACHE_PLD_DONE_INT_CLR_M (BIT(4)) -#define EXTMEM_DCACHE_PLD_DONE_INT_CLR_V 0x1 -#define EXTMEM_DCACHE_PLD_DONE_INT_CLR_S 4 +#define CACHE_SYNC_DONE_INT_CLR (BIT(6)) +#define CACHE_SYNC_DONE_INT_CLR_M (BIT(6)) +#define CACHE_SYNC_DONE_INT_CLR_V 0x1 +#define CACHE_SYNC_DONE_INT_CLR_S 6 +/* CACHE_L1_CACHE_PLD_DONE_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The bit is used to clear interrupt that occurs only when L1-Cache preload-operat +ion is done..*/ +#define CACHE_L1_CACHE_PLD_DONE_INT_CLR (BIT(4)) +#define CACHE_L1_CACHE_PLD_DONE_INT_CLR_M (BIT(4)) +#define CACHE_L1_CACHE_PLD_DONE_INT_CLR_V 0x1 +#define CACHE_L1_CACHE_PLD_DONE_INT_CLR_S 4 -#define EXTMEM_CACHE_SYNC_PRELOAD_INT_RAW_REG (DR_REG_EXTMEM_BASE + 0x22C) -/* EXTMEM_CACHE_SYNC_ERR_INT_RAW : R/WTC/SS ;bitpos:[13] ;default: 1'b0 ; */ +#define CACHE_L1_CACHE_SYNC_PRELOAD_INT_RAW_REG (DR_REG_CACHE_BASE + 0x22C) +/* CACHE_SYNC_ERR_INT_RAW : R/WTC/SS ;bitpos:[13] ;default: 1'b0 ; */ /*description: The raw bit of the interrupt that occurs only when Cache sync-operation error oc curs..*/ -#define EXTMEM_CACHE_SYNC_ERR_INT_RAW (BIT(13)) -#define EXTMEM_CACHE_SYNC_ERR_INT_RAW_M (BIT(13)) -#define EXTMEM_CACHE_SYNC_ERR_INT_RAW_V 0x1 -#define EXTMEM_CACHE_SYNC_ERR_INT_RAW_S 13 -/* EXTMEM_DCACHE_PLD_ERR_INT_RAW : R/WTC/SS ;bitpos:[11] ;default: 1'b0 ; */ -/*description: The raw bit of the interrupt that occurs only when L1-DCache preload-operation e -rror occurs..*/ -#define EXTMEM_DCACHE_PLD_ERR_INT_RAW (BIT(11)) -#define EXTMEM_DCACHE_PLD_ERR_INT_RAW_M (BIT(11)) -#define EXTMEM_DCACHE_PLD_ERR_INT_RAW_V 0x1 -#define EXTMEM_DCACHE_PLD_ERR_INT_RAW_S 11 -/* EXTMEM_CACHE_SYNC_DONE_INT_RAW : R/WTC/SS ;bitpos:[6] ;default: 1'b0 ; */ +#define CACHE_SYNC_ERR_INT_RAW (BIT(13)) +#define CACHE_SYNC_ERR_INT_RAW_M (BIT(13)) +#define CACHE_SYNC_ERR_INT_RAW_V 0x1 +#define CACHE_SYNC_ERR_INT_RAW_S 13 +/* CACHE_L1_CACHE_PLD_ERR_INT_RAW : R/WTC/SS ;bitpos:[11] ;default: 1'b0 ; */ +/*description: The raw bit of the interrupt that occurs only when L1-Cache preload-operation er +ror occurs..*/ +#define CACHE_L1_CACHE_PLD_ERR_INT_RAW (BIT(11)) +#define CACHE_L1_CACHE_PLD_ERR_INT_RAW_M (BIT(11)) +#define CACHE_L1_CACHE_PLD_ERR_INT_RAW_V 0x1 +#define CACHE_L1_CACHE_PLD_ERR_INT_RAW_S 11 +/* CACHE_SYNC_DONE_INT_RAW : R/WTC/SS ;bitpos:[6] ;default: 1'b0 ; */ /*description: The raw bit of the interrupt that occurs only when Cache sync-operation is done..*/ -#define EXTMEM_CACHE_SYNC_DONE_INT_RAW (BIT(6)) -#define EXTMEM_CACHE_SYNC_DONE_INT_RAW_M (BIT(6)) -#define EXTMEM_CACHE_SYNC_DONE_INT_RAW_V 0x1 -#define EXTMEM_CACHE_SYNC_DONE_INT_RAW_S 6 -/* EXTMEM_DCACHE_PLD_DONE_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The raw bit of the interrupt that occurs only when L1-DCache preload-operation i -s done..*/ -#define EXTMEM_DCACHE_PLD_DONE_INT_RAW (BIT(4)) -#define EXTMEM_DCACHE_PLD_DONE_INT_RAW_M (BIT(4)) -#define EXTMEM_DCACHE_PLD_DONE_INT_RAW_V 0x1 -#define EXTMEM_DCACHE_PLD_DONE_INT_RAW_S 4 +#define CACHE_SYNC_DONE_INT_RAW (BIT(6)) +#define CACHE_SYNC_DONE_INT_RAW_M (BIT(6)) +#define CACHE_SYNC_DONE_INT_RAW_V 0x1 +#define CACHE_SYNC_DONE_INT_RAW_S 6 +/* CACHE_L1_CACHE_PLD_DONE_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The raw bit of the interrupt that occurs only when L1-Cache preload-operation is + done..*/ +#define CACHE_L1_CACHE_PLD_DONE_INT_RAW (BIT(4)) +#define CACHE_L1_CACHE_PLD_DONE_INT_RAW_M (BIT(4)) +#define CACHE_L1_CACHE_PLD_DONE_INT_RAW_V 0x1 +#define CACHE_L1_CACHE_PLD_DONE_INT_RAW_S 4 -#define EXTMEM_CACHE_SYNC_PRELOAD_INT_ST_REG (DR_REG_EXTMEM_BASE + 0x230) -/* EXTMEM_CACHE_SYNC_ERR_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */ +#define CACHE_L1_CACHE_SYNC_PRELOAD_INT_ST_REG (DR_REG_CACHE_BASE + 0x230) +/* CACHE_SYNC_ERR_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */ /*description: The bit indicates the status of the interrupt of Cache sync-operation error..*/ -#define EXTMEM_CACHE_SYNC_ERR_INT_ST (BIT(13)) -#define EXTMEM_CACHE_SYNC_ERR_INT_ST_M (BIT(13)) -#define EXTMEM_CACHE_SYNC_ERR_INT_ST_V 0x1 -#define EXTMEM_CACHE_SYNC_ERR_INT_ST_S 13 -/* EXTMEM_DCACHE_PLD_ERR_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: The bit indicates the status of the interrupt of L1-DCache preload-operation err -or..*/ -#define EXTMEM_DCACHE_PLD_ERR_INT_ST (BIT(11)) -#define EXTMEM_DCACHE_PLD_ERR_INT_ST_M (BIT(11)) -#define EXTMEM_DCACHE_PLD_ERR_INT_ST_V 0x1 -#define EXTMEM_DCACHE_PLD_ERR_INT_ST_S 11 -/* EXTMEM_CACHE_SYNC_DONE_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ +#define CACHE_SYNC_ERR_INT_ST (BIT(13)) +#define CACHE_SYNC_ERR_INT_ST_M (BIT(13)) +#define CACHE_SYNC_ERR_INT_ST_V 0x1 +#define CACHE_SYNC_ERR_INT_ST_S 13 +/* CACHE_L1_CACHE_PLD_ERR_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: The bit indicates the status of the interrupt of L1-Cache preload-operation erro +r..*/ +#define CACHE_L1_CACHE_PLD_ERR_INT_ST (BIT(11)) +#define CACHE_L1_CACHE_PLD_ERR_INT_ST_M (BIT(11)) +#define CACHE_L1_CACHE_PLD_ERR_INT_ST_V 0x1 +#define CACHE_L1_CACHE_PLD_ERR_INT_ST_S 11 +/* CACHE_SYNC_DONE_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ /*description: The bit indicates the status of the interrupt that occurs only when Cache sync-o peration is done..*/ -#define EXTMEM_CACHE_SYNC_DONE_INT_ST (BIT(6)) -#define EXTMEM_CACHE_SYNC_DONE_INT_ST_M (BIT(6)) -#define EXTMEM_CACHE_SYNC_DONE_INT_ST_V 0x1 -#define EXTMEM_CACHE_SYNC_DONE_INT_ST_S 6 -/* EXTMEM_DCACHE_PLD_DONE_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The bit indicates the status of the interrupt that occurs only when L1-DCache pr -eload-operation is done..*/ -#define EXTMEM_DCACHE_PLD_DONE_INT_ST (BIT(4)) -#define EXTMEM_DCACHE_PLD_DONE_INT_ST_M (BIT(4)) -#define EXTMEM_DCACHE_PLD_DONE_INT_ST_V 0x1 -#define EXTMEM_DCACHE_PLD_DONE_INT_ST_S 4 +#define CACHE_SYNC_DONE_INT_ST (BIT(6)) +#define CACHE_SYNC_DONE_INT_ST_M (BIT(6)) +#define CACHE_SYNC_DONE_INT_ST_V 0x1 +#define CACHE_SYNC_DONE_INT_ST_S 6 +/* CACHE_L1_CACHE_PLD_DONE_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The bit indicates the status of the interrupt that occurs only when L1-Cache pre +load-operation is done..*/ +#define CACHE_L1_CACHE_PLD_DONE_INT_ST (BIT(4)) +#define CACHE_L1_CACHE_PLD_DONE_INT_ST_M (BIT(4)) +#define CACHE_L1_CACHE_PLD_DONE_INT_ST_V 0x1 +#define CACHE_L1_CACHE_PLD_DONE_INT_ST_S 4 -#define EXTMEM_CACHE_SYNC_PRELOAD_EXCEPTION_REG (DR_REG_EXTMEM_BASE + 0x234) -/* EXTMEM_CACHE_SYNC_ERR_CODE : RO ;bitpos:[13:12] ;default: 2'h0 ; */ +#define CACHE_L1_CACHE_SYNC_PRELOAD_EXCEPTION_REG (DR_REG_CACHE_BASE + 0x234) +/* CACHE_SYNC_ERR_CODE : RO ;bitpos:[13:12] ;default: 2'h0 ; */ /*description: The values 0-2 are available which means sync map, command conflict and size are error in Cache System..*/ -#define EXTMEM_CACHE_SYNC_ERR_CODE 0x00000003 -#define EXTMEM_CACHE_SYNC_ERR_CODE_M ((EXTMEM_CACHE_SYNC_ERR_CODE_V)<<(EXTMEM_CACHE_SYNC_ERR_CODE_S)) -#define EXTMEM_CACHE_SYNC_ERR_CODE_V 0x3 -#define EXTMEM_CACHE_SYNC_ERR_CODE_S 12 -/* EXTMEM_DCACHE_PLD_ERR_CODE : RO ;bitpos:[9:8] ;default: 2'h0 ; */ -/*description: The value 2 is Only available which means preload size is error in L1-DCache..*/ -#define EXTMEM_DCACHE_PLD_ERR_CODE 0x00000003 -#define EXTMEM_DCACHE_PLD_ERR_CODE_M ((EXTMEM_DCACHE_PLD_ERR_CODE_V)<<(EXTMEM_DCACHE_PLD_ERR_CODE_S)) -#define EXTMEM_DCACHE_PLD_ERR_CODE_V 0x3 -#define EXTMEM_DCACHE_PLD_ERR_CODE_S 8 +#define CACHE_SYNC_ERR_CODE 0x00000003 +#define CACHE_SYNC_ERR_CODE_M ((CACHE_SYNC_ERR_CODE_V)<<(CACHE_SYNC_ERR_CODE_S)) +#define CACHE_SYNC_ERR_CODE_V 0x3 +#define CACHE_SYNC_ERR_CODE_S 12 +/* CACHE_L1_CACHE_PLD_ERR_CODE : RO ;bitpos:[9:8] ;default: 2'h0 ; */ +/*description: The value 2 is Only available which means preload size is error in L1-Cache..*/ +#define CACHE_L1_CACHE_PLD_ERR_CODE 0x00000003 +#define CACHE_L1_CACHE_PLD_ERR_CODE_M ((CACHE_L1_CACHE_PLD_ERR_CODE_V)<<(CACHE_L1_CACHE_PLD_ERR_CODE_S)) +#define CACHE_L1_CACHE_PLD_ERR_CODE_V 0x3 +#define CACHE_L1_CACHE_PLD_ERR_CODE_S 8 -#define EXTMEM_CACHE_SYNC_RST_CTRL_REG (DR_REG_EXTMEM_BASE + 0x238) -/* EXTMEM_DCACHE_SYNC_RST : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: set this bit to reset sync-logic inside L1-DCache. Recommend that this should on -ly be used to initialize sync-logic when some fatal error of sync-logic occurs..*/ -#define EXTMEM_DCACHE_SYNC_RST (BIT(4)) -#define EXTMEM_DCACHE_SYNC_RST_M (BIT(4)) -#define EXTMEM_DCACHE_SYNC_RST_V 0x1 -#define EXTMEM_DCACHE_SYNC_RST_S 4 +#define CACHE_L1_CACHE_SYNC_RST_CTRL_REG (DR_REG_CACHE_BASE + 0x238) +/* CACHE_L1_CACHE_SYNC_RST : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: set this bit to reset sync-logic inside L1-Cache. Recommend that this should onl +y be used to initialize sync-logic when some fatal error of sync-logic occurs..*/ +#define CACHE_L1_CACHE_SYNC_RST (BIT(4)) +#define CACHE_L1_CACHE_SYNC_RST_M (BIT(4)) +#define CACHE_L1_CACHE_SYNC_RST_V 0x1 +#define CACHE_L1_CACHE_SYNC_RST_S 4 -#define EXTMEM_CACHE_PRELOAD_RST_CTRL_REG (DR_REG_EXTMEM_BASE + 0x23C) -/* EXTMEM_DCACHE_PLD_RST : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: set this bit to reset preload-logic inside L1-DCache. Recommend that this should - only be used to initialize preload-logic when some fatal error of preload-logic - occurs..*/ -#define EXTMEM_DCACHE_PLD_RST (BIT(4)) -#define EXTMEM_DCACHE_PLD_RST_M (BIT(4)) -#define EXTMEM_DCACHE_PLD_RST_V 0x1 -#define EXTMEM_DCACHE_PLD_RST_S 4 +#define CACHE_L1_CACHE_PRELOAD_RST_CTRL_REG (DR_REG_CACHE_BASE + 0x23C) +/* CACHE_L1_CACHE_PLD_RST : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: set this bit to reset preload-logic inside L1-Cache. Recommend that this should +only be used to initialize preload-logic when some fatal error of preload-logic +occurs..*/ +#define CACHE_L1_CACHE_PLD_RST (BIT(4)) +#define CACHE_L1_CACHE_PLD_RST_M (BIT(4)) +#define CACHE_L1_CACHE_PLD_RST_V 0x1 +#define CACHE_L1_CACHE_PLD_RST_S 4 -#define EXTMEM_CACHE_AUTOLOAD_BUF_CLR_CTRL_REG (DR_REG_EXTMEM_BASE + 0x240) -/* EXTMEM_DCACHE_ALD_BUF_CLR : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: set this bit to clear autoload-buffer inside L1-DCache. If this bit is active, a -utoload will not work in L1-DCache. This bit should not be active when autoload -works in L1-DCache..*/ -#define EXTMEM_DCACHE_ALD_BUF_CLR (BIT(4)) -#define EXTMEM_DCACHE_ALD_BUF_CLR_M (BIT(4)) -#define EXTMEM_DCACHE_ALD_BUF_CLR_V 0x1 -#define EXTMEM_DCACHE_ALD_BUF_CLR_S 4 +#define CACHE_L1_CACHE_AUTOLOAD_BUF_CLR_CTRL_REG (DR_REG_CACHE_BASE + 0x240) +/* CACHE_L1_CACHE_ALD_BUF_CLR : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: set this bit to clear autoload-buffer inside L1-Cache. If this bit is active, au +toload will not work in L1-Cache. This bit should not be active when autoload wo +rks in L1-Cache..*/ +#define CACHE_L1_CACHE_ALD_BUF_CLR (BIT(4)) +#define CACHE_L1_CACHE_ALD_BUF_CLR_M (BIT(4)) +#define CACHE_L1_CACHE_ALD_BUF_CLR_V 0x1 +#define CACHE_L1_CACHE_ALD_BUF_CLR_S 4 -#define EXTMEM_UNALLOCATE_BUFFER_CLEAR_REG (DR_REG_EXTMEM_BASE + 0x244) -/* EXTMEM_DCACHE_UNALLOC_CLR : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The bit is used to clear the unallocate request buffer of l1 dcache where the un -allocate request is responsed but not completed..*/ -#define EXTMEM_DCACHE_UNALLOC_CLR (BIT(4)) -#define EXTMEM_DCACHE_UNALLOC_CLR_M (BIT(4)) -#define EXTMEM_DCACHE_UNALLOC_CLR_V 0x1 -#define EXTMEM_DCACHE_UNALLOC_CLR_S 4 +#define CACHE_L1_UNALLOCATE_BUFFER_CLEAR_REG (DR_REG_CACHE_BASE + 0x244) +/* CACHE_L1_CACHE_UNALLOC_CLR : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The bit is used to clear the unallocate request buffer of l1 cache where the una +llocate request is responsed but not completed..*/ +#define CACHE_L1_CACHE_UNALLOC_CLR (BIT(4)) +#define CACHE_L1_CACHE_UNALLOC_CLR_M (BIT(4)) +#define CACHE_L1_CACHE_UNALLOC_CLR_V 0x1 +#define CACHE_L1_CACHE_UNALLOC_CLR_S 4 -#define EXTMEM_CACHE_OBJECT_CTRL_REG (DR_REG_EXTMEM_BASE + 0x248) -/* EXTMEM_DCACHE_MEM_OBJECT : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: Set this bit to set L1-DCache data memory as object. This bit should be onehot w -ith the others fields inside this register..*/ -#define EXTMEM_DCACHE_MEM_OBJECT (BIT(10)) -#define EXTMEM_DCACHE_MEM_OBJECT_M (BIT(10)) -#define EXTMEM_DCACHE_MEM_OBJECT_V 0x1 -#define EXTMEM_DCACHE_MEM_OBJECT_S 10 -/* EXTMEM_DCACHE_TAG_OBJECT : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: Set this bit to set L1-DCache tag memory as object. This bit should be onehot wi +#define CACHE_L1_CACHE_OBJECT_CTRL_REG (DR_REG_CACHE_BASE + 0x248) +/* CACHE_L1_CACHE_MEM_OBJECT : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: Set this bit to set L1-Cache data memory as object. This bit should be onehot wi th the others fields inside this register..*/ -#define EXTMEM_DCACHE_TAG_OBJECT (BIT(4)) -#define EXTMEM_DCACHE_TAG_OBJECT_M (BIT(4)) -#define EXTMEM_DCACHE_TAG_OBJECT_V 0x1 -#define EXTMEM_DCACHE_TAG_OBJECT_S 4 +#define CACHE_L1_CACHE_MEM_OBJECT (BIT(10)) +#define CACHE_L1_CACHE_MEM_OBJECT_M (BIT(10)) +#define CACHE_L1_CACHE_MEM_OBJECT_V 0x1 +#define CACHE_L1_CACHE_MEM_OBJECT_S 10 +/* CACHE_L1_CACHE_TAG_OBJECT : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit to set L1-Cache tag memory as object. This bit should be onehot wit +h the others fields inside this register..*/ +#define CACHE_L1_CACHE_TAG_OBJECT (BIT(4)) +#define CACHE_L1_CACHE_TAG_OBJECT_M (BIT(4)) +#define CACHE_L1_CACHE_TAG_OBJECT_V 0x1 +#define CACHE_L1_CACHE_TAG_OBJECT_S 4 -#define EXTMEM_CACHE_WAY_OBJECT_REG (DR_REG_EXTMEM_BASE + 0x24C) -/* EXTMEM_CACHE_WAY_OBJECT : R/W ;bitpos:[2:0] ;default: 3'h0 ; */ +#define CACHE_L1_CACHE_WAY_OBJECT_REG (DR_REG_CACHE_BASE + 0x24C) +/* CACHE_L1_CACHE_WAY_OBJECT : R/W ;bitpos:[2:0] ;default: 3'h0 ; */ /*description: Set this bits to select which way of the tag-object will be accessed. 0: way0, 1 : way1, 2: way2, 3: way3, ?, 7: way7..*/ -#define EXTMEM_CACHE_WAY_OBJECT 0x00000007 -#define EXTMEM_CACHE_WAY_OBJECT_M ((EXTMEM_CACHE_WAY_OBJECT_V)<<(EXTMEM_CACHE_WAY_OBJECT_S)) -#define EXTMEM_CACHE_WAY_OBJECT_V 0x7 -#define EXTMEM_CACHE_WAY_OBJECT_S 0 +#define CACHE_L1_CACHE_WAY_OBJECT 0x00000007 +#define CACHE_L1_CACHE_WAY_OBJECT_M ((CACHE_L1_CACHE_WAY_OBJECT_V)<<(CACHE_L1_CACHE_WAY_OBJECT_S)) +#define CACHE_L1_CACHE_WAY_OBJECT_V 0x7 +#define CACHE_L1_CACHE_WAY_OBJECT_S 0 -#define EXTMEM_CACHE_VADDR_REG (DR_REG_EXTMEM_BASE + 0x250) -/* EXTMEM_CACHE_VADDR : R/W ;bitpos:[31:0] ;default: 32'h40000000 ; */ +#define CACHE_L1_CACHE_VADDR_REG (DR_REG_CACHE_BASE + 0x250) +/* CACHE_L1_CACHE_VADDR : R/W ;bitpos:[31:0] ;default: 32'h40000000 ; */ /*description: Those bits stores the virtual address which will decide where inside the specifi ed tag memory object will be accessed..*/ -#define EXTMEM_CACHE_VADDR 0xFFFFFFFF -#define EXTMEM_CACHE_VADDR_M ((EXTMEM_CACHE_VADDR_V)<<(EXTMEM_CACHE_VADDR_S)) -#define EXTMEM_CACHE_VADDR_V 0xFFFFFFFF -#define EXTMEM_CACHE_VADDR_S 0 +#define CACHE_L1_CACHE_VADDR 0xFFFFFFFF +#define CACHE_L1_CACHE_VADDR_M ((CACHE_L1_CACHE_VADDR_V)<<(CACHE_L1_CACHE_VADDR_S)) +#define CACHE_L1_CACHE_VADDR_V 0xFFFFFFFF +#define CACHE_L1_CACHE_VADDR_S 0 -#define EXTMEM_CACHE_DEBUG_BUS_REG (DR_REG_EXTMEM_BASE + 0x254) -/* EXTMEM_CACHE_DEBUG_BUS : R/W ;bitpos:[31:0] ;default: 32'h254 ; */ +#define CACHE_L1_CACHE_DEBUG_BUS_REG (DR_REG_CACHE_BASE + 0x254) +/* CACHE_L1_CACHE_DEBUG_BUS : R/W ;bitpos:[31:0] ;default: 32'h254 ; */ /*description: This is a constant place where we can write data to or read data from the tag/da ta memory on the specified cache..*/ -#define EXTMEM_CACHE_DEBUG_BUS 0xFFFFFFFF -#define EXTMEM_CACHE_DEBUG_BUS_M ((EXTMEM_CACHE_DEBUG_BUS_V)<<(EXTMEM_CACHE_DEBUG_BUS_S)) -#define EXTMEM_CACHE_DEBUG_BUS_V 0xFFFFFFFF -#define EXTMEM_CACHE_DEBUG_BUS_S 0 +#define CACHE_L1_CACHE_DEBUG_BUS 0xFFFFFFFF +#define CACHE_L1_CACHE_DEBUG_BUS_M ((CACHE_L1_CACHE_DEBUG_BUS_V)<<(CACHE_L1_CACHE_DEBUG_BUS_S)) +#define CACHE_L1_CACHE_DEBUG_BUS_V 0xFFFFFFFF +#define CACHE_L1_CACHE_DEBUG_BUS_S 0 -#define EXTMEM_DATE_REG (DR_REG_EXTMEM_BASE + 0x3FC) -/* EXTMEM_DATE : R/W ;bitpos:[27:0] ;default: 28'h2202080 ; */ +#define CACHE_CLOCK_GATE_REG (DR_REG_CACHE_BASE + 0x3AC) +/* CACHE_CLK_EN : R/W ;bitpos:[0] ;default: 1'h1 ; */ +/*description: The bit is used to enable clock gate when access all registers in this module..*/ +#define CACHE_CLK_EN (BIT(0)) +#define CACHE_CLK_EN_M (BIT(0)) +#define CACHE_CLK_EN_V 0x1 +#define CACHE_CLK_EN_S 0 + +#define CACHE_REDUNDANCY_SIG0_REG (DR_REG_CACHE_BASE + 0x3B0) +/* CACHE_REDCY_SIG0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Those bits are prepared for ECO..*/ +#define CACHE_REDCY_SIG0 0xFFFFFFFF +#define CACHE_REDCY_SIG0_M ((CACHE_REDCY_SIG0_V)<<(CACHE_REDCY_SIG0_S)) +#define CACHE_REDCY_SIG0_V 0xFFFFFFFF +#define CACHE_REDCY_SIG0_S 0 + +#define CACHE_REDUNDANCY_SIG1_REG (DR_REG_CACHE_BASE + 0x3B4) +/* CACHE_REDCY_SIG1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Those bits are prepared for ECO..*/ +#define CACHE_REDCY_SIG1 0xFFFFFFFF +#define CACHE_REDCY_SIG1_M ((CACHE_REDCY_SIG1_V)<<(CACHE_REDCY_SIG1_S)) +#define CACHE_REDCY_SIG1_V 0xFFFFFFFF +#define CACHE_REDCY_SIG1_S 0 + +#define CACHE_REDUNDANCY_SIG2_REG (DR_REG_CACHE_BASE + 0x3B8) +/* CACHE_REDCY_SIG2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Those bits are prepared for ECO..*/ +#define CACHE_REDCY_SIG2 0xFFFFFFFF +#define CACHE_REDCY_SIG2_M ((CACHE_REDCY_SIG2_V)<<(CACHE_REDCY_SIG2_S)) +#define CACHE_REDCY_SIG2_V 0xFFFFFFFF +#define CACHE_REDCY_SIG2_S 0 + +#define CACHE_REDUNDANCY_SIG3_REG (DR_REG_CACHE_BASE + 0x3BC) +/* CACHE_REDCY_SIG3 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Those bits are prepared for ECO..*/ +#define CACHE_REDCY_SIG3 0xFFFFFFFF +#define CACHE_REDCY_SIG3_M ((CACHE_REDCY_SIG3_V)<<(CACHE_REDCY_SIG3_S)) +#define CACHE_REDCY_SIG3_V 0xFFFFFFFF +#define CACHE_REDCY_SIG3_S 0 + +#define CACHE_REDUNDANCY_SIG4_REG (DR_REG_CACHE_BASE + 0x3C0) +/* CACHE_REDCY_SIG4 : RO ;bitpos:[3:0] ;default: 4'h0 ; */ +/*description: Those bits are prepared for ECO..*/ +#define CACHE_REDCY_SIG4 0x0000000F +#define CACHE_REDCY_SIG4_M ((CACHE_REDCY_SIG4_V)<<(CACHE_REDCY_SIG4_S)) +#define CACHE_REDCY_SIG4_V 0xF +#define CACHE_REDCY_SIG4_S 0 + +#define CACHE_DATE_REG (DR_REG_CACHE_BASE + 0x3FC) +/* CACHE_DATE : R/W ;bitpos:[27:0] ;default: 28'h2207250 ; */ /*description: version control register. Note that this default value stored is the latest date when the hardware logic was updated..*/ -#define EXTMEM_DATE 0x0FFFFFFF -#define EXTMEM_DATE_M ((EXTMEM_DATE_V)<<(EXTMEM_DATE_S)) -#define EXTMEM_DATE_V 0xFFFFFFF -#define EXTMEM_DATE_S 0 +#define CACHE_DATE 0x0FFFFFFF +#define CACHE_DATE_M ((CACHE_DATE_V)<<(CACHE_DATE_S)) +#define CACHE_DATE_V 0xFFFFFFF +#define CACHE_DATE_S 0 #ifdef __cplusplus } #endif + + + +#endif /*_SOC_CACHE_REG_H_ */ diff --git a/components/soc/esp32h2/include/soc/reg_base.h b/components/soc/esp32h2/include/soc/reg_base.h index 96d24c157b..550c3b5094 100644 --- a/components/soc/esp32h2/include/soc/reg_base.h +++ b/components/soc/esp32h2/include/soc/reg_base.h @@ -65,6 +65,6 @@ #define DR_REG_TRACE_BASE 0x600C0000 #define DR_REG_ASSIST_DEBUG_BASE 0x600C2000 #define DR_REG_INTPRI_BASE 0x600C5000 -#define DR_REG_EXTMEM_BASE 0x600C8000 +#define DR_REG_CACHE_BASE 0x600C8000 #define PWDET_CONF_REG 0x600A8010 diff --git a/components/spi_flash/cache_utils.c b/components/spi_flash/cache_utils.c index 9f575a332a..6fc7e0fcc4 100644 --- a/components/spi_flash/cache_utils.c +++ b/components/spi_flash/cache_utils.c @@ -75,8 +75,12 @@ static __attribute__((unused)) const char *TAG = "cache"; #define DPORT_CACHE_GET_VAL(cpuid) (cpuid == 0) ? DPORT_CACHE_VAL(PRO) : DPORT_CACHE_VAL(APP) #define DPORT_CACHE_GET_MASK(cpuid) (cpuid == 0) ? DPORT_CACHE_MASK(PRO) : DPORT_CACHE_MASK(APP) -static void spi_flash_disable_cache(uint32_t cpuid, uint32_t *saved_state); -static void spi_flash_restore_cache(uint32_t cpuid, uint32_t saved_state); +/** + * These two shouldn't be declared as static otherwise if `CONFIG_SPI_FLASH_ROM_IMPL` is enabled, + * they won't get replaced by the rom version + */ +void spi_flash_disable_cache(uint32_t cpuid, uint32_t *saved_state); +void spi_flash_restore_cache(uint32_t cpuid, uint32_t saved_state); static uint32_t s_flash_op_cache_state[2]; @@ -357,7 +361,7 @@ void IRAM_ATTR spi_flash_enable_interrupts_caches_no_os(void) * function in ROM. They are used to work around a bug where Cache_Read_Disable requires a call to * Cache_Flush before Cache_Read_Enable, even if cached data was not modified. */ -static void IRAM_ATTR spi_flash_disable_cache(uint32_t cpuid, uint32_t *saved_state) +void IRAM_ATTR spi_flash_disable_cache(uint32_t cpuid, uint32_t *saved_state) { #if CONFIG_IDF_TARGET_ESP32 uint32_t ret = 0; @@ -398,7 +402,7 @@ static void IRAM_ATTR spi_flash_disable_cache(uint32_t cpuid, uint32_t *saved_st #endif } -static void IRAM_ATTR spi_flash_restore_cache(uint32_t cpuid, uint32_t saved_state) +void IRAM_ATTR spi_flash_restore_cache(uint32_t cpuid, uint32_t saved_state) { #if CONFIG_IDF_TARGET_ESP32 const uint32_t cache_mask = DPORT_CACHE_GET_MASK(cpuid); @@ -938,7 +942,7 @@ esp_err_t esp_enable_cache_wrap(bool icache_wrap_enable, bool dcache_wrap_enable } #endif -#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H4 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6 +#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H4 || CONFIG_IDF_TARGET_ESP32C2 static IRAM_ATTR void esp_enable_cache_flash_wrap(bool icache) { @@ -979,7 +983,7 @@ esp_err_t esp_enable_cache_wrap(bool icache_wrap_enable) } return ESP_OK; } -#endif // CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H4 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6 +#endif // CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H4 || CONFIG_IDF_TARGET_ESP32C2 void IRAM_ATTR spi_flash_enable_cache(uint32_t cpuid) { diff --git a/components/spi_flash/test/test_cache_disabled.c b/components/spi_flash/test/test_cache_disabled.c index 802fcc128c..6025f7ad37 100644 --- a/components/spi_flash/test/test_cache_disabled.c +++ b/components/spi_flash/test/test_cache_disabled.c @@ -19,7 +19,8 @@ #include "esp_private/cache_utils.h" -#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32C6, ESP32H2) +//TODO: IDF-6730, migrate this test to test_app + static QueueHandle_t result_queue; static IRAM_ATTR void cache_test_task(void *arg) @@ -61,6 +62,11 @@ TEST_CASE("spi_flash_cache_enabled() works on both CPUs", "[spi_flash][esp_flash #if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2) +#define C6_H2_ROM_IMPL (CONFIG_SPI_FLASH_ROM_IMPL && (CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2)) + +#if !C6_H2_ROM_IMPL +//TODO: IDF-6931 + // This needs to sufficiently large array, otherwise it may end up in // DRAM (e.g. size <= 8 bytes && ARCH == RISCV) static const uint32_t s_in_rodata[8] = { 0x12345678, 0xfedcba98 }; @@ -83,10 +89,12 @@ static void IRAM_ATTR cache_access_test_func(void* arg) #if CONFIG_IDF_TARGET_ESP32 #define CACHE_ERROR_REASON "Cache disabled,SW_RESET" -#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32H4 || CONFIG_IDF_TARGET_ESP32C6 +#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32H4 #define CACHE_ERROR_REASON "Cache error,RTC_SW_CPU_RST" #elif CONFIG_IDF_TARGET_ESP32S3 #define CACHE_ERROR_REASON "Cache disabled,RTC_SW_CPU_RST" +#elif CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 +#define CACHE_ERROR_REASON "Cache error,SW_CPU" #endif // These tests works properly if they resets the chip with the @@ -96,6 +104,7 @@ TEST_CASE("invalid access to cache raises panic (PRO CPU)", "[spi_flash][reset=" xTaskCreatePinnedToCore(&cache_access_test_func, "ia", 2048, NULL, 5, NULL, 0); vTaskDelay(1000/portTICK_PERIOD_MS); } +#endif //#if !C6_H2_ROM_IMPL #ifndef CONFIG_FREERTOS_UNICORE @@ -107,4 +116,3 @@ TEST_CASE("invalid access to cache raises panic (APP CPU)", "[spi_flash][reset=" #endif // !CONFIG_FREERTOS_UNICORE #endif // !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2) -#endif //!TEMPORARY_DISABLED_FOR_TARGETS(ESP32C6, ESP32H2)