change(clk_tree): add LP_DYN_FAST_CLK to soc_module_clk_t

components/esp_hw_support/port/esp32h2/include/soc/rtc.h

@@ -246,6 +246,8 @@ bool rtc_clk_8m_enabled(void);
 
 /**
  * @brief Enable or disable LP_PLL_CLK
+ * Note that to be able to use LP_PLL clock, besides turn on the power for LP_PLL, also needs to turn on the power for
+ * the LP_PLL clock source (either XTAL32K or RC32K).
  * @param enable true to enable, false to disable
  */
 void rtc_clk_lp_pll_enable(bool enable);

components/esp_hw_support/port/esp32p4/esp_clk_tree.c

@@ -59,6 +59,8 @@ uint32_t *freq_value)
         clk_src_freq = esp_clk_tree_lp_slow_get_freq_hz(precision);
         break;
     case SOC_MOD_CLK_RTC_FAST:
+    case SOC_MOD_CLK_LP_DYN_FAST: // This clock can be derived from RTC_SLOW_CLK or RTC_FAST_CLK depending on the chip’s power mode.
+                                  // However, this function is only supposed to run under active mode, so its frequency is the same as RTC_FAST_CLK.
         clk_src_freq = esp_clk_tree_lp_fast_get_freq_hz(precision);
         break;
     case SOC_MOD_CLK_RC_FAST:

components/esp_hw_support/port/esp32p4/include/soc/rtc.h

@@ -241,6 +241,20 @@ void rtc_clk_8m_enable(bool clk_8m_en);
  */
 bool rtc_clk_8m_enabled(void);
 
+/**
+ * @brief Enable or disable LP_PLL_CLK
+ * Note that to be able to use LP_PLL clock, besides turn on the power for LP_PLL, also needs to turn on the power for
+ * the LP_PLL clock source (either XTAL32K or RC32K).
+ * @param enable true to enable, false to disable
+ */
+void rtc_clk_lp_pll_enable(bool enable);
+
+/**
+ * @brief Select clock source for LP_PLL_CLK
+ * @param clk_src clock source (one of soc_lp_pll_clk_src_t values)
+ */
+void rtc_clk_lp_pll_src_set(soc_lp_pll_clk_src_t clk_src);
+
 /**
  * @brief Select source for RTC_SLOW_CLK
  * @param clk_src clock source (one of soc_rtc_slow_clk_src_t values)

components/soc/esp32p4/include/soc/clk_tree_defs.h

@@ -158,6 +158,10 @@ typedef enum {
     // For LP peripherals
     SOC_MOD_CLK_XTAL_D2,                       /*!< XTAL_D2_CLK comes from the external 40MHz crystal, passing a div of 2 to the LP peripherals */
     SOC_MOD_CLK_LP_PLL,                        /*!< LP_PLL is from 32kHz XTAL oscillator frequency multipliers, it has a fixed frequency of 8MHz */
+    SOC_MOD_CLK_LP_DYN_FAST,                   /*!< LP_DYN_FAST can be derived from RTC_SLOW_CLK or RTC_FAST_CLK depending on the chip’s power mode:
+                                                    in active mode, select RTC_FAST_CLK as the clock source;
+                                                    in light/deep sleep mode, select RTC_SLOW_CLK as the clock source */
+    SOC_MOD_CLK_LP_PERI,                       /*!< LP_PERI_CLK is derived from LP_DYN_FAST (configurable divider) */
     SOC_MOD_CLK_INVALID,                       /*!< Indication of the end of the available module clock sources */
 } soc_module_clk_t;
 
@@ -616,14 +620,14 @@ typedef enum {
 /**
  * @brief Array initializer for all supported clock sources of Temperature Sensor
  */
-#define SOC_TEMP_SENSOR_CLKS {SOC_MOD_CLK_LP_PLL}
+#define SOC_TEMP_SENSOR_CLKS {SOC_MOD_CLK_LP_PERI}
 
 /**
  * @brief Type of Temp Sensor clock source
  */
 typedef enum {
-    TEMPERATURE_SENSOR_CLK_SRC_LP_PLL = SOC_MOD_CLK_LP_PLL,     /*!< Select LP_PLL as the source clock */
+    TEMPERATURE_SENSOR_CLK_SRC_LP_PERI = SOC_MOD_CLK_LP_PERI,     /*!< Select LP_PERI as the source clock */
-    TEMPERATURE_SENSOR_CLK_SRC_DEFAULT = SOC_MOD_CLK_LP_PLL,    /*!< Select LP_PLL as the default choice */
+    TEMPERATURE_SENSOR_CLK_SRC_DEFAULT = SOC_MOD_CLK_LP_PERI,    /*!< Select LP_PERI as the default choice */
 } soc_periph_temperature_sensor_clk_src_t;
 
 #ifdef __cplusplus