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Merge branch 'feature/add_esp32p4_soc_support' into 'master'

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soc: added soc headers for esp32p4 (part 1)

See merge request espressif/esp-idf!24284
This commit is contained in:
Armando (Dou Yiwen)
2023-06-26 14:44:13 +08:00
parent 67552c31da 4d5506a31b
commit ddb9c1172f
84 changed files with 163322 additions and 0 deletions
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components/soc/esp32p4/include/soc/adc_reg.h Normal file
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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** ADC_CTRL_REG_REG register
* Register
*/
#define ADC_CTRL_REG_REG (DR_REG_ADC_BASE + 0x0)
/** ADC_START_FORCE : R/W; bitpos: [0]; default: 0;
* need_des
*/
#define ADC_START_FORCE (BIT(0))
#define ADC_START_FORCE_M (ADC_START_FORCE_V << ADC_START_FORCE_S)
#define ADC_START_FORCE_V 0x00000001U
#define ADC_START_FORCE_S 0
/** ADC_START : R/W; bitpos: [1]; default: 0;
* need_des
*/
#define ADC_START (BIT(1))
#define ADC_START_M (ADC_START_V << ADC_START_S)
#define ADC_START_V 0x00000001U
#define ADC_START_S 1
/** ADC_WORK_MODE : R/W; bitpos: [3:2]; default: 0;
* 0: single mode, 1: double mode, 2: alternate mode
*/
#define ADC_WORK_MODE 0x00000003U
#define ADC_WORK_MODE_M (ADC_WORK_MODE_V << ADC_WORK_MODE_S)
#define ADC_WORK_MODE_V 0x00000003U
#define ADC_WORK_MODE_S 2
/** ADC_SAR_SEL : R/W; bitpos: [4]; default: 0;
* 0: SAR1, 1: SAR2, only work for single SAR mode
*/
#define ADC_SAR_SEL (BIT(4))
#define ADC_SAR_SEL_M (ADC_SAR_SEL_V << ADC_SAR_SEL_S)
#define ADC_SAR_SEL_V 0x00000001U
#define ADC_SAR_SEL_S 4
/** ADC_SAR_CLK_GATED : R/W; bitpos: [5]; default: 1;
* need_des
*/
#define ADC_SAR_CLK_GATED (BIT(5))
#define ADC_SAR_CLK_GATED_M (ADC_SAR_CLK_GATED_V << ADC_SAR_CLK_GATED_S)
#define ADC_SAR_CLK_GATED_V 0x00000001U
#define ADC_SAR_CLK_GATED_S 5
/** ADC_SAR_CLK_DIV : R/W; bitpos: [13:6]; default: 4;
* SAR clock divider
*/
#define ADC_SAR_CLK_DIV 0x000000FFU
#define ADC_SAR_CLK_DIV_M (ADC_SAR_CLK_DIV_V << ADC_SAR_CLK_DIV_S)
#define ADC_SAR_CLK_DIV_V 0x000000FFU
#define ADC_SAR_CLK_DIV_S 6
/** ADC_SAR1_PATT_LEN : R/W; bitpos: [17:14]; default: 15;
* 0 ~ 15 means length 1 ~ 16
*/
#define ADC_SAR1_PATT_LEN 0x0000000FU
#define ADC_SAR1_PATT_LEN_M (ADC_SAR1_PATT_LEN_V << ADC_SAR1_PATT_LEN_S)
#define ADC_SAR1_PATT_LEN_V 0x0000000FU
#define ADC_SAR1_PATT_LEN_S 14
/** ADC_SAR2_PATT_LEN : R/W; bitpos: [21:18]; default: 15;
* 0 ~ 15 means length 1 ~ 16
*/
#define ADC_SAR2_PATT_LEN 0x0000000FU
#define ADC_SAR2_PATT_LEN_M (ADC_SAR2_PATT_LEN_V << ADC_SAR2_PATT_LEN_S)
#define ADC_SAR2_PATT_LEN_V 0x0000000FU
#define ADC_SAR2_PATT_LEN_S 18
/** ADC_SAR1_PATT_P_CLEAR : R/W; bitpos: [22]; default: 0;
* clear the pointer of pattern table for DIG ADC1 CTRL
*/
#define ADC_SAR1_PATT_P_CLEAR (BIT(22))
#define ADC_SAR1_PATT_P_CLEAR_M (ADC_SAR1_PATT_P_CLEAR_V << ADC_SAR1_PATT_P_CLEAR_S)
#define ADC_SAR1_PATT_P_CLEAR_V 0x00000001U
#define ADC_SAR1_PATT_P_CLEAR_S 22
/** ADC_SAR2_PATT_P_CLEAR : R/W; bitpos: [23]; default: 0;
* clear the pointer of pattern table for DIG ADC2 CTRL
*/
#define ADC_SAR2_PATT_P_CLEAR (BIT(23))
#define ADC_SAR2_PATT_P_CLEAR_M (ADC_SAR2_PATT_P_CLEAR_V << ADC_SAR2_PATT_P_CLEAR_S)
#define ADC_SAR2_PATT_P_CLEAR_V 0x00000001U
#define ADC_SAR2_PATT_P_CLEAR_S 23
/** ADC_DATA_SAR_SEL : R/W; bitpos: [24]; default: 0;
* 1: sar_sel will be coded by the MSB of the 16-bit output data, in this case the
* resolution should not be larger than 11 bits.
*/
#define ADC_DATA_SAR_SEL (BIT(24))
#define ADC_DATA_SAR_SEL_M (ADC_DATA_SAR_SEL_V << ADC_DATA_SAR_SEL_S)
#define ADC_DATA_SAR_SEL_V 0x00000001U
#define ADC_DATA_SAR_SEL_S 24
/** ADC_DATA_TO_I2S : R/W; bitpos: [25]; default: 0;
* 1: I2S input data is from SAR ADC (for DMA), 0: I2S input data is from GPIO matrix
*/
#define ADC_DATA_TO_I2S (BIT(25))
#define ADC_DATA_TO_I2S_M (ADC_DATA_TO_I2S_V << ADC_DATA_TO_I2S_S)
#define ADC_DATA_TO_I2S_V 0x00000001U
#define ADC_DATA_TO_I2S_S 25
/** ADC_XPD_SAR1_FORCE : R/W; bitpos: [27:26]; default: 0;
* force option to xpd sar1 blocks
*/
#define ADC_XPD_SAR1_FORCE 0x00000003U
#define ADC_XPD_SAR1_FORCE_M (ADC_XPD_SAR1_FORCE_V << ADC_XPD_SAR1_FORCE_S)
#define ADC_XPD_SAR1_FORCE_V 0x00000003U
#define ADC_XPD_SAR1_FORCE_S 26
/** ADC_XPD_SAR2_FORCE : R/W; bitpos: [29:28]; default: 0;
* force option to xpd sar2 blocks
*/
#define ADC_XPD_SAR2_FORCE 0x00000003U
#define ADC_XPD_SAR2_FORCE_M (ADC_XPD_SAR2_FORCE_V << ADC_XPD_SAR2_FORCE_S)
#define ADC_XPD_SAR2_FORCE_V 0x00000003U
#define ADC_XPD_SAR2_FORCE_S 28
/** ADC_WAIT_ARB_CYCLE : R/W; bitpos: [31:30]; default: 1;
* wait arbit signal stable after sar_done
*/
#define ADC_WAIT_ARB_CYCLE 0x00000003U
#define ADC_WAIT_ARB_CYCLE_M (ADC_WAIT_ARB_CYCLE_V << ADC_WAIT_ARB_CYCLE_S)
#define ADC_WAIT_ARB_CYCLE_V 0x00000003U
#define ADC_WAIT_ARB_CYCLE_S 30
/** ADC_CTRL2_REG register
* Register
*/
#define ADC_CTRL2_REG (DR_REG_ADC_BASE + 0x4)
/** ADC_MEAS_NUM_LIMIT : R/W; bitpos: [0]; default: 0;
* need_des
*/
#define ADC_MEAS_NUM_LIMIT (BIT(0))
#define ADC_MEAS_NUM_LIMIT_M (ADC_MEAS_NUM_LIMIT_V << ADC_MEAS_NUM_LIMIT_S)
#define ADC_MEAS_NUM_LIMIT_V 0x00000001U
#define ADC_MEAS_NUM_LIMIT_S 0
/** ADC_MAX_MEAS_NUM : R/W; bitpos: [8:1]; default: 255;
* max conversion number
*/
#define ADC_MAX_MEAS_NUM 0x000000FFU
#define ADC_MAX_MEAS_NUM_M (ADC_MAX_MEAS_NUM_V << ADC_MAX_MEAS_NUM_S)
#define ADC_MAX_MEAS_NUM_V 0x000000FFU
#define ADC_MAX_MEAS_NUM_S 1
/** ADC_SAR1_INV : R/W; bitpos: [9]; default: 0;
* 1: data to DIG ADC1 CTRL is inverted, otherwise not
*/
#define ADC_SAR1_INV (BIT(9))
#define ADC_SAR1_INV_M (ADC_SAR1_INV_V << ADC_SAR1_INV_S)
#define ADC_SAR1_INV_V 0x00000001U
#define ADC_SAR1_INV_S 9
/** ADC_SAR2_INV : R/W; bitpos: [10]; default: 0;
* 1: data to DIG ADC2 CTRL is inverted, otherwise not
*/
#define ADC_SAR2_INV (BIT(10))
#define ADC_SAR2_INV_M (ADC_SAR2_INV_V << ADC_SAR2_INV_S)
#define ADC_SAR2_INV_V 0x00000001U
#define ADC_SAR2_INV_S 10
/** ADC_TIMER_SEL : R/W; bitpos: [11]; default: 0;
* 1: select saradc timer 0: i2s_ws trigger
*/
#define ADC_TIMER_SEL (BIT(11))
#define ADC_TIMER_SEL_M (ADC_TIMER_SEL_V << ADC_TIMER_SEL_S)
#define ADC_TIMER_SEL_V 0x00000001U
#define ADC_TIMER_SEL_S 11
/** ADC_TIMER_TARGET : R/W; bitpos: [23:12]; default: 10;
* to set saradc timer target
*/
#define ADC_TIMER_TARGET 0x00000FFFU
#define ADC_TIMER_TARGET_M (ADC_TIMER_TARGET_V << ADC_TIMER_TARGET_S)
#define ADC_TIMER_TARGET_V 0x00000FFFU
#define ADC_TIMER_TARGET_S 12
/** ADC_TIMER_EN : R/W; bitpos: [24]; default: 0;
* to enable saradc timer trigger
*/
#define ADC_TIMER_EN (BIT(24))
#define ADC_TIMER_EN_M (ADC_TIMER_EN_V << ADC_TIMER_EN_S)
#define ADC_TIMER_EN_V 0x00000001U
#define ADC_TIMER_EN_S 24
/** ADC_FILTER_CTRL1_REG register
* Register
*/
#define ADC_FILTER_CTRL1_REG (DR_REG_ADC_BASE + 0x8)
/** ADC_FILTER_FACTOR1 : R/W; bitpos: [28:26]; default: 0;
* need_des
*/
#define ADC_FILTER_FACTOR1 0x00000007U
#define ADC_FILTER_FACTOR1_M (ADC_FILTER_FACTOR1_V << ADC_FILTER_FACTOR1_S)
#define ADC_FILTER_FACTOR1_V 0x00000007U
#define ADC_FILTER_FACTOR1_S 26
/** ADC_FILTER_FACTOR0 : R/W; bitpos: [31:29]; default: 0;
* need_des
*/
#define ADC_FILTER_FACTOR0 0x00000007U
#define ADC_FILTER_FACTOR0_M (ADC_FILTER_FACTOR0_V << ADC_FILTER_FACTOR0_S)
#define ADC_FILTER_FACTOR0_V 0x00000007U
#define ADC_FILTER_FACTOR0_S 29
/** ADC_SAR1_PATT_TAB1_REG register
* Register
*/
#define ADC_SAR1_PATT_TAB1_REG (DR_REG_ADC_BASE + 0x18)
/** ADC_SAR1_PATT_TAB1 : R/W; bitpos: [23:0]; default: 0;
* item 0 ~ 3 for pattern table 1 (each item one byte)
*/
#define ADC_SAR1_PATT_TAB1 0x00FFFFFFU
#define ADC_SAR1_PATT_TAB1_M (ADC_SAR1_PATT_TAB1_V << ADC_SAR1_PATT_TAB1_S)
#define ADC_SAR1_PATT_TAB1_V 0x00FFFFFFU
#define ADC_SAR1_PATT_TAB1_S 0
/** ADC_SAR1_PATT_TAB2_REG register
* Register
*/
#define ADC_SAR1_PATT_TAB2_REG (DR_REG_ADC_BASE + 0x1c)
/** ADC_SAR1_PATT_TAB2 : R/W; bitpos: [23:0]; default: 0;
* Item 4 ~ 7 for pattern table 1 (each item one byte)
*/
#define ADC_SAR1_PATT_TAB2 0x00FFFFFFU
#define ADC_SAR1_PATT_TAB2_M (ADC_SAR1_PATT_TAB2_V << ADC_SAR1_PATT_TAB2_S)
#define ADC_SAR1_PATT_TAB2_V 0x00FFFFFFU
#define ADC_SAR1_PATT_TAB2_S 0
/** ADC_SAR1_PATT_TAB3_REG register
* Register
*/
#define ADC_SAR1_PATT_TAB3_REG (DR_REG_ADC_BASE + 0x20)
/** ADC_SAR1_PATT_TAB3 : R/W; bitpos: [23:0]; default: 0;
* Item 8 ~ 11 for pattern table 1 (each item one byte)
*/
#define ADC_SAR1_PATT_TAB3 0x00FFFFFFU
#define ADC_SAR1_PATT_TAB3_M (ADC_SAR1_PATT_TAB3_V << ADC_SAR1_PATT_TAB3_S)
#define ADC_SAR1_PATT_TAB3_V 0x00FFFFFFU
#define ADC_SAR1_PATT_TAB3_S 0
/** ADC_SAR1_PATT_TAB4_REG register
* Register
*/
#define ADC_SAR1_PATT_TAB4_REG (DR_REG_ADC_BASE + 0x24)
/** ADC_SAR1_PATT_TAB4 : R/W; bitpos: [23:0]; default: 0;
* Item 12 ~ 15 for pattern table 1 (each item one byte)
*/
#define ADC_SAR1_PATT_TAB4 0x00FFFFFFU
#define ADC_SAR1_PATT_TAB4_M (ADC_SAR1_PATT_TAB4_V << ADC_SAR1_PATT_TAB4_S)
#define ADC_SAR1_PATT_TAB4_V 0x00FFFFFFU
#define ADC_SAR1_PATT_TAB4_S 0
/** ADC_SAR2_PATT_TAB1_REG register
* Register
*/
#define ADC_SAR2_PATT_TAB1_REG (DR_REG_ADC_BASE + 0x28)
/** ADC_SAR2_PATT_TAB1 : R/W; bitpos: [23:0]; default: 0;
* item 0 ~ 3 for pattern table 2 (each item one byte)
*/
#define ADC_SAR2_PATT_TAB1 0x00FFFFFFU
#define ADC_SAR2_PATT_TAB1_M (ADC_SAR2_PATT_TAB1_V << ADC_SAR2_PATT_TAB1_S)
#define ADC_SAR2_PATT_TAB1_V 0x00FFFFFFU
#define ADC_SAR2_PATT_TAB1_S 0
/** ADC_SAR2_PATT_TAB2_REG register
* Register
*/
#define ADC_SAR2_PATT_TAB2_REG (DR_REG_ADC_BASE + 0x2c)
/** ADC_SAR2_PATT_TAB2 : R/W; bitpos: [23:0]; default: 0;
* Item 4 ~ 7 for pattern table 2 (each item one byte)
*/
#define ADC_SAR2_PATT_TAB2 0x00FFFFFFU
#define ADC_SAR2_PATT_TAB2_M (ADC_SAR2_PATT_TAB2_V << ADC_SAR2_PATT_TAB2_S)
#define ADC_SAR2_PATT_TAB2_V 0x00FFFFFFU
#define ADC_SAR2_PATT_TAB2_S 0
/** ADC_SAR2_PATT_TAB3_REG register
* Register
*/
#define ADC_SAR2_PATT_TAB3_REG (DR_REG_ADC_BASE + 0x30)
/** ADC_SAR2_PATT_TAB3 : R/W; bitpos: [23:0]; default: 0;
* Item 8 ~ 11 for pattern table 2 (each item one byte)
*/
#define ADC_SAR2_PATT_TAB3 0x00FFFFFFU
#define ADC_SAR2_PATT_TAB3_M (ADC_SAR2_PATT_TAB3_V << ADC_SAR2_PATT_TAB3_S)
#define ADC_SAR2_PATT_TAB3_V 0x00FFFFFFU
#define ADC_SAR2_PATT_TAB3_S 0
/** ADC_SAR2_PATT_TAB4_REG register
* Register
*/
#define ADC_SAR2_PATT_TAB4_REG (DR_REG_ADC_BASE + 0x34)
/** ADC_SAR2_PATT_TAB4 : R/W; bitpos: [23:0]; default: 0;
* Item 12 ~ 15 for pattern table 2 (each item one byte)
*/
#define ADC_SAR2_PATT_TAB4 0x00FFFFFFU
#define ADC_SAR2_PATT_TAB4_M (ADC_SAR2_PATT_TAB4_V << ADC_SAR2_PATT_TAB4_S)
#define ADC_SAR2_PATT_TAB4_V 0x00FFFFFFU
#define ADC_SAR2_PATT_TAB4_S 0
/** ADC_ARB_CTRL_REG register
* Register
*/
#define ADC_ARB_CTRL_REG (DR_REG_ADC_BASE + 0x38)
/** ADC_ARB_APB_FORCE : R/W; bitpos: [2]; default: 0;
* adc2 arbiter force to enableapb controller
*/
#define ADC_ARB_APB_FORCE (BIT(2))
#define ADC_ARB_APB_FORCE_M (ADC_ARB_APB_FORCE_V << ADC_ARB_APB_FORCE_S)
#define ADC_ARB_APB_FORCE_V 0x00000001U
#define ADC_ARB_APB_FORCE_S 2
/** ADC_ARB_RTC_FORCE : R/W; bitpos: [3]; default: 0;
* adc2 arbiter force to enable rtc controller
*/
#define ADC_ARB_RTC_FORCE (BIT(3))
#define ADC_ARB_RTC_FORCE_M (ADC_ARB_RTC_FORCE_V << ADC_ARB_RTC_FORCE_S)
#define ADC_ARB_RTC_FORCE_V 0x00000001U
#define ADC_ARB_RTC_FORCE_S 3
/** ADC_ARB_WIFI_FORCE : R/W; bitpos: [4]; default: 0;
* adc2 arbiter force to enable wifi controller
*/
#define ADC_ARB_WIFI_FORCE (BIT(4))
#define ADC_ARB_WIFI_FORCE_M (ADC_ARB_WIFI_FORCE_V << ADC_ARB_WIFI_FORCE_S)
#define ADC_ARB_WIFI_FORCE_V 0x00000001U
#define ADC_ARB_WIFI_FORCE_S 4
/** ADC_ARB_GRANT_FORCE : R/W; bitpos: [5]; default: 0;
* adc2 arbiter force grant
*/
#define ADC_ARB_GRANT_FORCE (BIT(5))
#define ADC_ARB_GRANT_FORCE_M (ADC_ARB_GRANT_FORCE_V << ADC_ARB_GRANT_FORCE_S)
#define ADC_ARB_GRANT_FORCE_V 0x00000001U
#define ADC_ARB_GRANT_FORCE_S 5
/** ADC_ARB_APB_PRIORITY : R/W; bitpos: [7:6]; default: 0;
* Set adc2 arbiterapb priority
*/
#define ADC_ARB_APB_PRIORITY 0x00000003U
#define ADC_ARB_APB_PRIORITY_M (ADC_ARB_APB_PRIORITY_V << ADC_ARB_APB_PRIORITY_S)
#define ADC_ARB_APB_PRIORITY_V 0x00000003U
#define ADC_ARB_APB_PRIORITY_S 6
/** ADC_ARB_RTC_PRIORITY : R/W; bitpos: [9:8]; default: 1;
* Set adc2 arbiter rtc priority
*/
#define ADC_ARB_RTC_PRIORITY 0x00000003U
#define ADC_ARB_RTC_PRIORITY_M (ADC_ARB_RTC_PRIORITY_V << ADC_ARB_RTC_PRIORITY_S)
#define ADC_ARB_RTC_PRIORITY_V 0x00000003U
#define ADC_ARB_RTC_PRIORITY_S 8
/** ADC_ARB_WIFI_PRIORITY : R/W; bitpos: [11:10]; default: 2;
* Set adc2 arbiter wifi priority
*/
#define ADC_ARB_WIFI_PRIORITY 0x00000003U
#define ADC_ARB_WIFI_PRIORITY_M (ADC_ARB_WIFI_PRIORITY_V << ADC_ARB_WIFI_PRIORITY_S)
#define ADC_ARB_WIFI_PRIORITY_V 0x00000003U
#define ADC_ARB_WIFI_PRIORITY_S 10
/** ADC_ARB_FIX_PRIORITY : R/W; bitpos: [12]; default: 0;
* adc2 arbiter uses fixed priority
*/
#define ADC_ARB_FIX_PRIORITY (BIT(12))
#define ADC_ARB_FIX_PRIORITY_M (ADC_ARB_FIX_PRIORITY_V << ADC_ARB_FIX_PRIORITY_S)
#define ADC_ARB_FIX_PRIORITY_V 0x00000001U
#define ADC_ARB_FIX_PRIORITY_S 12
/** ADC_FILTER_CTRL0_REG register
* Register
*/
#define ADC_FILTER_CTRL0_REG (DR_REG_ADC_BASE + 0x3c)
/** ADC_FILTER_CHANNEL1 : R/W; bitpos: [18:14]; default: 13;
* need_des
*/
#define ADC_FILTER_CHANNEL1 0x0000001FU
#define ADC_FILTER_CHANNEL1_M (ADC_FILTER_CHANNEL1_V << ADC_FILTER_CHANNEL1_S)
#define ADC_FILTER_CHANNEL1_V 0x0000001FU
#define ADC_FILTER_CHANNEL1_S 14
/** ADC_FILTER_CHANNEL0 : R/W; bitpos: [23:19]; default: 13;
* apb_adc1_filter_factor
*/
#define ADC_FILTER_CHANNEL0 0x0000001FU
#define ADC_FILTER_CHANNEL0_M (ADC_FILTER_CHANNEL0_V << ADC_FILTER_CHANNEL0_S)
#define ADC_FILTER_CHANNEL0_V 0x0000001FU
#define ADC_FILTER_CHANNEL0_S 19
/** ADC_FILTER_RESET : R/W; bitpos: [31]; default: 0;
* enable apb_adc1_filter
*/
#define ADC_FILTER_RESET (BIT(31))
#define ADC_FILTER_RESET_M (ADC_FILTER_RESET_V << ADC_FILTER_RESET_S)
#define ADC_FILTER_RESET_V 0x00000001U
#define ADC_FILTER_RESET_S 31
/** ADC_SAR1_DATA_STATUS_REG register
* Register
*/
#define ADC_SAR1_DATA_STATUS_REG (DR_REG_ADC_BASE + 0x40)
/** ADC_APB_SARADC1_DATA : RO; bitpos: [16:0]; default: 0;
* need_des
*/
#define ADC_APB_SARADC1_DATA 0x0001FFFFU
#define ADC_APB_SARADC1_DATA_M (ADC_APB_SARADC1_DATA_V << ADC_APB_SARADC1_DATA_S)
#define ADC_APB_SARADC1_DATA_V 0x0001FFFFU
#define ADC_APB_SARADC1_DATA_S 0
/** ADC_THRES0_CTRL_REG register
* Register
*/
#define ADC_THRES0_CTRL_REG (DR_REG_ADC_BASE + 0x44)
/** ADC_THRES0_CHANNEL : R/W; bitpos: [4:0]; default: 13;
* need_des
*/
#define ADC_THRES0_CHANNEL 0x0000001FU
#define ADC_THRES0_CHANNEL_M (ADC_THRES0_CHANNEL_V << ADC_THRES0_CHANNEL_S)
#define ADC_THRES0_CHANNEL_V 0x0000001FU
#define ADC_THRES0_CHANNEL_S 0
/** ADC_THRES0_HIGH : R/W; bitpos: [17:5]; default: 8191;
* saradc1's thres0 monitor thres
*/
#define ADC_THRES0_HIGH 0x00001FFFU
#define ADC_THRES0_HIGH_M (ADC_THRES0_HIGH_V << ADC_THRES0_HIGH_S)
#define ADC_THRES0_HIGH_V 0x00001FFFU
#define ADC_THRES0_HIGH_S 5
/** ADC_THRES0_LOW : R/W; bitpos: [30:18]; default: 0;
* saradc1's thres0 monitor thres
*/
#define ADC_THRES0_LOW 0x00001FFFU
#define ADC_THRES0_LOW_M (ADC_THRES0_LOW_V << ADC_THRES0_LOW_S)
#define ADC_THRES0_LOW_V 0x00001FFFU
#define ADC_THRES0_LOW_S 18
/** ADC_THRES1_CTRL_REG register
* Register
*/
#define ADC_THRES1_CTRL_REG (DR_REG_ADC_BASE + 0x48)
/** ADC_THRES1_CHANNEL : R/W; bitpos: [4:0]; default: 13;
* need_des
*/
#define ADC_THRES1_CHANNEL 0x0000001FU
#define ADC_THRES1_CHANNEL_M (ADC_THRES1_CHANNEL_V << ADC_THRES1_CHANNEL_S)
#define ADC_THRES1_CHANNEL_V 0x0000001FU
#define ADC_THRES1_CHANNEL_S 0
/** ADC_THRES1_HIGH : R/W; bitpos: [17:5]; default: 8191;
* saradc1's thres0 monitor thres
*/
#define ADC_THRES1_HIGH 0x00001FFFU
#define ADC_THRES1_HIGH_M (ADC_THRES1_HIGH_V << ADC_THRES1_HIGH_S)
#define ADC_THRES1_HIGH_V 0x00001FFFU
#define ADC_THRES1_HIGH_S 5
/** ADC_THRES1_LOW : R/W; bitpos: [30:18]; default: 0;
* saradc1's thres0 monitor thres
*/
#define ADC_THRES1_LOW 0x00001FFFU
#define ADC_THRES1_LOW_M (ADC_THRES1_LOW_V << ADC_THRES1_LOW_S)
#define ADC_THRES1_LOW_V 0x00001FFFU
#define ADC_THRES1_LOW_S 18
/** ADC_THRES_CTRL_REG register
* Register
*/
#define ADC_THRES_CTRL_REG (DR_REG_ADC_BASE + 0x4c)
/** ADC_THRES_ALL_EN : R/W; bitpos: [27]; default: 0;
* need_des
*/
#define ADC_THRES_ALL_EN (BIT(27))
#define ADC_THRES_ALL_EN_M (ADC_THRES_ALL_EN_V << ADC_THRES_ALL_EN_S)
#define ADC_THRES_ALL_EN_V 0x00000001U
#define ADC_THRES_ALL_EN_S 27
/** ADC_THRES3_EN : R/W; bitpos: [28]; default: 0;
* need_des
*/
#define ADC_THRES3_EN (BIT(28))
#define ADC_THRES3_EN_M (ADC_THRES3_EN_V << ADC_THRES3_EN_S)
#define ADC_THRES3_EN_V 0x00000001U
#define ADC_THRES3_EN_S 28
/** ADC_THRES2_EN : R/W; bitpos: [29]; default: 0;
* need_des
*/
#define ADC_THRES2_EN (BIT(29))
#define ADC_THRES2_EN_M (ADC_THRES2_EN_V << ADC_THRES2_EN_S)
#define ADC_THRES2_EN_V 0x00000001U
#define ADC_THRES2_EN_S 29
/** ADC_THRES1_EN : R/W; bitpos: [30]; default: 0;
* need_des
*/
#define ADC_THRES1_EN (BIT(30))
#define ADC_THRES1_EN_M (ADC_THRES1_EN_V << ADC_THRES1_EN_S)
#define ADC_THRES1_EN_V 0x00000001U
#define ADC_THRES1_EN_S 30
/** ADC_THRES0_EN : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define ADC_THRES0_EN (BIT(31))
#define ADC_THRES0_EN_M (ADC_THRES0_EN_V << ADC_THRES0_EN_S)
#define ADC_THRES0_EN_V 0x00000001U
#define ADC_THRES0_EN_S 31
/** ADC_INT_ENA_REG register
* Register
*/
#define ADC_INT_ENA_REG (DR_REG_ADC_BASE + 0x50)
/** ADC_THRES1_LOW_INT_ENA : R/W; bitpos: [26]; default: 0;
* need_des
*/
#define ADC_THRES1_LOW_INT_ENA (BIT(26))
#define ADC_THRES1_LOW_INT_ENA_M (ADC_THRES1_LOW_INT_ENA_V << ADC_THRES1_LOW_INT_ENA_S)
#define ADC_THRES1_LOW_INT_ENA_V 0x00000001U
#define ADC_THRES1_LOW_INT_ENA_S 26
/** ADC_THRES0_LOW_INT_ENA : R/W; bitpos: [27]; default: 0;
* need_des
*/
#define ADC_THRES0_LOW_INT_ENA (BIT(27))
#define ADC_THRES0_LOW_INT_ENA_M (ADC_THRES0_LOW_INT_ENA_V << ADC_THRES0_LOW_INT_ENA_S)
#define ADC_THRES0_LOW_INT_ENA_V 0x00000001U
#define ADC_THRES0_LOW_INT_ENA_S 27
/** ADC_THRES1_HIGH_INT_ENA : R/W; bitpos: [28]; default: 0;
* need_des
*/
#define ADC_THRES1_HIGH_INT_ENA (BIT(28))
#define ADC_THRES1_HIGH_INT_ENA_M (ADC_THRES1_HIGH_INT_ENA_V << ADC_THRES1_HIGH_INT_ENA_S)
#define ADC_THRES1_HIGH_INT_ENA_V 0x00000001U
#define ADC_THRES1_HIGH_INT_ENA_S 28
/** ADC_THRES0_HIGH_INT_ENA : R/W; bitpos: [29]; default: 0;
* need_des
*/
#define ADC_THRES0_HIGH_INT_ENA (BIT(29))
#define ADC_THRES0_HIGH_INT_ENA_M (ADC_THRES0_HIGH_INT_ENA_V << ADC_THRES0_HIGH_INT_ENA_S)
#define ADC_THRES0_HIGH_INT_ENA_V 0x00000001U
#define ADC_THRES0_HIGH_INT_ENA_S 29
/** ADC_SAR2_DONE_INT_ENA : R/W; bitpos: [30]; default: 0;
* need_des
*/
#define ADC_SAR2_DONE_INT_ENA (BIT(30))
#define ADC_SAR2_DONE_INT_ENA_M (ADC_SAR2_DONE_INT_ENA_V << ADC_SAR2_DONE_INT_ENA_S)
#define ADC_SAR2_DONE_INT_ENA_V 0x00000001U
#define ADC_SAR2_DONE_INT_ENA_S 30
/** ADC_SAR1_DONE_INT_ENA : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define ADC_SAR1_DONE_INT_ENA (BIT(31))
#define ADC_SAR1_DONE_INT_ENA_M (ADC_SAR1_DONE_INT_ENA_V << ADC_SAR1_DONE_INT_ENA_S)
#define ADC_SAR1_DONE_INT_ENA_V 0x00000001U
#define ADC_SAR1_DONE_INT_ENA_S 31
/** ADC_INT_RAW_REG register
* Register
*/
#define ADC_INT_RAW_REG (DR_REG_ADC_BASE + 0x54)
/** ADC_THRES1_LOW_INT_RAW : R/WTC/SS; bitpos: [26]; default: 0;
* need_des
*/
#define ADC_THRES1_LOW_INT_RAW (BIT(26))
#define ADC_THRES1_LOW_INT_RAW_M (ADC_THRES1_LOW_INT_RAW_V << ADC_THRES1_LOW_INT_RAW_S)
#define ADC_THRES1_LOW_INT_RAW_V 0x00000001U
#define ADC_THRES1_LOW_INT_RAW_S 26
/** ADC_THRES0_LOW_INT_RAW : R/WTC/SS; bitpos: [27]; default: 0;
* need_des
*/
#define ADC_THRES0_LOW_INT_RAW (BIT(27))
#define ADC_THRES0_LOW_INT_RAW_M (ADC_THRES0_LOW_INT_RAW_V << ADC_THRES0_LOW_INT_RAW_S)
#define ADC_THRES0_LOW_INT_RAW_V 0x00000001U
#define ADC_THRES0_LOW_INT_RAW_S 27
/** ADC_THRES1_HIGH_INT_RAW : R/WTC/SS; bitpos: [28]; default: 0;
* need_des
*/
#define ADC_THRES1_HIGH_INT_RAW (BIT(28))
#define ADC_THRES1_HIGH_INT_RAW_M (ADC_THRES1_HIGH_INT_RAW_V << ADC_THRES1_HIGH_INT_RAW_S)
#define ADC_THRES1_HIGH_INT_RAW_V 0x00000001U
#define ADC_THRES1_HIGH_INT_RAW_S 28
/** ADC_THRES0_HIGH_INT_RAW : R/WTC/SS; bitpos: [29]; default: 0;
* need_des
*/
#define ADC_THRES0_HIGH_INT_RAW (BIT(29))
#define ADC_THRES0_HIGH_INT_RAW_M (ADC_THRES0_HIGH_INT_RAW_V << ADC_THRES0_HIGH_INT_RAW_S)
#define ADC_THRES0_HIGH_INT_RAW_V 0x00000001U
#define ADC_THRES0_HIGH_INT_RAW_S 29
/** ADC_SAR2_DONE_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0;
* need_des
*/
#define ADC_SAR2_DONE_INT_RAW (BIT(30))
#define ADC_SAR2_DONE_INT_RAW_M (ADC_SAR2_DONE_INT_RAW_V << ADC_SAR2_DONE_INT_RAW_S)
#define ADC_SAR2_DONE_INT_RAW_V 0x00000001U
#define ADC_SAR2_DONE_INT_RAW_S 30
/** ADC_SAR1_DONE_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
* need_des
*/
#define ADC_SAR1_DONE_INT_RAW (BIT(31))
#define ADC_SAR1_DONE_INT_RAW_M (ADC_SAR1_DONE_INT_RAW_V << ADC_SAR1_DONE_INT_RAW_S)
#define ADC_SAR1_DONE_INT_RAW_V 0x00000001U
#define ADC_SAR1_DONE_INT_RAW_S 31
/** ADC_INT_ST_REG register
* Register
*/
#define ADC_INT_ST_REG (DR_REG_ADC_BASE + 0x58)
/** ADC_THRES1_LOW_INT_ST : RO; bitpos: [26]; default: 0;
* need_des
*/
#define ADC_THRES1_LOW_INT_ST (BIT(26))
#define ADC_THRES1_LOW_INT_ST_M (ADC_THRES1_LOW_INT_ST_V << ADC_THRES1_LOW_INT_ST_S)
#define ADC_THRES1_LOW_INT_ST_V 0x00000001U
#define ADC_THRES1_LOW_INT_ST_S 26
/** ADC_THRES0_LOW_INT_ST : RO; bitpos: [27]; default: 0;
* need_des
*/
#define ADC_THRES0_LOW_INT_ST (BIT(27))
#define ADC_THRES0_LOW_INT_ST_M (ADC_THRES0_LOW_INT_ST_V << ADC_THRES0_LOW_INT_ST_S)
#define ADC_THRES0_LOW_INT_ST_V 0x00000001U
#define ADC_THRES0_LOW_INT_ST_S 27
/** ADC_THRES1_HIGH_INT_ST : RO; bitpos: [28]; default: 0;
* need_des
*/
#define ADC_THRES1_HIGH_INT_ST (BIT(28))
#define ADC_THRES1_HIGH_INT_ST_M (ADC_THRES1_HIGH_INT_ST_V << ADC_THRES1_HIGH_INT_ST_S)
#define ADC_THRES1_HIGH_INT_ST_V 0x00000001U
#define ADC_THRES1_HIGH_INT_ST_S 28
/** ADC_THRES0_HIGH_INT_ST : RO; bitpos: [29]; default: 0;
* need_des
*/
#define ADC_THRES0_HIGH_INT_ST (BIT(29))
#define ADC_THRES0_HIGH_INT_ST_M (ADC_THRES0_HIGH_INT_ST_V << ADC_THRES0_HIGH_INT_ST_S)
#define ADC_THRES0_HIGH_INT_ST_V 0x00000001U
#define ADC_THRES0_HIGH_INT_ST_S 29
/** ADC_APB_SARADC2_DONE_INT_ST : RO; bitpos: [30]; default: 0;
* need_des
*/
#define ADC_APB_SARADC2_DONE_INT_ST (BIT(30))
#define ADC_APB_SARADC2_DONE_INT_ST_M (ADC_APB_SARADC2_DONE_INT_ST_V << ADC_APB_SARADC2_DONE_INT_ST_S)
#define ADC_APB_SARADC2_DONE_INT_ST_V 0x00000001U
#define ADC_APB_SARADC2_DONE_INT_ST_S 30
/** ADC_APB_SARADC1_DONE_INT_ST : RO; bitpos: [31]; default: 0;
* need_des
*/
#define ADC_APB_SARADC1_DONE_INT_ST (BIT(31))
#define ADC_APB_SARADC1_DONE_INT_ST_M (ADC_APB_SARADC1_DONE_INT_ST_V << ADC_APB_SARADC1_DONE_INT_ST_S)
#define ADC_APB_SARADC1_DONE_INT_ST_V 0x00000001U
#define ADC_APB_SARADC1_DONE_INT_ST_S 31
/** ADC_INT_CLR_REG register
* Register
*/
#define ADC_INT_CLR_REG (DR_REG_ADC_BASE + 0x5c)
/** ADC_THRES1_LOW_INT_CLR : WT; bitpos: [26]; default: 0;
* need_des
*/
#define ADC_THRES1_LOW_INT_CLR (BIT(26))
#define ADC_THRES1_LOW_INT_CLR_M (ADC_THRES1_LOW_INT_CLR_V << ADC_THRES1_LOW_INT_CLR_S)
#define ADC_THRES1_LOW_INT_CLR_V 0x00000001U
#define ADC_THRES1_LOW_INT_CLR_S 26
/** ADC_THRES0_LOW_INT_CLR : WT; bitpos: [27]; default: 0;
* need_des
*/
#define ADC_THRES0_LOW_INT_CLR (BIT(27))
#define ADC_THRES0_LOW_INT_CLR_M (ADC_THRES0_LOW_INT_CLR_V << ADC_THRES0_LOW_INT_CLR_S)
#define ADC_THRES0_LOW_INT_CLR_V 0x00000001U
#define ADC_THRES0_LOW_INT_CLR_S 27
/** ADC_THRES1_HIGH_INT_CLR : WT; bitpos: [28]; default: 0;
* need_des
*/
#define ADC_THRES1_HIGH_INT_CLR (BIT(28))
#define ADC_THRES1_HIGH_INT_CLR_M (ADC_THRES1_HIGH_INT_CLR_V << ADC_THRES1_HIGH_INT_CLR_S)
#define ADC_THRES1_HIGH_INT_CLR_V 0x00000001U
#define ADC_THRES1_HIGH_INT_CLR_S 28
/** ADC_THRES0_HIGH_INT_CLR : WT; bitpos: [29]; default: 0;
* need_des
*/
#define ADC_THRES0_HIGH_INT_CLR (BIT(29))
#define ADC_THRES0_HIGH_INT_CLR_M (ADC_THRES0_HIGH_INT_CLR_V << ADC_THRES0_HIGH_INT_CLR_S)
#define ADC_THRES0_HIGH_INT_CLR_V 0x00000001U
#define ADC_THRES0_HIGH_INT_CLR_S 29
/** ADC_APB_SARADC2_DONE_INT_CLR : WT; bitpos: [30]; default: 0;
* need_des
*/
#define ADC_APB_SARADC2_DONE_INT_CLR (BIT(30))
#define ADC_APB_SARADC2_DONE_INT_CLR_M (ADC_APB_SARADC2_DONE_INT_CLR_V << ADC_APB_SARADC2_DONE_INT_CLR_S)
#define ADC_APB_SARADC2_DONE_INT_CLR_V 0x00000001U
#define ADC_APB_SARADC2_DONE_INT_CLR_S 30
/** ADC_APB_SARADC1_DONE_INT_CLR : WT; bitpos: [31]; default: 0;
* need_des
*/
#define ADC_APB_SARADC1_DONE_INT_CLR (BIT(31))
#define ADC_APB_SARADC1_DONE_INT_CLR_M (ADC_APB_SARADC1_DONE_INT_CLR_V << ADC_APB_SARADC1_DONE_INT_CLR_S)
#define ADC_APB_SARADC1_DONE_INT_CLR_V 0x00000001U
#define ADC_APB_SARADC1_DONE_INT_CLR_S 31
/** ADC_DMA_CONF_REG register
* Register
*/
#define ADC_DMA_CONF_REG (DR_REG_ADC_BASE + 0x60)
/** ADC_APB_ADC_EOF_NUM : R/W; bitpos: [15:0]; default: 255;
* the dma_in_suc_eof gen when sample cnt = spi_eof_num
*/
#define ADC_APB_ADC_EOF_NUM 0x0000FFFFU
#define ADC_APB_ADC_EOF_NUM_M (ADC_APB_ADC_EOF_NUM_V << ADC_APB_ADC_EOF_NUM_S)
#define ADC_APB_ADC_EOF_NUM_V 0x0000FFFFU
#define ADC_APB_ADC_EOF_NUM_S 0
/** ADC_APB_ADC_RESET_FSM : R/W; bitpos: [30]; default: 0;
* reset_apb_adc_state
*/
#define ADC_APB_ADC_RESET_FSM (BIT(30))
#define ADC_APB_ADC_RESET_FSM_M (ADC_APB_ADC_RESET_FSM_V << ADC_APB_ADC_RESET_FSM_S)
#define ADC_APB_ADC_RESET_FSM_V 0x00000001U
#define ADC_APB_ADC_RESET_FSM_S 30
/** ADC_APB_ADC_TRANS : R/W; bitpos: [31]; default: 0;
* enable apb_adc use spi_dma
*/
#define ADC_APB_ADC_TRANS (BIT(31))
#define ADC_APB_ADC_TRANS_M (ADC_APB_ADC_TRANS_V << ADC_APB_ADC_TRANS_S)
#define ADC_APB_ADC_TRANS_V 0x00000001U
#define ADC_APB_ADC_TRANS_S 31
/** ADC_SAR2_DATA_STATUS_REG register
* Register
*/
#define ADC_SAR2_DATA_STATUS_REG (DR_REG_ADC_BASE + 0x64)
/** ADC_APB_SARADC2_DATA : RO; bitpos: [16:0]; default: 0;
* need_des
*/
#define ADC_APB_SARADC2_DATA 0x0001FFFFU
#define ADC_APB_SARADC2_DATA_M (ADC_APB_SARADC2_DATA_V << ADC_APB_SARADC2_DATA_S)
#define ADC_APB_SARADC2_DATA_V 0x0001FFFFU
#define ADC_APB_SARADC2_DATA_S 0
/** ADC_CALI_REG register
* Register
*/
#define ADC_CALI_REG (DR_REG_ADC_BASE + 0x68)
/** ADC_CALI_CFG : R/W; bitpos: [16:0]; default: 32768;
* need_des
*/
#define ADC_CALI_CFG 0x0001FFFFU
#define ADC_CALI_CFG_M (ADC_CALI_CFG_V << ADC_CALI_CFG_S)
#define ADC_CALI_CFG_V 0x0001FFFFU
#define ADC_CALI_CFG_S 0
/** ADC_RND_ECO_LOW_REG register
* Register
*/
#define ADC_RND_ECO_LOW_REG (DR_REG_ADC_BASE + 0x6c)
/** ADC_RND_ECO_LOW : R/W; bitpos: [31:0]; default: 0;
* rnd eco low
*/
#define ADC_RND_ECO_LOW 0xFFFFFFFFU
#define ADC_RND_ECO_LOW_M (ADC_RND_ECO_LOW_V << ADC_RND_ECO_LOW_S)
#define ADC_RND_ECO_LOW_V 0xFFFFFFFFU
#define ADC_RND_ECO_LOW_S 0
/** ADC_RND_ECO_HIGH_REG register
* Register
*/
#define ADC_RND_ECO_HIGH_REG (DR_REG_ADC_BASE + 0x70)
/** ADC_RND_ECO_HIGH : R/W; bitpos: [31:0]; default: 4294967295;
* rnd eco high
*/
#define ADC_RND_ECO_HIGH 0xFFFFFFFFU
#define ADC_RND_ECO_HIGH_M (ADC_RND_ECO_HIGH_V << ADC_RND_ECO_HIGH_S)
#define ADC_RND_ECO_HIGH_V 0xFFFFFFFFU
#define ADC_RND_ECO_HIGH_S 0
/** ADC_RND_ECO_CS_REG register
* Register
*/
#define ADC_RND_ECO_CS_REG (DR_REG_ADC_BASE + 0x74)
/** ADC_RND_ECO_EN : R/W; bitpos: [0]; default: 0;
* need_des
*/
#define ADC_RND_ECO_EN (BIT(0))
#define ADC_RND_ECO_EN_M (ADC_RND_ECO_EN_V << ADC_RND_ECO_EN_S)
#define ADC_RND_ECO_EN_V 0x00000001U
#define ADC_RND_ECO_EN_S 0
/** ADC_RND_ECO_RESULT : RO; bitpos: [1]; default: 0;
* need_des
*/
#define ADC_RND_ECO_RESULT (BIT(1))
#define ADC_RND_ECO_RESULT_M (ADC_RND_ECO_RESULT_V << ADC_RND_ECO_RESULT_S)
#define ADC_RND_ECO_RESULT_V 0x00000001U
#define ADC_RND_ECO_RESULT_S 1
/** ADC_CTRL_DATE_REG register
* Register
*/
#define ADC_CTRL_DATE_REG (DR_REG_ADC_BASE + 0x3fc)
/** ADC_CTRL_DATE : R/W; bitpos: [30:0]; default: 35725920;
* need_des
*/
#define ADC_CTRL_DATE 0x7FFFFFFFU
#define ADC_CTRL_DATE_M (ADC_CTRL_DATE_V << ADC_CTRL_DATE_S)
#define ADC_CTRL_DATE_V 0x7FFFFFFFU
#define ADC_CTRL_DATE_S 0
/** ADC_CLK_EN : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define ADC_CLK_EN (BIT(31))
#define ADC_CLK_EN_M (ADC_CLK_EN_V << ADC_CLK_EN_S)
#define ADC_CLK_EN_V 0x00000001U
#define ADC_CLK_EN_S 31
#ifdef __cplusplus
}
#endif

694
components/soc/esp32p4/include/soc/adc_struct.h Normal file
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@@ -0,0 +1,694 @@
/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Configure Register */
/** Type of ctrl_reg register
* Register
*/
typedef union {
struct {
/** start_force : R/W; bitpos: [0]; default: 0;
* need_des
*/
uint32_t start_force:1;
/** start : R/W; bitpos: [1]; default: 0;
* need_des
*/
uint32_t start:1;
/** work_mode : R/W; bitpos: [3:2]; default: 0;
* 0: single mode, 1: double mode, 2: alternate mode
*/
uint32_t work_mode:2;
/** sar_sel : R/W; bitpos: [4]; default: 0;
* 0: SAR1, 1: SAR2, only work for single SAR mode
*/
uint32_t sar_sel:1;
/** sar_clk_gated : R/W; bitpos: [5]; default: 1;
* need_des
*/
uint32_t sar_clk_gated:1;
/** sar_clk_div : R/W; bitpos: [13:6]; default: 4;
* SAR clock divider
*/
uint32_t sar_clk_div:8;
/** sar1_patt_len : R/W; bitpos: [17:14]; default: 15;
* 0 ~ 15 means length 1 ~ 16
*/
uint32_t sar1_patt_len:4;
/** sar2_patt_len : R/W; bitpos: [21:18]; default: 15;
* 0 ~ 15 means length 1 ~ 16
*/
uint32_t sar2_patt_len:4;
/** sar1_patt_p_clear : R/W; bitpos: [22]; default: 0;
* clear the pointer of pattern table for DIG ADC1 CTRL
*/
uint32_t sar1_patt_p_clear:1;
/** sar2_patt_p_clear : R/W; bitpos: [23]; default: 0;
* clear the pointer of pattern table for DIG ADC2 CTRL
*/
uint32_t sar2_patt_p_clear:1;
/** data_sar_sel : R/W; bitpos: [24]; default: 0;
* 1: sar_sel will be coded by the MSB of the 16-bit output data, in this case the
* resolution should not be larger than 11 bits.
*/
uint32_t data_sar_sel:1;
/** data_to_i2s : R/W; bitpos: [25]; default: 0;
* 1: I2S input data is from SAR ADC (for DMA), 0: I2S input data is from GPIO matrix
*/
uint32_t data_to_i2s:1;
/** xpd_sar1_force : R/W; bitpos: [27:26]; default: 0;
* force option to xpd sar1 blocks
*/
uint32_t xpd_sar1_force:2;
/** xpd_sar2_force : R/W; bitpos: [29:28]; default: 0;
* force option to xpd sar2 blocks
*/
uint32_t xpd_sar2_force:2;
/** wait_arb_cycle : R/W; bitpos: [31:30]; default: 1;
* wait arbit signal stable after sar_done
*/
uint32_t wait_arb_cycle:2;
};
uint32_t val;
} adc_ctrl_reg_reg_t;
/** Type of ctrl2 register
* Register
*/
typedef union {
struct {
/** meas_num_limit : R/W; bitpos: [0]; default: 0;
* need_des
*/
uint32_t meas_num_limit:1;
/** max_meas_num : R/W; bitpos: [8:1]; default: 255;
* max conversion number
*/
uint32_t max_meas_num:8;
/** sar1_inv : R/W; bitpos: [9]; default: 0;
* 1: data to DIG ADC1 CTRL is inverted, otherwise not
*/
uint32_t sar1_inv:1;
/** sar2_inv : R/W; bitpos: [10]; default: 0;
* 1: data to DIG ADC2 CTRL is inverted, otherwise not
*/
uint32_t sar2_inv:1;
/** timer_sel : R/W; bitpos: [11]; default: 0;
* 1: select saradc timer 0: i2s_ws trigger
*/
uint32_t timer_sel:1;
/** timer_target : R/W; bitpos: [23:12]; default: 10;
* to set saradc timer target
*/
uint32_t timer_target:12;
/** timer_en : R/W; bitpos: [24]; default: 0;
* to enable saradc timer trigger
*/
uint32_t timer_en:1;
uint32_t reserved_25:7;
};
uint32_t val;
} adc_ctrl2_reg_t;
/** Type of filter_ctrl1 register
* Register
*/
typedef union {
struct {
uint32_t reserved_0:26;
/** filter_factor1 : R/W; bitpos: [28:26]; default: 0;
* need_des
*/
uint32_t filter_factor1:3;
/** filter_factor0 : R/W; bitpos: [31:29]; default: 0;
* need_des
*/
uint32_t filter_factor0:3;
};
uint32_t val;
} adc_filter_ctrl1_reg_t;
/** Type of sar1_patt_tab1 register
* Register
*/
typedef union {
struct {
/** sar1_patt_tab1 : R/W; bitpos: [23:0]; default: 0;
* item 0 ~ 3 for pattern table 1 (each item one byte)
*/
uint32_t sar1_patt_tab1:24;
uint32_t reserved_24:8;
};
uint32_t val;
} adc_sar1_patt_tab1_reg_t;
/** Type of sar1_patt_tab2 register
* Register
*/
typedef union {
struct {
/** sar1_patt_tab2 : R/W; bitpos: [23:0]; default: 0;
* Item 4 ~ 7 for pattern table 1 (each item one byte)
*/
uint32_t sar1_patt_tab2:24;
uint32_t reserved_24:8;
};
uint32_t val;
} adc_sar1_patt_tab2_reg_t;
/** Type of sar1_patt_tab3 register
* Register
*/
typedef union {
struct {
/** sar1_patt_tab3 : R/W; bitpos: [23:0]; default: 0;
* Item 8 ~ 11 for pattern table 1 (each item one byte)
*/
uint32_t sar1_patt_tab3:24;
uint32_t reserved_24:8;
};
uint32_t val;
} adc_sar1_patt_tab3_reg_t;
/** Type of sar1_patt_tab4 register
* Register
*/
typedef union {
struct {
/** sar1_patt_tab4 : R/W; bitpos: [23:0]; default: 0;
* Item 12 ~ 15 for pattern table 1 (each item one byte)
*/
uint32_t sar1_patt_tab4:24;
uint32_t reserved_24:8;
};
uint32_t val;
} adc_sar1_patt_tab4_reg_t;
/** Type of sar2_patt_tab1 register
* Register
*/
typedef union {
struct {
/** sar2_patt_tab1 : R/W; bitpos: [23:0]; default: 0;
* item 0 ~ 3 for pattern table 2 (each item one byte)
*/
uint32_t sar2_patt_tab1:24;
uint32_t reserved_24:8;
};
uint32_t val;
} adc_sar2_patt_tab1_reg_t;
/** Type of sar2_patt_tab2 register
* Register
*/
typedef union {
struct {
/** sar2_patt_tab2 : R/W; bitpos: [23:0]; default: 0;
* Item 4 ~ 7 for pattern table 2 (each item one byte)
*/
uint32_t sar2_patt_tab2:24;
uint32_t reserved_24:8;
};
uint32_t val;
} adc_sar2_patt_tab2_reg_t;
/** Type of sar2_patt_tab3 register
* Register
*/
typedef union {
struct {
/** sar2_patt_tab3 : R/W; bitpos: [23:0]; default: 0;
* Item 8 ~ 11 for pattern table 2 (each item one byte)
*/
uint32_t sar2_patt_tab3:24;
uint32_t reserved_24:8;
};
uint32_t val;
} adc_sar2_patt_tab3_reg_t;
/** Type of sar2_patt_tab4 register
* Register
*/
typedef union {
struct {
/** sar2_patt_tab4 : R/W; bitpos: [23:0]; default: 0;
* Item 12 ~ 15 for pattern table 2 (each item one byte)
*/
uint32_t sar2_patt_tab4:24;
uint32_t reserved_24:8;
};
uint32_t val;
} adc_sar2_patt_tab4_reg_t;
/** Type of arb_ctrl register
* Register
*/
typedef union {
struct {
uint32_t reserved_0:2;
/** arb_apb_force : R/W; bitpos: [2]; default: 0;
* adc2 arbiter force to enableapb controller
*/
uint32_t arb_apb_force:1;
/** arb_rtc_force : R/W; bitpos: [3]; default: 0;
* adc2 arbiter force to enable rtc controller
*/
uint32_t arb_rtc_force:1;
/** arb_wifi_force : R/W; bitpos: [4]; default: 0;
* adc2 arbiter force to enable wifi controller
*/
uint32_t arb_wifi_force:1;
/** arb_grant_force : R/W; bitpos: [5]; default: 0;
* adc2 arbiter force grant
*/
uint32_t arb_grant_force:1;
/** arb_apb_priority : R/W; bitpos: [7:6]; default: 0;
* Set adc2 arbiterapb priority
*/
uint32_t arb_apb_priority:2;
/** arb_rtc_priority : R/W; bitpos: [9:8]; default: 1;
* Set adc2 arbiter rtc priority
*/
uint32_t arb_rtc_priority:2;
/** arb_wifi_priority : R/W; bitpos: [11:10]; default: 2;
* Set adc2 arbiter wifi priority
*/
uint32_t arb_wifi_priority:2;
/** arb_fix_priority : R/W; bitpos: [12]; default: 0;
* adc2 arbiter uses fixed priority
*/
uint32_t arb_fix_priority:1;
uint32_t reserved_13:19;
};
uint32_t val;
} adc_arb_ctrl_reg_t;
/** Type of filter_ctrl0 register
* Register
*/
typedef union {
struct {
uint32_t reserved_0:14;
/** filter_channel1 : R/W; bitpos: [18:14]; default: 13;
* need_des
*/
uint32_t filter_channel1:5;
/** filter_channel0 : R/W; bitpos: [23:19]; default: 13;
* apb_adc1_filter_factor
*/
uint32_t filter_channel0:5;
uint32_t reserved_24:7;
/** filter_reset : R/W; bitpos: [31]; default: 0;
* enable apb_adc1_filter
*/
uint32_t filter_reset:1;
};
uint32_t val;
} adc_filter_ctrl0_reg_t;
/** Type of sar1_data_status register
* Register
*/
typedef union {
struct {
/** apb_saradc1_data : RO; bitpos: [16:0]; default: 0;
* need_des
*/
uint32_t apb_saradc1_data:17;
uint32_t reserved_17:15;
};
uint32_t val;
} adc_sar1_data_status_reg_t;
/** Type of thres0_ctrl register
* Register
*/
typedef union {
struct {
/** thres0_channel : R/W; bitpos: [4:0]; default: 13;
* need_des
*/
uint32_t thres0_channel:5;
/** thres0_high : R/W; bitpos: [17:5]; default: 8191;
* saradc1's thres0 monitor thres
*/
uint32_t thres0_high:13;
/** thres0_low : R/W; bitpos: [30:18]; default: 0;
* saradc1's thres0 monitor thres
*/
uint32_t thres0_low:13;
uint32_t reserved_31:1;
};
uint32_t val;
} adc_thres0_ctrl_reg_t;
/** Type of thres1_ctrl register
* Register
*/
typedef union {
struct {
/** thres1_channel : R/W; bitpos: [4:0]; default: 13;
* need_des
*/
uint32_t thres1_channel:5;
/** thres1_high : R/W; bitpos: [17:5]; default: 8191;
* saradc1's thres0 monitor thres
*/
uint32_t thres1_high:13;
/** thres1_low : R/W; bitpos: [30:18]; default: 0;
* saradc1's thres0 monitor thres
*/
uint32_t thres1_low:13;
uint32_t reserved_31:1;
};
uint32_t val;
} adc_thres1_ctrl_reg_t;
/** Type of thres_ctrl register
* Register
*/
typedef union {
struct {
uint32_t reserved_0:27;
/** thres_all_en : R/W; bitpos: [27]; default: 0;
* need_des
*/
uint32_t thres_all_en:1;
/** thres3_en : R/W; bitpos: [28]; default: 0;
* need_des
*/
uint32_t thres3_en:1;
/** thres2_en : R/W; bitpos: [29]; default: 0;
* need_des
*/
uint32_t thres2_en:1;
/** thres1_en : R/W; bitpos: [30]; default: 0;
* need_des
*/
uint32_t thres1_en:1;
/** thres0_en : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t thres0_en:1;
};
uint32_t val;
} adc_thres_ctrl_reg_t;
/** Type of int_ena register
* Register
*/
typedef union {
struct {
uint32_t reserved_0:26;
/** thres1_low_int_ena : R/W; bitpos: [26]; default: 0;
* need_des
*/
uint32_t thres1_low_int_ena:1;
/** thres0_low_int_ena : R/W; bitpos: [27]; default: 0;
* need_des
*/
uint32_t thres0_low_int_ena:1;
/** thres1_high_int_ena : R/W; bitpos: [28]; default: 0;
* need_des
*/
uint32_t thres1_high_int_ena:1;
/** thres0_high_int_ena : R/W; bitpos: [29]; default: 0;
* need_des
*/
uint32_t thres0_high_int_ena:1;
/** sar2_done_int_ena : R/W; bitpos: [30]; default: 0;
* need_des
*/
uint32_t sar2_done_int_ena:1;
/** sar1_done_int_ena : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t sar1_done_int_ena:1;
};
uint32_t val;
} adc_int_ena_reg_t;
/** Type of int_raw register
* Register
*/
typedef union {
struct {
uint32_t reserved_0:26;
/** thres1_low_int_raw : R/WTC/SS; bitpos: [26]; default: 0;
* need_des
*/
uint32_t thres1_low_int_raw:1;
/** thres0_low_int_raw : R/WTC/SS; bitpos: [27]; default: 0;
* need_des
*/
uint32_t thres0_low_int_raw:1;
/** thres1_high_int_raw : R/WTC/SS; bitpos: [28]; default: 0;
* need_des
*/
uint32_t thres1_high_int_raw:1;
/** thres0_high_int_raw : R/WTC/SS; bitpos: [29]; default: 0;
* need_des
*/
uint32_t thres0_high_int_raw:1;
/** sar2_done_int_raw : R/WTC/SS; bitpos: [30]; default: 0;
* need_des
*/
uint32_t sar2_done_int_raw:1;
/** sar1_done_int_raw : R/WTC/SS; bitpos: [31]; default: 0;
* need_des
*/
uint32_t sar1_done_int_raw:1;
};
uint32_t val;
} adc_int_raw_reg_t;
/** Type of int_st register
* Register
*/
typedef union {
struct {
uint32_t reserved_0:26;
/** thres1_low_int_st : RO; bitpos: [26]; default: 0;
* need_des
*/
uint32_t thres1_low_int_st:1;
/** thres0_low_int_st : RO; bitpos: [27]; default: 0;
* need_des
*/
uint32_t thres0_low_int_st:1;
/** thres1_high_int_st : RO; bitpos: [28]; default: 0;
* need_des
*/
uint32_t thres1_high_int_st:1;
/** thres0_high_int_st : RO; bitpos: [29]; default: 0;
* need_des
*/
uint32_t thres0_high_int_st:1;
/** apb_saradc2_done_int_st : RO; bitpos: [30]; default: 0;
* need_des
*/
uint32_t apb_saradc2_done_int_st:1;
/** apb_saradc1_done_int_st : RO; bitpos: [31]; default: 0;
* need_des
*/
uint32_t apb_saradc1_done_int_st:1;
};
uint32_t val;
} adc_int_st_reg_t;
/** Type of int_clr register
* Register
*/
typedef union {
struct {
uint32_t reserved_0:26;
/** thres1_low_int_clr : WT; bitpos: [26]; default: 0;
* need_des
*/
uint32_t thres1_low_int_clr:1;
/** thres0_low_int_clr : WT; bitpos: [27]; default: 0;
* need_des
*/
uint32_t thres0_low_int_clr:1;
/** thres1_high_int_clr : WT; bitpos: [28]; default: 0;
* need_des
*/
uint32_t thres1_high_int_clr:1;
/** thres0_high_int_clr : WT; bitpos: [29]; default: 0;
* need_des
*/
uint32_t thres0_high_int_clr:1;
/** apb_saradc2_done_int_clr : WT; bitpos: [30]; default: 0;
* need_des
*/
uint32_t apb_saradc2_done_int_clr:1;
/** apb_saradc1_done_int_clr : WT; bitpos: [31]; default: 0;
* need_des
*/
uint32_t apb_saradc1_done_int_clr:1;
};
uint32_t val;
} adc_int_clr_reg_t;
/** Type of dma_conf register
* Register
*/
typedef union {
struct {
/** apb_adc_eof_num : R/W; bitpos: [15:0]; default: 255;
* the dma_in_suc_eof gen when sample cnt = spi_eof_num
*/
uint32_t apb_adc_eof_num:16;
uint32_t reserved_16:14;
/** apb_adc_reset_fsm : R/W; bitpos: [30]; default: 0;
* reset_apb_adc_state
*/
uint32_t apb_adc_reset_fsm:1;
/** apb_adc_trans : R/W; bitpos: [31]; default: 0;
* enable apb_adc use spi_dma
*/
uint32_t apb_adc_trans:1;
};
uint32_t val;
} adc_dma_conf_reg_t;
/** Type of sar2_data_status register
* Register
*/
typedef union {
struct {
/** apb_saradc2_data : RO; bitpos: [16:0]; default: 0;
* need_des
*/
uint32_t apb_saradc2_data:17;
uint32_t reserved_17:15;
};
uint32_t val;
} adc_sar2_data_status_reg_t;
/** Type of cali register
* Register
*/
typedef union {
struct {
/** cali_cfg : R/W; bitpos: [16:0]; default: 32768;
* need_des
*/
uint32_t cali_cfg:17;
uint32_t reserved_17:15;
};
uint32_t val;
} adc_cali_reg_t;
/** Type of rnd_eco_low register
* Register
*/
typedef union {
struct {
/** rnd_eco_low : R/W; bitpos: [31:0]; default: 0;
* rnd eco low
*/
uint32_t rnd_eco_low:32;
};
uint32_t val;
} adc_rnd_eco_low_reg_t;
/** Type of rnd_eco_high register
* Register
*/
typedef union {
struct {
/** rnd_eco_high : R/W; bitpos: [31:0]; default: 4294967295;
* rnd eco high
*/
uint32_t rnd_eco_high:32;
};
uint32_t val;
} adc_rnd_eco_high_reg_t;
/** Type of rnd_eco_cs register
* Register
*/
typedef union {
struct {
/** rnd_eco_en : R/W; bitpos: [0]; default: 0;
* need_des
*/
uint32_t rnd_eco_en:1;
/** rnd_eco_result : RO; bitpos: [1]; default: 0;
* need_des
*/
uint32_t rnd_eco_result:1;
uint32_t reserved_2:30;
};
uint32_t val;
} adc_rnd_eco_cs_reg_t;
/** Type of ctrl_date register
* Register
*/
typedef union {
struct {
/** ctrl_date : R/W; bitpos: [30:0]; default: 35725920;
* need_des
*/
uint32_t ctrl_date:31;
/** clk_en : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t clk_en:1;
};
uint32_t val;
} adc_ctrl_date_reg_t;
typedef struct {
volatile adc_ctrl_reg_reg_t ctrl_reg;
volatile adc_ctrl2_reg_t ctrl2;
volatile adc_filter_ctrl1_reg_t filter_ctrl1;
uint32_t reserved_00c[3];
volatile adc_sar1_patt_tab1_reg_t sar1_patt_tab1;
volatile adc_sar1_patt_tab2_reg_t sar1_patt_tab2;
volatile adc_sar1_patt_tab3_reg_t sar1_patt_tab3;
volatile adc_sar1_patt_tab4_reg_t sar1_patt_tab4;
volatile adc_sar2_patt_tab1_reg_t sar2_patt_tab1;
volatile adc_sar2_patt_tab2_reg_t sar2_patt_tab2;
volatile adc_sar2_patt_tab3_reg_t sar2_patt_tab3;
volatile adc_sar2_patt_tab4_reg_t sar2_patt_tab4;
volatile adc_arb_ctrl_reg_t arb_ctrl;
volatile adc_filter_ctrl0_reg_t filter_ctrl0;
volatile adc_sar1_data_status_reg_t sar1_data_status;
volatile adc_thres0_ctrl_reg_t thres0_ctrl;
volatile adc_thres1_ctrl_reg_t thres1_ctrl;
volatile adc_thres_ctrl_reg_t thres_ctrl;
volatile adc_int_ena_reg_t int_ena;
volatile adc_int_raw_reg_t int_raw;
volatile adc_int_st_reg_t int_st;
volatile adc_int_clr_reg_t int_clr;
volatile adc_dma_conf_reg_t dma_conf;
volatile adc_sar2_data_status_reg_t sar2_data_status;
volatile adc_cali_reg_t cali;
volatile adc_rnd_eco_low_reg_t rnd_eco_low;
volatile adc_rnd_eco_high_reg_t rnd_eco_high;
volatile adc_rnd_eco_cs_reg_t rnd_eco_cs;
uint32_t reserved_078[225];
volatile adc_ctrl_date_reg_t ctrl_date;
} adc_dev_t;
#ifndef __cplusplus
_Static_assert(sizeof(adc_dev_t) == 0x400, "Invalid size of adc_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

368
components/soc/esp32p4/include/soc/aes_reg.h Normal file
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@@ -0,0 +1,368 @@
/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** AES_KEY_0_REG register
* Key material key_0 configure register
*/
#define AES_KEY_0_REG (DR_REG_AES_BASE + 0x0)
/** AES_KEY_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_0 that is a part of key material.
*/
#define AES_KEY_0 0xFFFFFFFFU
#define AES_KEY_0_M (AES_KEY_0_V << AES_KEY_0_S)
#define AES_KEY_0_V 0xFFFFFFFFU
#define AES_KEY_0_S 0
/** AES_KEY_1_REG register
* Key material key_1 configure register
*/
#define AES_KEY_1_REG (DR_REG_AES_BASE + 0x4)
/** AES_KEY_1 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_1 that is a part of key material.
*/
#define AES_KEY_1 0xFFFFFFFFU
#define AES_KEY_1_M (AES_KEY_1_V << AES_KEY_1_S)
#define AES_KEY_1_V 0xFFFFFFFFU
#define AES_KEY_1_S 0
/** AES_KEY_2_REG register
* Key material key_2 configure register
*/
#define AES_KEY_2_REG (DR_REG_AES_BASE + 0x8)
/** AES_KEY_2 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_2 that is a part of key material.
*/
#define AES_KEY_2 0xFFFFFFFFU
#define AES_KEY_2_M (AES_KEY_2_V << AES_KEY_2_S)
#define AES_KEY_2_V 0xFFFFFFFFU
#define AES_KEY_2_S 0
/** AES_KEY_3_REG register
* Key material key_3 configure register
*/
#define AES_KEY_3_REG (DR_REG_AES_BASE + 0xc)
/** AES_KEY_3 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_3 that is a part of key material.
*/
#define AES_KEY_3 0xFFFFFFFFU
#define AES_KEY_3_M (AES_KEY_3_V << AES_KEY_3_S)
#define AES_KEY_3_V 0xFFFFFFFFU
#define AES_KEY_3_S 0
/** AES_KEY_4_REG register
* Key material key_4 configure register
*/
#define AES_KEY_4_REG (DR_REG_AES_BASE + 0x10)
/** AES_KEY_4 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_4 that is a part of key material.
*/
#define AES_KEY_4 0xFFFFFFFFU
#define AES_KEY_4_M (AES_KEY_4_V << AES_KEY_4_S)
#define AES_KEY_4_V 0xFFFFFFFFU
#define AES_KEY_4_S 0
/** AES_KEY_5_REG register
* Key material key_5 configure register
*/
#define AES_KEY_5_REG (DR_REG_AES_BASE + 0x14)
/** AES_KEY_5 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_5 that is a part of key material.
*/
#define AES_KEY_5 0xFFFFFFFFU
#define AES_KEY_5_M (AES_KEY_5_V << AES_KEY_5_S)
#define AES_KEY_5_V 0xFFFFFFFFU
#define AES_KEY_5_S 0
/** AES_KEY_6_REG register
* Key material key_6 configure register
*/
#define AES_KEY_6_REG (DR_REG_AES_BASE + 0x18)
/** AES_KEY_6 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_6 that is a part of key material.
*/
#define AES_KEY_6 0xFFFFFFFFU
#define AES_KEY_6_M (AES_KEY_6_V << AES_KEY_6_S)
#define AES_KEY_6_V 0xFFFFFFFFU
#define AES_KEY_6_S 0
/** AES_KEY_7_REG register
* Key material key_7 configure register
*/
#define AES_KEY_7_REG (DR_REG_AES_BASE + 0x1c)
/** AES_KEY_7 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_7 that is a part of key material.
*/
#define AES_KEY_7 0xFFFFFFFFU
#define AES_KEY_7_M (AES_KEY_7_V << AES_KEY_7_S)
#define AES_KEY_7_V 0xFFFFFFFFU
#define AES_KEY_7_S 0
/** AES_TEXT_IN_0_REG register
* source text material text_in_0 configure register
*/
#define AES_TEXT_IN_0_REG (DR_REG_AES_BASE + 0x20)
/** AES_TEXT_IN_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_in_0 that is a part of source text material.
*/
#define AES_TEXT_IN_0 0xFFFFFFFFU
#define AES_TEXT_IN_0_M (AES_TEXT_IN_0_V << AES_TEXT_IN_0_S)
#define AES_TEXT_IN_0_V 0xFFFFFFFFU
#define AES_TEXT_IN_0_S 0
/** AES_TEXT_IN_1_REG register
* source text material text_in_1 configure register
*/
#define AES_TEXT_IN_1_REG (DR_REG_AES_BASE + 0x24)
/** AES_TEXT_IN_1 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_in_1 that is a part of source text material.
*/
#define AES_TEXT_IN_1 0xFFFFFFFFU
#define AES_TEXT_IN_1_M (AES_TEXT_IN_1_V << AES_TEXT_IN_1_S)
#define AES_TEXT_IN_1_V 0xFFFFFFFFU
#define AES_TEXT_IN_1_S 0
/** AES_TEXT_IN_2_REG register
* source text material text_in_2 configure register
*/
#define AES_TEXT_IN_2_REG (DR_REG_AES_BASE + 0x28)
/** AES_TEXT_IN_2 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_in_2 that is a part of source text material.
*/
#define AES_TEXT_IN_2 0xFFFFFFFFU
#define AES_TEXT_IN_2_M (AES_TEXT_IN_2_V << AES_TEXT_IN_2_S)
#define AES_TEXT_IN_2_V 0xFFFFFFFFU
#define AES_TEXT_IN_2_S 0
/** AES_TEXT_IN_3_REG register
* source text material text_in_3 configure register
*/
#define AES_TEXT_IN_3_REG (DR_REG_AES_BASE + 0x2c)
/** AES_TEXT_IN_3 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_in_3 that is a part of source text material.
*/
#define AES_TEXT_IN_3 0xFFFFFFFFU
#define AES_TEXT_IN_3_M (AES_TEXT_IN_3_V << AES_TEXT_IN_3_S)
#define AES_TEXT_IN_3_V 0xFFFFFFFFU
#define AES_TEXT_IN_3_S 0
/** AES_TEXT_OUT_0_REG register
* result text material text_out_0 configure register
*/
#define AES_TEXT_OUT_0_REG (DR_REG_AES_BASE + 0x30)
/** AES_TEXT_OUT_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_out_0 that is a part of result text material.
*/
#define AES_TEXT_OUT_0 0xFFFFFFFFU
#define AES_TEXT_OUT_0_M (AES_TEXT_OUT_0_V << AES_TEXT_OUT_0_S)
#define AES_TEXT_OUT_0_V 0xFFFFFFFFU
#define AES_TEXT_OUT_0_S 0
/** AES_TEXT_OUT_1_REG register
* result text material text_out_1 configure register
*/
#define AES_TEXT_OUT_1_REG (DR_REG_AES_BASE + 0x34)
/** AES_TEXT_OUT_1 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_out_1 that is a part of result text material.
*/
#define AES_TEXT_OUT_1 0xFFFFFFFFU
#define AES_TEXT_OUT_1_M (AES_TEXT_OUT_1_V << AES_TEXT_OUT_1_S)
#define AES_TEXT_OUT_1_V 0xFFFFFFFFU
#define AES_TEXT_OUT_1_S 0
/** AES_TEXT_OUT_2_REG register
* result text material text_out_2 configure register
*/
#define AES_TEXT_OUT_2_REG (DR_REG_AES_BASE + 0x38)
/** AES_TEXT_OUT_2 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_out_2 that is a part of result text material.
*/
#define AES_TEXT_OUT_2 0xFFFFFFFFU
#define AES_TEXT_OUT_2_M (AES_TEXT_OUT_2_V << AES_TEXT_OUT_2_S)
#define AES_TEXT_OUT_2_V 0xFFFFFFFFU
#define AES_TEXT_OUT_2_S 0
/** AES_TEXT_OUT_3_REG register
* result text material text_out_3 configure register
*/
#define AES_TEXT_OUT_3_REG (DR_REG_AES_BASE + 0x3c)
/** AES_TEXT_OUT_3 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_out_3 that is a part of result text material.
*/
#define AES_TEXT_OUT_3 0xFFFFFFFFU
#define AES_TEXT_OUT_3_M (AES_TEXT_OUT_3_V << AES_TEXT_OUT_3_S)
#define AES_TEXT_OUT_3_V 0xFFFFFFFFU
#define AES_TEXT_OUT_3_S 0
/** AES_MODE_REG register
* AES Mode register
*/
#define AES_MODE_REG (DR_REG_AES_BASE + 0x40)
/** AES_MODE : R/W; bitpos: [2:0]; default: 0;
* This bits decides which one operation mode will be used. 3'd0: AES-EN-128, 3'd1:
* AES-EN-192, 3'd2: AES-EN-256, 3'd4: AES-DE-128, 3'd5: AES-DE-192, 3'd6: AES-DE-256.
*/
#define AES_MODE 0x00000007U
#define AES_MODE_M (AES_MODE_V << AES_MODE_S)
#define AES_MODE_V 0x00000007U
#define AES_MODE_S 0
/** AES_TRIGGER_REG register
* AES trigger register
*/
#define AES_TRIGGER_REG (DR_REG_AES_BASE + 0x48)
/** AES_TRIGGER : WT; bitpos: [0]; default: 0;
* Set this bit to start AES calculation.
*/
#define AES_TRIGGER (BIT(0))
#define AES_TRIGGER_M (AES_TRIGGER_V << AES_TRIGGER_S)
#define AES_TRIGGER_V 0x00000001U
#define AES_TRIGGER_S 0
/** AES_STATE_REG register
* AES state register
*/
#define AES_STATE_REG (DR_REG_AES_BASE + 0x4c)
/** AES_STATE : RO; bitpos: [1:0]; default: 0;
* Those bits shows AES status. For typical AES, 0: idle, 1: busy. For DMA-AES, 0:
* idle, 1: busy, 2: calculation_done.
*/
#define AES_STATE 0x00000003U
#define AES_STATE_M (AES_STATE_V << AES_STATE_S)
#define AES_STATE_V 0x00000003U
#define AES_STATE_S 0
/** AES_IV_MEM register
* The memory that stores initialization vector
*/
#define AES_IV_MEM (DR_REG_AES_BASE + 0x50)
#define AES_IV_MEM_SIZE_BYTES 16
/** AES_H_MEM register
* The memory that stores GCM hash subkey
*/
#define AES_H_MEM (DR_REG_AES_BASE + 0x60)
#define AES_H_MEM_SIZE_BYTES 16
/** AES_J0_MEM register
* The memory that stores J0
*/
#define AES_J0_MEM (DR_REG_AES_BASE + 0x70)
#define AES_J0_MEM_SIZE_BYTES 16
/** AES_T0_MEM register
* The memory that stores T0
*/
#define AES_T0_MEM (DR_REG_AES_BASE + 0x80)
#define AES_T0_MEM_SIZE_BYTES 16
/** AES_DMA_ENABLE_REG register
* DMA-AES working mode register
*/
#define AES_DMA_ENABLE_REG (DR_REG_AES_BASE + 0x90)
/** AES_DMA_ENABLE : R/W; bitpos: [0]; default: 0;
* 1'b0: typical AES working mode, 1'b1: DMA-AES working mode.
*/
#define AES_DMA_ENABLE (BIT(0))
#define AES_DMA_ENABLE_M (AES_DMA_ENABLE_V << AES_DMA_ENABLE_S)
#define AES_DMA_ENABLE_V 0x00000001U
#define AES_DMA_ENABLE_S 0
/** AES_BLOCK_MODE_REG register
* AES cipher block mode register
*/
#define AES_BLOCK_MODE_REG (DR_REG_AES_BASE + 0x94)
/** AES_BLOCK_MODE : R/W; bitpos: [2:0]; default: 0;
* Those bits decides which block mode will be used. 0x0: ECB, 0x1: CBC, 0x2: OFB,
* 0x3: CTR, 0x4: CFB-8, 0x5: CFB-128, 0x6: GCM, 0x7: reserved.
*/
#define AES_BLOCK_MODE 0x00000007U
#define AES_BLOCK_MODE_M (AES_BLOCK_MODE_V << AES_BLOCK_MODE_S)
#define AES_BLOCK_MODE_V 0x00000007U
#define AES_BLOCK_MODE_S 0
/** AES_BLOCK_NUM_REG register
* AES block number register
*/
#define AES_BLOCK_NUM_REG (DR_REG_AES_BASE + 0x98)
/** AES_BLOCK_NUM : R/W; bitpos: [31:0]; default: 0;
* Those bits stores the number of Plaintext/ciphertext block.
*/
#define AES_BLOCK_NUM 0xFFFFFFFFU
#define AES_BLOCK_NUM_M (AES_BLOCK_NUM_V << AES_BLOCK_NUM_S)
#define AES_BLOCK_NUM_V 0xFFFFFFFFU
#define AES_BLOCK_NUM_S 0
/** AES_INC_SEL_REG register
* Standard incrementing function configure register
*/
#define AES_INC_SEL_REG (DR_REG_AES_BASE + 0x9c)
/** AES_INC_SEL : R/W; bitpos: [0]; default: 0;
* This bit decides the standard incrementing function. 0: INC32. 1: INC128.
*/
#define AES_INC_SEL (BIT(0))
#define AES_INC_SEL_M (AES_INC_SEL_V << AES_INC_SEL_S)
#define AES_INC_SEL_V 0x00000001U
#define AES_INC_SEL_S 0
/** AES_INT_CLEAR_REG register
* AES Interrupt clear register
*/
#define AES_INT_CLEAR_REG (DR_REG_AES_BASE + 0xac)
/** AES_INT_CLEAR : WT; bitpos: [0]; default: 0;
* Set this bit to clear the AES interrupt.
*/
#define AES_INT_CLEAR (BIT(0))
#define AES_INT_CLEAR_M (AES_INT_CLEAR_V << AES_INT_CLEAR_S)
#define AES_INT_CLEAR_V 0x00000001U
#define AES_INT_CLEAR_S 0
/** AES_INT_ENA_REG register
* AES Interrupt enable register
*/
#define AES_INT_ENA_REG (DR_REG_AES_BASE + 0xb0)
/** AES_INT_ENA : R/W; bitpos: [0]; default: 0;
* Set this bit to enable interrupt that occurs when DMA-AES calculation is done.
*/
#define AES_INT_ENA (BIT(0))
#define AES_INT_ENA_M (AES_INT_ENA_V << AES_INT_ENA_S)
#define AES_INT_ENA_V 0x00000001U
#define AES_INT_ENA_S 0
/** AES_DATE_REG register
* AES version control register
*/
#define AES_DATE_REG (DR_REG_AES_BASE + 0xb4)
/** AES_DATE : R/W; bitpos: [29:0]; default: 538513936;
* This bits stores the version information of AES.
*/
#define AES_DATE 0x3FFFFFFFU
#define AES_DATE_M (AES_DATE_V << AES_DATE_S)
#define AES_DATE_V 0x3FFFFFFFU
#define AES_DATE_S 0
/** AES_DMA_EXIT_REG register
* AES-DMA exit config
*/
#define AES_DMA_EXIT_REG (DR_REG_AES_BASE + 0xb8)
/** AES_DMA_EXIT : WT; bitpos: [0]; default: 0;
* Set this register to leave calculation done stage. Recommend to use it after
* software finishes reading DMA's output buffer.
*/
#define AES_DMA_EXIT (BIT(0))
#define AES_DMA_EXIT_M (AES_DMA_EXIT_V << AES_DMA_EXIT_S)
#define AES_DMA_EXIT_V 0x00000001U
#define AES_DMA_EXIT_S 0
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: key register */
/** Type of key_0 register
* Key material key_0 configure register
*/
typedef union {
struct {
/** key_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_0 that is a part of key material.
*/
uint32_t key_0:32;
};
uint32_t val;
} aes_key_0_reg_t;
/** Type of key_1 register
* Key material key_1 configure register
*/
typedef union {
struct {
/** key_1 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_1 that is a part of key material.
*/
uint32_t key_1:32;
};
uint32_t val;
} aes_key_1_reg_t;
/** Type of key_2 register
* Key material key_2 configure register
*/
typedef union {
struct {
/** key_2 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_2 that is a part of key material.
*/
uint32_t key_2:32;
};
uint32_t val;
} aes_key_2_reg_t;
/** Type of key_3 register
* Key material key_3 configure register
*/
typedef union {
struct {
/** key_3 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_3 that is a part of key material.
*/
uint32_t key_3:32;
};
uint32_t val;
} aes_key_3_reg_t;
/** Type of key_4 register
* Key material key_4 configure register
*/
typedef union {
struct {
/** key_4 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_4 that is a part of key material.
*/
uint32_t key_4:32;
};
uint32_t val;
} aes_key_4_reg_t;
/** Type of key_5 register
* Key material key_5 configure register
*/
typedef union {
struct {
/** key_5 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_5 that is a part of key material.
*/
uint32_t key_5:32;
};
uint32_t val;
} aes_key_5_reg_t;
/** Type of key_6 register
* Key material key_6 configure register
*/
typedef union {
struct {
/** key_6 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_6 that is a part of key material.
*/
uint32_t key_6:32;
};
uint32_t val;
} aes_key_6_reg_t;
/** Type of key_7 register
* Key material key_7 configure register
*/
typedef union {
struct {
/** key_7 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_7 that is a part of key material.
*/
uint32_t key_7:32;
};
uint32_t val;
} aes_key_7_reg_t;
/** Group: text in register */
/** Type of text_in_0 register
* source text material text_in_0 configure register
*/
typedef union {
struct {
/** text_in_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_in_0 that is a part of source text material.
*/
uint32_t text_in_0:32;
};
uint32_t val;
} aes_text_in_0_reg_t;
/** Type of text_in_1 register
* source text material text_in_1 configure register
*/
typedef union {
struct {
/** text_in_1 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_in_1 that is a part of source text material.
*/
uint32_t text_in_1:32;
};
uint32_t val;
} aes_text_in_1_reg_t;
/** Type of text_in_2 register
* source text material text_in_2 configure register
*/
typedef union {
struct {
/** text_in_2 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_in_2 that is a part of source text material.
*/
uint32_t text_in_2:32;
};
uint32_t val;
} aes_text_in_2_reg_t;
/** Type of text_in_3 register
* source text material text_in_3 configure register
*/
typedef union {
struct {
/** text_in_3 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_in_3 that is a part of source text material.
*/
uint32_t text_in_3:32;
};
uint32_t val;
} aes_text_in_3_reg_t;
/** Group: text out register */
/** Type of text_out_0 register
* result text material text_out_0 configure register
*/
typedef union {
struct {
/** text_out_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_out_0 that is a part of result text material.
*/
uint32_t text_out_0:32;
};
uint32_t val;
} aes_text_out_0_reg_t;
/** Type of text_out_1 register
* result text material text_out_1 configure register
*/
typedef union {
struct {
/** text_out_1 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_out_1 that is a part of result text material.
*/
uint32_t text_out_1:32;
};
uint32_t val;
} aes_text_out_1_reg_t;
/** Type of text_out_2 register
* result text material text_out_2 configure register
*/
typedef union {
struct {
/** text_out_2 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_out_2 that is a part of result text material.
*/
uint32_t text_out_2:32;
};
uint32_t val;
} aes_text_out_2_reg_t;
/** Type of text_out_3 register
* result text material text_out_3 configure register
*/
typedef union {
struct {
/** text_out_3 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_out_3 that is a part of result text material.
*/
uint32_t text_out_3:32;
};
uint32_t val;
} aes_text_out_3_reg_t;
/** Group: Configuration register */
/** Type of mode register
* AES Mode register
*/
typedef union {
struct {
/** mode : R/W; bitpos: [2:0]; default: 0;
* This bits decides which one operation mode will be used. 3'd0: AES-EN-128, 3'd1:
* AES-EN-192, 3'd2: AES-EN-256, 3'd4: AES-DE-128, 3'd5: AES-DE-192, 3'd6: AES-DE-256.
*/
uint32_t mode:3;
uint32_t reserved_3:29;
};
uint32_t val;
} aes_mode_reg_t;
/** Type of block_mode register
* AES cipher block mode register
*/
typedef union {
struct {
/** block_mode : R/W; bitpos: [2:0]; default: 0;
* Those bits decides which block mode will be used. 0x0: ECB, 0x1: CBC, 0x2: OFB,
* 0x3: CTR, 0x4: CFB-8, 0x5: CFB-128, 0x6: GCM, 0x7: reserved.
*/
uint32_t block_mode:3;
uint32_t reserved_3:29;
};
uint32_t val;
} aes_block_mode_reg_t;
/** Type of block_num register
* AES block number register
*/
typedef union {
struct {
/** block_num : R/W; bitpos: [31:0]; default: 0;
* Those bits stores the number of Plaintext/ciphertext block.
*/
uint32_t block_num:32;
};
uint32_t val;
} aes_block_num_reg_t;
/** Type of inc_sel register
* Standard incrementing function configure register
*/
typedef union {
struct {
/** inc_sel : R/W; bitpos: [0]; default: 0;
* This bit decides the standard incrementing function. 0: INC32. 1: INC128.
*/
uint32_t inc_sel:1;
uint32_t reserved_1:31;
};
uint32_t val;
} aes_inc_sel_reg_t;
/** Group: Control/Status register */
/** Type of trigger register
* AES trigger register
*/
typedef union {
struct {
/** trigger : WT; bitpos: [0]; default: 0;
* Set this bit to start AES calculation.
*/
uint32_t trigger:1;
uint32_t reserved_1:31;
};
uint32_t val;
} aes_trigger_reg_t;
/** Type of state register
* AES state register
*/
typedef union {
struct {
/** state : RO; bitpos: [1:0]; default: 0;
* Those bits shows AES status. For typical AES, 0: idle, 1: busy. For DMA-AES, 0:
* idle, 1: busy, 2: calculation_done.
*/
uint32_t state:2;
uint32_t reserved_2:30;
};
uint32_t val;
} aes_state_reg_t;
/** Type of dma_enable register
* DMA-AES working mode register
*/
typedef union {
struct {
/** dma_enable : R/W; bitpos: [0]; default: 0;
* 1'b0: typical AES working mode, 1'b1: DMA-AES working mode.
*/
uint32_t dma_enable:1;
uint32_t reserved_1:31;
};
uint32_t val;
} aes_dma_enable_reg_t;
/** Type of dma_exit register
* AES-DMA exit config
*/
typedef union {
struct {
/** dma_exit : WT; bitpos: [0]; default: 0;
* Set this register to leave calculation done stage. Recommend to use it after
* software finishes reading DMA's output buffer.
*/
uint32_t dma_exit:1;
uint32_t reserved_1:31;
};
uint32_t val;
} aes_dma_exit_reg_t;
/** Group: memory type */
/** Group: interrupt register */
/** Type of int_clear register
* AES Interrupt clear register
*/
typedef union {
struct {
/** int_clear : WT; bitpos: [0]; default: 0;
* Set this bit to clear the AES interrupt.
*/
uint32_t int_clear:1;
uint32_t reserved_1:31;
};
uint32_t val;
} aes_int_clear_reg_t;
/** Type of int_ena register
* AES Interrupt enable register
*/
typedef union {
struct {
/** int_ena : R/W; bitpos: [0]; default: 0;
* Set this bit to enable interrupt that occurs when DMA-AES calculation is done.
*/
uint32_t int_ena:1;
uint32_t reserved_1:31;
};
uint32_t val;
} aes_int_ena_reg_t;
/** Group: Version control register */
/** Type of date register
* AES version control register
*/
typedef union {
struct {
/** date : R/W; bitpos: [29:0]; default: 538513936;
* This bits stores the version information of AES.
*/
uint32_t date:30;
uint32_t reserved_30:2;
};
uint32_t val;
} aes_date_reg_t;
typedef struct {
volatile aes_key_0_reg_t key_0;
volatile aes_key_1_reg_t key_1;
volatile aes_key_2_reg_t key_2;
volatile aes_key_3_reg_t key_3;
volatile aes_key_4_reg_t key_4;
volatile aes_key_5_reg_t key_5;
volatile aes_key_6_reg_t key_6;
volatile aes_key_7_reg_t key_7;
volatile aes_text_in_0_reg_t text_in_0;
volatile aes_text_in_1_reg_t text_in_1;
volatile aes_text_in_2_reg_t text_in_2;
volatile aes_text_in_3_reg_t text_in_3;
volatile aes_text_out_0_reg_t text_out_0;
volatile aes_text_out_1_reg_t text_out_1;
volatile aes_text_out_2_reg_t text_out_2;
volatile aes_text_out_3_reg_t text_out_3;
volatile aes_mode_reg_t mode;
uint32_t reserved_044;
volatile aes_trigger_reg_t trigger;
volatile aes_state_reg_t state;
volatile uint32_t iv[4];
volatile uint32_t h[4];
volatile uint32_t j0[4];
volatile uint32_t t0[4];
volatile aes_dma_enable_reg_t dma_enable;
volatile aes_block_mode_reg_t block_mode;
volatile aes_block_num_reg_t block_num;
volatile aes_inc_sel_reg_t inc_sel;
uint32_t reserved_0a0[3];
volatile aes_int_clear_reg_t int_clear;
volatile aes_int_ena_reg_t int_ena;
volatile aes_date_reg_t date;
volatile aes_dma_exit_reg_t dma_exit;
} aes_dev_t;
#ifndef __cplusplus
_Static_assert(sizeof(aes_dev_t) == 0xbc, "Invalid size of aes_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** BITSCRAMBLER_TX_INST_CFG0_REG register
* Control and configuration registers
*/
#define BITSCRAMBLER_TX_INST_CFG0_REG (DR_REG_BITSCRAMBLER_BASE + 0x0)
/** BITSCRAMBLER_TX_INST_IDX : R/W; bitpos: [2:0]; default: 0;
* write this bits to specify the one of 8 instruction
*/
#define BITSCRAMBLER_TX_INST_IDX 0x00000007U
#define BITSCRAMBLER_TX_INST_IDX_M (BITSCRAMBLER_TX_INST_IDX_V << BITSCRAMBLER_TX_INST_IDX_S)
#define BITSCRAMBLER_TX_INST_IDX_V 0x00000007U
#define BITSCRAMBLER_TX_INST_IDX_S 0
/** BITSCRAMBLER_TX_INST_POS : R/W; bitpos: [6:3]; default: 0;
* write this bits to specify the bit position of 257 bit instruction which in units
* of 32 bits
*/
#define BITSCRAMBLER_TX_INST_POS 0x0000000FU
#define BITSCRAMBLER_TX_INST_POS_M (BITSCRAMBLER_TX_INST_POS_V << BITSCRAMBLER_TX_INST_POS_S)
#define BITSCRAMBLER_TX_INST_POS_V 0x0000000FU
#define BITSCRAMBLER_TX_INST_POS_S 3
/** BITSCRAMBLER_TX_INST_CFG1_REG register
* Control and configuration registers
*/
#define BITSCRAMBLER_TX_INST_CFG1_REG (DR_REG_BITSCRAMBLER_BASE + 0x4)
/** BITSCRAMBLER_TX_INST : R/W; bitpos: [31:0]; default: 4;
* write this bits to update instruction which specified by
* BITSCRAMBLER_TX_INST_CFG0_REG, Read this bits to get instruction which specified by
* BITSCRAMBLER_TX_INST_CFG0_REG
*/
#define BITSCRAMBLER_TX_INST 0xFFFFFFFFU
#define BITSCRAMBLER_TX_INST_M (BITSCRAMBLER_TX_INST_V << BITSCRAMBLER_TX_INST_S)
#define BITSCRAMBLER_TX_INST_V 0xFFFFFFFFU
#define BITSCRAMBLER_TX_INST_S 0
/** BITSCRAMBLER_RX_INST_CFG0_REG register
* Control and configuration registers
*/
#define BITSCRAMBLER_RX_INST_CFG0_REG (DR_REG_BITSCRAMBLER_BASE + 0x8)
/** BITSCRAMBLER_RX_INST_IDX : R/W; bitpos: [2:0]; default: 0;
* write this bits to specify the one of 8 instruction
*/
#define BITSCRAMBLER_RX_INST_IDX 0x00000007U
#define BITSCRAMBLER_RX_INST_IDX_M (BITSCRAMBLER_RX_INST_IDX_V << BITSCRAMBLER_RX_INST_IDX_S)
#define BITSCRAMBLER_RX_INST_IDX_V 0x00000007U
#define BITSCRAMBLER_RX_INST_IDX_S 0
/** BITSCRAMBLER_RX_INST_POS : R/W; bitpos: [6:3]; default: 0;
* write this bits to specify the bit position of 257 bit instruction which in units
* of 32 bits
*/
#define BITSCRAMBLER_RX_INST_POS 0x0000000FU
#define BITSCRAMBLER_RX_INST_POS_M (BITSCRAMBLER_RX_INST_POS_V << BITSCRAMBLER_RX_INST_POS_S)
#define BITSCRAMBLER_RX_INST_POS_V 0x0000000FU
#define BITSCRAMBLER_RX_INST_POS_S 3
/** BITSCRAMBLER_RX_INST_CFG1_REG register
* Control and configuration registers
*/
#define BITSCRAMBLER_RX_INST_CFG1_REG (DR_REG_BITSCRAMBLER_BASE + 0xc)
/** BITSCRAMBLER_RX_INST : R/W; bitpos: [31:0]; default: 12;
* write this bits to update instruction which specified by
* BITSCRAMBLER_RX_INST_CFG0_REG, Read this bits to get instruction which specified by
* BITSCRAMBLER_RX_INST_CFG0_REG
*/
#define BITSCRAMBLER_RX_INST 0xFFFFFFFFU
#define BITSCRAMBLER_RX_INST_M (BITSCRAMBLER_RX_INST_V << BITSCRAMBLER_RX_INST_S)
#define BITSCRAMBLER_RX_INST_V 0xFFFFFFFFU
#define BITSCRAMBLER_RX_INST_S 0
/** BITSCRAMBLER_TX_LUT_CFG0_REG register
* Control and configuration registers
*/
#define BITSCRAMBLER_TX_LUT_CFG0_REG (DR_REG_BITSCRAMBLER_BASE + 0x10)
/** BITSCRAMBLER_TX_LUT_IDX : R/W; bitpos: [10:0]; default: 0;
* write this bits to specify the bytes position of LUT RAM based on
* reg_bitscrambler_tx_lut_mode
*/
#define BITSCRAMBLER_TX_LUT_IDX 0x000007FFU
#define BITSCRAMBLER_TX_LUT_IDX_M (BITSCRAMBLER_TX_LUT_IDX_V << BITSCRAMBLER_TX_LUT_IDX_S)
#define BITSCRAMBLER_TX_LUT_IDX_V 0x000007FFU
#define BITSCRAMBLER_TX_LUT_IDX_S 0
/** BITSCRAMBLER_TX_LUT_MODE : R/W; bitpos: [12:11]; default: 0;
* write this bits to specify the bytes mode of LUT RAM, 0: 1 byte,1: 2bytes, 2: 4
* bytes
*/
#define BITSCRAMBLER_TX_LUT_MODE 0x00000003U
#define BITSCRAMBLER_TX_LUT_MODE_M (BITSCRAMBLER_TX_LUT_MODE_V << BITSCRAMBLER_TX_LUT_MODE_S)
#define BITSCRAMBLER_TX_LUT_MODE_V 0x00000003U
#define BITSCRAMBLER_TX_LUT_MODE_S 11
/** BITSCRAMBLER_TX_LUT_CFG1_REG register
* Control and configuration registers
*/
#define BITSCRAMBLER_TX_LUT_CFG1_REG (DR_REG_BITSCRAMBLER_BASE + 0x14)
/** BITSCRAMBLER_TX_LUT : R/W; bitpos: [31:0]; default: 20;
* write this bits to update LUT which specified by BITSCRAMBLER_TX_LUT_CFG0_REG, Read
* this bits to get LUT which specified by BITSCRAMBLER_TX_LUT_CFG0_REG
*/
#define BITSCRAMBLER_TX_LUT 0xFFFFFFFFU
#define BITSCRAMBLER_TX_LUT_M (BITSCRAMBLER_TX_LUT_V << BITSCRAMBLER_TX_LUT_S)
#define BITSCRAMBLER_TX_LUT_V 0xFFFFFFFFU
#define BITSCRAMBLER_TX_LUT_S 0
/** BITSCRAMBLER_RX_LUT_CFG0_REG register
* Control and configuration registers
*/
#define BITSCRAMBLER_RX_LUT_CFG0_REG (DR_REG_BITSCRAMBLER_BASE + 0x18)
/** BITSCRAMBLER_RX_LUT_IDX : R/W; bitpos: [10:0]; default: 0;
* write this bits to specify the bytes position of LUT RAM based on
* reg_bitscrambler_rx_lut_mode
*/
#define BITSCRAMBLER_RX_LUT_IDX 0x000007FFU
#define BITSCRAMBLER_RX_LUT_IDX_M (BITSCRAMBLER_RX_LUT_IDX_V << BITSCRAMBLER_RX_LUT_IDX_S)
#define BITSCRAMBLER_RX_LUT_IDX_V 0x000007FFU
#define BITSCRAMBLER_RX_LUT_IDX_S 0
/** BITSCRAMBLER_RX_LUT_MODE : R/W; bitpos: [12:11]; default: 0;
* write this bits to specify the bytes mode of LUT RAM, 0: 1 byte,1: 2bytes, 2: 4
* bytes
*/
#define BITSCRAMBLER_RX_LUT_MODE 0x00000003U
#define BITSCRAMBLER_RX_LUT_MODE_M (BITSCRAMBLER_RX_LUT_MODE_V << BITSCRAMBLER_RX_LUT_MODE_S)
#define BITSCRAMBLER_RX_LUT_MODE_V 0x00000003U
#define BITSCRAMBLER_RX_LUT_MODE_S 11
/** BITSCRAMBLER_RX_LUT_CFG1_REG register
* Control and configuration registers
*/
#define BITSCRAMBLER_RX_LUT_CFG1_REG (DR_REG_BITSCRAMBLER_BASE + 0x1c)
/** BITSCRAMBLER_RX_LUT : R/W; bitpos: [31:0]; default: 28;
* write this bits to update LUT which specified by BITSCRAMBLER_RX_LUT_CFG0_REG, Read
* this bits to get LUT which specified by BITSCRAMBLER_RX_LUT_CFG0_REG
*/
#define BITSCRAMBLER_RX_LUT 0xFFFFFFFFU
#define BITSCRAMBLER_RX_LUT_M (BITSCRAMBLER_RX_LUT_V << BITSCRAMBLER_RX_LUT_S)
#define BITSCRAMBLER_RX_LUT_V 0xFFFFFFFFU
#define BITSCRAMBLER_RX_LUT_S 0
/** BITSCRAMBLER_TX_TAILING_BITS_REG register
* Control and configuration registers
*/
#define BITSCRAMBLER_TX_TAILING_BITS_REG (DR_REG_BITSCRAMBLER_BASE + 0x20)
/** BITSCRAMBLER_TX_TAILING_BITS : R/W; bitpos: [15:0]; default: 0;
* write this bits to specify the extra data bit length after getting EOF
*/
#define BITSCRAMBLER_TX_TAILING_BITS 0x0000FFFFU
#define BITSCRAMBLER_TX_TAILING_BITS_M (BITSCRAMBLER_TX_TAILING_BITS_V << BITSCRAMBLER_TX_TAILING_BITS_S)
#define BITSCRAMBLER_TX_TAILING_BITS_V 0x0000FFFFU
#define BITSCRAMBLER_TX_TAILING_BITS_S 0
/** BITSCRAMBLER_RX_TAILING_BITS_REG register
* Control and configuration registers
*/
#define BITSCRAMBLER_RX_TAILING_BITS_REG (DR_REG_BITSCRAMBLER_BASE + 0x24)
/** BITSCRAMBLER_RX_TAILING_BITS : R/W; bitpos: [15:0]; default: 0;
* write this bits to specify the extra data bit length after getting EOF
*/
#define BITSCRAMBLER_RX_TAILING_BITS 0x0000FFFFU
#define BITSCRAMBLER_RX_TAILING_BITS_M (BITSCRAMBLER_RX_TAILING_BITS_V << BITSCRAMBLER_RX_TAILING_BITS_S)
#define BITSCRAMBLER_RX_TAILING_BITS_V 0x0000FFFFU
#define BITSCRAMBLER_RX_TAILING_BITS_S 0
/** BITSCRAMBLER_TX_CTRL_REG register
* Control and configuration registers
*/
#define BITSCRAMBLER_TX_CTRL_REG (DR_REG_BITSCRAMBLER_BASE + 0x28)
/** BITSCRAMBLER_TX_ENA : R/W; bitpos: [0]; default: 0;
* write this bit to enable the bitscrambler tx
*/
#define BITSCRAMBLER_TX_ENA (BIT(0))
#define BITSCRAMBLER_TX_ENA_M (BITSCRAMBLER_TX_ENA_V << BITSCRAMBLER_TX_ENA_S)
#define BITSCRAMBLER_TX_ENA_V 0x00000001U
#define BITSCRAMBLER_TX_ENA_S 0
/** BITSCRAMBLER_TX_PAUSE : R/W; bitpos: [1]; default: 0;
* write this bit to pause the bitscrambler tx core
*/
#define BITSCRAMBLER_TX_PAUSE (BIT(1))
#define BITSCRAMBLER_TX_PAUSE_M (BITSCRAMBLER_TX_PAUSE_V << BITSCRAMBLER_TX_PAUSE_S)
#define BITSCRAMBLER_TX_PAUSE_V 0x00000001U
#define BITSCRAMBLER_TX_PAUSE_S 1
/** BITSCRAMBLER_TX_HALT : R/W; bitpos: [2]; default: 1;
* write this bit to halt the bitscrambler tx core
*/
#define BITSCRAMBLER_TX_HALT (BIT(2))
#define BITSCRAMBLER_TX_HALT_M (BITSCRAMBLER_TX_HALT_V << BITSCRAMBLER_TX_HALT_S)
#define BITSCRAMBLER_TX_HALT_V 0x00000001U
#define BITSCRAMBLER_TX_HALT_S 2
/** BITSCRAMBLER_TX_EOF_MODE : R/W; bitpos: [3]; default: 0;
* write this bit to ser the bitscrambler tx core EOF signal generating mode which is
* combined with reg_bitscrambler_tx_tailing_bits, 0: counter by read dma fifo, 0
* counter by write peripheral buffer
*/
#define BITSCRAMBLER_TX_EOF_MODE (BIT(3))
#define BITSCRAMBLER_TX_EOF_MODE_M (BITSCRAMBLER_TX_EOF_MODE_V << BITSCRAMBLER_TX_EOF_MODE_S)
#define BITSCRAMBLER_TX_EOF_MODE_V 0x00000001U
#define BITSCRAMBLER_TX_EOF_MODE_S 3
/** BITSCRAMBLER_TX_COND_MODE : R/W; bitpos: [4]; default: 0;
* write this bit to specify the LOOP instruction condition mode of bitscrambler tx
* core, 0: use the little than operator to get the condition, 1: use not equal
* operator to get the condition
*/
#define BITSCRAMBLER_TX_COND_MODE (BIT(4))
#define BITSCRAMBLER_TX_COND_MODE_M (BITSCRAMBLER_TX_COND_MODE_V << BITSCRAMBLER_TX_COND_MODE_S)
#define BITSCRAMBLER_TX_COND_MODE_V 0x00000001U
#define BITSCRAMBLER_TX_COND_MODE_S 4
/** BITSCRAMBLER_TX_FETCH_MODE : R/W; bitpos: [5]; default: 0;
* write this bit to set the bitscrambler tx core fetch instruction mode, 0: prefetch
* by reset, 1: fetch by instrutions
*/
#define BITSCRAMBLER_TX_FETCH_MODE (BIT(5))
#define BITSCRAMBLER_TX_FETCH_MODE_M (BITSCRAMBLER_TX_FETCH_MODE_V << BITSCRAMBLER_TX_FETCH_MODE_S)
#define BITSCRAMBLER_TX_FETCH_MODE_V 0x00000001U
#define BITSCRAMBLER_TX_FETCH_MODE_S 5
/** BITSCRAMBLER_TX_HALT_MODE : R/W; bitpos: [6]; default: 0;
* write this bit to set the bitscrambler tx core halt mode when tx_halt is set, 0:
* wait write data back done, , 1: ignore write data back
*/
#define BITSCRAMBLER_TX_HALT_MODE (BIT(6))
#define BITSCRAMBLER_TX_HALT_MODE_M (BITSCRAMBLER_TX_HALT_MODE_V << BITSCRAMBLER_TX_HALT_MODE_S)
#define BITSCRAMBLER_TX_HALT_MODE_V 0x00000001U
#define BITSCRAMBLER_TX_HALT_MODE_S 6
/** BITSCRAMBLER_TX_RD_DUMMY : R/W; bitpos: [7]; default: 0;
* write this bit to set the bitscrambler tx core read data mode when EOF received.0:
* wait read data, 1: ignore read data
*/
#define BITSCRAMBLER_TX_RD_DUMMY (BIT(7))
#define BITSCRAMBLER_TX_RD_DUMMY_M (BITSCRAMBLER_TX_RD_DUMMY_V << BITSCRAMBLER_TX_RD_DUMMY_S)
#define BITSCRAMBLER_TX_RD_DUMMY_V 0x00000001U
#define BITSCRAMBLER_TX_RD_DUMMY_S 7
/** BITSCRAMBLER_TX_FIFO_RST : WT; bitpos: [8]; default: 0;
* write this bit to reset the bitscrambler tx fifo
*/
#define BITSCRAMBLER_TX_FIFO_RST (BIT(8))
#define BITSCRAMBLER_TX_FIFO_RST_M (BITSCRAMBLER_TX_FIFO_RST_V << BITSCRAMBLER_TX_FIFO_RST_S)
#define BITSCRAMBLER_TX_FIFO_RST_V 0x00000001U
#define BITSCRAMBLER_TX_FIFO_RST_S 8
/** BITSCRAMBLER_RX_CTRL_REG register
* Control and configuration registers
*/
#define BITSCRAMBLER_RX_CTRL_REG (DR_REG_BITSCRAMBLER_BASE + 0x2c)
/** BITSCRAMBLER_RX_ENA : R/W; bitpos: [0]; default: 0;
* write this bit to enable the bitscrambler rx
*/
#define BITSCRAMBLER_RX_ENA (BIT(0))
#define BITSCRAMBLER_RX_ENA_M (BITSCRAMBLER_RX_ENA_V << BITSCRAMBLER_RX_ENA_S)
#define BITSCRAMBLER_RX_ENA_V 0x00000001U
#define BITSCRAMBLER_RX_ENA_S 0
/** BITSCRAMBLER_RX_PAUSE : R/W; bitpos: [1]; default: 0;
* write this bit to pause the bitscrambler rx core
*/
#define BITSCRAMBLER_RX_PAUSE (BIT(1))
#define BITSCRAMBLER_RX_PAUSE_M (BITSCRAMBLER_RX_PAUSE_V << BITSCRAMBLER_RX_PAUSE_S)
#define BITSCRAMBLER_RX_PAUSE_V 0x00000001U
#define BITSCRAMBLER_RX_PAUSE_S 1
/** BITSCRAMBLER_RX_HALT : R/W; bitpos: [2]; default: 1;
* write this bit to halt the bitscrambler rx core
*/
#define BITSCRAMBLER_RX_HALT (BIT(2))
#define BITSCRAMBLER_RX_HALT_M (BITSCRAMBLER_RX_HALT_V << BITSCRAMBLER_RX_HALT_S)
#define BITSCRAMBLER_RX_HALT_V 0x00000001U
#define BITSCRAMBLER_RX_HALT_S 2
/** BITSCRAMBLER_RX_EOF_MODE : R/W; bitpos: [3]; default: 0;
* write this bit to ser the bitscrambler rx core EOF signal generating mode which is
* combined with reg_bitscrambler_rx_tailing_bits, 0: counter by read peripheral
* buffer, 0 counter by write dma fifo
*/
#define BITSCRAMBLER_RX_EOF_MODE (BIT(3))
#define BITSCRAMBLER_RX_EOF_MODE_M (BITSCRAMBLER_RX_EOF_MODE_V << BITSCRAMBLER_RX_EOF_MODE_S)
#define BITSCRAMBLER_RX_EOF_MODE_V 0x00000001U
#define BITSCRAMBLER_RX_EOF_MODE_S 3
/** BITSCRAMBLER_RX_COND_MODE : R/W; bitpos: [4]; default: 0;
* write this bit to specify the LOOP instruction condition mode of bitscrambler rx
* core, 0: use the little than operator to get the condition, 1: use not equal
* operator to get the condition
*/
#define BITSCRAMBLER_RX_COND_MODE (BIT(4))
#define BITSCRAMBLER_RX_COND_MODE_M (BITSCRAMBLER_RX_COND_MODE_V << BITSCRAMBLER_RX_COND_MODE_S)
#define BITSCRAMBLER_RX_COND_MODE_V 0x00000001U
#define BITSCRAMBLER_RX_COND_MODE_S 4
/** BITSCRAMBLER_RX_FETCH_MODE : R/W; bitpos: [5]; default: 0;
* write this bit to set the bitscrambler rx core fetch instruction mode, 0: prefetch
* by reset, 1: fetch by instrutions
*/
#define BITSCRAMBLER_RX_FETCH_MODE (BIT(5))
#define BITSCRAMBLER_RX_FETCH_MODE_M (BITSCRAMBLER_RX_FETCH_MODE_V << BITSCRAMBLER_RX_FETCH_MODE_S)
#define BITSCRAMBLER_RX_FETCH_MODE_V 0x00000001U
#define BITSCRAMBLER_RX_FETCH_MODE_S 5
/** BITSCRAMBLER_RX_HALT_MODE : R/W; bitpos: [6]; default: 0;
* write this bit to set the bitscrambler rx core halt mode when rx_halt is set, 0:
* wait write data back done, , 1: ignore write data back
*/
#define BITSCRAMBLER_RX_HALT_MODE (BIT(6))
#define BITSCRAMBLER_RX_HALT_MODE_M (BITSCRAMBLER_RX_HALT_MODE_V << BITSCRAMBLER_RX_HALT_MODE_S)
#define BITSCRAMBLER_RX_HALT_MODE_V 0x00000001U
#define BITSCRAMBLER_RX_HALT_MODE_S 6
/** BITSCRAMBLER_RX_RD_DUMMY : R/W; bitpos: [7]; default: 0;
* write this bit to set the bitscrambler rx core read data mode when EOF received.0:
* wait read data, 1: ignore read data
*/
#define BITSCRAMBLER_RX_RD_DUMMY (BIT(7))
#define BITSCRAMBLER_RX_RD_DUMMY_M (BITSCRAMBLER_RX_RD_DUMMY_V << BITSCRAMBLER_RX_RD_DUMMY_S)
#define BITSCRAMBLER_RX_RD_DUMMY_V 0x00000001U
#define BITSCRAMBLER_RX_RD_DUMMY_S 7
/** BITSCRAMBLER_RX_FIFO_RST : WT; bitpos: [8]; default: 0;
* write this bit to reset the bitscrambler rx fifo
*/
#define BITSCRAMBLER_RX_FIFO_RST (BIT(8))
#define BITSCRAMBLER_RX_FIFO_RST_M (BITSCRAMBLER_RX_FIFO_RST_V << BITSCRAMBLER_RX_FIFO_RST_S)
#define BITSCRAMBLER_RX_FIFO_RST_V 0x00000001U
#define BITSCRAMBLER_RX_FIFO_RST_S 8
/** BITSCRAMBLER_TX_STATE_REG register
* Status registers
*/
#define BITSCRAMBLER_TX_STATE_REG (DR_REG_BITSCRAMBLER_BASE + 0x30)
/** BITSCRAMBLER_TX_IN_IDLE : RO; bitpos: [0]; default: 1;
* represents the bitscrambler tx core in halt mode
*/
#define BITSCRAMBLER_TX_IN_IDLE (BIT(0))
#define BITSCRAMBLER_TX_IN_IDLE_M (BITSCRAMBLER_TX_IN_IDLE_V << BITSCRAMBLER_TX_IN_IDLE_S)
#define BITSCRAMBLER_TX_IN_IDLE_V 0x00000001U
#define BITSCRAMBLER_TX_IN_IDLE_S 0
/** BITSCRAMBLER_TX_IN_RUN : RO; bitpos: [1]; default: 0;
* represents the bitscrambler tx core in run mode
*/
#define BITSCRAMBLER_TX_IN_RUN (BIT(1))
#define BITSCRAMBLER_TX_IN_RUN_M (BITSCRAMBLER_TX_IN_RUN_V << BITSCRAMBLER_TX_IN_RUN_S)
#define BITSCRAMBLER_TX_IN_RUN_V 0x00000001U
#define BITSCRAMBLER_TX_IN_RUN_S 1
/** BITSCRAMBLER_TX_IN_WAIT : RO; bitpos: [2]; default: 0;
* represents the bitscrambler tx core in wait mode to wait write back done
*/
#define BITSCRAMBLER_TX_IN_WAIT (BIT(2))
#define BITSCRAMBLER_TX_IN_WAIT_M (BITSCRAMBLER_TX_IN_WAIT_V << BITSCRAMBLER_TX_IN_WAIT_S)
#define BITSCRAMBLER_TX_IN_WAIT_V 0x00000001U
#define BITSCRAMBLER_TX_IN_WAIT_S 2
/** BITSCRAMBLER_TX_IN_PAUSE : RO; bitpos: [3]; default: 0;
* represents the bitscrambler tx core in pause mode
*/
#define BITSCRAMBLER_TX_IN_PAUSE (BIT(3))
#define BITSCRAMBLER_TX_IN_PAUSE_M (BITSCRAMBLER_TX_IN_PAUSE_V << BITSCRAMBLER_TX_IN_PAUSE_S)
#define BITSCRAMBLER_TX_IN_PAUSE_V 0x00000001U
#define BITSCRAMBLER_TX_IN_PAUSE_S 3
/** BITSCRAMBLER_TX_FIFO_EMPTY : RO; bitpos: [4]; default: 0;
* represents the bitscrambler tx fifo in empty state
*/
#define BITSCRAMBLER_TX_FIFO_EMPTY (BIT(4))
#define BITSCRAMBLER_TX_FIFO_EMPTY_M (BITSCRAMBLER_TX_FIFO_EMPTY_V << BITSCRAMBLER_TX_FIFO_EMPTY_S)
#define BITSCRAMBLER_TX_FIFO_EMPTY_V 0x00000001U
#define BITSCRAMBLER_TX_FIFO_EMPTY_S 4
/** BITSCRAMBLER_TX_EOF_GET_CNT : RO; bitpos: [29:16]; default: 0;
* represents the bytes numbers of bitscrambler tx core when get EOF
*/
#define BITSCRAMBLER_TX_EOF_GET_CNT 0x00003FFFU
#define BITSCRAMBLER_TX_EOF_GET_CNT_M (BITSCRAMBLER_TX_EOF_GET_CNT_V << BITSCRAMBLER_TX_EOF_GET_CNT_S)
#define BITSCRAMBLER_TX_EOF_GET_CNT_V 0x00003FFFU
#define BITSCRAMBLER_TX_EOF_GET_CNT_S 16
/** BITSCRAMBLER_TX_EOF_OVERLOAD : RO; bitpos: [30]; default: 0;
* represents the some EOFs will be lost for bitscrambler tx core
*/
#define BITSCRAMBLER_TX_EOF_OVERLOAD (BIT(30))
#define BITSCRAMBLER_TX_EOF_OVERLOAD_M (BITSCRAMBLER_TX_EOF_OVERLOAD_V << BITSCRAMBLER_TX_EOF_OVERLOAD_S)
#define BITSCRAMBLER_TX_EOF_OVERLOAD_V 0x00000001U
#define BITSCRAMBLER_TX_EOF_OVERLOAD_S 30
/** BITSCRAMBLER_TX_EOF_TRACE_CLR : WT; bitpos: [31]; default: 0;
* write this bit to clear reg_bitscrambler_tx_eof_overload and
* reg_bitscrambler_tx_eof_get_cnt registers
*/
#define BITSCRAMBLER_TX_EOF_TRACE_CLR (BIT(31))
#define BITSCRAMBLER_TX_EOF_TRACE_CLR_M (BITSCRAMBLER_TX_EOF_TRACE_CLR_V << BITSCRAMBLER_TX_EOF_TRACE_CLR_S)
#define BITSCRAMBLER_TX_EOF_TRACE_CLR_V 0x00000001U
#define BITSCRAMBLER_TX_EOF_TRACE_CLR_S 31
/** BITSCRAMBLER_RX_STATE_REG register
* Status registers
*/
#define BITSCRAMBLER_RX_STATE_REG (DR_REG_BITSCRAMBLER_BASE + 0x34)
/** BITSCRAMBLER_RX_IN_IDLE : RO; bitpos: [0]; default: 1;
* represents the bitscrambler rx core in halt mode
*/
#define BITSCRAMBLER_RX_IN_IDLE (BIT(0))
#define BITSCRAMBLER_RX_IN_IDLE_M (BITSCRAMBLER_RX_IN_IDLE_V << BITSCRAMBLER_RX_IN_IDLE_S)
#define BITSCRAMBLER_RX_IN_IDLE_V 0x00000001U
#define BITSCRAMBLER_RX_IN_IDLE_S 0
/** BITSCRAMBLER_RX_IN_RUN : RO; bitpos: [1]; default: 0;
* represents the bitscrambler rx core in run mode
*/
#define BITSCRAMBLER_RX_IN_RUN (BIT(1))
#define BITSCRAMBLER_RX_IN_RUN_M (BITSCRAMBLER_RX_IN_RUN_V << BITSCRAMBLER_RX_IN_RUN_S)
#define BITSCRAMBLER_RX_IN_RUN_V 0x00000001U
#define BITSCRAMBLER_RX_IN_RUN_S 1
/** BITSCRAMBLER_RX_IN_WAIT : RO; bitpos: [2]; default: 0;
* represents the bitscrambler rx core in wait mode to wait write back done
*/
#define BITSCRAMBLER_RX_IN_WAIT (BIT(2))
#define BITSCRAMBLER_RX_IN_WAIT_M (BITSCRAMBLER_RX_IN_WAIT_V << BITSCRAMBLER_RX_IN_WAIT_S)
#define BITSCRAMBLER_RX_IN_WAIT_V 0x00000001U
#define BITSCRAMBLER_RX_IN_WAIT_S 2
/** BITSCRAMBLER_RX_IN_PAUSE : RO; bitpos: [3]; default: 0;
* represents the bitscrambler rx core in pause mode
*/
#define BITSCRAMBLER_RX_IN_PAUSE (BIT(3))
#define BITSCRAMBLER_RX_IN_PAUSE_M (BITSCRAMBLER_RX_IN_PAUSE_V << BITSCRAMBLER_RX_IN_PAUSE_S)
#define BITSCRAMBLER_RX_IN_PAUSE_V 0x00000001U
#define BITSCRAMBLER_RX_IN_PAUSE_S 3
/** BITSCRAMBLER_RX_FIFO_FULL : RO; bitpos: [4]; default: 0;
* represents the bitscrambler rx fifo in full state
*/
#define BITSCRAMBLER_RX_FIFO_FULL (BIT(4))
#define BITSCRAMBLER_RX_FIFO_FULL_M (BITSCRAMBLER_RX_FIFO_FULL_V << BITSCRAMBLER_RX_FIFO_FULL_S)
#define BITSCRAMBLER_RX_FIFO_FULL_V 0x00000001U
#define BITSCRAMBLER_RX_FIFO_FULL_S 4
/** BITSCRAMBLER_RX_EOF_GET_CNT : RO; bitpos: [29:16]; default: 0;
* represents the bytes numbers of bitscrambler rx core when get EOF
*/
#define BITSCRAMBLER_RX_EOF_GET_CNT 0x00003FFFU
#define BITSCRAMBLER_RX_EOF_GET_CNT_M (BITSCRAMBLER_RX_EOF_GET_CNT_V << BITSCRAMBLER_RX_EOF_GET_CNT_S)
#define BITSCRAMBLER_RX_EOF_GET_CNT_V 0x00003FFFU
#define BITSCRAMBLER_RX_EOF_GET_CNT_S 16
/** BITSCRAMBLER_RX_EOF_OVERLOAD : RO; bitpos: [30]; default: 0;
* represents the some EOFs will be lost for bitscrambler rx core
*/
#define BITSCRAMBLER_RX_EOF_OVERLOAD (BIT(30))
#define BITSCRAMBLER_RX_EOF_OVERLOAD_M (BITSCRAMBLER_RX_EOF_OVERLOAD_V << BITSCRAMBLER_RX_EOF_OVERLOAD_S)
#define BITSCRAMBLER_RX_EOF_OVERLOAD_V 0x00000001U
#define BITSCRAMBLER_RX_EOF_OVERLOAD_S 30
/** BITSCRAMBLER_RX_EOF_TRACE_CLR : WT; bitpos: [31]; default: 0;
* write this bit to clear reg_bitscrambler_rx_eof_overload and
* reg_bitscrambler_rx_eof_get_cnt registers
*/
#define BITSCRAMBLER_RX_EOF_TRACE_CLR (BIT(31))
#define BITSCRAMBLER_RX_EOF_TRACE_CLR_M (BITSCRAMBLER_RX_EOF_TRACE_CLR_V << BITSCRAMBLER_RX_EOF_TRACE_CLR_S)
#define BITSCRAMBLER_RX_EOF_TRACE_CLR_V 0x00000001U
#define BITSCRAMBLER_RX_EOF_TRACE_CLR_S 31
/** BITSCRAMBLER_SYS_REG register
* Control and configuration registers
*/
#define BITSCRAMBLER_SYS_REG (DR_REG_BITSCRAMBLER_BASE + 0xf8)
/** BITSCRAMBLER_LOOP_MODE : R/W; bitpos: [0]; default: 0;
* write this bit to set the bitscrambler tx loop back to DMA rx
*/
#define BITSCRAMBLER_LOOP_MODE (BIT(0))
#define BITSCRAMBLER_LOOP_MODE_M (BITSCRAMBLER_LOOP_MODE_V << BITSCRAMBLER_LOOP_MODE_S)
#define BITSCRAMBLER_LOOP_MODE_V 0x00000001U
#define BITSCRAMBLER_LOOP_MODE_S 0
/** BITSCRAMBLER_CLK_EN : R/W; bitpos: [31]; default: 0;
* Reserved
*/
#define BITSCRAMBLER_CLK_EN (BIT(31))
#define BITSCRAMBLER_CLK_EN_M (BITSCRAMBLER_CLK_EN_V << BITSCRAMBLER_CLK_EN_S)
#define BITSCRAMBLER_CLK_EN_V 0x00000001U
#define BITSCRAMBLER_CLK_EN_S 31
/** BITSCRAMBLER_VERSION_REG register
* Control and configuration registers
*/
#define BITSCRAMBLER_VERSION_REG (DR_REG_BITSCRAMBLER_BASE + 0xfc)
/** BITSCRAMBLER_BITSCRAMBLER_VER : R/W; bitpos: [27:0]; default: 36713024;
* Reserved
*/
#define BITSCRAMBLER_BITSCRAMBLER_VER 0x0FFFFFFFU
#define BITSCRAMBLER_BITSCRAMBLER_VER_M (BITSCRAMBLER_BITSCRAMBLER_VER_V << BITSCRAMBLER_BITSCRAMBLER_VER_S)
#define BITSCRAMBLER_BITSCRAMBLER_VER_V 0x0FFFFFFFU
#define BITSCRAMBLER_BITSCRAMBLER_VER_S 0
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Control and configuration registers */
/** Type of tx_inst_cfg0 register
* Control and configuration registers
*/
typedef union {
struct {
/** tx_inst_idx : R/W; bitpos: [2:0]; default: 0;
* write this bits to specify the one of 8 instruction
*/
uint32_t tx_inst_idx:3;
/** tx_inst_pos : R/W; bitpos: [6:3]; default: 0;
* write this bits to specify the bit position of 257 bit instruction which in units
* of 32 bits
*/
uint32_t tx_inst_pos:4;
uint32_t reserved_7:25;
};
uint32_t val;
} bitscrambler_tx_inst_cfg0_reg_t;
/** Type of tx_inst_cfg1 register
* Control and configuration registers
*/
typedef union {
struct {
/** tx_inst : R/W; bitpos: [31:0]; default: 4;
* write this bits to update instruction which specified by
* BITSCRAMBLER_TX_INST_CFG0_REG, Read this bits to get instruction which specified by
* BITSCRAMBLER_TX_INST_CFG0_REG
*/
uint32_t tx_inst:32;
};
uint32_t val;
} bitscrambler_tx_inst_cfg1_reg_t;
/** Type of rx_inst_cfg0 register
* Control and configuration registers
*/
typedef union {
struct {
/** rx_inst_idx : R/W; bitpos: [2:0]; default: 0;
* write this bits to specify the one of 8 instruction
*/
uint32_t rx_inst_idx:3;
/** rx_inst_pos : R/W; bitpos: [6:3]; default: 0;
* write this bits to specify the bit position of 257 bit instruction which in units
* of 32 bits
*/
uint32_t rx_inst_pos:4;
uint32_t reserved_7:25;
};
uint32_t val;
} bitscrambler_rx_inst_cfg0_reg_t;
/** Type of rx_inst_cfg1 register
* Control and configuration registers
*/
typedef union {
struct {
/** rx_inst : R/W; bitpos: [31:0]; default: 12;
* write this bits to update instruction which specified by
* BITSCRAMBLER_RX_INST_CFG0_REG, Read this bits to get instruction which specified by
* BITSCRAMBLER_RX_INST_CFG0_REG
*/
uint32_t rx_inst:32;
};
uint32_t val;
} bitscrambler_rx_inst_cfg1_reg_t;
/** Type of tx_lut_cfg0 register
* Control and configuration registers
*/
typedef union {
struct {
/** tx_lut_idx : R/W; bitpos: [10:0]; default: 0;
* write this bits to specify the bytes position of LUT RAM based on
* reg_bitscrambler_tx_lut_mode
*/
uint32_t tx_lut_idx:11;
/** tx_lut_mode : R/W; bitpos: [12:11]; default: 0;
* write this bits to specify the bytes mode of LUT RAM, 0: 1 byte,1: 2bytes, 2: 4
* bytes
*/
uint32_t tx_lut_mode:2;
uint32_t reserved_13:19;
};
uint32_t val;
} bitscrambler_tx_lut_cfg0_reg_t;
/** Type of tx_lut_cfg1 register
* Control and configuration registers
*/
typedef union {
struct {
/** tx_lut : R/W; bitpos: [31:0]; default: 20;
* write this bits to update LUT which specified by BITSCRAMBLER_TX_LUT_CFG0_REG, Read
* this bits to get LUT which specified by BITSCRAMBLER_TX_LUT_CFG0_REG
*/
uint32_t tx_lut:32;
};
uint32_t val;
} bitscrambler_tx_lut_cfg1_reg_t;
/** Type of rx_lut_cfg0 register
* Control and configuration registers
*/
typedef union {
struct {
/** rx_lut_idx : R/W; bitpos: [10:0]; default: 0;
* write this bits to specify the bytes position of LUT RAM based on
* reg_bitscrambler_rx_lut_mode
*/
uint32_t rx_lut_idx:11;
/** rx_lut_mode : R/W; bitpos: [12:11]; default: 0;
* write this bits to specify the bytes mode of LUT RAM, 0: 1 byte,1: 2bytes, 2: 4
* bytes
*/
uint32_t rx_lut_mode:2;
uint32_t reserved_13:19;
};
uint32_t val;
} bitscrambler_rx_lut_cfg0_reg_t;
/** Type of rx_lut_cfg1 register
* Control and configuration registers
*/
typedef union {
struct {
/** rx_lut : R/W; bitpos: [31:0]; default: 28;
* write this bits to update LUT which specified by BITSCRAMBLER_RX_LUT_CFG0_REG, Read
* this bits to get LUT which specified by BITSCRAMBLER_RX_LUT_CFG0_REG
*/
uint32_t rx_lut:32;
};
uint32_t val;
} bitscrambler_rx_lut_cfg1_reg_t;
/** Group: Configuration registers */
/** Type of tx_tailing_bits register
* Control and configuration registers
*/
typedef union {
struct {
/** tx_tailing_bits : R/W; bitpos: [15:0]; default: 0;
* write this bits to specify the extra data bit length after getting EOF
*/
uint32_t tx_tailing_bits:16;
uint32_t reserved_16:16;
};
uint32_t val;
} bitscrambler_tx_tailing_bits_reg_t;
/** Type of rx_tailing_bits register
* Control and configuration registers
*/
typedef union {
struct {
/** rx_tailing_bits : R/W; bitpos: [15:0]; default: 0;
* write this bits to specify the extra data bit length after getting EOF
*/
uint32_t rx_tailing_bits:16;
uint32_t reserved_16:16;
};
uint32_t val;
} bitscrambler_rx_tailing_bits_reg_t;
/** Type of tx_ctrl register
* Control and configuration registers
*/
typedef union {
struct {
/** tx_ena : R/W; bitpos: [0]; default: 0;
* write this bit to enable the bitscrambler tx
*/
uint32_t tx_ena:1;
/** tx_pause : R/W; bitpos: [1]; default: 0;
* write this bit to pause the bitscrambler tx core
*/
uint32_t tx_pause:1;
/** tx_halt : R/W; bitpos: [2]; default: 1;
* write this bit to halt the bitscrambler tx core
*/
uint32_t tx_halt:1;
/** tx_eof_mode : R/W; bitpos: [3]; default: 0;
* write this bit to ser the bitscrambler tx core EOF signal generating mode which is
* combined with reg_bitscrambler_tx_tailing_bits, 0: counter by read dma fifo, 0
* counter by write peripheral buffer
*/
uint32_t tx_eof_mode:1;
/** tx_cond_mode : R/W; bitpos: [4]; default: 0;
* write this bit to specify the LOOP instruction condition mode of bitscrambler tx
* core, 0: use the little than operator to get the condition, 1: use not equal
* operator to get the condition
*/
uint32_t tx_cond_mode:1;
/** tx_fetch_mode : R/W; bitpos: [5]; default: 0;
* write this bit to set the bitscrambler tx core fetch instruction mode, 0: prefetch
* by reset, 1: fetch by instrutions
*/
uint32_t tx_fetch_mode:1;
/** tx_halt_mode : R/W; bitpos: [6]; default: 0;
* write this bit to set the bitscrambler tx core halt mode when tx_halt is set, 0:
* wait write data back done, , 1: ignore write data back
*/
uint32_t tx_halt_mode:1;
/** tx_rd_dummy : R/W; bitpos: [7]; default: 0;
* write this bit to set the bitscrambler tx core read data mode when EOF received.0:
* wait read data, 1: ignore read data
*/
uint32_t tx_rd_dummy:1;
/** tx_fifo_rst : WT; bitpos: [8]; default: 0;
* write this bit to reset the bitscrambler tx fifo
*/
uint32_t tx_fifo_rst:1;
uint32_t reserved_9:23;
};
uint32_t val;
} bitscrambler_tx_ctrl_reg_t;
/** Type of rx_ctrl register
* Control and configuration registers
*/
typedef union {
struct {
/** rx_ena : R/W; bitpos: [0]; default: 0;
* write this bit to enable the bitscrambler rx
*/
uint32_t rx_ena:1;
/** rx_pause : R/W; bitpos: [1]; default: 0;
* write this bit to pause the bitscrambler rx core
*/
uint32_t rx_pause:1;
/** rx_halt : R/W; bitpos: [2]; default: 1;
* write this bit to halt the bitscrambler rx core
*/
uint32_t rx_halt:1;
/** rx_eof_mode : R/W; bitpos: [3]; default: 0;
* write this bit to ser the bitscrambler rx core EOF signal generating mode which is
* combined with reg_bitscrambler_rx_tailing_bits, 0: counter by read peripheral
* buffer, 0 counter by write dma fifo
*/
uint32_t rx_eof_mode:1;
/** rx_cond_mode : R/W; bitpos: [4]; default: 0;
* write this bit to specify the LOOP instruction condition mode of bitscrambler rx
* core, 0: use the little than operator to get the condition, 1: use not equal
* operator to get the condition
*/
uint32_t rx_cond_mode:1;
/** rx_fetch_mode : R/W; bitpos: [5]; default: 0;
* write this bit to set the bitscrambler rx core fetch instruction mode, 0: prefetch
* by reset, 1: fetch by instrutions
*/
uint32_t rx_fetch_mode:1;
/** rx_halt_mode : R/W; bitpos: [6]; default: 0;
* write this bit to set the bitscrambler rx core halt mode when rx_halt is set, 0:
* wait write data back done, , 1: ignore write data back
*/
uint32_t rx_halt_mode:1;
/** rx_rd_dummy : R/W; bitpos: [7]; default: 0;
* write this bit to set the bitscrambler rx core read data mode when EOF received.0:
* wait read data, 1: ignore read data
*/
uint32_t rx_rd_dummy:1;
/** rx_fifo_rst : WT; bitpos: [8]; default: 0;
* write this bit to reset the bitscrambler rx fifo
*/
uint32_t rx_fifo_rst:1;
uint32_t reserved_9:23;
};
uint32_t val;
} bitscrambler_rx_ctrl_reg_t;
/** Type of sys register
* Control and configuration registers
*/
typedef union {
struct {
/** loop_mode : R/W; bitpos: [0]; default: 0;
* write this bit to set the bitscrambler tx loop back to DMA rx
*/
uint32_t loop_mode:1;
uint32_t reserved_1:30;
/** clk_en : R/W; bitpos: [31]; default: 0;
* Reserved
*/
uint32_t clk_en:1;
};
uint32_t val;
} bitscrambler_sys_reg_t;
/** Group: Status registers */
/** Type of tx_state register
* Status registers
*/
typedef union {
struct {
/** tx_in_idle : RO; bitpos: [0]; default: 1;
* represents the bitscrambler tx core in halt mode
*/
uint32_t tx_in_idle:1;
/** tx_in_run : RO; bitpos: [1]; default: 0;
* represents the bitscrambler tx core in run mode
*/
uint32_t tx_in_run:1;
/** tx_in_wait : RO; bitpos: [2]; default: 0;
* represents the bitscrambler tx core in wait mode to wait write back done
*/
uint32_t tx_in_wait:1;
/** tx_in_pause : RO; bitpos: [3]; default: 0;
* represents the bitscrambler tx core in pause mode
*/
uint32_t tx_in_pause:1;
/** tx_fifo_empty : RO; bitpos: [4]; default: 0;
* represents the bitscrambler tx fifo in empty state
*/
uint32_t tx_fifo_empty:1;
uint32_t reserved_5:11;
/** tx_eof_get_cnt : RO; bitpos: [29:16]; default: 0;
* represents the bytes numbers of bitscrambler tx core when get EOF
*/
uint32_t tx_eof_get_cnt:14;
/** tx_eof_overload : RO; bitpos: [30]; default: 0;
* represents the some EOFs will be lost for bitscrambler tx core
*/
uint32_t tx_eof_overload:1;
/** tx_eof_trace_clr : WT; bitpos: [31]; default: 0;
* write this bit to clear reg_bitscrambler_tx_eof_overload and
* reg_bitscrambler_tx_eof_get_cnt registers
*/
uint32_t tx_eof_trace_clr:1;
};
uint32_t val;
} bitscrambler_tx_state_reg_t;
/** Type of rx_state register
* Status registers
*/
typedef union {
struct {
/** rx_in_idle : RO; bitpos: [0]; default: 1;
* represents the bitscrambler rx core in halt mode
*/
uint32_t rx_in_idle:1;
/** rx_in_run : RO; bitpos: [1]; default: 0;
* represents the bitscrambler rx core in run mode
*/
uint32_t rx_in_run:1;
/** rx_in_wait : RO; bitpos: [2]; default: 0;
* represents the bitscrambler rx core in wait mode to wait write back done
*/
uint32_t rx_in_wait:1;
/** rx_in_pause : RO; bitpos: [3]; default: 0;
* represents the bitscrambler rx core in pause mode
*/
uint32_t rx_in_pause:1;
/** rx_fifo_full : RO; bitpos: [4]; default: 0;
* represents the bitscrambler rx fifo in full state
*/
uint32_t rx_fifo_full:1;
uint32_t reserved_5:11;
/** rx_eof_get_cnt : RO; bitpos: [29:16]; default: 0;
* represents the bytes numbers of bitscrambler rx core when get EOF
*/
uint32_t rx_eof_get_cnt:14;
/** rx_eof_overload : RO; bitpos: [30]; default: 0;
* represents the some EOFs will be lost for bitscrambler rx core
*/
uint32_t rx_eof_overload:1;
/** rx_eof_trace_clr : WT; bitpos: [31]; default: 0;
* write this bit to clear reg_bitscrambler_rx_eof_overload and
* reg_bitscrambler_rx_eof_get_cnt registers
*/
uint32_t rx_eof_trace_clr:1;
};
uint32_t val;
} bitscrambler_rx_state_reg_t;
/** Group: Version register */
/** Type of version register
* Control and configuration registers
*/
typedef union {
struct {
/** bitscrambler_ver : R/W; bitpos: [27:0]; default: 36713024;
* Reserved
*/
uint32_t bitscrambler_ver:28;
uint32_t reserved_28:4;
};
uint32_t val;
} bitscrambler_version_reg_t;
typedef struct {
volatile bitscrambler_tx_inst_cfg0_reg_t tx_inst_cfg0;
volatile bitscrambler_tx_inst_cfg1_reg_t tx_inst_cfg1;
volatile bitscrambler_rx_inst_cfg0_reg_t rx_inst_cfg0;
volatile bitscrambler_rx_inst_cfg1_reg_t rx_inst_cfg1;
volatile bitscrambler_tx_lut_cfg0_reg_t tx_lut_cfg0;
volatile bitscrambler_tx_lut_cfg1_reg_t tx_lut_cfg1;
volatile bitscrambler_rx_lut_cfg0_reg_t rx_lut_cfg0;
volatile bitscrambler_rx_lut_cfg1_reg_t rx_lut_cfg1;
volatile bitscrambler_tx_tailing_bits_reg_t tx_tailing_bits;
volatile bitscrambler_rx_tailing_bits_reg_t rx_tailing_bits;
volatile bitscrambler_tx_ctrl_reg_t tx_ctrl;
volatile bitscrambler_rx_ctrl_reg_t rx_ctrl;
volatile bitscrambler_tx_state_reg_t tx_state;
volatile bitscrambler_rx_state_reg_t rx_state;
uint32_t reserved_038[48];
volatile bitscrambler_sys_reg_t sys;
volatile bitscrambler_version_reg_t version;
} bitscrambler_dev_t;
#ifndef __cplusplus
_Static_assert(sizeof(bitscrambler_dev_t) == 0x100, "Invalid size of bitscrambler_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** DS_Y_MEM register
* memory that stores Y
*/
#define DS_Y_MEM (DR_REG_DS_BASE + 0x0)
#define DS_Y_MEM_SIZE_BYTES 512
/** DS_M_MEM register
* memory that stores M
*/
#define DS_M_MEM (DR_REG_DS_BASE + 0x200)
#define DS_M_MEM_SIZE_BYTES 512
/** DS_RB_MEM register
* memory that stores Rb
*/
#define DS_RB_MEM (DR_REG_DS_BASE + 0x400)
#define DS_RB_MEM_SIZE_BYTES 512
/** DS_BOX_MEM register
* memory that stores BOX
*/
#define DS_BOX_MEM (DR_REG_DS_BASE + 0x600)
#define DS_BOX_MEM_SIZE_BYTES 48
/** DS_IV_MEM register
* memory that stores IV
*/
#define DS_IV_MEM (DR_REG_DS_BASE + 0x630)
#define DS_IV_MEM_SIZE_BYTES 16
/** DS_X_MEM register
* memory that stores X
*/
#define DS_X_MEM (DR_REG_DS_BASE + 0x800)
#define DS_X_MEM_SIZE_BYTES 512
/** DS_Z_MEM register
* memory that stores Z
*/
#define DS_Z_MEM (DR_REG_DS_BASE + 0xa00)
#define DS_Z_MEM_SIZE_BYTES 512
/** DS_SET_START_REG register
* DS start control register
*/
#define DS_SET_START_REG (DR_REG_DS_BASE + 0xe00)
/** DS_SET_START : WT; bitpos: [0]; default: 0;
* set this bit to start DS operation.
*/
#define DS_SET_START (BIT(0))
#define DS_SET_START_M (DS_SET_START_V << DS_SET_START_S)
#define DS_SET_START_V 0x00000001U
#define DS_SET_START_S 0
/** DS_SET_CONTINUE_REG register
* DS continue control register
*/
#define DS_SET_CONTINUE_REG (DR_REG_DS_BASE + 0xe04)
/** DS_SET_CONTINUE : WT; bitpos: [0]; default: 0;
* set this bit to continue DS operation.
*/
#define DS_SET_CONTINUE (BIT(0))
#define DS_SET_CONTINUE_M (DS_SET_CONTINUE_V << DS_SET_CONTINUE_S)
#define DS_SET_CONTINUE_V 0x00000001U
#define DS_SET_CONTINUE_S 0
/** DS_SET_FINISH_REG register
* DS finish control register
*/
#define DS_SET_FINISH_REG (DR_REG_DS_BASE + 0xe08)
/** DS_SET_FINISH : WT; bitpos: [0]; default: 0;
* Set this bit to finish DS process.
*/
#define DS_SET_FINISH (BIT(0))
#define DS_SET_FINISH_M (DS_SET_FINISH_V << DS_SET_FINISH_S)
#define DS_SET_FINISH_V 0x00000001U
#define DS_SET_FINISH_S 0
/** DS_QUERY_BUSY_REG register
* DS query busy register
*/
#define DS_QUERY_BUSY_REG (DR_REG_DS_BASE + 0xe0c)
/** DS_QUERY_BUSY : RO; bitpos: [0]; default: 0;
* digital signature state. 1'b0: idle, 1'b1: busy
*/
#define DS_QUERY_BUSY (BIT(0))
#define DS_QUERY_BUSY_M (DS_QUERY_BUSY_V << DS_QUERY_BUSY_S)
#define DS_QUERY_BUSY_V 0x00000001U
#define DS_QUERY_BUSY_S 0
/** DS_QUERY_KEY_WRONG_REG register
* DS query key-wrong counter register
*/
#define DS_QUERY_KEY_WRONG_REG (DR_REG_DS_BASE + 0xe10)
/** DS_QUERY_KEY_WRONG : RO; bitpos: [3:0]; default: 0;
* digital signature key wrong counter
*/
#define DS_QUERY_KEY_WRONG 0x0000000FU
#define DS_QUERY_KEY_WRONG_M (DS_QUERY_KEY_WRONG_V << DS_QUERY_KEY_WRONG_S)
#define DS_QUERY_KEY_WRONG_V 0x0000000FU
#define DS_QUERY_KEY_WRONG_S 0
/** DS_QUERY_CHECK_REG register
* DS query check result register
*/
#define DS_QUERY_CHECK_REG (DR_REG_DS_BASE + 0xe14)
/** DS_MD_ERROR : RO; bitpos: [0]; default: 0;
* MD checkout result. 1'b0: MD check pass, 1'b1: MD check fail
*/
#define DS_MD_ERROR (BIT(0))
#define DS_MD_ERROR_M (DS_MD_ERROR_V << DS_MD_ERROR_S)
#define DS_MD_ERROR_V 0x00000001U
#define DS_MD_ERROR_S 0
/** DS_PADDING_BAD : RO; bitpos: [1]; default: 0;
* padding checkout result. 1'b0: a good padding, 1'b1: a bad padding
*/
#define DS_PADDING_BAD (BIT(1))
#define DS_PADDING_BAD_M (DS_PADDING_BAD_V << DS_PADDING_BAD_S)
#define DS_PADDING_BAD_V 0x00000001U
#define DS_PADDING_BAD_S 1
/** DS_DATE_REG register
* DS version control register
*/
#define DS_DATE_REG (DR_REG_DS_BASE + 0xe20)
/** DS_DATE : R/W; bitpos: [29:0]; default: 538969624;
* ds version information
*/
#define DS_DATE 0x3FFFFFFFU
#define DS_DATE_M (DS_DATE_V << DS_DATE_S)
#define DS_DATE_V 0x3FFFFFFFU
#define DS_DATE_S 0
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: memory type */
/** Group: Control/Status registers */
/** Type of set_start register
* DS start control register
*/
typedef union {
struct {
/** set_start : WT; bitpos: [0]; default: 0;
* set this bit to start DS operation.
*/
uint32_t set_start:1;
uint32_t reserved_1:31;
};
uint32_t val;
} ds_set_start_reg_t;
/** Type of set_continue register
* DS continue control register
*/
typedef union {
struct {
/** set_continue : WT; bitpos: [0]; default: 0;
* set this bit to continue DS operation.
*/
uint32_t set_continue:1;
uint32_t reserved_1:31;
};
uint32_t val;
} ds_set_continue_reg_t;
/** Type of set_finish register
* DS finish control register
*/
typedef union {
struct {
/** set_finish : WT; bitpos: [0]; default: 0;
* Set this bit to finish DS process.
*/
uint32_t set_finish:1;
uint32_t reserved_1:31;
};
uint32_t val;
} ds_set_finish_reg_t;
/** Type of query_busy register
* DS query busy register
*/
typedef union {
struct {
/** query_busy : RO; bitpos: [0]; default: 0;
* digital signature state. 1'b0: idle, 1'b1: busy
*/
uint32_t query_busy:1;
uint32_t reserved_1:31;
};
uint32_t val;
} ds_query_busy_reg_t;
/** Type of query_key_wrong register
* DS query key-wrong counter register
*/
typedef union {
struct {
/** query_key_wrong : RO; bitpos: [3:0]; default: 0;
* digital signature key wrong counter
*/
uint32_t query_key_wrong:4;
uint32_t reserved_4:28;
};
uint32_t val;
} ds_query_key_wrong_reg_t;
/** Type of query_check register
* DS query check result register
*/
typedef union {
struct {
/** md_error : RO; bitpos: [0]; default: 0;
* MD checkout result. 1'b0: MD check pass, 1'b1: MD check fail
*/
uint32_t md_error:1;
/** padding_bad : RO; bitpos: [1]; default: 0;
* padding checkout result. 1'b0: a good padding, 1'b1: a bad padding
*/
uint32_t padding_bad:1;
uint32_t reserved_2:30;
};
uint32_t val;
} ds_query_check_reg_t;
/** Group: version control register */
/** Type of date register
* DS version control register
*/
typedef union {
struct {
/** date : R/W; bitpos: [29:0]; default: 538969624;
* ds version information
*/
uint32_t date:30;
uint32_t reserved_30:2;
};
uint32_t val;
} ds_date_reg_t;
typedef struct {
volatile uint32_t y[128];
volatile uint32_t m[128];
volatile uint32_t rb[128];
volatile uint32_t box[12];
volatile uint32_t iv[4];
uint32_t reserved_640[112];
volatile uint32_t x[128];
volatile uint32_t z[128];
uint32_t reserved_c00[128];
volatile ds_set_start_reg_t set_start;
volatile ds_set_continue_reg_t set_continue;
volatile ds_set_finish_reg_t set_finish;
volatile ds_query_busy_reg_t query_busy;
volatile ds_query_key_wrong_reg_t query_key_wrong;
volatile ds_query_check_reg_t query_check;
uint32_t reserved_e18[2];
volatile ds_date_reg_t date;
} ds_dev_t;
#ifndef __cplusplus
_Static_assert(sizeof(ds_dev_t) == 0xe24, "Invalid size of ds_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** ECC_MULT_INT_RAW_REG register
* ECC interrupt raw register, valid in level.
*/
#define ECC_MULT_INT_RAW_REG (DR_REG_ECC_MULT_BASE + 0xc)
/** ECC_MULT_CALC_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
* The raw interrupt status bit for the ecc_calc_done_int interrupt
*/
#define ECC_MULT_CALC_DONE_INT_RAW (BIT(0))
#define ECC_MULT_CALC_DONE_INT_RAW_M (ECC_MULT_CALC_DONE_INT_RAW_V << ECC_MULT_CALC_DONE_INT_RAW_S)
#define ECC_MULT_CALC_DONE_INT_RAW_V 0x00000001U
#define ECC_MULT_CALC_DONE_INT_RAW_S 0
/** ECC_MULT_INT_ST_REG register
* ECC interrupt status register.
*/
#define ECC_MULT_INT_ST_REG (DR_REG_ECC_MULT_BASE + 0x10)
/** ECC_MULT_CALC_DONE_INT_ST : RO; bitpos: [0]; default: 0;
* The masked interrupt status bit for the ecc_calc_done_int interrupt
*/
#define ECC_MULT_CALC_DONE_INT_ST (BIT(0))
#define ECC_MULT_CALC_DONE_INT_ST_M (ECC_MULT_CALC_DONE_INT_ST_V << ECC_MULT_CALC_DONE_INT_ST_S)
#define ECC_MULT_CALC_DONE_INT_ST_V 0x00000001U
#define ECC_MULT_CALC_DONE_INT_ST_S 0
/** ECC_MULT_INT_ENA_REG register
* ECC interrupt enable register.
*/
#define ECC_MULT_INT_ENA_REG (DR_REG_ECC_MULT_BASE + 0x14)
/** ECC_MULT_CALC_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
* The interrupt enable bit for the ecc_calc_done_int interrupt
*/
#define ECC_MULT_CALC_DONE_INT_ENA (BIT(0))
#define ECC_MULT_CALC_DONE_INT_ENA_M (ECC_MULT_CALC_DONE_INT_ENA_V << ECC_MULT_CALC_DONE_INT_ENA_S)
#define ECC_MULT_CALC_DONE_INT_ENA_V 0x00000001U
#define ECC_MULT_CALC_DONE_INT_ENA_S 0
/** ECC_MULT_INT_CLR_REG register
* ECC interrupt clear register.
*/
#define ECC_MULT_INT_CLR_REG (DR_REG_ECC_MULT_BASE + 0x18)
/** ECC_MULT_CALC_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
* Set this bit to clear the ecc_calc_done_int interrupt
*/
#define ECC_MULT_CALC_DONE_INT_CLR (BIT(0))
#define ECC_MULT_CALC_DONE_INT_CLR_M (ECC_MULT_CALC_DONE_INT_CLR_V << ECC_MULT_CALC_DONE_INT_CLR_S)
#define ECC_MULT_CALC_DONE_INT_CLR_V 0x00000001U
#define ECC_MULT_CALC_DONE_INT_CLR_S 0
/** ECC_MULT_CONF_REG register
* ECC configure register
*/
#define ECC_MULT_CONF_REG (DR_REG_ECC_MULT_BASE + 0x1c)
/** ECC_MULT_START : R/W/SC; bitpos: [0]; default: 0;
* Write 1 to start caculation of ECC Accelerator. This bit will be self-cleared after
* the caculatrion is done.
*/
#define ECC_MULT_START (BIT(0))
#define ECC_MULT_START_M (ECC_MULT_START_V << ECC_MULT_START_S)
#define ECC_MULT_START_V 0x00000001U
#define ECC_MULT_START_S 0
/** ECC_MULT_RESET : WT; bitpos: [1]; default: 0;
* Write 1 to reset ECC Accelerator.
*/
#define ECC_MULT_RESET (BIT(1))
#define ECC_MULT_RESET_M (ECC_MULT_RESET_V << ECC_MULT_RESET_S)
#define ECC_MULT_RESET_V 0x00000001U
#define ECC_MULT_RESET_S 1
/** ECC_MULT_KEY_LENGTH : R/W; bitpos: [2]; default: 0;
* The key length mode bit of ECC Accelerator. 0: P-192. 1: P-256.
*/
#define ECC_MULT_KEY_LENGTH (BIT(2))
#define ECC_MULT_KEY_LENGTH_M (ECC_MULT_KEY_LENGTH_V << ECC_MULT_KEY_LENGTH_S)
#define ECC_MULT_KEY_LENGTH_V 0x00000001U
#define ECC_MULT_KEY_LENGTH_S 2
/** ECC_MULT_MOD_BASE : R/W; bitpos: [3]; default: 0;
* The mod base of mod operation, only valid in work_mode 8-11. 0: n(order of curve).
* 1: p(mod base of curve)
*/
#define ECC_MULT_MOD_BASE (BIT(3))
#define ECC_MULT_MOD_BASE_M (ECC_MULT_MOD_BASE_V << ECC_MULT_MOD_BASE_S)
#define ECC_MULT_MOD_BASE_V 0x00000001U
#define ECC_MULT_MOD_BASE_S 3
/** ECC_MULT_WORK_MODE : R/W; bitpos: [7:4]; default: 0;
* The work mode bits of ECC Accelerator. 0: Point Mult Mode. 1: Reserved. 2: Point
* verification mode. 3: Point Verif+mult mode. 4: Jacobian Point Mult Mode. 5: Point
* Add Mode. 6: Jacobian Point Verification Mode. 7: Point Verif + Jacobian Mult Mode.
* 8: mod addition. 9. mod substraction. 10: mod multiplication. 11: mod division.
*/
#define ECC_MULT_WORK_MODE 0x0000000FU
#define ECC_MULT_WORK_MODE_M (ECC_MULT_WORK_MODE_V << ECC_MULT_WORK_MODE_S)
#define ECC_MULT_WORK_MODE_V 0x0000000FU
#define ECC_MULT_WORK_MODE_S 4
/** ECC_MULT_SECURITY_MODE : R/W; bitpos: [8]; default: 0;
* Reserved
*/
#define ECC_MULT_SECURITY_MODE (BIT(8))
#define ECC_MULT_SECURITY_MODE_M (ECC_MULT_SECURITY_MODE_V << ECC_MULT_SECURITY_MODE_S)
#define ECC_MULT_SECURITY_MODE_V 0x00000001U
#define ECC_MULT_SECURITY_MODE_S 8
/** ECC_MULT_VERIFICATION_RESULT : RO/SS; bitpos: [29]; default: 0;
* The verification result bit of ECC Accelerator, only valid when calculation is done.
*/
#define ECC_MULT_VERIFICATION_RESULT (BIT(29))
#define ECC_MULT_VERIFICATION_RESULT_M (ECC_MULT_VERIFICATION_RESULT_V << ECC_MULT_VERIFICATION_RESULT_S)
#define ECC_MULT_VERIFICATION_RESULT_V 0x00000001U
#define ECC_MULT_VERIFICATION_RESULT_S 29
/** ECC_MULT_CLK_EN : R/W; bitpos: [30]; default: 0;
* Write 1 to force on register clock gate.
*/
#define ECC_MULT_CLK_EN (BIT(30))
#define ECC_MULT_CLK_EN_M (ECC_MULT_CLK_EN_V << ECC_MULT_CLK_EN_S)
#define ECC_MULT_CLK_EN_V 0x00000001U
#define ECC_MULT_CLK_EN_S 30
/** ECC_MULT_MEM_CLOCK_GATE_FORCE_ON : R/W; bitpos: [31]; default: 0;
* ECC memory clock gate force on register
*/
#define ECC_MULT_MEM_CLOCK_GATE_FORCE_ON (BIT(31))
#define ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_M (ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_V << ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_S)
#define ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_V 0x00000001U
#define ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_S 31
/** ECC_MULT_DATE_REG register
* Version control register
*/
#define ECC_MULT_DATE_REG (DR_REG_ECC_MULT_BASE + 0xfc)
/** ECC_MULT_DATE : R/W; bitpos: [27:0]; default: 36720704;
* ECC mult version control register
*/
#define ECC_MULT_DATE 0x0FFFFFFFU
#define ECC_MULT_DATE_M (ECC_MULT_DATE_V << ECC_MULT_DATE_S)
#define ECC_MULT_DATE_V 0x0FFFFFFFU
#define ECC_MULT_DATE_S 0
/** ECC_MULT_K_MEM register
* The memory that stores k.
*/
#define ECC_MULT_K_MEM (DR_REG_ECC_MULT_BASE + 0x100)
#define ECC_MULT_K_MEM_SIZE_BYTES 32
/** ECC_MULT_PX_MEM register
* The memory that stores Px.
*/
#define ECC_MULT_PX_MEM (DR_REG_ECC_MULT_BASE + 0x120)
#define ECC_MULT_PX_MEM_SIZE_BYTES 32
/** ECC_MULT_PY_MEM register
* The memory that stores Py.
*/
#define ECC_MULT_PY_MEM (DR_REG_ECC_MULT_BASE + 0x140)
#define ECC_MULT_PY_MEM_SIZE_BYTES 32
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Memory data */
/** Group: Interrupt registers */
/** Type of int_raw register
* ECC interrupt raw register, valid in level.
*/
typedef union {
struct {
/** calc_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0;
* The raw interrupt status bit for the ecc_calc_done_int interrupt
*/
uint32_t calc_done_int_raw:1;
uint32_t reserved_1:31;
};
uint32_t val;
} ecc_mult_int_raw_reg_t;
/** Type of int_st register
* ECC interrupt status register.
*/
typedef union {
struct {
/** calc_done_int_st : RO; bitpos: [0]; default: 0;
* The masked interrupt status bit for the ecc_calc_done_int interrupt
*/
uint32_t calc_done_int_st:1;
uint32_t reserved_1:31;
};
uint32_t val;
} ecc_mult_int_st_reg_t;
/** Type of int_ena register
* ECC interrupt enable register.
*/
typedef union {
struct {
/** calc_done_int_ena : R/W; bitpos: [0]; default: 0;
* The interrupt enable bit for the ecc_calc_done_int interrupt
*/
uint32_t calc_done_int_ena:1;
uint32_t reserved_1:31;
};
uint32_t val;
} ecc_mult_int_ena_reg_t;
/** Type of int_clr register
* ECC interrupt clear register.
*/
typedef union {
struct {
/** calc_done_int_clr : WT; bitpos: [0]; default: 0;
* Set this bit to clear the ecc_calc_done_int interrupt
*/
uint32_t calc_done_int_clr:1;
uint32_t reserved_1:31;
};
uint32_t val;
} ecc_mult_int_clr_reg_t;
/** Group: RX Control and configuration registers */
/** Type of conf register
* ECC configure register
*/
typedef union {
struct {
/** start : R/W/SC; bitpos: [0]; default: 0;
* Write 1 to start caculation of ECC Accelerator. This bit will be self-cleared after
* the caculatrion is done.
*/
uint32_t start:1;
/** reset : WT; bitpos: [1]; default: 0;
* Write 1 to reset ECC Accelerator.
*/
uint32_t reset:1;
/** key_length : R/W; bitpos: [2]; default: 0;
* The key length mode bit of ECC Accelerator. 0: P-192. 1: P-256.
*/
uint32_t key_length:1;
/** mod_base : R/W; bitpos: [3]; default: 0;
* The mod base of mod operation, only valid in work_mode 8-11. 0: n(order of curve).
* 1: p(mod base of curve)
*/
uint32_t mod_base:1;
/** work_mode : R/W; bitpos: [7:4]; default: 0;
* The work mode bits of ECC Accelerator. 0: Point Mult Mode. 1: Reserved. 2: Point
* verification mode. 3: Point Verif+mult mode. 4: Jacobian Point Mult Mode. 5: Point
* Add Mode. 6: Jacobian Point Verification Mode. 7: Point Verif + Jacobian Mult Mode.
* 8: mod addition. 9. mod substraction. 10: mod multiplication. 11: mod division.
*/
uint32_t work_mode:4;
/** security_mode : R/W; bitpos: [8]; default: 0;
* Reserved
*/
uint32_t security_mode:1;
uint32_t reserved_9:20;
/** verification_result : RO/SS; bitpos: [29]; default: 0;
* The verification result bit of ECC Accelerator, only valid when calculation is done.
*/
uint32_t verification_result:1;
/** clk_en : R/W; bitpos: [30]; default: 0;
* Write 1 to force on register clock gate.
*/
uint32_t clk_en:1;
/** mem_clock_gate_force_on : R/W; bitpos: [31]; default: 0;
* ECC memory clock gate force on register
*/
uint32_t mem_clock_gate_force_on:1;
};
uint32_t val;
} ecc_mult_conf_reg_t;
/** Group: Version register */
/** Type of date register
* Version control register
*/
typedef union {
struct {
/** date : R/W; bitpos: [27:0]; default: 36720704;
* ECC mult version control register
*/
uint32_t date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} ecc_mult_date_reg_t;
typedef struct {
uint32_t reserved_000[3];
volatile ecc_mult_int_raw_reg_t int_raw;
volatile ecc_mult_int_st_reg_t int_st;
volatile ecc_mult_int_ena_reg_t int_ena;
volatile ecc_mult_int_clr_reg_t int_clr;
volatile ecc_mult_conf_reg_t conf;
uint32_t reserved_020[55];
volatile ecc_mult_date_reg_t date;
volatile uint32_t k[8];
volatile uint32_t px[8];
volatile uint32_t py[8];
} ecc_mult_dev_t;
#ifndef __cplusplus
_Static_assert(sizeof(ecc_mult_dev_t) == 0x160, "Invalid size of ecc_mult_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** ECDSA_CONF_REG register
* ECDSA configure register
*/
#define ECDSA_CONF_REG (DR_REG_ECDSA_BASE + 0x4)
/** ECDSA_WORK_MODE : R/W; bitpos: [1:0]; default: 0;
* The work mode bits of ECDSA Accelerator. 0: Signature Verify Mode. 1: Signature
* Generate Mode. 2: Export Public Key Mode. 3: invalid.
*/
#define ECDSA_WORK_MODE 0x00000003U
#define ECDSA_WORK_MODE_M (ECDSA_WORK_MODE_V << ECDSA_WORK_MODE_S)
#define ECDSA_WORK_MODE_V 0x00000003U
#define ECDSA_WORK_MODE_S 0
/** ECDSA_ECC_CURVE : R/W; bitpos: [2]; default: 0;
* The ecc curve select bit of ECDSA Accelerator. 0: P-192. 1: P-256.
*/
#define ECDSA_ECC_CURVE (BIT(2))
#define ECDSA_ECC_CURVE_M (ECDSA_ECC_CURVE_V << ECDSA_ECC_CURVE_S)
#define ECDSA_ECC_CURVE_V 0x00000001U
#define ECDSA_ECC_CURVE_S 2
/** ECDSA_SOFTWARE_SET_K : R/W; bitpos: [3]; default: 0;
* The source of k select bit. 0: k is automatically generated by hardware. 1: k is
* written by software.
*/
#define ECDSA_SOFTWARE_SET_K (BIT(3))
#define ECDSA_SOFTWARE_SET_K_M (ECDSA_SOFTWARE_SET_K_V << ECDSA_SOFTWARE_SET_K_S)
#define ECDSA_SOFTWARE_SET_K_V 0x00000001U
#define ECDSA_SOFTWARE_SET_K_S 3
/** ECDSA_SOFTWARE_SET_Z : R/W; bitpos: [4]; default: 0;
* The source of z select bit. 0: z is generated from SHA result. 1: z is written by
* software.
*/
#define ECDSA_SOFTWARE_SET_Z (BIT(4))
#define ECDSA_SOFTWARE_SET_Z_M (ECDSA_SOFTWARE_SET_Z_V << ECDSA_SOFTWARE_SET_Z_S)
#define ECDSA_SOFTWARE_SET_Z_V 0x00000001U
#define ECDSA_SOFTWARE_SET_Z_S 4
/** ECDSA_DETERMINISTIC_K : R/W; bitpos: [5]; default: 0;
* The source of hardware generated k. 0: k is generated by TRNG. 1: k is generated by
* deterministic derivation algorithm.
*/
#define ECDSA_DETERMINISTIC_K (BIT(5))
#define ECDSA_DETERMINISTIC_K_M (ECDSA_DETERMINISTIC_K_V << ECDSA_DETERMINISTIC_K_S)
#define ECDSA_DETERMINISTIC_K_V 0x00000001U
#define ECDSA_DETERMINISTIC_K_S 5
/** ECDSA_DETERMINISTIC_LOOP : R/W; bitpos: [21:6]; default: 0;
* The (loop number - 1) value in the deterministic derivation algorithm to derive k.
*/
#define ECDSA_DETERMINISTIC_LOOP 0x0000FFFFU
#define ECDSA_DETERMINISTIC_LOOP_M (ECDSA_DETERMINISTIC_LOOP_V << ECDSA_DETERMINISTIC_LOOP_S)
#define ECDSA_DETERMINISTIC_LOOP_V 0x0000FFFFU
#define ECDSA_DETERMINISTIC_LOOP_S 6
/** ECDSA_CLK_REG register
* ECDSA clock gate register
*/
#define ECDSA_CLK_REG (DR_REG_ECDSA_BASE + 0x8)
/** ECDSA_CLK_GATE_FORCE_ON : R/W; bitpos: [0]; default: 0;
* Write 1 to force on register clock gate.
*/
#define ECDSA_CLK_GATE_FORCE_ON (BIT(0))
#define ECDSA_CLK_GATE_FORCE_ON_M (ECDSA_CLK_GATE_FORCE_ON_V << ECDSA_CLK_GATE_FORCE_ON_S)
#define ECDSA_CLK_GATE_FORCE_ON_V 0x00000001U
#define ECDSA_CLK_GATE_FORCE_ON_S 0
/** ECDSA_INT_RAW_REG register
* ECDSA interrupt raw register, valid in level.
*/
#define ECDSA_INT_RAW_REG (DR_REG_ECDSA_BASE + 0xc)
/** ECDSA_CALC_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
* The raw interrupt status bit for the ecdsa_calc_done_int interrupt
*/
#define ECDSA_CALC_DONE_INT_RAW (BIT(0))
#define ECDSA_CALC_DONE_INT_RAW_M (ECDSA_CALC_DONE_INT_RAW_V << ECDSA_CALC_DONE_INT_RAW_S)
#define ECDSA_CALC_DONE_INT_RAW_V 0x00000001U
#define ECDSA_CALC_DONE_INT_RAW_S 0
/** ECDSA_SHA_RELEASE_INT_RAW : RO/WTC/SS; bitpos: [1]; default: 0;
* The raw interrupt status bit for the ecdsa_sha_release_int interrupt
*/
#define ECDSA_SHA_RELEASE_INT_RAW (BIT(1))
#define ECDSA_SHA_RELEASE_INT_RAW_M (ECDSA_SHA_RELEASE_INT_RAW_V << ECDSA_SHA_RELEASE_INT_RAW_S)
#define ECDSA_SHA_RELEASE_INT_RAW_V 0x00000001U
#define ECDSA_SHA_RELEASE_INT_RAW_S 1
/** ECDSA_INT_ST_REG register
* ECDSA interrupt status register.
*/
#define ECDSA_INT_ST_REG (DR_REG_ECDSA_BASE + 0x10)
/** ECDSA_CALC_DONE_INT_ST : RO; bitpos: [0]; default: 0;
* The masked interrupt status bit for the ecdsa_calc_done_int interrupt
*/
#define ECDSA_CALC_DONE_INT_ST (BIT(0))
#define ECDSA_CALC_DONE_INT_ST_M (ECDSA_CALC_DONE_INT_ST_V << ECDSA_CALC_DONE_INT_ST_S)
#define ECDSA_CALC_DONE_INT_ST_V 0x00000001U
#define ECDSA_CALC_DONE_INT_ST_S 0
/** ECDSA_SHA_RELEASE_INT_ST : RO; bitpos: [1]; default: 0;
* The masked interrupt status bit for the ecdsa_sha_release_int interrupt
*/
#define ECDSA_SHA_RELEASE_INT_ST (BIT(1))
#define ECDSA_SHA_RELEASE_INT_ST_M (ECDSA_SHA_RELEASE_INT_ST_V << ECDSA_SHA_RELEASE_INT_ST_S)
#define ECDSA_SHA_RELEASE_INT_ST_V 0x00000001U
#define ECDSA_SHA_RELEASE_INT_ST_S 1
/** ECDSA_INT_ENA_REG register
* ECDSA interrupt enable register.
*/
#define ECDSA_INT_ENA_REG (DR_REG_ECDSA_BASE + 0x14)
/** ECDSA_CALC_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
* The interrupt enable bit for the ecdsa_calc_done_int interrupt
*/
#define ECDSA_CALC_DONE_INT_ENA (BIT(0))
#define ECDSA_CALC_DONE_INT_ENA_M (ECDSA_CALC_DONE_INT_ENA_V << ECDSA_CALC_DONE_INT_ENA_S)
#define ECDSA_CALC_DONE_INT_ENA_V 0x00000001U
#define ECDSA_CALC_DONE_INT_ENA_S 0
/** ECDSA_SHA_RELEASE_INT_ENA : R/W; bitpos: [1]; default: 0;
* The interrupt enable bit for the ecdsa_sha_release_int interrupt
*/
#define ECDSA_SHA_RELEASE_INT_ENA (BIT(1))
#define ECDSA_SHA_RELEASE_INT_ENA_M (ECDSA_SHA_RELEASE_INT_ENA_V << ECDSA_SHA_RELEASE_INT_ENA_S)
#define ECDSA_SHA_RELEASE_INT_ENA_V 0x00000001U
#define ECDSA_SHA_RELEASE_INT_ENA_S 1
/** ECDSA_INT_CLR_REG register
* ECDSA interrupt clear register.
*/
#define ECDSA_INT_CLR_REG (DR_REG_ECDSA_BASE + 0x18)
/** ECDSA_CALC_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
* Set this bit to clear the ecdsa_calc_done_int interrupt
*/
#define ECDSA_CALC_DONE_INT_CLR (BIT(0))
#define ECDSA_CALC_DONE_INT_CLR_M (ECDSA_CALC_DONE_INT_CLR_V << ECDSA_CALC_DONE_INT_CLR_S)
#define ECDSA_CALC_DONE_INT_CLR_V 0x00000001U
#define ECDSA_CALC_DONE_INT_CLR_S 0
/** ECDSA_SHA_RELEASE_INT_CLR : WT; bitpos: [1]; default: 0;
* Set this bit to clear the ecdsa_sha_release_int interrupt
*/
#define ECDSA_SHA_RELEASE_INT_CLR (BIT(1))
#define ECDSA_SHA_RELEASE_INT_CLR_M (ECDSA_SHA_RELEASE_INT_CLR_V << ECDSA_SHA_RELEASE_INT_CLR_S)
#define ECDSA_SHA_RELEASE_INT_CLR_V 0x00000001U
#define ECDSA_SHA_RELEASE_INT_CLR_S 1
/** ECDSA_START_REG register
* ECDSA start register
*/
#define ECDSA_START_REG (DR_REG_ECDSA_BASE + 0x1c)
/** ECDSA_START : WT; bitpos: [0]; default: 0;
* Write 1 to start caculation of ECDSA Accelerator. This bit will be self-cleared
* after configuration.
*/
#define ECDSA_START (BIT(0))
#define ECDSA_START_M (ECDSA_START_V << ECDSA_START_S)
#define ECDSA_START_V 0x00000001U
#define ECDSA_START_S 0
/** ECDSA_LOAD_DONE : WT; bitpos: [1]; default: 0;
* Write 1 to input load done signal of ECDSA Accelerator. This bit will be
* self-cleared after configuration.
*/
#define ECDSA_LOAD_DONE (BIT(1))
#define ECDSA_LOAD_DONE_M (ECDSA_LOAD_DONE_V << ECDSA_LOAD_DONE_S)
#define ECDSA_LOAD_DONE_V 0x00000001U
#define ECDSA_LOAD_DONE_S 1
/** ECDSA_GET_DONE : WT; bitpos: [2]; default: 0;
* Write 1 to input get done signal of ECDSA Accelerator. This bit will be
* self-cleared after configuration.
*/
#define ECDSA_GET_DONE (BIT(2))
#define ECDSA_GET_DONE_M (ECDSA_GET_DONE_V << ECDSA_GET_DONE_S)
#define ECDSA_GET_DONE_V 0x00000001U
#define ECDSA_GET_DONE_S 2
/** ECDSA_STATE_REG register
* ECDSA status register
*/
#define ECDSA_STATE_REG (DR_REG_ECDSA_BASE + 0x20)
/** ECDSA_BUSY : RO; bitpos: [1:0]; default: 0;
* The status bits of ECDSA Accelerator. ECDSA is at 0: IDLE, 1: LOAD, 2: GET, 3: BUSY
* state.
*/
#define ECDSA_BUSY 0x00000003U
#define ECDSA_BUSY_M (ECDSA_BUSY_V << ECDSA_BUSY_S)
#define ECDSA_BUSY_V 0x00000003U
#define ECDSA_BUSY_S 0
/** ECDSA_RESULT_REG register
* ECDSA result register
*/
#define ECDSA_RESULT_REG (DR_REG_ECDSA_BASE + 0x24)
/** ECDSA_OPERATION_RESULT : RO/SS; bitpos: [0]; default: 0;
* The operation result bit of ECDSA Accelerator, only valid when ECDSA calculation is
* done.
*/
#define ECDSA_OPERATION_RESULT (BIT(0))
#define ECDSA_OPERATION_RESULT_M (ECDSA_OPERATION_RESULT_V << ECDSA_OPERATION_RESULT_S)
#define ECDSA_OPERATION_RESULT_V 0x00000001U
#define ECDSA_OPERATION_RESULT_S 0
/** ECDSA_K_VALUE_WARNING : RO/SS; bitpos: [1]; default: 0;
* The k value warning bit of ECDSA Accelerator, valid when k value is bigger than the
* curve order, then actually taken k = k mod n.
*/
#define ECDSA_K_VALUE_WARNING (BIT(1))
#define ECDSA_K_VALUE_WARNING_M (ECDSA_K_VALUE_WARNING_V << ECDSA_K_VALUE_WARNING_S)
#define ECDSA_K_VALUE_WARNING_V 0x00000001U
#define ECDSA_K_VALUE_WARNING_S 1
/** ECDSA_DATE_REG register
* Version control register
*/
#define ECDSA_DATE_REG (DR_REG_ECDSA_BASE + 0xfc)
/** ECDSA_DATE : R/W; bitpos: [27:0]; default: 36716656;
* ECDSA version control register
*/
#define ECDSA_DATE 0x0FFFFFFFU
#define ECDSA_DATE_M (ECDSA_DATE_V << ECDSA_DATE_S)
#define ECDSA_DATE_V 0x0FFFFFFFU
#define ECDSA_DATE_S 0
/** ECDSA_SHA_MODE_REG register
* ECDSA control SHA register
*/
#define ECDSA_SHA_MODE_REG (DR_REG_ECDSA_BASE + 0x200)
/** ECDSA_SHA_MODE : R/W; bitpos: [2:0]; default: 0;
* The work mode bits of SHA Calculator in ECDSA Accelerator. 1: SHA-224. 2: SHA-256.
* Others: invalid.
*/
#define ECDSA_SHA_MODE 0x00000007U
#define ECDSA_SHA_MODE_M (ECDSA_SHA_MODE_V << ECDSA_SHA_MODE_S)
#define ECDSA_SHA_MODE_V 0x00000007U
#define ECDSA_SHA_MODE_S 0
/** ECDSA_SHA_START_REG register
* ECDSA control SHA register
*/
#define ECDSA_SHA_START_REG (DR_REG_ECDSA_BASE + 0x210)
/** ECDSA_SHA_START : WT; bitpos: [0]; default: 0;
* Write 1 to start the first caculation of SHA Calculator in ECDSA Accelerator. This
* bit will be self-cleared after configuration.
*/
#define ECDSA_SHA_START (BIT(0))
#define ECDSA_SHA_START_M (ECDSA_SHA_START_V << ECDSA_SHA_START_S)
#define ECDSA_SHA_START_V 0x00000001U
#define ECDSA_SHA_START_S 0
/** ECDSA_SHA_CONTINUE_REG register
* ECDSA control SHA register
*/
#define ECDSA_SHA_CONTINUE_REG (DR_REG_ECDSA_BASE + 0x214)
/** ECDSA_SHA_CONTINUE : WT; bitpos: [0]; default: 0;
* Write 1 to start the latter caculation of SHA Calculator in ECDSA Accelerator. This
* bit will be self-cleared after configuration.
*/
#define ECDSA_SHA_CONTINUE (BIT(0))
#define ECDSA_SHA_CONTINUE_M (ECDSA_SHA_CONTINUE_V << ECDSA_SHA_CONTINUE_S)
#define ECDSA_SHA_CONTINUE_V 0x00000001U
#define ECDSA_SHA_CONTINUE_S 0
/** ECDSA_SHA_BUSY_REG register
* ECDSA status register
*/
#define ECDSA_SHA_BUSY_REG (DR_REG_ECDSA_BASE + 0x218)
/** ECDSA_SHA_BUSY : RO; bitpos: [0]; default: 0;
* The busy status bit of SHA Calculator in ECDSA Accelerator. 1:SHA is in
* calculation. 0: SHA is idle.
*/
#define ECDSA_SHA_BUSY (BIT(0))
#define ECDSA_SHA_BUSY_M (ECDSA_SHA_BUSY_V << ECDSA_SHA_BUSY_S)
#define ECDSA_SHA_BUSY_V 0x00000001U
#define ECDSA_SHA_BUSY_S 0
/** ECDSA_MESSAGE_MEM register
* The memory that stores message.
*/
#define ECDSA_MESSAGE_MEM (DR_REG_ECDSA_BASE + 0x280)
#define ECDSA_MESSAGE_MEM_SIZE_BYTES 32
/** ECDSA_R_MEM register
* The memory that stores r.
*/
#define ECDSA_R_MEM (DR_REG_ECDSA_BASE + 0xa00)
#define ECDSA_R_MEM_SIZE_BYTES 32
/** ECDSA_S_MEM register
* The memory that stores s.
*/
#define ECDSA_S_MEM (DR_REG_ECDSA_BASE + 0xa20)
#define ECDSA_S_MEM_SIZE_BYTES 32
/** ECDSA_Z_MEM register
* The memory that stores software written z.
*/
#define ECDSA_Z_MEM (DR_REG_ECDSA_BASE + 0xa40)
#define ECDSA_Z_MEM_SIZE_BYTES 32
/** ECDSA_QAX_MEM register
* The memory that stores x coordinates of QA or software written k.
*/
#define ECDSA_QAX_MEM (DR_REG_ECDSA_BASE + 0xa60)
#define ECDSA_QAX_MEM_SIZE_BYTES 32
/** ECDSA_QAY_MEM register
* The memory that stores y coordinates of QA.
*/
#define ECDSA_QAY_MEM (DR_REG_ECDSA_BASE + 0xa80)
#define ECDSA_QAY_MEM_SIZE_BYTES 32
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Data Memory */
/** Group: Configuration registers */
/** Type of conf register
* ECDSA configure register
*/
typedef union {
struct {
/** work_mode : R/W; bitpos: [1:0]; default: 0;
* The work mode bits of ECDSA Accelerator. 0: Signature Verify Mode. 1: Signature
* Generate Mode. 2: Export Public Key Mode. 3: invalid.
*/
uint32_t work_mode:2;
/** ecc_curve : R/W; bitpos: [2]; default: 0;
* The ecc curve select bit of ECDSA Accelerator. 0: P-192. 1: P-256.
*/
uint32_t ecc_curve:1;
/** software_set_k : R/W; bitpos: [3]; default: 0;
* The source of k select bit. 0: k is automatically generated by hardware. 1: k is
* written by software.
*/
uint32_t software_set_k:1;
/** software_set_z : R/W; bitpos: [4]; default: 0;
* The source of z select bit. 0: z is generated from SHA result. 1: z is written by
* software.
*/
uint32_t software_set_z:1;
/** deterministic_k : R/W; bitpos: [5]; default: 0;
* The source of hardware generated k. 0: k is generated by TRNG. 1: k is generated by
* deterministic derivation algorithm.
*/
uint32_t deterministic_k:1;
/** deterministic_loop : R/W; bitpos: [21:6]; default: 0;
* The (loop number - 1) value in the deterministic derivation algorithm to derive k.
*/
uint32_t deterministic_loop:16;
uint32_t reserved_22:10;
};
uint32_t val;
} ecdsa_conf_reg_t;
/** Type of start register
* ECDSA start register
*/
typedef union {
struct {
/** start : WT; bitpos: [0]; default: 0;
* Write 1 to start caculation of ECDSA Accelerator. This bit will be self-cleared
* after configuration.
*/
uint32_t start:1;
/** load_done : WT; bitpos: [1]; default: 0;
* Write 1 to input load done signal of ECDSA Accelerator. This bit will be
* self-cleared after configuration.
*/
uint32_t load_done:1;
/** get_done : WT; bitpos: [2]; default: 0;
* Write 1 to input get done signal of ECDSA Accelerator. This bit will be
* self-cleared after configuration.
*/
uint32_t get_done:1;
uint32_t reserved_3:29;
};
uint32_t val;
} ecdsa_start_reg_t;
/** Group: Clock and reset registers */
/** Type of clk register
* ECDSA clock gate register
*/
typedef union {
struct {
/** clk_gate_force_on : R/W; bitpos: [0]; default: 0;
* Write 1 to force on register clock gate.
*/
uint32_t clk_gate_force_on:1;
uint32_t reserved_1:31;
};
uint32_t val;
} ecdsa_clk_reg_t;
/** Group: Interrupt registers */
/** Type of int_raw register
* ECDSA interrupt raw register, valid in level.
*/
typedef union {
struct {
/** calc_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0;
* The raw interrupt status bit for the ecdsa_calc_done_int interrupt
*/
uint32_t calc_done_int_raw:1;
/** sha_release_int_raw : RO/WTC/SS; bitpos: [1]; default: 0;
* The raw interrupt status bit for the ecdsa_sha_release_int interrupt
*/
uint32_t sha_release_int_raw:1;
uint32_t reserved_2:30;
};
uint32_t val;
} ecdsa_int_raw_reg_t;
/** Type of int_st register
* ECDSA interrupt status register.
*/
typedef union {
struct {
/** calc_done_int_st : RO; bitpos: [0]; default: 0;
* The masked interrupt status bit for the ecdsa_calc_done_int interrupt
*/
uint32_t calc_done_int_st:1;
/** sha_release_int_st : RO; bitpos: [1]; default: 0;
* The masked interrupt status bit for the ecdsa_sha_release_int interrupt
*/
uint32_t sha_release_int_st:1;
uint32_t reserved_2:30;
};
uint32_t val;
} ecdsa_int_st_reg_t;
/** Type of int_ena register
* ECDSA interrupt enable register.
*/
typedef union {
struct {
/** calc_done_int_ena : R/W; bitpos: [0]; default: 0;
* The interrupt enable bit for the ecdsa_calc_done_int interrupt
*/
uint32_t calc_done_int_ena:1;
/** sha_release_int_ena : R/W; bitpos: [1]; default: 0;
* The interrupt enable bit for the ecdsa_sha_release_int interrupt
*/
uint32_t sha_release_int_ena:1;
uint32_t reserved_2:30;
};
uint32_t val;
} ecdsa_int_ena_reg_t;
/** Type of int_clr register
* ECDSA interrupt clear register.
*/
typedef union {
struct {
/** calc_done_int_clr : WT; bitpos: [0]; default: 0;
* Set this bit to clear the ecdsa_calc_done_int interrupt
*/
uint32_t calc_done_int_clr:1;
/** sha_release_int_clr : WT; bitpos: [1]; default: 0;
* Set this bit to clear the ecdsa_sha_release_int interrupt
*/
uint32_t sha_release_int_clr:1;
uint32_t reserved_2:30;
};
uint32_t val;
} ecdsa_int_clr_reg_t;
/** Group: Status registers */
/** Type of state register
* ECDSA status register
*/
typedef union {
struct {
/** busy : RO; bitpos: [1:0]; default: 0;
* The status bits of ECDSA Accelerator. ECDSA is at 0: IDLE, 1: LOAD, 2: GET, 3: BUSY
* state.
*/
uint32_t busy:2;
uint32_t reserved_2:30;
};
uint32_t val;
} ecdsa_state_reg_t;
/** Group: Result registers */
/** Type of result register
* ECDSA result register
*/
typedef union {
struct {
/** operation_result : RO/SS; bitpos: [0]; default: 0;
* The operation result bit of ECDSA Accelerator, only valid when ECDSA calculation is
* done.
*/
uint32_t operation_result:1;
/** k_value_warning : RO/SS; bitpos: [1]; default: 0;
* The k value warning bit of ECDSA Accelerator, valid when k value is bigger than the
* curve order, then actually taken k = k mod n.
*/
uint32_t k_value_warning:1;
uint32_t reserved_2:30;
};
uint32_t val;
} ecdsa_result_reg_t;
/** Group: SHA register */
/** Type of sha_mode register
* ECDSA control SHA register
*/
typedef union {
struct {
/** sha_mode : R/W; bitpos: [2:0]; default: 0;
* The work mode bits of SHA Calculator in ECDSA Accelerator. 1: SHA-224. 2: SHA-256.
* Others: invalid.
*/
uint32_t sha_mode:3;
uint32_t reserved_3:29;
};
uint32_t val;
} ecdsa_sha_mode_reg_t;
/** Type of sha_start register
* ECDSA control SHA register
*/
typedef union {
struct {
/** sha_start : WT; bitpos: [0]; default: 0;
* Write 1 to start the first caculation of SHA Calculator in ECDSA Accelerator. This
* bit will be self-cleared after configuration.
*/
uint32_t sha_start:1;
uint32_t reserved_1:31;
};
uint32_t val;
} ecdsa_sha_start_reg_t;
/** Type of sha_continue register
* ECDSA control SHA register
*/
typedef union {
struct {
/** sha_continue : WT; bitpos: [0]; default: 0;
* Write 1 to start the latter caculation of SHA Calculator in ECDSA Accelerator. This
* bit will be self-cleared after configuration.
*/
uint32_t sha_continue:1;
uint32_t reserved_1:31;
};
uint32_t val;
} ecdsa_sha_continue_reg_t;
/** Type of sha_busy register
* ECDSA status register
*/
typedef union {
struct {
/** sha_busy : RO; bitpos: [0]; default: 0;
* The busy status bit of SHA Calculator in ECDSA Accelerator. 1:SHA is in
* calculation. 0: SHA is idle.
*/
uint32_t sha_busy:1;
uint32_t reserved_1:31;
};
uint32_t val;
} ecdsa_sha_busy_reg_t;
/** Group: Version register */
/** Type of date register
* Version control register
*/
typedef union {
struct {
/** date : R/W; bitpos: [27:0]; default: 36716656;
* ECDSA version control register
*/
uint32_t date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} ecdsa_date_reg_t;
typedef struct {
uint32_t reserved_000;
volatile ecdsa_conf_reg_t conf;
volatile ecdsa_clk_reg_t clk;
volatile ecdsa_int_raw_reg_t int_raw;
volatile ecdsa_int_st_reg_t int_st;
volatile ecdsa_int_ena_reg_t int_ena;
volatile ecdsa_int_clr_reg_t int_clr;
volatile ecdsa_start_reg_t start;
volatile ecdsa_state_reg_t state;
volatile ecdsa_result_reg_t result;
uint32_t reserved_028[53];
volatile ecdsa_date_reg_t date;
uint32_t reserved_100[64];
volatile ecdsa_sha_mode_reg_t sha_mode;
uint32_t reserved_204[3];
volatile ecdsa_sha_start_reg_t sha_start;
volatile ecdsa_sha_continue_reg_t sha_continue;
volatile ecdsa_sha_busy_reg_t sha_busy;
uint32_t reserved_21c[25];
volatile uint32_t message[8];
uint32_t reserved_2a0[472];
volatile uint32_t r[8];
volatile uint32_t s[8];
volatile uint32_t z[8];
volatile uint32_t qax[8];
volatile uint32_t qay[8];
} ecdsa_dev_t;
#ifndef __cplusplus
_Static_assert(sizeof(ecdsa_dev_t) == 0xaa0, "Invalid size of ecdsa_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: SDM Configure Registers */
/** Type of sigmadeltan register
* Duty Cycle Configure Register of SDMn
*/
typedef union {
struct {
/** sd0_in : R/W; bitpos: [7:0]; default: 0;
* This field is used to configure the duty cycle of sigma delta modulation output.
*/
uint32_t sd0_in:8;
/** sd0_prescale : R/W; bitpos: [15:8]; default: 255;
* This field is used to set a divider value to divide APB clock.
*/
uint32_t sd0_prescale:8;
uint32_t reserved_16:16;
};
uint32_t val;
} gpiosd_sigmadeltan_reg_t;
/** Type of sigmadelta_misc register
* MISC Register
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** function_clk_en : R/W; bitpos: [30]; default: 0;
* Clock enable bit of sigma delta modulation.
*/
uint32_t function_clk_en:1;
/** spi_swap : R/W; bitpos: [31]; default: 0;
* Reserved.
*/
uint32_t spi_swap:1;
};
uint32_t val;
} gpiosd_sigmadelta_misc_reg_t;
/** Group: Glitch filter Configure Registers */
/** Type of glitch_filter_chn register
* Glitch Filter Configure Register of Channeln
*/
typedef union {
struct {
/** filter_ch0_en : R/W; bitpos: [0]; default: 0;
* Glitch Filter channel enable bit.
*/
uint32_t filter_ch0_en:1;
/** filter_ch0_input_io_num : R/W; bitpos: [6:1]; default: 0;
* Glitch Filter input io number.
*/
uint32_t filter_ch0_input_io_num:6;
/** filter_ch0_window_thres : R/W; bitpos: [12:7]; default: 0;
* Glitch Filter window threshold.
*/
uint32_t filter_ch0_window_thres:6;
/** filter_ch0_window_width : R/W; bitpos: [18:13]; default: 0;
* Glitch Filter window width.
*/
uint32_t filter_ch0_window_width:6;
uint32_t reserved_19:13;
};
uint32_t val;
} gpiosd_glitch_filter_chn_reg_t;
/** Group: Etm Configure Registers */
/** Type of etm_event_chn_cfg register
* Etm Config register of Channeln
*/
typedef union {
struct {
/** etm_ch0_event_sel : R/W; bitpos: [5:0]; default: 0;
* Etm event channel select gpio.
*/
uint32_t etm_ch0_event_sel:6;
uint32_t reserved_6:1;
/** etm_ch0_event_en : R/W; bitpos: [7]; default: 0;
* Etm event send enable bit.
*/
uint32_t etm_ch0_event_en:1;
uint32_t reserved_8:24;
};
uint32_t val;
} gpiosd_etm_event_chn_cfg_reg_t;
/** Type of etm_task_p0_cfg register
* Etm Configure Register to decide which GPIO been chosen
*/
typedef union {
struct {
/** etm_task_gpio0_en : R/W; bitpos: [0]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio0_en:1;
/** etm_task_gpio0_sel : R/W; bitpos: [3:1]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio0_sel:3;
uint32_t reserved_4:4;
/** etm_task_gpio1_en : R/W; bitpos: [8]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio1_en:1;
/** etm_task_gpio1_sel : R/W; bitpos: [11:9]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio1_sel:3;
uint32_t reserved_12:4;
/** etm_task_gpio2_en : R/W; bitpos: [16]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio2_en:1;
/** etm_task_gpio2_sel : R/W; bitpos: [19:17]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio2_sel:3;
uint32_t reserved_20:4;
/** etm_task_gpio3_en : R/W; bitpos: [24]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio3_en:1;
/** etm_task_gpio3_sel : R/W; bitpos: [27:25]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio3_sel:3;
uint32_t reserved_28:4;
};
uint32_t val;
} gpiosd_etm_task_p0_cfg_reg_t;
/** Type of etm_task_p1_cfg register
* Etm Configure Register to decide which GPIO been chosen
*/
typedef union {
struct {
/** etm_task_gpio4_en : R/W; bitpos: [0]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio4_en:1;
/** etm_task_gpio4_sel : R/W; bitpos: [3:1]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio4_sel:3;
uint32_t reserved_4:4;
/** etm_task_gpio5_en : R/W; bitpos: [8]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio5_en:1;
/** etm_task_gpio5_sel : R/W; bitpos: [11:9]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio5_sel:3;
uint32_t reserved_12:4;
/** etm_task_gpio6_en : R/W; bitpos: [16]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio6_en:1;
/** etm_task_gpio6_sel : R/W; bitpos: [19:17]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio6_sel:3;
uint32_t reserved_20:4;
/** etm_task_gpio7_en : R/W; bitpos: [24]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio7_en:1;
/** etm_task_gpio7_sel : R/W; bitpos: [27:25]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio7_sel:3;
uint32_t reserved_28:4;
};
uint32_t val;
} gpiosd_etm_task_p1_cfg_reg_t;
/** Type of etm_task_p2_cfg register
* Etm Configure Register to decide which GPIO been chosen
*/
typedef union {
struct {
/** etm_task_gpio8_en : R/W; bitpos: [0]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio8_en:1;
/** etm_task_gpio8_sel : R/W; bitpos: [3:1]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio8_sel:3;
uint32_t reserved_4:4;
/** etm_task_gpio9_en : R/W; bitpos: [8]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio9_en:1;
/** etm_task_gpio9_sel : R/W; bitpos: [11:9]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio9_sel:3;
uint32_t reserved_12:4;
/** etm_task_gpio10_en : R/W; bitpos: [16]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio10_en:1;
/** etm_task_gpio10_sel : R/W; bitpos: [19:17]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio10_sel:3;
uint32_t reserved_20:4;
/** etm_task_gpio11_en : R/W; bitpos: [24]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio11_en:1;
/** etm_task_gpio11_sel : R/W; bitpos: [27:25]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio11_sel:3;
uint32_t reserved_28:4;
};
uint32_t val;
} gpiosd_etm_task_p2_cfg_reg_t;
/** Type of etm_task_p3_cfg register
* Etm Configure Register to decide which GPIO been chosen
*/
typedef union {
struct {
/** etm_task_gpio12_en : R/W; bitpos: [0]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio12_en:1;
/** etm_task_gpio12_sel : R/W; bitpos: [3:1]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio12_sel:3;
uint32_t reserved_4:4;
/** etm_task_gpio13_en : R/W; bitpos: [8]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio13_en:1;
/** etm_task_gpio13_sel : R/W; bitpos: [11:9]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio13_sel:3;
uint32_t reserved_12:4;
/** etm_task_gpio14_en : R/W; bitpos: [16]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio14_en:1;
/** etm_task_gpio14_sel : R/W; bitpos: [19:17]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio14_sel:3;
uint32_t reserved_20:4;
/** etm_task_gpio15_en : R/W; bitpos: [24]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio15_en:1;
/** etm_task_gpio15_sel : R/W; bitpos: [27:25]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio15_sel:3;
uint32_t reserved_28:4;
};
uint32_t val;
} gpiosd_etm_task_p3_cfg_reg_t;
/** Type of etm_task_p4_cfg register
* Etm Configure Register to decide which GPIO been chosen
*/
typedef union {
struct {
/** etm_task_gpio16_en : R/W; bitpos: [0]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio16_en:1;
/** etm_task_gpio16_sel : R/W; bitpos: [3:1]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio16_sel:3;
uint32_t reserved_4:4;
/** etm_task_gpio17_en : R/W; bitpos: [8]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio17_en:1;
/** etm_task_gpio17_sel : R/W; bitpos: [11:9]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio17_sel:3;
uint32_t reserved_12:4;
/** etm_task_gpio18_en : R/W; bitpos: [16]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio18_en:1;
/** etm_task_gpio18_sel : R/W; bitpos: [19:17]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio18_sel:3;
uint32_t reserved_20:4;
/** etm_task_gpio19_en : R/W; bitpos: [24]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio19_en:1;
/** etm_task_gpio19_sel : R/W; bitpos: [27:25]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio19_sel:3;
uint32_t reserved_28:4;
};
uint32_t val;
} gpiosd_etm_task_p4_cfg_reg_t;
/** Type of etm_task_p5_cfg register
* Etm Configure Register to decide which GPIO been chosen
*/
typedef union {
struct {
/** etm_task_gpio20_en : R/W; bitpos: [0]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio20_en:1;
/** etm_task_gpio20_sel : R/W; bitpos: [3:1]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio20_sel:3;
uint32_t reserved_4:4;
/** etm_task_gpio21_en : R/W; bitpos: [8]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio21_en:1;
/** etm_task_gpio21_sel : R/W; bitpos: [11:9]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio21_sel:3;
uint32_t reserved_12:4;
/** etm_task_gpio22_en : R/W; bitpos: [16]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio22_en:1;
/** etm_task_gpio22_sel : R/W; bitpos: [19:17]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio22_sel:3;
uint32_t reserved_20:4;
/** etm_task_gpio23_en : R/W; bitpos: [24]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio23_en:1;
/** etm_task_gpio23_sel : R/W; bitpos: [27:25]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio23_sel:3;
uint32_t reserved_28:4;
};
uint32_t val;
} gpiosd_etm_task_p5_cfg_reg_t;
/** Type of etm_task_p6_cfg register
* Etm Configure Register to decide which GPIO been chosen
*/
typedef union {
struct {
/** etm_task_gpio24_en : R/W; bitpos: [0]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio24_en:1;
/** etm_task_gpio24_sel : R/W; bitpos: [3:1]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio24_sel:3;
uint32_t reserved_4:4;
/** etm_task_gpio25_en : R/W; bitpos: [8]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio25_en:1;
/** etm_task_gpio25_sel : R/W; bitpos: [11:9]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio25_sel:3;
uint32_t reserved_12:4;
/** etm_task_gpio26_en : R/W; bitpos: [16]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio26_en:1;
/** etm_task_gpio26_sel : R/W; bitpos: [19:17]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio26_sel:3;
uint32_t reserved_20:4;
/** etm_task_gpio27_en : R/W; bitpos: [24]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio27_en:1;
/** etm_task_gpio27_sel : R/W; bitpos: [27:25]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio27_sel:3;
uint32_t reserved_28:4;
};
uint32_t val;
} gpiosd_etm_task_p6_cfg_reg_t;
/** Type of etm_task_p7_cfg register
* Etm Configure Register to decide which GPIO been chosen
*/
typedef union {
struct {
/** etm_task_gpio28_en : R/W; bitpos: [0]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio28_en:1;
/** etm_task_gpio28_sel : R/W; bitpos: [3:1]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio28_sel:3;
uint32_t reserved_4:4;
/** etm_task_gpio29_en : R/W; bitpos: [8]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio29_en:1;
/** etm_task_gpio29_sel : R/W; bitpos: [11:9]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio29_sel:3;
uint32_t reserved_12:4;
/** etm_task_gpio30_en : R/W; bitpos: [16]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio30_en:1;
/** etm_task_gpio30_sel : R/W; bitpos: [19:17]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio30_sel:3;
uint32_t reserved_20:4;
/** etm_task_gpio31_en : R/W; bitpos: [24]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio31_en:1;
/** etm_task_gpio31_sel : R/W; bitpos: [27:25]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio31_sel:3;
uint32_t reserved_28:4;
};
uint32_t val;
} gpiosd_etm_task_p7_cfg_reg_t;
/** Type of etm_task_p8_cfg register
* Etm Configure Register to decide which GPIO been chosen
*/
typedef union {
struct {
/** etm_task_gpio32_en : R/W; bitpos: [0]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio32_en:1;
/** etm_task_gpio32_sel : R/W; bitpos: [3:1]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio32_sel:3;
uint32_t reserved_4:4;
/** etm_task_gpio33_en : R/W; bitpos: [8]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio33_en:1;
/** etm_task_gpio33_sel : R/W; bitpos: [11:9]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio33_sel:3;
uint32_t reserved_12:4;
/** etm_task_gpio34_en : R/W; bitpos: [16]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio34_en:1;
/** etm_task_gpio34_sel : R/W; bitpos: [19:17]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio34_sel:3;
uint32_t reserved_20:4;
/** etm_task_gpio35_en : R/W; bitpos: [24]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio35_en:1;
/** etm_task_gpio35_sel : R/W; bitpos: [27:25]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio35_sel:3;
uint32_t reserved_28:4;
};
uint32_t val;
} gpiosd_etm_task_p8_cfg_reg_t;
/** Type of etm_task_p9_cfg register
* Etm Configure Register to decide which GPIO been chosen
*/
typedef union {
struct {
/** etm_task_gpio36_en : R/W; bitpos: [0]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio36_en:1;
/** etm_task_gpio36_sel : R/W; bitpos: [3:1]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio36_sel:3;
uint32_t reserved_4:4;
/** etm_task_gpio37_en : R/W; bitpos: [8]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio37_en:1;
/** etm_task_gpio37_sel : R/W; bitpos: [11:9]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio37_sel:3;
uint32_t reserved_12:4;
/** etm_task_gpio38_en : R/W; bitpos: [16]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio38_en:1;
/** etm_task_gpio38_sel : R/W; bitpos: [19:17]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio38_sel:3;
uint32_t reserved_20:4;
/** etm_task_gpio39_en : R/W; bitpos: [24]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio39_en:1;
/** etm_task_gpio39_sel : R/W; bitpos: [27:25]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio39_sel:3;
uint32_t reserved_28:4;
};
uint32_t val;
} gpiosd_etm_task_p9_cfg_reg_t;
/** Type of etm_task_p10_cfg register
* Etm Configure Register to decide which GPIO been chosen
*/
typedef union {
struct {
/** etm_task_gpio40_en : R/W; bitpos: [0]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio40_en:1;
/** etm_task_gpio40_sel : R/W; bitpos: [3:1]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio40_sel:3;
uint32_t reserved_4:4;
/** etm_task_gpio41_en : R/W; bitpos: [8]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio41_en:1;
/** etm_task_gpio41_sel : R/W; bitpos: [11:9]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio41_sel:3;
uint32_t reserved_12:4;
/** etm_task_gpio42_en : R/W; bitpos: [16]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio42_en:1;
/** etm_task_gpio42_sel : R/W; bitpos: [19:17]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio42_sel:3;
uint32_t reserved_20:4;
/** etm_task_gpio43_en : R/W; bitpos: [24]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio43_en:1;
/** etm_task_gpio43_sel : R/W; bitpos: [27:25]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio43_sel:3;
uint32_t reserved_28:4;
};
uint32_t val;
} gpiosd_etm_task_p10_cfg_reg_t;
/** Type of etm_task_p11_cfg register
* Etm Configure Register to decide which GPIO been chosen
*/
typedef union {
struct {
/** etm_task_gpio44_en : R/W; bitpos: [0]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio44_en:1;
/** etm_task_gpio44_sel : R/W; bitpos: [3:1]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio44_sel:3;
uint32_t reserved_4:4;
/** etm_task_gpio45_en : R/W; bitpos: [8]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio45_en:1;
/** etm_task_gpio45_sel : R/W; bitpos: [11:9]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio45_sel:3;
uint32_t reserved_12:4;
/** etm_task_gpio46_en : R/W; bitpos: [16]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio46_en:1;
/** etm_task_gpio46_sel : R/W; bitpos: [19:17]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio46_sel:3;
uint32_t reserved_20:4;
/** etm_task_gpio47_en : R/W; bitpos: [24]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio47_en:1;
/** etm_task_gpio47_sel : R/W; bitpos: [27:25]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio47_sel:3;
uint32_t reserved_28:4;
};
uint32_t val;
} gpiosd_etm_task_p11_cfg_reg_t;
/** Type of etm_task_p12_cfg register
* Etm Configure Register to decide which GPIO been chosen
*/
typedef union {
struct {
/** etm_task_gpio48_en : R/W; bitpos: [0]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio48_en:1;
/** etm_task_gpio48_sel : R/W; bitpos: [3:1]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio48_sel:3;
uint32_t reserved_4:4;
/** etm_task_gpio49_en : R/W; bitpos: [8]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio49_en:1;
/** etm_task_gpio49_sel : R/W; bitpos: [11:9]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio49_sel:3;
uint32_t reserved_12:4;
/** etm_task_gpio50_en : R/W; bitpos: [16]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio50_en:1;
/** etm_task_gpio50_sel : R/W; bitpos: [19:17]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio50_sel:3;
uint32_t reserved_20:4;
/** etm_task_gpio51_en : R/W; bitpos: [24]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio51_en:1;
/** etm_task_gpio51_sel : R/W; bitpos: [27:25]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio51_sel:3;
uint32_t reserved_28:4;
};
uint32_t val;
} gpiosd_etm_task_p12_cfg_reg_t;
/** Type of etm_task_p13_cfg register
* Etm Configure Register to decide which GPIO been chosen
*/
typedef union {
struct {
/** etm_task_gpio52_en : R/W; bitpos: [0]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio52_en:1;
/** etm_task_gpio52_sel : R/W; bitpos: [3:1]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio52_sel:3;
uint32_t reserved_4:4;
/** etm_task_gpio53_en : R/W; bitpos: [8]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio53_en:1;
/** etm_task_gpio53_sel : R/W; bitpos: [11:9]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio53_sel:3;
uint32_t reserved_12:4;
/** etm_task_gpio54_en : R/W; bitpos: [16]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio54_en:1;
/** etm_task_gpio54_sel : R/W; bitpos: [19:17]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio54_sel:3;
uint32_t reserved_20:12;
};
uint32_t val;
} gpiosd_etm_task_p13_cfg_reg_t;
/** Group: Version Register */
/** Type of version register
* Version Control Register
*/
typedef union {
struct {
/** gpio_sd_date : R/W; bitpos: [27:0]; default: 35663952;
* Version control register.
*/
uint32_t gpio_sd_date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} gpiosd_version_reg_t;
typedef struct {
volatile gpiosd_sigmadeltan_reg_t sigmadeltan[8];
uint32_t reserved_020;
volatile gpiosd_sigmadelta_misc_reg_t sigmadelta_misc;
uint32_t reserved_028[2];
volatile gpiosd_glitch_filter_chn_reg_t glitch_filter_chn[8];
uint32_t reserved_050[4];
volatile gpiosd_etm_event_chn_cfg_reg_t etm_event_chn_cfg[8];
uint32_t reserved_080[8];
volatile gpiosd_etm_task_p0_cfg_reg_t etm_task_p0_cfg;
volatile gpiosd_etm_task_p1_cfg_reg_t etm_task_p1_cfg;
volatile gpiosd_etm_task_p2_cfg_reg_t etm_task_p2_cfg;
volatile gpiosd_etm_task_p3_cfg_reg_t etm_task_p3_cfg;
volatile gpiosd_etm_task_p4_cfg_reg_t etm_task_p4_cfg;
volatile gpiosd_etm_task_p5_cfg_reg_t etm_task_p5_cfg;
volatile gpiosd_etm_task_p6_cfg_reg_t etm_task_p6_cfg;
volatile gpiosd_etm_task_p7_cfg_reg_t etm_task_p7_cfg;
volatile gpiosd_etm_task_p8_cfg_reg_t etm_task_p8_cfg;
volatile gpiosd_etm_task_p9_cfg_reg_t etm_task_p9_cfg;
volatile gpiosd_etm_task_p10_cfg_reg_t etm_task_p10_cfg;
volatile gpiosd_etm_task_p11_cfg_reg_t etm_task_p11_cfg;
volatile gpiosd_etm_task_p12_cfg_reg_t etm_task_p12_cfg;
volatile gpiosd_etm_task_p13_cfg_reg_t etm_task_p13_cfg;
uint32_t reserved_0d8[9];
volatile gpiosd_version_reg_t version;
} gpiosd_dev_t;
#ifndef __cplusplus
_Static_assert(sizeof(gpiosd_dev_t) == 0x100, "Invalid size of gpiosd_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** HMAC_SET_START_REG register
* Process control register 0.
*/
#define HMAC_SET_START_REG (DR_REG_HMAC_BASE + 0x40)
/** HMAC_SET_START : WS; bitpos: [0]; default: 0;
* Start hmac operation.
*/
#define HMAC_SET_START (BIT(0))
#define HMAC_SET_START_M (HMAC_SET_START_V << HMAC_SET_START_S)
#define HMAC_SET_START_V 0x00000001U
#define HMAC_SET_START_S 0
/** HMAC_SET_PARA_PURPOSE_REG register
* Configure purpose.
*/
#define HMAC_SET_PARA_PURPOSE_REG (DR_REG_HMAC_BASE + 0x44)
/** HMAC_PURPOSE_SET : WO; bitpos: [3:0]; default: 0;
* Set hmac parameter purpose.
*/
#define HMAC_PURPOSE_SET 0x0000000FU
#define HMAC_PURPOSE_SET_M (HMAC_PURPOSE_SET_V << HMAC_PURPOSE_SET_S)
#define HMAC_PURPOSE_SET_V 0x0000000FU
#define HMAC_PURPOSE_SET_S 0
/** HMAC_SET_PARA_KEY_REG register
* Configure key.
*/
#define HMAC_SET_PARA_KEY_REG (DR_REG_HMAC_BASE + 0x48)
/** HMAC_KEY_SET : WO; bitpos: [2:0]; default: 0;
* Set hmac parameter key.
*/
#define HMAC_KEY_SET 0x00000007U
#define HMAC_KEY_SET_M (HMAC_KEY_SET_V << HMAC_KEY_SET_S)
#define HMAC_KEY_SET_V 0x00000007U
#define HMAC_KEY_SET_S 0
/** HMAC_SET_PARA_FINISH_REG register
* Finish initial configuration.
*/
#define HMAC_SET_PARA_FINISH_REG (DR_REG_HMAC_BASE + 0x4c)
/** HMAC_SET_PARA_END : WS; bitpos: [0]; default: 0;
* Finish hmac configuration.
*/
#define HMAC_SET_PARA_END (BIT(0))
#define HMAC_SET_PARA_END_M (HMAC_SET_PARA_END_V << HMAC_SET_PARA_END_S)
#define HMAC_SET_PARA_END_V 0x00000001U
#define HMAC_SET_PARA_END_S 0
/** HMAC_SET_MESSAGE_ONE_REG register
* Process control register 1.
*/
#define HMAC_SET_MESSAGE_ONE_REG (DR_REG_HMAC_BASE + 0x50)
/** HMAC_SET_TEXT_ONE : WS; bitpos: [0]; default: 0;
* Call SHA to calculate one message block.
*/
#define HMAC_SET_TEXT_ONE (BIT(0))
#define HMAC_SET_TEXT_ONE_M (HMAC_SET_TEXT_ONE_V << HMAC_SET_TEXT_ONE_S)
#define HMAC_SET_TEXT_ONE_V 0x00000001U
#define HMAC_SET_TEXT_ONE_S 0
/** HMAC_SET_MESSAGE_ING_REG register
* Process control register 2.
*/
#define HMAC_SET_MESSAGE_ING_REG (DR_REG_HMAC_BASE + 0x54)
/** HMAC_SET_TEXT_ING : WS; bitpos: [0]; default: 0;
* Continue typical hmac.
*/
#define HMAC_SET_TEXT_ING (BIT(0))
#define HMAC_SET_TEXT_ING_M (HMAC_SET_TEXT_ING_V << HMAC_SET_TEXT_ING_S)
#define HMAC_SET_TEXT_ING_V 0x00000001U
#define HMAC_SET_TEXT_ING_S 0
/** HMAC_SET_MESSAGE_END_REG register
* Process control register 3.
*/
#define HMAC_SET_MESSAGE_END_REG (DR_REG_HMAC_BASE + 0x58)
/** HMAC_SET_TEXT_END : WS; bitpos: [0]; default: 0;
* Start hardware padding.
*/
#define HMAC_SET_TEXT_END (BIT(0))
#define HMAC_SET_TEXT_END_M (HMAC_SET_TEXT_END_V << HMAC_SET_TEXT_END_S)
#define HMAC_SET_TEXT_END_V 0x00000001U
#define HMAC_SET_TEXT_END_S 0
/** HMAC_SET_RESULT_FINISH_REG register
* Process control register 4.
*/
#define HMAC_SET_RESULT_FINISH_REG (DR_REG_HMAC_BASE + 0x5c)
/** HMAC_SET_RESULT_END : WS; bitpos: [0]; default: 0;
* After read result from upstream, then let hmac back to idle.
*/
#define HMAC_SET_RESULT_END (BIT(0))
#define HMAC_SET_RESULT_END_M (HMAC_SET_RESULT_END_V << HMAC_SET_RESULT_END_S)
#define HMAC_SET_RESULT_END_V 0x00000001U
#define HMAC_SET_RESULT_END_S 0
/** HMAC_SET_INVALIDATE_JTAG_REG register
* Invalidate register 0.
*/
#define HMAC_SET_INVALIDATE_JTAG_REG (DR_REG_HMAC_BASE + 0x60)
/** HMAC_SET_INVALIDATE_JTAG : WS; bitpos: [0]; default: 0;
* Clear result from hmac downstream JTAG.
*/
#define HMAC_SET_INVALIDATE_JTAG (BIT(0))
#define HMAC_SET_INVALIDATE_JTAG_M (HMAC_SET_INVALIDATE_JTAG_V << HMAC_SET_INVALIDATE_JTAG_S)
#define HMAC_SET_INVALIDATE_JTAG_V 0x00000001U
#define HMAC_SET_INVALIDATE_JTAG_S 0
/** HMAC_SET_INVALIDATE_DS_REG register
* Invalidate register 1.
*/
#define HMAC_SET_INVALIDATE_DS_REG (DR_REG_HMAC_BASE + 0x64)
/** HMAC_SET_INVALIDATE_DS : WS; bitpos: [0]; default: 0;
* Clear result from hmac downstream DS.
*/
#define HMAC_SET_INVALIDATE_DS (BIT(0))
#define HMAC_SET_INVALIDATE_DS_M (HMAC_SET_INVALIDATE_DS_V << HMAC_SET_INVALIDATE_DS_S)
#define HMAC_SET_INVALIDATE_DS_V 0x00000001U
#define HMAC_SET_INVALIDATE_DS_S 0
/** HMAC_QUERY_ERROR_REG register
* Error register.
*/
#define HMAC_QUERY_ERROR_REG (DR_REG_HMAC_BASE + 0x68)
/** HMAC_QUREY_CHECK : RO; bitpos: [0]; default: 0;
* Hmac configuration state. 0: key are agree with purpose. 1: error
*/
#define HMAC_QUREY_CHECK (BIT(0))
#define HMAC_QUREY_CHECK_M (HMAC_QUREY_CHECK_V << HMAC_QUREY_CHECK_S)
#define HMAC_QUREY_CHECK_V 0x00000001U
#define HMAC_QUREY_CHECK_S 0
/** HMAC_QUERY_BUSY_REG register
* Busy register.
*/
#define HMAC_QUERY_BUSY_REG (DR_REG_HMAC_BASE + 0x6c)
/** HMAC_BUSY_STATE : RO; bitpos: [0]; default: 0;
* Hmac state. 1'b0: idle. 1'b1: busy
*/
#define HMAC_BUSY_STATE (BIT(0))
#define HMAC_BUSY_STATE_M (HMAC_BUSY_STATE_V << HMAC_BUSY_STATE_S)
#define HMAC_BUSY_STATE_V 0x00000001U
#define HMAC_BUSY_STATE_S 0
/** HMAC_WR_MESSAGE_MEM register
* Message block memory.
*/
#define HMAC_WR_MESSAGE_MEM (DR_REG_HMAC_BASE + 0x80)
#define HMAC_WR_MESSAGE_MEM_SIZE_BYTES 64
/** HMAC_RD_RESULT_MEM register
* Result from upstream.
*/
#define HMAC_RD_RESULT_MEM (DR_REG_HMAC_BASE + 0xc0)
#define HMAC_RD_RESULT_MEM_SIZE_BYTES 32
/** HMAC_SET_MESSAGE_PAD_REG register
* Process control register 5.
*/
#define HMAC_SET_MESSAGE_PAD_REG (DR_REG_HMAC_BASE + 0xf0)
/** HMAC_SET_TEXT_PAD : WO; bitpos: [0]; default: 0;
* Start software padding.
*/
#define HMAC_SET_TEXT_PAD (BIT(0))
#define HMAC_SET_TEXT_PAD_M (HMAC_SET_TEXT_PAD_V << HMAC_SET_TEXT_PAD_S)
#define HMAC_SET_TEXT_PAD_V 0x00000001U
#define HMAC_SET_TEXT_PAD_S 0
/** HMAC_ONE_BLOCK_REG register
* Process control register 6.
*/
#define HMAC_ONE_BLOCK_REG (DR_REG_HMAC_BASE + 0xf4)
/** HMAC_SET_ONE_BLOCK : WS; bitpos: [0]; default: 0;
* Don't have to do padding.
*/
#define HMAC_SET_ONE_BLOCK (BIT(0))
#define HMAC_SET_ONE_BLOCK_M (HMAC_SET_ONE_BLOCK_V << HMAC_SET_ONE_BLOCK_S)
#define HMAC_SET_ONE_BLOCK_V 0x00000001U
#define HMAC_SET_ONE_BLOCK_S 0
/** HMAC_SOFT_JTAG_CTRL_REG register
* Jtag register 0.
*/
#define HMAC_SOFT_JTAG_CTRL_REG (DR_REG_HMAC_BASE + 0xf8)
/** HMAC_SOFT_JTAG_CTRL : WS; bitpos: [0]; default: 0;
* Turn on JTAG verification.
*/
#define HMAC_SOFT_JTAG_CTRL (BIT(0))
#define HMAC_SOFT_JTAG_CTRL_M (HMAC_SOFT_JTAG_CTRL_V << HMAC_SOFT_JTAG_CTRL_S)
#define HMAC_SOFT_JTAG_CTRL_V 0x00000001U
#define HMAC_SOFT_JTAG_CTRL_S 0
/** HMAC_WR_JTAG_REG register
* Jtag register 1.
*/
#define HMAC_WR_JTAG_REG (DR_REG_HMAC_BASE + 0xfc)
/** HMAC_WR_JTAG : WO; bitpos: [31:0]; default: 0;
* 32-bit of key to be compared.
*/
#define HMAC_WR_JTAG 0xFFFFFFFFU
#define HMAC_WR_JTAG_M (HMAC_WR_JTAG_V << HMAC_WR_JTAG_S)
#define HMAC_WR_JTAG_V 0xFFFFFFFFU
#define HMAC_WR_JTAG_S 0
/** HMAC_DATE_REG register
* Date register.
*/
#define HMAC_DATE_REG (DR_REG_HMAC_BASE + 0x1fc)
/** HMAC_DATE : R/W; bitpos: [29:0]; default: 538969624;
* Hmac date information/ hmac version information.
*/
#define HMAC_DATE 0x3FFFFFFFU
#define HMAC_DATE_M (HMAC_DATE_V << HMAC_DATE_S)
#define HMAC_DATE_V 0x3FFFFFFFU
#define HMAC_DATE_S 0
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Configuration Register */
/** Type of set_start register
* Process control register 0.
*/
typedef union {
struct {
/** set_start : WS; bitpos: [0]; default: 0;
* Start hmac operation.
*/
uint32_t set_start:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_set_start_reg_t;
/** Type of set_para_purpose register
* Configure purpose.
*/
typedef union {
struct {
/** purpose_set : WO; bitpos: [3:0]; default: 0;
* Set hmac parameter purpose.
*/
uint32_t purpose_set:4;
uint32_t reserved_4:28;
};
uint32_t val;
} hmac_set_para_purpose_reg_t;
/** Type of set_para_key register
* Configure key.
*/
typedef union {
struct {
/** key_set : WO; bitpos: [2:0]; default: 0;
* Set hmac parameter key.
*/
uint32_t key_set:3;
uint32_t reserved_3:29;
};
uint32_t val;
} hmac_set_para_key_reg_t;
/** Type of set_para_finish register
* Finish initial configuration.
*/
typedef union {
struct {
/** set_para_end : WS; bitpos: [0]; default: 0;
* Finish hmac configuration.
*/
uint32_t set_para_end:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_set_para_finish_reg_t;
/** Type of set_message_one register
* Process control register 1.
*/
typedef union {
struct {
/** set_text_one : WS; bitpos: [0]; default: 0;
* Call SHA to calculate one message block.
*/
uint32_t set_text_one:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_set_message_one_reg_t;
/** Type of set_message_ing register
* Process control register 2.
*/
typedef union {
struct {
/** set_text_ing : WS; bitpos: [0]; default: 0;
* Continue typical hmac.
*/
uint32_t set_text_ing:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_set_message_ing_reg_t;
/** Type of set_message_end register
* Process control register 3.
*/
typedef union {
struct {
/** set_text_end : WS; bitpos: [0]; default: 0;
* Start hardware padding.
*/
uint32_t set_text_end:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_set_message_end_reg_t;
/** Type of set_result_finish register
* Process control register 4.
*/
typedef union {
struct {
/** set_result_end : WS; bitpos: [0]; default: 0;
* After read result from upstream, then let hmac back to idle.
*/
uint32_t set_result_end:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_set_result_finish_reg_t;
/** Type of set_invalidate_jtag register
* Invalidate register 0.
*/
typedef union {
struct {
/** set_invalidate_jtag : WS; bitpos: [0]; default: 0;
* Clear result from hmac downstream JTAG.
*/
uint32_t set_invalidate_jtag:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_set_invalidate_jtag_reg_t;
/** Type of set_invalidate_ds register
* Invalidate register 1.
*/
typedef union {
struct {
/** set_invalidate_ds : WS; bitpos: [0]; default: 0;
* Clear result from hmac downstream DS.
*/
uint32_t set_invalidate_ds:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_set_invalidate_ds_reg_t;
/** Type of set_message_pad register
* Process control register 5.
*/
typedef union {
struct {
/** set_text_pad : WO; bitpos: [0]; default: 0;
* Start software padding.
*/
uint32_t set_text_pad:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_set_message_pad_reg_t;
/** Type of one_block register
* Process control register 6.
*/
typedef union {
struct {
/** set_one_block : WS; bitpos: [0]; default: 0;
* Don't have to do padding.
*/
uint32_t set_one_block:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_one_block_reg_t;
/** Type of soft_jtag_ctrl register
* Jtag register 0.
*/
typedef union {
struct {
/** soft_jtag_ctrl : WS; bitpos: [0]; default: 0;
* Turn on JTAG verification.
*/
uint32_t soft_jtag_ctrl:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_soft_jtag_ctrl_reg_t;
/** Type of wr_jtag register
* Jtag register 1.
*/
typedef union {
struct {
/** wr_jtag : WO; bitpos: [31:0]; default: 0;
* 32-bit of key to be compared.
*/
uint32_t wr_jtag:32;
};
uint32_t val;
} hmac_wr_jtag_reg_t;
/** Group: Status Register */
/** Type of query_error register
* Error register.
*/
typedef union {
struct {
/** qurey_check : RO; bitpos: [0]; default: 0;
* Hmac configuration state. 0: key are agree with purpose. 1: error
*/
uint32_t qurey_check:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_query_error_reg_t;
/** Type of query_busy register
* Busy register.
*/
typedef union {
struct {
/** busy_state : RO; bitpos: [0]; default: 0;
* Hmac state. 1'b0: idle. 1'b1: busy
*/
uint32_t busy_state:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_query_busy_reg_t;
/** Group: Memory Type */
/** Group: Version Register */
/** Type of date register
* Date register.
*/
typedef union {
struct {
/** date : R/W; bitpos: [29:0]; default: 538969624;
* Hmac date information/ hmac version information.
*/
uint32_t date:30;
uint32_t reserved_30:2;
};
uint32_t val;
} hmac_date_reg_t;
typedef struct {
uint32_t reserved_000[16];
volatile hmac_set_start_reg_t set_start;
volatile hmac_set_para_purpose_reg_t set_para_purpose;
volatile hmac_set_para_key_reg_t set_para_key;
volatile hmac_set_para_finish_reg_t set_para_finish;
volatile hmac_set_message_one_reg_t set_message_one;
volatile hmac_set_message_ing_reg_t set_message_ing;
volatile hmac_set_message_end_reg_t set_message_end;
volatile hmac_set_result_finish_reg_t set_result_finish;
volatile hmac_set_invalidate_jtag_reg_t set_invalidate_jtag;
volatile hmac_set_invalidate_ds_reg_t set_invalidate_ds;
volatile hmac_query_error_reg_t query_error;
volatile hmac_query_busy_reg_t query_busy;
uint32_t reserved_070[4];
volatile uint32_t wr_message[16];
volatile uint32_t rd_result[8];
uint32_t reserved_0e0[4];
volatile hmac_set_message_pad_reg_t set_message_pad;
volatile hmac_one_block_reg_t one_block;
volatile hmac_soft_jtag_ctrl_reg_t soft_jtag_ctrl;
volatile hmac_wr_jtag_reg_t wr_jtag;
uint32_t reserved_100[63];
volatile hmac_date_reg_t date;
} hmac_dev_t;
#ifndef __cplusplus
_Static_assert(sizeof(hmac_dev_t) == 0x200, "Invalid size of hmac_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** TEE_HP2LP_TEE_PMS_DATE_REG register
* NA
*/
#define TEE_HP2LP_TEE_PMS_DATE_REG (DR_REG_TEE_BASE + 0x0)
/** TEE_TEE_DATE : R/W; bitpos: [31:0]; default: 2294790;
* NA
*/
#define TEE_TEE_DATE 0xFFFFFFFFU
#define TEE_TEE_DATE_M (TEE_TEE_DATE_V << TEE_TEE_DATE_S)
#define TEE_TEE_DATE_V 0xFFFFFFFFU
#define TEE_TEE_DATE_S 0
/** TEE_PMS_CLK_EN_REG register
* NA
*/
#define TEE_PMS_CLK_EN_REG (DR_REG_TEE_BASE + 0x4)
/** TEE_REG_CLK_EN : R/W; bitpos: [0]; default: 1;
* NA
*/
#define TEE_REG_CLK_EN (BIT(0))
#define TEE_REG_CLK_EN_M (TEE_REG_CLK_EN_V << TEE_REG_CLK_EN_S)
#define TEE_REG_CLK_EN_V 0x00000001U
#define TEE_REG_CLK_EN_S 0
/** TEE_HP_CORE0_MM_PMS_REG0_REG register
* NA
*/
#define TEE_HP_CORE0_MM_PMS_REG0_REG (DR_REG_TEE_BASE + 0x8)
/** TEE_REG_HP_CORE0_MM_LP_SYSREG_ALLOW : R/W; bitpos: [0]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_MM_LP_SYSREG_ALLOW (BIT(0))
#define TEE_REG_HP_CORE0_MM_LP_SYSREG_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_SYSREG_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_SYSREG_ALLOW_S)
#define TEE_REG_HP_CORE0_MM_LP_SYSREG_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_MM_LP_SYSREG_ALLOW_S 0
/** TEE_REG_HP_CORE0_MM_LP_AONCLKRST_ALLOW : R/W; bitpos: [1]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_MM_LP_AONCLKRST_ALLOW (BIT(1))
#define TEE_REG_HP_CORE0_MM_LP_AONCLKRST_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_AONCLKRST_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_AONCLKRST_ALLOW_S)
#define TEE_REG_HP_CORE0_MM_LP_AONCLKRST_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_MM_LP_AONCLKRST_ALLOW_S 1
/** TEE_REG_HP_CORE0_MM_LP_TIMER_ALLOW : R/W; bitpos: [2]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_MM_LP_TIMER_ALLOW (BIT(2))
#define TEE_REG_HP_CORE0_MM_LP_TIMER_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_TIMER_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_TIMER_ALLOW_S)
#define TEE_REG_HP_CORE0_MM_LP_TIMER_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_MM_LP_TIMER_ALLOW_S 2
/** TEE_REG_HP_CORE0_MM_LP_ANAPERI_ALLOW : R/W; bitpos: [3]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_MM_LP_ANAPERI_ALLOW (BIT(3))
#define TEE_REG_HP_CORE0_MM_LP_ANAPERI_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_ANAPERI_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_ANAPERI_ALLOW_S)
#define TEE_REG_HP_CORE0_MM_LP_ANAPERI_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_MM_LP_ANAPERI_ALLOW_S 3
/** TEE_REG_HP_CORE0_MM_LP_PMU_ALLOW : R/W; bitpos: [4]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_MM_LP_PMU_ALLOW (BIT(4))
#define TEE_REG_HP_CORE0_MM_LP_PMU_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_PMU_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_PMU_ALLOW_S)
#define TEE_REG_HP_CORE0_MM_LP_PMU_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_MM_LP_PMU_ALLOW_S 4
/** TEE_REG_HP_CORE0_MM_LP_WDT_ALLOW : R/W; bitpos: [5]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_MM_LP_WDT_ALLOW (BIT(5))
#define TEE_REG_HP_CORE0_MM_LP_WDT_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_WDT_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_WDT_ALLOW_S)
#define TEE_REG_HP_CORE0_MM_LP_WDT_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_MM_LP_WDT_ALLOW_S 5
/** TEE_REG_HP_CORE0_MM_LP_MAILBOX_ALLOW : R/W; bitpos: [6]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_MM_LP_MAILBOX_ALLOW (BIT(6))
#define TEE_REG_HP_CORE0_MM_LP_MAILBOX_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_MAILBOX_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_MAILBOX_ALLOW_S)
#define TEE_REG_HP_CORE0_MM_LP_MAILBOX_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_MM_LP_MAILBOX_ALLOW_S 6
/** TEE_REG_HP_CORE0_MM_LP_RTC_ALLOW : R/W; bitpos: [7]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_MM_LP_RTC_ALLOW (BIT(7))
#define TEE_REG_HP_CORE0_MM_LP_RTC_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_RTC_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_RTC_ALLOW_S)
#define TEE_REG_HP_CORE0_MM_LP_RTC_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_MM_LP_RTC_ALLOW_S 7
/** TEE_REG_HP_CORE0_MM_LP_PERICLKRST_ALLOW : R/W; bitpos: [8]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_MM_LP_PERICLKRST_ALLOW (BIT(8))
#define TEE_REG_HP_CORE0_MM_LP_PERICLKRST_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_PERICLKRST_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_PERICLKRST_ALLOW_S)
#define TEE_REG_HP_CORE0_MM_LP_PERICLKRST_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_MM_LP_PERICLKRST_ALLOW_S 8
/** TEE_REG_HP_CORE0_MM_LP_UART_ALLOW : R/W; bitpos: [9]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_MM_LP_UART_ALLOW (BIT(9))
#define TEE_REG_HP_CORE0_MM_LP_UART_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_UART_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_UART_ALLOW_S)
#define TEE_REG_HP_CORE0_MM_LP_UART_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_MM_LP_UART_ALLOW_S 9
/** TEE_REG_HP_CORE0_MM_LP_I2C_ALLOW : R/W; bitpos: [10]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_MM_LP_I2C_ALLOW (BIT(10))
#define TEE_REG_HP_CORE0_MM_LP_I2C_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_I2C_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_I2C_ALLOW_S)
#define TEE_REG_HP_CORE0_MM_LP_I2C_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_MM_LP_I2C_ALLOW_S 10
/** TEE_REG_HP_CORE0_MM_LP_SPI_ALLOW : R/W; bitpos: [11]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_MM_LP_SPI_ALLOW (BIT(11))
#define TEE_REG_HP_CORE0_MM_LP_SPI_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_SPI_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_SPI_ALLOW_S)
#define TEE_REG_HP_CORE0_MM_LP_SPI_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_MM_LP_SPI_ALLOW_S 11
/** TEE_REG_HP_CORE0_MM_LP_I2CMST_ALLOW : R/W; bitpos: [12]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_MM_LP_I2CMST_ALLOW (BIT(12))
#define TEE_REG_HP_CORE0_MM_LP_I2CMST_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_I2CMST_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_I2CMST_ALLOW_S)
#define TEE_REG_HP_CORE0_MM_LP_I2CMST_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_MM_LP_I2CMST_ALLOW_S 12
/** TEE_REG_HP_CORE0_MM_LP_I2S_ALLOW : R/W; bitpos: [13]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_MM_LP_I2S_ALLOW (BIT(13))
#define TEE_REG_HP_CORE0_MM_LP_I2S_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_I2S_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_I2S_ALLOW_S)
#define TEE_REG_HP_CORE0_MM_LP_I2S_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_MM_LP_I2S_ALLOW_S 13
/** TEE_REG_HP_CORE0_MM_LP_ADC_ALLOW : R/W; bitpos: [14]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_MM_LP_ADC_ALLOW (BIT(14))
#define TEE_REG_HP_CORE0_MM_LP_ADC_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_ADC_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_ADC_ALLOW_S)
#define TEE_REG_HP_CORE0_MM_LP_ADC_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_MM_LP_ADC_ALLOW_S 14
/** TEE_REG_HP_CORE0_MM_LP_TOUCH_ALLOW : R/W; bitpos: [15]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_MM_LP_TOUCH_ALLOW (BIT(15))
#define TEE_REG_HP_CORE0_MM_LP_TOUCH_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_TOUCH_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_TOUCH_ALLOW_S)
#define TEE_REG_HP_CORE0_MM_LP_TOUCH_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_MM_LP_TOUCH_ALLOW_S 15
/** TEE_REG_HP_CORE0_MM_LP_IOMUX_ALLOW : R/W; bitpos: [16]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_MM_LP_IOMUX_ALLOW (BIT(16))
#define TEE_REG_HP_CORE0_MM_LP_IOMUX_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_IOMUX_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_IOMUX_ALLOW_S)
#define TEE_REG_HP_CORE0_MM_LP_IOMUX_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_MM_LP_IOMUX_ALLOW_S 16
/** TEE_REG_HP_CORE0_MM_LP_INTR_ALLOW : R/W; bitpos: [17]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_MM_LP_INTR_ALLOW (BIT(17))
#define TEE_REG_HP_CORE0_MM_LP_INTR_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_INTR_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_INTR_ALLOW_S)
#define TEE_REG_HP_CORE0_MM_LP_INTR_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_MM_LP_INTR_ALLOW_S 17
/** TEE_REG_HP_CORE0_MM_LP_EFUSE_ALLOW : R/W; bitpos: [18]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_MM_LP_EFUSE_ALLOW (BIT(18))
#define TEE_REG_HP_CORE0_MM_LP_EFUSE_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_EFUSE_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_EFUSE_ALLOW_S)
#define TEE_REG_HP_CORE0_MM_LP_EFUSE_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_MM_LP_EFUSE_ALLOW_S 18
/** TEE_REG_HP_CORE0_MM_LP_PMS_ALLOW : R/W; bitpos: [19]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_MM_LP_PMS_ALLOW (BIT(19))
#define TEE_REG_HP_CORE0_MM_LP_PMS_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_PMS_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_PMS_ALLOW_S)
#define TEE_REG_HP_CORE0_MM_LP_PMS_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_MM_LP_PMS_ALLOW_S 19
/** TEE_REG_HP_CORE0_MM_HP2LP_PMS_ALLOW : R/W; bitpos: [20]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_MM_HP2LP_PMS_ALLOW (BIT(20))
#define TEE_REG_HP_CORE0_MM_HP2LP_PMS_ALLOW_M (TEE_REG_HP_CORE0_MM_HP2LP_PMS_ALLOW_V << TEE_REG_HP_CORE0_MM_HP2LP_PMS_ALLOW_S)
#define TEE_REG_HP_CORE0_MM_HP2LP_PMS_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_MM_HP2LP_PMS_ALLOW_S 20
/** TEE_REG_HP_CORE0_MM_LP_TSENS_ALLOW : R/W; bitpos: [21]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_MM_LP_TSENS_ALLOW (BIT(21))
#define TEE_REG_HP_CORE0_MM_LP_TSENS_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_TSENS_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_TSENS_ALLOW_S)
#define TEE_REG_HP_CORE0_MM_LP_TSENS_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_MM_LP_TSENS_ALLOW_S 21
/** TEE_REG_HP_CORE0_MM_LP_HUK_ALLOW : R/W; bitpos: [22]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_MM_LP_HUK_ALLOW (BIT(22))
#define TEE_REG_HP_CORE0_MM_LP_HUK_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_HUK_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_HUK_ALLOW_S)
#define TEE_REG_HP_CORE0_MM_LP_HUK_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_MM_LP_HUK_ALLOW_S 22
/** TEE_REG_HP_CORE0_MM_LP_TCM_RAM_ALLOW : R/W; bitpos: [23]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_MM_LP_TCM_RAM_ALLOW (BIT(23))
#define TEE_REG_HP_CORE0_MM_LP_TCM_RAM_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_TCM_RAM_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_TCM_RAM_ALLOW_S)
#define TEE_REG_HP_CORE0_MM_LP_TCM_RAM_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_MM_LP_TCM_RAM_ALLOW_S 23
/** TEE_HP_CORE0_UM_PMS_REG0_REG register
* NA
*/
#define TEE_HP_CORE0_UM_PMS_REG0_REG (DR_REG_TEE_BASE + 0xc)
/** TEE_REG_HP_CORE0_UM_LP_SYSREG_ALLOW : R/W; bitpos: [0]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_UM_LP_SYSREG_ALLOW (BIT(0))
#define TEE_REG_HP_CORE0_UM_LP_SYSREG_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_SYSREG_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_SYSREG_ALLOW_S)
#define TEE_REG_HP_CORE0_UM_LP_SYSREG_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_UM_LP_SYSREG_ALLOW_S 0
/** TEE_REG_HP_CORE0_UM_LP_AONCLKRST_ALLOW : R/W; bitpos: [1]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_UM_LP_AONCLKRST_ALLOW (BIT(1))
#define TEE_REG_HP_CORE0_UM_LP_AONCLKRST_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_AONCLKRST_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_AONCLKRST_ALLOW_S)
#define TEE_REG_HP_CORE0_UM_LP_AONCLKRST_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_UM_LP_AONCLKRST_ALLOW_S 1
/** TEE_REG_HP_CORE0_UM_LP_TIMER_ALLOW : R/W; bitpos: [2]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_UM_LP_TIMER_ALLOW (BIT(2))
#define TEE_REG_HP_CORE0_UM_LP_TIMER_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_TIMER_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_TIMER_ALLOW_S)
#define TEE_REG_HP_CORE0_UM_LP_TIMER_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_UM_LP_TIMER_ALLOW_S 2
/** TEE_REG_HP_CORE0_UM_LP_ANAPERI_ALLOW : R/W; bitpos: [3]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_UM_LP_ANAPERI_ALLOW (BIT(3))
#define TEE_REG_HP_CORE0_UM_LP_ANAPERI_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_ANAPERI_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_ANAPERI_ALLOW_S)
#define TEE_REG_HP_CORE0_UM_LP_ANAPERI_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_UM_LP_ANAPERI_ALLOW_S 3
/** TEE_REG_HP_CORE0_UM_LP_PMU_ALLOW : R/W; bitpos: [4]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_UM_LP_PMU_ALLOW (BIT(4))
#define TEE_REG_HP_CORE0_UM_LP_PMU_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_PMU_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_PMU_ALLOW_S)
#define TEE_REG_HP_CORE0_UM_LP_PMU_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_UM_LP_PMU_ALLOW_S 4
/** TEE_REG_HP_CORE0_UM_LP_WDT_ALLOW : R/W; bitpos: [5]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_UM_LP_WDT_ALLOW (BIT(5))
#define TEE_REG_HP_CORE0_UM_LP_WDT_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_WDT_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_WDT_ALLOW_S)
#define TEE_REG_HP_CORE0_UM_LP_WDT_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_UM_LP_WDT_ALLOW_S 5
/** TEE_REG_HP_CORE0_UM_LP_MAILBOX_ALLOW : R/W; bitpos: [6]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_UM_LP_MAILBOX_ALLOW (BIT(6))
#define TEE_REG_HP_CORE0_UM_LP_MAILBOX_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_MAILBOX_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_MAILBOX_ALLOW_S)
#define TEE_REG_HP_CORE0_UM_LP_MAILBOX_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_UM_LP_MAILBOX_ALLOW_S 6
/** TEE_REG_HP_CORE0_UM_LP_RTC_ALLOW : R/W; bitpos: [7]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_UM_LP_RTC_ALLOW (BIT(7))
#define TEE_REG_HP_CORE0_UM_LP_RTC_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_RTC_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_RTC_ALLOW_S)
#define TEE_REG_HP_CORE0_UM_LP_RTC_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_UM_LP_RTC_ALLOW_S 7
/** TEE_REG_HP_CORE0_UM_LP_PERICLKRST_ALLOW : R/W; bitpos: [8]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_UM_LP_PERICLKRST_ALLOW (BIT(8))
#define TEE_REG_HP_CORE0_UM_LP_PERICLKRST_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_PERICLKRST_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_PERICLKRST_ALLOW_S)
#define TEE_REG_HP_CORE0_UM_LP_PERICLKRST_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_UM_LP_PERICLKRST_ALLOW_S 8
/** TEE_REG_HP_CORE0_UM_LP_UART_ALLOW : R/W; bitpos: [9]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_UM_LP_UART_ALLOW (BIT(9))
#define TEE_REG_HP_CORE0_UM_LP_UART_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_UART_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_UART_ALLOW_S)
#define TEE_REG_HP_CORE0_UM_LP_UART_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_UM_LP_UART_ALLOW_S 9
/** TEE_REG_HP_CORE0_UM_LP_I2C_ALLOW : R/W; bitpos: [10]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_UM_LP_I2C_ALLOW (BIT(10))
#define TEE_REG_HP_CORE0_UM_LP_I2C_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_I2C_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_I2C_ALLOW_S)
#define TEE_REG_HP_CORE0_UM_LP_I2C_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_UM_LP_I2C_ALLOW_S 10
/** TEE_REG_HP_CORE0_UM_LP_SPI_ALLOW : R/W; bitpos: [11]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_UM_LP_SPI_ALLOW (BIT(11))
#define TEE_REG_HP_CORE0_UM_LP_SPI_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_SPI_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_SPI_ALLOW_S)
#define TEE_REG_HP_CORE0_UM_LP_SPI_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_UM_LP_SPI_ALLOW_S 11
/** TEE_REG_HP_CORE0_UM_LP_I2CMST_ALLOW : R/W; bitpos: [12]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_UM_LP_I2CMST_ALLOW (BIT(12))
#define TEE_REG_HP_CORE0_UM_LP_I2CMST_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_I2CMST_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_I2CMST_ALLOW_S)
#define TEE_REG_HP_CORE0_UM_LP_I2CMST_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_UM_LP_I2CMST_ALLOW_S 12
/** TEE_REG_HP_CORE0_UM_LP_I2S_ALLOW : R/W; bitpos: [13]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_UM_LP_I2S_ALLOW (BIT(13))
#define TEE_REG_HP_CORE0_UM_LP_I2S_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_I2S_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_I2S_ALLOW_S)
#define TEE_REG_HP_CORE0_UM_LP_I2S_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_UM_LP_I2S_ALLOW_S 13
/** TEE_REG_HP_CORE0_UM_LP_ADC_ALLOW : R/W; bitpos: [14]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_UM_LP_ADC_ALLOW (BIT(14))
#define TEE_REG_HP_CORE0_UM_LP_ADC_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_ADC_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_ADC_ALLOW_S)
#define TEE_REG_HP_CORE0_UM_LP_ADC_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_UM_LP_ADC_ALLOW_S 14
/** TEE_REG_HP_CORE0_UM_LP_TOUCH_ALLOW : R/W; bitpos: [15]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_UM_LP_TOUCH_ALLOW (BIT(15))
#define TEE_REG_HP_CORE0_UM_LP_TOUCH_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_TOUCH_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_TOUCH_ALLOW_S)
#define TEE_REG_HP_CORE0_UM_LP_TOUCH_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_UM_LP_TOUCH_ALLOW_S 15
/** TEE_REG_HP_CORE0_UM_LP_IOMUX_ALLOW : R/W; bitpos: [16]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_UM_LP_IOMUX_ALLOW (BIT(16))
#define TEE_REG_HP_CORE0_UM_LP_IOMUX_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_IOMUX_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_IOMUX_ALLOW_S)
#define TEE_REG_HP_CORE0_UM_LP_IOMUX_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_UM_LP_IOMUX_ALLOW_S 16
/** TEE_REG_HP_CORE0_UM_LP_INTR_ALLOW : R/W; bitpos: [17]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_UM_LP_INTR_ALLOW (BIT(17))
#define TEE_REG_HP_CORE0_UM_LP_INTR_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_INTR_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_INTR_ALLOW_S)
#define TEE_REG_HP_CORE0_UM_LP_INTR_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_UM_LP_INTR_ALLOW_S 17
/** TEE_REG_HP_CORE0_UM_LP_EFUSE_ALLOW : R/W; bitpos: [18]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_UM_LP_EFUSE_ALLOW (BIT(18))
#define TEE_REG_HP_CORE0_UM_LP_EFUSE_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_EFUSE_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_EFUSE_ALLOW_S)
#define TEE_REG_HP_CORE0_UM_LP_EFUSE_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_UM_LP_EFUSE_ALLOW_S 18
/** TEE_REG_HP_CORE0_UM_LP_PMS_ALLOW : R/W; bitpos: [19]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_UM_LP_PMS_ALLOW (BIT(19))
#define TEE_REG_HP_CORE0_UM_LP_PMS_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_PMS_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_PMS_ALLOW_S)
#define TEE_REG_HP_CORE0_UM_LP_PMS_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_UM_LP_PMS_ALLOW_S 19
/** TEE_REG_HP_CORE0_UM_HP2LP_PMS_ALLOW : R/W; bitpos: [20]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_UM_HP2LP_PMS_ALLOW (BIT(20))
#define TEE_REG_HP_CORE0_UM_HP2LP_PMS_ALLOW_M (TEE_REG_HP_CORE0_UM_HP2LP_PMS_ALLOW_V << TEE_REG_HP_CORE0_UM_HP2LP_PMS_ALLOW_S)
#define TEE_REG_HP_CORE0_UM_HP2LP_PMS_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_UM_HP2LP_PMS_ALLOW_S 20
/** TEE_REG_HP_CORE0_UM_LP_TSENS_ALLOW : R/W; bitpos: [21]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_UM_LP_TSENS_ALLOW (BIT(21))
#define TEE_REG_HP_CORE0_UM_LP_TSENS_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_TSENS_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_TSENS_ALLOW_S)
#define TEE_REG_HP_CORE0_UM_LP_TSENS_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_UM_LP_TSENS_ALLOW_S 21
/** TEE_REG_HP_CORE0_UM_LP_HUK_ALLOW : R/W; bitpos: [22]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_UM_LP_HUK_ALLOW (BIT(22))
#define TEE_REG_HP_CORE0_UM_LP_HUK_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_HUK_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_HUK_ALLOW_S)
#define TEE_REG_HP_CORE0_UM_LP_HUK_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_UM_LP_HUK_ALLOW_S 22
/** TEE_REG_HP_CORE0_UM_LP_TCM_RAM_ALLOW : R/W; bitpos: [23]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_UM_LP_TCM_RAM_ALLOW (BIT(23))
#define TEE_REG_HP_CORE0_UM_LP_TCM_RAM_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_TCM_RAM_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_TCM_RAM_ALLOW_S)
#define TEE_REG_HP_CORE0_UM_LP_TCM_RAM_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_UM_LP_TCM_RAM_ALLOW_S 23
/** TEE_HP_CORE1_MM_PMS_REG0_REG register
* NA
*/
#define TEE_HP_CORE1_MM_PMS_REG0_REG (DR_REG_TEE_BASE + 0x10)
/** TEE_REG_HP_CORE1_MM_LP_SYSREG_ALLOW : R/W; bitpos: [0]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_MM_LP_SYSREG_ALLOW (BIT(0))
#define TEE_REG_HP_CORE1_MM_LP_SYSREG_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_SYSREG_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_SYSREG_ALLOW_S)
#define TEE_REG_HP_CORE1_MM_LP_SYSREG_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_MM_LP_SYSREG_ALLOW_S 0
/** TEE_REG_HP_CORE1_MM_LP_AONCLKRST_ALLOW : R/W; bitpos: [1]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_MM_LP_AONCLKRST_ALLOW (BIT(1))
#define TEE_REG_HP_CORE1_MM_LP_AONCLKRST_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_AONCLKRST_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_AONCLKRST_ALLOW_S)
#define TEE_REG_HP_CORE1_MM_LP_AONCLKRST_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_MM_LP_AONCLKRST_ALLOW_S 1
/** TEE_REG_HP_CORE1_MM_LP_TIMER_ALLOW : R/W; bitpos: [2]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_MM_LP_TIMER_ALLOW (BIT(2))
#define TEE_REG_HP_CORE1_MM_LP_TIMER_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_TIMER_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_TIMER_ALLOW_S)
#define TEE_REG_HP_CORE1_MM_LP_TIMER_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_MM_LP_TIMER_ALLOW_S 2
/** TEE_REG_HP_CORE1_MM_LP_ANAPERI_ALLOW : R/W; bitpos: [3]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_MM_LP_ANAPERI_ALLOW (BIT(3))
#define TEE_REG_HP_CORE1_MM_LP_ANAPERI_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_ANAPERI_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_ANAPERI_ALLOW_S)
#define TEE_REG_HP_CORE1_MM_LP_ANAPERI_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_MM_LP_ANAPERI_ALLOW_S 3
/** TEE_REG_HP_CORE1_MM_LP_PMU_ALLOW : R/W; bitpos: [4]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_MM_LP_PMU_ALLOW (BIT(4))
#define TEE_REG_HP_CORE1_MM_LP_PMU_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_PMU_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_PMU_ALLOW_S)
#define TEE_REG_HP_CORE1_MM_LP_PMU_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_MM_LP_PMU_ALLOW_S 4
/** TEE_REG_HP_CORE1_MM_LP_WDT_ALLOW : R/W; bitpos: [5]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_MM_LP_WDT_ALLOW (BIT(5))
#define TEE_REG_HP_CORE1_MM_LP_WDT_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_WDT_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_WDT_ALLOW_S)
#define TEE_REG_HP_CORE1_MM_LP_WDT_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_MM_LP_WDT_ALLOW_S 5
/** TEE_REG_HP_CORE1_MM_LP_MAILBOX_ALLOW : R/W; bitpos: [6]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_MM_LP_MAILBOX_ALLOW (BIT(6))
#define TEE_REG_HP_CORE1_MM_LP_MAILBOX_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_MAILBOX_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_MAILBOX_ALLOW_S)
#define TEE_REG_HP_CORE1_MM_LP_MAILBOX_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_MM_LP_MAILBOX_ALLOW_S 6
/** TEE_REG_HP_CORE1_MM_LP_RTC_ALLOW : R/W; bitpos: [7]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_MM_LP_RTC_ALLOW (BIT(7))
#define TEE_REG_HP_CORE1_MM_LP_RTC_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_RTC_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_RTC_ALLOW_S)
#define TEE_REG_HP_CORE1_MM_LP_RTC_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_MM_LP_RTC_ALLOW_S 7
/** TEE_REG_HP_CORE1_MM_LP_PERICLKRST_ALLOW : R/W; bitpos: [8]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_MM_LP_PERICLKRST_ALLOW (BIT(8))
#define TEE_REG_HP_CORE1_MM_LP_PERICLKRST_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_PERICLKRST_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_PERICLKRST_ALLOW_S)
#define TEE_REG_HP_CORE1_MM_LP_PERICLKRST_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_MM_LP_PERICLKRST_ALLOW_S 8
/** TEE_REG_HP_CORE1_MM_LP_UART_ALLOW : R/W; bitpos: [9]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_MM_LP_UART_ALLOW (BIT(9))
#define TEE_REG_HP_CORE1_MM_LP_UART_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_UART_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_UART_ALLOW_S)
#define TEE_REG_HP_CORE1_MM_LP_UART_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_MM_LP_UART_ALLOW_S 9
/** TEE_REG_HP_CORE1_MM_LP_I2C_ALLOW : R/W; bitpos: [10]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_MM_LP_I2C_ALLOW (BIT(10))
#define TEE_REG_HP_CORE1_MM_LP_I2C_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_I2C_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_I2C_ALLOW_S)
#define TEE_REG_HP_CORE1_MM_LP_I2C_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_MM_LP_I2C_ALLOW_S 10
/** TEE_REG_HP_CORE1_MM_LP_SPI_ALLOW : R/W; bitpos: [11]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_MM_LP_SPI_ALLOW (BIT(11))
#define TEE_REG_HP_CORE1_MM_LP_SPI_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_SPI_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_SPI_ALLOW_S)
#define TEE_REG_HP_CORE1_MM_LP_SPI_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_MM_LP_SPI_ALLOW_S 11
/** TEE_REG_HP_CORE1_MM_LP_I2CMST_ALLOW : R/W; bitpos: [12]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_MM_LP_I2CMST_ALLOW (BIT(12))
#define TEE_REG_HP_CORE1_MM_LP_I2CMST_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_I2CMST_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_I2CMST_ALLOW_S)
#define TEE_REG_HP_CORE1_MM_LP_I2CMST_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_MM_LP_I2CMST_ALLOW_S 12
/** TEE_REG_HP_CORE1_MM_LP_I2S_ALLOW : R/W; bitpos: [13]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_MM_LP_I2S_ALLOW (BIT(13))
#define TEE_REG_HP_CORE1_MM_LP_I2S_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_I2S_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_I2S_ALLOW_S)
#define TEE_REG_HP_CORE1_MM_LP_I2S_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_MM_LP_I2S_ALLOW_S 13
/** TEE_REG_HP_CORE1_MM_LP_ADC_ALLOW : R/W; bitpos: [14]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_MM_LP_ADC_ALLOW (BIT(14))
#define TEE_REG_HP_CORE1_MM_LP_ADC_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_ADC_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_ADC_ALLOW_S)
#define TEE_REG_HP_CORE1_MM_LP_ADC_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_MM_LP_ADC_ALLOW_S 14
/** TEE_REG_HP_CORE1_MM_LP_TOUCH_ALLOW : R/W; bitpos: [15]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_MM_LP_TOUCH_ALLOW (BIT(15))
#define TEE_REG_HP_CORE1_MM_LP_TOUCH_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_TOUCH_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_TOUCH_ALLOW_S)
#define TEE_REG_HP_CORE1_MM_LP_TOUCH_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_MM_LP_TOUCH_ALLOW_S 15
/** TEE_REG_HP_CORE1_MM_LP_IOMUX_ALLOW : R/W; bitpos: [16]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_MM_LP_IOMUX_ALLOW (BIT(16))
#define TEE_REG_HP_CORE1_MM_LP_IOMUX_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_IOMUX_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_IOMUX_ALLOW_S)
#define TEE_REG_HP_CORE1_MM_LP_IOMUX_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_MM_LP_IOMUX_ALLOW_S 16
/** TEE_REG_HP_CORE1_MM_LP_INTR_ALLOW : R/W; bitpos: [17]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_MM_LP_INTR_ALLOW (BIT(17))
#define TEE_REG_HP_CORE1_MM_LP_INTR_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_INTR_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_INTR_ALLOW_S)
#define TEE_REG_HP_CORE1_MM_LP_INTR_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_MM_LP_INTR_ALLOW_S 17
/** TEE_REG_HP_CORE1_MM_LP_EFUSE_ALLOW : R/W; bitpos: [18]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_MM_LP_EFUSE_ALLOW (BIT(18))
#define TEE_REG_HP_CORE1_MM_LP_EFUSE_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_EFUSE_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_EFUSE_ALLOW_S)
#define TEE_REG_HP_CORE1_MM_LP_EFUSE_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_MM_LP_EFUSE_ALLOW_S 18
/** TEE_REG_HP_CORE1_MM_LP_PMS_ALLOW : R/W; bitpos: [19]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_MM_LP_PMS_ALLOW (BIT(19))
#define TEE_REG_HP_CORE1_MM_LP_PMS_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_PMS_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_PMS_ALLOW_S)
#define TEE_REG_HP_CORE1_MM_LP_PMS_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_MM_LP_PMS_ALLOW_S 19
/** TEE_REG_HP_CORE1_MM_HP2LP_PMS_ALLOW : R/W; bitpos: [20]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_MM_HP2LP_PMS_ALLOW (BIT(20))
#define TEE_REG_HP_CORE1_MM_HP2LP_PMS_ALLOW_M (TEE_REG_HP_CORE1_MM_HP2LP_PMS_ALLOW_V << TEE_REG_HP_CORE1_MM_HP2LP_PMS_ALLOW_S)
#define TEE_REG_HP_CORE1_MM_HP2LP_PMS_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_MM_HP2LP_PMS_ALLOW_S 20
/** TEE_REG_HP_CORE1_MM_LP_TSENS_ALLOW : R/W; bitpos: [21]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_MM_LP_TSENS_ALLOW (BIT(21))
#define TEE_REG_HP_CORE1_MM_LP_TSENS_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_TSENS_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_TSENS_ALLOW_S)
#define TEE_REG_HP_CORE1_MM_LP_TSENS_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_MM_LP_TSENS_ALLOW_S 21
/** TEE_REG_HP_CORE1_MM_LP_HUK_ALLOW : R/W; bitpos: [22]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_MM_LP_HUK_ALLOW (BIT(22))
#define TEE_REG_HP_CORE1_MM_LP_HUK_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_HUK_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_HUK_ALLOW_S)
#define TEE_REG_HP_CORE1_MM_LP_HUK_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_MM_LP_HUK_ALLOW_S 22
/** TEE_REG_HP_CORE1_MM_LP_TCM_RAM_ALLOW : R/W; bitpos: [23]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_MM_LP_TCM_RAM_ALLOW (BIT(23))
#define TEE_REG_HP_CORE1_MM_LP_TCM_RAM_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_TCM_RAM_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_TCM_RAM_ALLOW_S)
#define TEE_REG_HP_CORE1_MM_LP_TCM_RAM_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_MM_LP_TCM_RAM_ALLOW_S 23
/** TEE_HP_CORE1_UM_PMS_REG0_REG register
* NA
*/
#define TEE_HP_CORE1_UM_PMS_REG0_REG (DR_REG_TEE_BASE + 0x14)
/** TEE_REG_HP_CORE1_UM_LP_SYSREG_ALLOW : R/W; bitpos: [0]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_UM_LP_SYSREG_ALLOW (BIT(0))
#define TEE_REG_HP_CORE1_UM_LP_SYSREG_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_SYSREG_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_SYSREG_ALLOW_S)
#define TEE_REG_HP_CORE1_UM_LP_SYSREG_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_UM_LP_SYSREG_ALLOW_S 0
/** TEE_REG_HP_CORE1_UM_LP_AONCLKRST_ALLOW : R/W; bitpos: [1]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_UM_LP_AONCLKRST_ALLOW (BIT(1))
#define TEE_REG_HP_CORE1_UM_LP_AONCLKRST_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_AONCLKRST_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_AONCLKRST_ALLOW_S)
#define TEE_REG_HP_CORE1_UM_LP_AONCLKRST_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_UM_LP_AONCLKRST_ALLOW_S 1
/** TEE_REG_HP_CORE1_UM_LP_TIMER_ALLOW : R/W; bitpos: [2]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_UM_LP_TIMER_ALLOW (BIT(2))
#define TEE_REG_HP_CORE1_UM_LP_TIMER_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_TIMER_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_TIMER_ALLOW_S)
#define TEE_REG_HP_CORE1_UM_LP_TIMER_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_UM_LP_TIMER_ALLOW_S 2
/** TEE_REG_HP_CORE1_UM_LP_ANAPERI_ALLOW : R/W; bitpos: [3]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_UM_LP_ANAPERI_ALLOW (BIT(3))
#define TEE_REG_HP_CORE1_UM_LP_ANAPERI_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_ANAPERI_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_ANAPERI_ALLOW_S)
#define TEE_REG_HP_CORE1_UM_LP_ANAPERI_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_UM_LP_ANAPERI_ALLOW_S 3
/** TEE_REG_HP_CORE1_UM_LP_PMU_ALLOW : R/W; bitpos: [4]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_UM_LP_PMU_ALLOW (BIT(4))
#define TEE_REG_HP_CORE1_UM_LP_PMU_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_PMU_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_PMU_ALLOW_S)
#define TEE_REG_HP_CORE1_UM_LP_PMU_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_UM_LP_PMU_ALLOW_S 4
/** TEE_REG_HP_CORE1_UM_LP_WDT_ALLOW : R/W; bitpos: [5]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_UM_LP_WDT_ALLOW (BIT(5))
#define TEE_REG_HP_CORE1_UM_LP_WDT_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_WDT_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_WDT_ALLOW_S)
#define TEE_REG_HP_CORE1_UM_LP_WDT_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_UM_LP_WDT_ALLOW_S 5
/** TEE_REG_HP_CORE1_UM_LP_MAILBOX_ALLOW : R/W; bitpos: [6]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_UM_LP_MAILBOX_ALLOW (BIT(6))
#define TEE_REG_HP_CORE1_UM_LP_MAILBOX_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_MAILBOX_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_MAILBOX_ALLOW_S)
#define TEE_REG_HP_CORE1_UM_LP_MAILBOX_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_UM_LP_MAILBOX_ALLOW_S 6
/** TEE_REG_HP_CORE1_UM_LP_RTC_ALLOW : R/W; bitpos: [7]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_UM_LP_RTC_ALLOW (BIT(7))
#define TEE_REG_HP_CORE1_UM_LP_RTC_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_RTC_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_RTC_ALLOW_S)
#define TEE_REG_HP_CORE1_UM_LP_RTC_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_UM_LP_RTC_ALLOW_S 7
/** TEE_REG_HP_CORE1_UM_LP_PERICLKRST_ALLOW : R/W; bitpos: [8]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_UM_LP_PERICLKRST_ALLOW (BIT(8))
#define TEE_REG_HP_CORE1_UM_LP_PERICLKRST_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_PERICLKRST_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_PERICLKRST_ALLOW_S)
#define TEE_REG_HP_CORE1_UM_LP_PERICLKRST_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_UM_LP_PERICLKRST_ALLOW_S 8
/** TEE_REG_HP_CORE1_UM_LP_UART_ALLOW : R/W; bitpos: [9]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_UM_LP_UART_ALLOW (BIT(9))
#define TEE_REG_HP_CORE1_UM_LP_UART_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_UART_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_UART_ALLOW_S)
#define TEE_REG_HP_CORE1_UM_LP_UART_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_UM_LP_UART_ALLOW_S 9
/** TEE_REG_HP_CORE1_UM_LP_I2C_ALLOW : R/W; bitpos: [10]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_UM_LP_I2C_ALLOW (BIT(10))
#define TEE_REG_HP_CORE1_UM_LP_I2C_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_I2C_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_I2C_ALLOW_S)
#define TEE_REG_HP_CORE1_UM_LP_I2C_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_UM_LP_I2C_ALLOW_S 10
/** TEE_REG_HP_CORE1_UM_LP_SPI_ALLOW : R/W; bitpos: [11]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_UM_LP_SPI_ALLOW (BIT(11))
#define TEE_REG_HP_CORE1_UM_LP_SPI_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_SPI_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_SPI_ALLOW_S)
#define TEE_REG_HP_CORE1_UM_LP_SPI_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_UM_LP_SPI_ALLOW_S 11
/** TEE_REG_HP_CORE1_UM_LP_I2CMST_ALLOW : R/W; bitpos: [12]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_UM_LP_I2CMST_ALLOW (BIT(12))
#define TEE_REG_HP_CORE1_UM_LP_I2CMST_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_I2CMST_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_I2CMST_ALLOW_S)
#define TEE_REG_HP_CORE1_UM_LP_I2CMST_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_UM_LP_I2CMST_ALLOW_S 12
/** TEE_REG_HP_CORE1_UM_LP_I2S_ALLOW : R/W; bitpos: [13]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_UM_LP_I2S_ALLOW (BIT(13))
#define TEE_REG_HP_CORE1_UM_LP_I2S_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_I2S_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_I2S_ALLOW_S)
#define TEE_REG_HP_CORE1_UM_LP_I2S_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_UM_LP_I2S_ALLOW_S 13
/** TEE_REG_HP_CORE1_UM_LP_ADC_ALLOW : R/W; bitpos: [14]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_UM_LP_ADC_ALLOW (BIT(14))
#define TEE_REG_HP_CORE1_UM_LP_ADC_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_ADC_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_ADC_ALLOW_S)
#define TEE_REG_HP_CORE1_UM_LP_ADC_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_UM_LP_ADC_ALLOW_S 14
/** TEE_REG_HP_CORE1_UM_LP_TOUCH_ALLOW : R/W; bitpos: [15]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_UM_LP_TOUCH_ALLOW (BIT(15))
#define TEE_REG_HP_CORE1_UM_LP_TOUCH_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_TOUCH_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_TOUCH_ALLOW_S)
#define TEE_REG_HP_CORE1_UM_LP_TOUCH_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_UM_LP_TOUCH_ALLOW_S 15
/** TEE_REG_HP_CORE1_UM_LP_IOMUX_ALLOW : R/W; bitpos: [16]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_UM_LP_IOMUX_ALLOW (BIT(16))
#define TEE_REG_HP_CORE1_UM_LP_IOMUX_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_IOMUX_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_IOMUX_ALLOW_S)
#define TEE_REG_HP_CORE1_UM_LP_IOMUX_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_UM_LP_IOMUX_ALLOW_S 16
/** TEE_REG_HP_CORE1_UM_LP_INTR_ALLOW : R/W; bitpos: [17]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_UM_LP_INTR_ALLOW (BIT(17))
#define TEE_REG_HP_CORE1_UM_LP_INTR_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_INTR_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_INTR_ALLOW_S)
#define TEE_REG_HP_CORE1_UM_LP_INTR_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_UM_LP_INTR_ALLOW_S 17
/** TEE_REG_HP_CORE1_UM_LP_EFUSE_ALLOW : R/W; bitpos: [18]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_UM_LP_EFUSE_ALLOW (BIT(18))
#define TEE_REG_HP_CORE1_UM_LP_EFUSE_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_EFUSE_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_EFUSE_ALLOW_S)
#define TEE_REG_HP_CORE1_UM_LP_EFUSE_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_UM_LP_EFUSE_ALLOW_S 18
/** TEE_REG_HP_CORE1_UM_LP_PMS_ALLOW : R/W; bitpos: [19]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_UM_LP_PMS_ALLOW (BIT(19))
#define TEE_REG_HP_CORE1_UM_LP_PMS_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_PMS_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_PMS_ALLOW_S)
#define TEE_REG_HP_CORE1_UM_LP_PMS_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_UM_LP_PMS_ALLOW_S 19
/** TEE_REG_HP_CORE1_UM_HP2LP_PMS_ALLOW : R/W; bitpos: [20]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_UM_HP2LP_PMS_ALLOW (BIT(20))
#define TEE_REG_HP_CORE1_UM_HP2LP_PMS_ALLOW_M (TEE_REG_HP_CORE1_UM_HP2LP_PMS_ALLOW_V << TEE_REG_HP_CORE1_UM_HP2LP_PMS_ALLOW_S)
#define TEE_REG_HP_CORE1_UM_HP2LP_PMS_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_UM_HP2LP_PMS_ALLOW_S 20
/** TEE_REG_HP_CORE1_UM_LP_TSENS_ALLOW : R/W; bitpos: [21]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_UM_LP_TSENS_ALLOW (BIT(21))
#define TEE_REG_HP_CORE1_UM_LP_TSENS_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_TSENS_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_TSENS_ALLOW_S)
#define TEE_REG_HP_CORE1_UM_LP_TSENS_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_UM_LP_TSENS_ALLOW_S 21
/** TEE_REG_HP_CORE1_UM_LP_HUK_ALLOW : R/W; bitpos: [22]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_UM_LP_HUK_ALLOW (BIT(22))
#define TEE_REG_HP_CORE1_UM_LP_HUK_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_HUK_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_HUK_ALLOW_S)
#define TEE_REG_HP_CORE1_UM_LP_HUK_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_UM_LP_HUK_ALLOW_S 22
/** TEE_REG_HP_CORE1_UM_LP_TCM_RAM_ALLOW : R/W; bitpos: [23]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_UM_LP_TCM_RAM_ALLOW (BIT(23))
#define TEE_REG_HP_CORE1_UM_LP_TCM_RAM_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_TCM_RAM_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_TCM_RAM_ALLOW_S)
#define TEE_REG_HP_CORE1_UM_LP_TCM_RAM_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_UM_LP_TCM_RAM_ALLOW_S 23
/** TEE_REGDMA_PERI_PMS_REG register
* NA
*/
#define TEE_REGDMA_PERI_PMS_REG (DR_REG_TEE_BASE + 0x18)
/** TEE_REG_REGDMA_PERI_LP_RAM_ALLOW : R/W; bitpos: [0]; default: 1;
* NA
*/
#define TEE_REG_REGDMA_PERI_LP_RAM_ALLOW (BIT(0))
#define TEE_REG_REGDMA_PERI_LP_RAM_ALLOW_M (TEE_REG_REGDMA_PERI_LP_RAM_ALLOW_V << TEE_REG_REGDMA_PERI_LP_RAM_ALLOW_S)
#define TEE_REG_REGDMA_PERI_LP_RAM_ALLOW_V 0x00000001U
#define TEE_REG_REGDMA_PERI_LP_RAM_ALLOW_S 0
/** TEE_REG_REGDMA_PERI_LP_PERI_ALLOW : R/W; bitpos: [1]; default: 1;
* NA
*/
#define TEE_REG_REGDMA_PERI_LP_PERI_ALLOW (BIT(1))
#define TEE_REG_REGDMA_PERI_LP_PERI_ALLOW_M (TEE_REG_REGDMA_PERI_LP_PERI_ALLOW_V << TEE_REG_REGDMA_PERI_LP_PERI_ALLOW_S)
#define TEE_REG_REGDMA_PERI_LP_PERI_ALLOW_V 0x00000001U
#define TEE_REG_REGDMA_PERI_LP_PERI_ALLOW_S 1
#ifdef __cplusplus
}
#endif

513
components/soc/esp32p4/include/soc/hp2lp_peri_pms_struct.h Normal file
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@@ -0,0 +1,513 @@
/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: TEE HP2LP TEE PMS DATE REG */
/** Type of hp2lp_tee_pms_date register
* NA
*/
typedef union {
struct {
/** tee_date : R/W; bitpos: [31:0]; default: 2294790;
* NA
*/
uint32_t tee_date:32;
};
uint32_t val;
} tee_hp2lp_tee_pms_date_reg_t;
/** Group: TEE PMS CLK EN REG */
/** Type of pms_clk_en register
* NA
*/
typedef union {
struct {
/** reg_clk_en : R/W; bitpos: [0]; default: 1;
* NA
*/
uint32_t reg_clk_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} tee_pms_clk_en_reg_t;
/** Group: TEE HP CORE0 MM PMS REG0 REG */
/** Type of hp_core0_mm_pms_reg0 register
* NA
*/
typedef union {
struct {
/** reg_hp_core0_mm_lp_sysreg_allow : R/W; bitpos: [0]; default: 1;
* NA
*/
uint32_t reg_hp_core0_mm_lp_sysreg_allow:1;
/** reg_hp_core0_mm_lp_aonclkrst_allow : R/W; bitpos: [1]; default: 1;
* NA
*/
uint32_t reg_hp_core0_mm_lp_aonclkrst_allow:1;
/** reg_hp_core0_mm_lp_timer_allow : R/W; bitpos: [2]; default: 1;
* NA
*/
uint32_t reg_hp_core0_mm_lp_timer_allow:1;
/** reg_hp_core0_mm_lp_anaperi_allow : R/W; bitpos: [3]; default: 1;
* NA
*/
uint32_t reg_hp_core0_mm_lp_anaperi_allow:1;
/** reg_hp_core0_mm_lp_pmu_allow : R/W; bitpos: [4]; default: 1;
* NA
*/
uint32_t reg_hp_core0_mm_lp_pmu_allow:1;
/** reg_hp_core0_mm_lp_wdt_allow : R/W; bitpos: [5]; default: 1;
* NA
*/
uint32_t reg_hp_core0_mm_lp_wdt_allow:1;
/** reg_hp_core0_mm_lp_mailbox_allow : R/W; bitpos: [6]; default: 1;
* NA
*/
uint32_t reg_hp_core0_mm_lp_mailbox_allow:1;
/** reg_hp_core0_mm_lp_rtc_allow : R/W; bitpos: [7]; default: 1;
* NA
*/
uint32_t reg_hp_core0_mm_lp_rtc_allow:1;
/** reg_hp_core0_mm_lp_periclkrst_allow : R/W; bitpos: [8]; default: 1;
* NA
*/
uint32_t reg_hp_core0_mm_lp_periclkrst_allow:1;
/** reg_hp_core0_mm_lp_uart_allow : R/W; bitpos: [9]; default: 1;
* NA
*/
uint32_t reg_hp_core0_mm_lp_uart_allow:1;
/** reg_hp_core0_mm_lp_i2c_allow : R/W; bitpos: [10]; default: 1;
* NA
*/
uint32_t reg_hp_core0_mm_lp_i2c_allow:1;
/** reg_hp_core0_mm_lp_spi_allow : R/W; bitpos: [11]; default: 1;
* NA
*/
uint32_t reg_hp_core0_mm_lp_spi_allow:1;
/** reg_hp_core0_mm_lp_i2cmst_allow : R/W; bitpos: [12]; default: 1;
* NA
*/
uint32_t reg_hp_core0_mm_lp_i2cmst_allow:1;
/** reg_hp_core0_mm_lp_i2s_allow : R/W; bitpos: [13]; default: 1;
* NA
*/
uint32_t reg_hp_core0_mm_lp_i2s_allow:1;
/** reg_hp_core0_mm_lp_adc_allow : R/W; bitpos: [14]; default: 1;
* NA
*/
uint32_t reg_hp_core0_mm_lp_adc_allow:1;
/** reg_hp_core0_mm_lp_touch_allow : R/W; bitpos: [15]; default: 1;
* NA
*/
uint32_t reg_hp_core0_mm_lp_touch_allow:1;
/** reg_hp_core0_mm_lp_iomux_allow : R/W; bitpos: [16]; default: 1;
* NA
*/
uint32_t reg_hp_core0_mm_lp_iomux_allow:1;
/** reg_hp_core0_mm_lp_intr_allow : R/W; bitpos: [17]; default: 1;
* NA
*/
uint32_t reg_hp_core0_mm_lp_intr_allow:1;
/** reg_hp_core0_mm_lp_efuse_allow : R/W; bitpos: [18]; default: 1;
* NA
*/
uint32_t reg_hp_core0_mm_lp_efuse_allow:1;
/** reg_hp_core0_mm_lp_pms_allow : R/W; bitpos: [19]; default: 1;
* NA
*/
uint32_t reg_hp_core0_mm_lp_pms_allow:1;
/** reg_hp_core0_mm_hp2lp_pms_allow : R/W; bitpos: [20]; default: 1;
* NA
*/
uint32_t reg_hp_core0_mm_hp2lp_pms_allow:1;
/** reg_hp_core0_mm_lp_tsens_allow : R/W; bitpos: [21]; default: 1;
* NA
*/
uint32_t reg_hp_core0_mm_lp_tsens_allow:1;
/** reg_hp_core0_mm_lp_huk_allow : R/W; bitpos: [22]; default: 1;
* NA
*/
uint32_t reg_hp_core0_mm_lp_huk_allow:1;
/** reg_hp_core0_mm_lp_tcm_ram_allow : R/W; bitpos: [23]; default: 1;
* NA
*/
uint32_t reg_hp_core0_mm_lp_tcm_ram_allow:1;
uint32_t reserved_24:8;
};
uint32_t val;
} tee_hp_core0_mm_pms_reg0_reg_t;
/** Group: TEE HP CORE0 UM PMS REG0 REG */
/** Type of hp_core0_um_pms_reg0 register
* NA
*/
typedef union {
struct {
/** reg_hp_core0_um_lp_sysreg_allow : R/W; bitpos: [0]; default: 1;
* NA
*/
uint32_t reg_hp_core0_um_lp_sysreg_allow:1;
/** reg_hp_core0_um_lp_aonclkrst_allow : R/W; bitpos: [1]; default: 1;
* NA
*/
uint32_t reg_hp_core0_um_lp_aonclkrst_allow:1;
/** reg_hp_core0_um_lp_timer_allow : R/W; bitpos: [2]; default: 1;
* NA
*/
uint32_t reg_hp_core0_um_lp_timer_allow:1;
/** reg_hp_core0_um_lp_anaperi_allow : R/W; bitpos: [3]; default: 1;
* NA
*/
uint32_t reg_hp_core0_um_lp_anaperi_allow:1;
/** reg_hp_core0_um_lp_pmu_allow : R/W; bitpos: [4]; default: 1;
* NA
*/
uint32_t reg_hp_core0_um_lp_pmu_allow:1;
/** reg_hp_core0_um_lp_wdt_allow : R/W; bitpos: [5]; default: 1;
* NA
*/
uint32_t reg_hp_core0_um_lp_wdt_allow:1;
/** reg_hp_core0_um_lp_mailbox_allow : R/W; bitpos: [6]; default: 1;
* NA
*/
uint32_t reg_hp_core0_um_lp_mailbox_allow:1;
/** reg_hp_core0_um_lp_rtc_allow : R/W; bitpos: [7]; default: 1;
* NA
*/
uint32_t reg_hp_core0_um_lp_rtc_allow:1;
/** reg_hp_core0_um_lp_periclkrst_allow : R/W; bitpos: [8]; default: 1;
* NA
*/
uint32_t reg_hp_core0_um_lp_periclkrst_allow:1;
/** reg_hp_core0_um_lp_uart_allow : R/W; bitpos: [9]; default: 1;
* NA
*/
uint32_t reg_hp_core0_um_lp_uart_allow:1;
/** reg_hp_core0_um_lp_i2c_allow : R/W; bitpos: [10]; default: 1;
* NA
*/
uint32_t reg_hp_core0_um_lp_i2c_allow:1;
/** reg_hp_core0_um_lp_spi_allow : R/W; bitpos: [11]; default: 1;
* NA
*/
uint32_t reg_hp_core0_um_lp_spi_allow:1;
/** reg_hp_core0_um_lp_i2cmst_allow : R/W; bitpos: [12]; default: 1;
* NA
*/
uint32_t reg_hp_core0_um_lp_i2cmst_allow:1;
/** reg_hp_core0_um_lp_i2s_allow : R/W; bitpos: [13]; default: 1;
* NA
*/
uint32_t reg_hp_core0_um_lp_i2s_allow:1;
/** reg_hp_core0_um_lp_adc_allow : R/W; bitpos: [14]; default: 1;
* NA
*/
uint32_t reg_hp_core0_um_lp_adc_allow:1;
/** reg_hp_core0_um_lp_touch_allow : R/W; bitpos: [15]; default: 1;
* NA
*/
uint32_t reg_hp_core0_um_lp_touch_allow:1;
/** reg_hp_core0_um_lp_iomux_allow : R/W; bitpos: [16]; default: 1;
* NA
*/
uint32_t reg_hp_core0_um_lp_iomux_allow:1;
/** reg_hp_core0_um_lp_intr_allow : R/W; bitpos: [17]; default: 1;
* NA
*/
uint32_t reg_hp_core0_um_lp_intr_allow:1;
/** reg_hp_core0_um_lp_efuse_allow : R/W; bitpos: [18]; default: 1;
* NA
*/
uint32_t reg_hp_core0_um_lp_efuse_allow:1;
/** reg_hp_core0_um_lp_pms_allow : R/W; bitpos: [19]; default: 1;
* NA
*/
uint32_t reg_hp_core0_um_lp_pms_allow:1;
/** reg_hp_core0_um_hp2lp_pms_allow : R/W; bitpos: [20]; default: 1;
* NA
*/
uint32_t reg_hp_core0_um_hp2lp_pms_allow:1;
/** reg_hp_core0_um_lp_tsens_allow : R/W; bitpos: [21]; default: 1;
* NA
*/
uint32_t reg_hp_core0_um_lp_tsens_allow:1;
/** reg_hp_core0_um_lp_huk_allow : R/W; bitpos: [22]; default: 1;
* NA
*/
uint32_t reg_hp_core0_um_lp_huk_allow:1;
/** reg_hp_core0_um_lp_tcm_ram_allow : R/W; bitpos: [23]; default: 1;
* NA
*/
uint32_t reg_hp_core0_um_lp_tcm_ram_allow:1;
uint32_t reserved_24:8;
};
uint32_t val;
} tee_hp_core0_um_pms_reg0_reg_t;
/** Group: TEE HP CORE1 MM PMS REG0 REG */
/** Type of hp_core1_mm_pms_reg0 register
* NA
*/
typedef union {
struct {
/** reg_hp_core1_mm_lp_sysreg_allow : R/W; bitpos: [0]; default: 1;
* NA
*/
uint32_t reg_hp_core1_mm_lp_sysreg_allow:1;
/** reg_hp_core1_mm_lp_aonclkrst_allow : R/W; bitpos: [1]; default: 1;
* NA
*/
uint32_t reg_hp_core1_mm_lp_aonclkrst_allow:1;
/** reg_hp_core1_mm_lp_timer_allow : R/W; bitpos: [2]; default: 1;
* NA
*/
uint32_t reg_hp_core1_mm_lp_timer_allow:1;
/** reg_hp_core1_mm_lp_anaperi_allow : R/W; bitpos: [3]; default: 1;
* NA
*/
uint32_t reg_hp_core1_mm_lp_anaperi_allow:1;
/** reg_hp_core1_mm_lp_pmu_allow : R/W; bitpos: [4]; default: 1;
* NA
*/
uint32_t reg_hp_core1_mm_lp_pmu_allow:1;
/** reg_hp_core1_mm_lp_wdt_allow : R/W; bitpos: [5]; default: 1;
* NA
*/
uint32_t reg_hp_core1_mm_lp_wdt_allow:1;
/** reg_hp_core1_mm_lp_mailbox_allow : R/W; bitpos: [6]; default: 1;
* NA
*/
uint32_t reg_hp_core1_mm_lp_mailbox_allow:1;
/** reg_hp_core1_mm_lp_rtc_allow : R/W; bitpos: [7]; default: 1;
* NA
*/
uint32_t reg_hp_core1_mm_lp_rtc_allow:1;
/** reg_hp_core1_mm_lp_periclkrst_allow : R/W; bitpos: [8]; default: 1;
* NA
*/
uint32_t reg_hp_core1_mm_lp_periclkrst_allow:1;
/** reg_hp_core1_mm_lp_uart_allow : R/W; bitpos: [9]; default: 1;
* NA
*/
uint32_t reg_hp_core1_mm_lp_uart_allow:1;
/** reg_hp_core1_mm_lp_i2c_allow : R/W; bitpos: [10]; default: 1;
* NA
*/
uint32_t reg_hp_core1_mm_lp_i2c_allow:1;
/** reg_hp_core1_mm_lp_spi_allow : R/W; bitpos: [11]; default: 1;
* NA
*/
uint32_t reg_hp_core1_mm_lp_spi_allow:1;
/** reg_hp_core1_mm_lp_i2cmst_allow : R/W; bitpos: [12]; default: 1;
* NA
*/
uint32_t reg_hp_core1_mm_lp_i2cmst_allow:1;
/** reg_hp_core1_mm_lp_i2s_allow : R/W; bitpos: [13]; default: 1;
* NA
*/
uint32_t reg_hp_core1_mm_lp_i2s_allow:1;
/** reg_hp_core1_mm_lp_adc_allow : R/W; bitpos: [14]; default: 1;
* NA
*/
uint32_t reg_hp_core1_mm_lp_adc_allow:1;
/** reg_hp_core1_mm_lp_touch_allow : R/W; bitpos: [15]; default: 1;
* NA
*/
uint32_t reg_hp_core1_mm_lp_touch_allow:1;
/** reg_hp_core1_mm_lp_iomux_allow : R/W; bitpos: [16]; default: 1;
* NA
*/
uint32_t reg_hp_core1_mm_lp_iomux_allow:1;
/** reg_hp_core1_mm_lp_intr_allow : R/W; bitpos: [17]; default: 1;
* NA
*/
uint32_t reg_hp_core1_mm_lp_intr_allow:1;
/** reg_hp_core1_mm_lp_efuse_allow : R/W; bitpos: [18]; default: 1;
* NA
*/
uint32_t reg_hp_core1_mm_lp_efuse_allow:1;
/** reg_hp_core1_mm_lp_pms_allow : R/W; bitpos: [19]; default: 1;
* NA
*/
uint32_t reg_hp_core1_mm_lp_pms_allow:1;
/** reg_hp_core1_mm_hp2lp_pms_allow : R/W; bitpos: [20]; default: 1;
* NA
*/
uint32_t reg_hp_core1_mm_hp2lp_pms_allow:1;
/** reg_hp_core1_mm_lp_tsens_allow : R/W; bitpos: [21]; default: 1;
* NA
*/
uint32_t reg_hp_core1_mm_lp_tsens_allow:1;
/** reg_hp_core1_mm_lp_huk_allow : R/W; bitpos: [22]; default: 1;
* NA
*/
uint32_t reg_hp_core1_mm_lp_huk_allow:1;
/** reg_hp_core1_mm_lp_tcm_ram_allow : R/W; bitpos: [23]; default: 1;
* NA
*/
uint32_t reg_hp_core1_mm_lp_tcm_ram_allow:1;
uint32_t reserved_24:8;
};
uint32_t val;
} tee_hp_core1_mm_pms_reg0_reg_t;
/** Group: TEE HP CORE1 UM PMS REG0 REG */
/** Type of hp_core1_um_pms_reg0 register
* NA
*/
typedef union {
struct {
/** reg_hp_core1_um_lp_sysreg_allow : R/W; bitpos: [0]; default: 1;
* NA
*/
uint32_t reg_hp_core1_um_lp_sysreg_allow:1;
/** reg_hp_core1_um_lp_aonclkrst_allow : R/W; bitpos: [1]; default: 1;
* NA
*/
uint32_t reg_hp_core1_um_lp_aonclkrst_allow:1;
/** reg_hp_core1_um_lp_timer_allow : R/W; bitpos: [2]; default: 1;
* NA
*/
uint32_t reg_hp_core1_um_lp_timer_allow:1;
/** reg_hp_core1_um_lp_anaperi_allow : R/W; bitpos: [3]; default: 1;
* NA
*/
uint32_t reg_hp_core1_um_lp_anaperi_allow:1;
/** reg_hp_core1_um_lp_pmu_allow : R/W; bitpos: [4]; default: 1;
* NA
*/
uint32_t reg_hp_core1_um_lp_pmu_allow:1;
/** reg_hp_core1_um_lp_wdt_allow : R/W; bitpos: [5]; default: 1;
* NA
*/
uint32_t reg_hp_core1_um_lp_wdt_allow:1;
/** reg_hp_core1_um_lp_mailbox_allow : R/W; bitpos: [6]; default: 1;
* NA
*/
uint32_t reg_hp_core1_um_lp_mailbox_allow:1;
/** reg_hp_core1_um_lp_rtc_allow : R/W; bitpos: [7]; default: 1;
* NA
*/
uint32_t reg_hp_core1_um_lp_rtc_allow:1;
/** reg_hp_core1_um_lp_periclkrst_allow : R/W; bitpos: [8]; default: 1;
* NA
*/
uint32_t reg_hp_core1_um_lp_periclkrst_allow:1;
/** reg_hp_core1_um_lp_uart_allow : R/W; bitpos: [9]; default: 1;
* NA
*/
uint32_t reg_hp_core1_um_lp_uart_allow:1;
/** reg_hp_core1_um_lp_i2c_allow : R/W; bitpos: [10]; default: 1;
* NA
*/
uint32_t reg_hp_core1_um_lp_i2c_allow:1;
/** reg_hp_core1_um_lp_spi_allow : R/W; bitpos: [11]; default: 1;
* NA
*/
uint32_t reg_hp_core1_um_lp_spi_allow:1;
/** reg_hp_core1_um_lp_i2cmst_allow : R/W; bitpos: [12]; default: 1;
* NA
*/
uint32_t reg_hp_core1_um_lp_i2cmst_allow:1;
/** reg_hp_core1_um_lp_i2s_allow : R/W; bitpos: [13]; default: 1;
* NA
*/
uint32_t reg_hp_core1_um_lp_i2s_allow:1;
/** reg_hp_core1_um_lp_adc_allow : R/W; bitpos: [14]; default: 1;
* NA
*/
uint32_t reg_hp_core1_um_lp_adc_allow:1;
/** reg_hp_core1_um_lp_touch_allow : R/W; bitpos: [15]; default: 1;
* NA
*/
uint32_t reg_hp_core1_um_lp_touch_allow:1;
/** reg_hp_core1_um_lp_iomux_allow : R/W; bitpos: [16]; default: 1;
* NA
*/
uint32_t reg_hp_core1_um_lp_iomux_allow:1;
/** reg_hp_core1_um_lp_intr_allow : R/W; bitpos: [17]; default: 1;
* NA
*/
uint32_t reg_hp_core1_um_lp_intr_allow:1;
/** reg_hp_core1_um_lp_efuse_allow : R/W; bitpos: [18]; default: 1;
* NA
*/
uint32_t reg_hp_core1_um_lp_efuse_allow:1;
/** reg_hp_core1_um_lp_pms_allow : R/W; bitpos: [19]; default: 1;
* NA
*/
uint32_t reg_hp_core1_um_lp_pms_allow:1;
/** reg_hp_core1_um_hp2lp_pms_allow : R/W; bitpos: [20]; default: 1;
* NA
*/
uint32_t reg_hp_core1_um_hp2lp_pms_allow:1;
/** reg_hp_core1_um_lp_tsens_allow : R/W; bitpos: [21]; default: 1;
* NA
*/
uint32_t reg_hp_core1_um_lp_tsens_allow:1;
/** reg_hp_core1_um_lp_huk_allow : R/W; bitpos: [22]; default: 1;
* NA
*/
uint32_t reg_hp_core1_um_lp_huk_allow:1;
/** reg_hp_core1_um_lp_tcm_ram_allow : R/W; bitpos: [23]; default: 1;
* NA
*/
uint32_t reg_hp_core1_um_lp_tcm_ram_allow:1;
uint32_t reserved_24:8;
};
uint32_t val;
} tee_hp_core1_um_pms_reg0_reg_t;
/** Group: TEE REGDMA PERI PMS REG */
/** Type of regdma_peri_pms register
* NA
*/
typedef union {
struct {
/** reg_regdma_peri_lp_ram_allow : R/W; bitpos: [0]; default: 1;
* NA
*/
uint32_t reg_regdma_peri_lp_ram_allow:1;
/** reg_regdma_peri_lp_peri_allow : R/W; bitpos: [1]; default: 1;
* NA
*/
uint32_t reg_regdma_peri_lp_peri_allow:1;
uint32_t reserved_2:30;
};
uint32_t val;
} tee_regdma_peri_pms_reg_t;
typedef struct {
volatile tee_hp2lp_tee_pms_date_reg_t hp2lp_tee_pms_date;
volatile tee_pms_clk_en_reg_t pms_clk_en;
volatile tee_hp_core0_mm_pms_reg0_reg_t hp_core0_mm_pms_reg0;
volatile tee_hp_core0_um_pms_reg0_reg_t hp_core0_um_pms_reg0;
volatile tee_hp_core1_mm_pms_reg0_reg_t hp_core1_mm_pms_reg0;
volatile tee_hp_core1_um_pms_reg0_reg_t hp_core1_um_pms_reg0;
volatile tee_regdma_peri_pms_reg_t regdma_peri_pms;
} tee_dev_t;
#ifndef __cplusplus
_Static_assert(sizeof(tee_dev_t) == 0x1c, "Invalid size of tee_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** HUK_CLK_REG register
* HUK Generator clock gate control register
*/
#define HUK_CLK_REG (DR_REG_HUK_BASE + 0x4)
/** HUK_CLK_EN : R/W; bitpos: [0]; default: 1;
* Write 1 to force on register clock gate.
*/
#define HUK_CLK_EN (BIT(0))
#define HUK_CLK_EN_M (HUK_CLK_EN_V << HUK_CLK_EN_S)
#define HUK_CLK_EN_V 0x00000001U
#define HUK_CLK_EN_S 0
/** HUK_MEM_CG_FORCE_ON : R/W; bitpos: [1]; default: 0;
* Write 1 to force on memory clock gate.
*/
#define HUK_MEM_CG_FORCE_ON (BIT(1))
#define HUK_MEM_CG_FORCE_ON_M (HUK_MEM_CG_FORCE_ON_V << HUK_MEM_CG_FORCE_ON_S)
#define HUK_MEM_CG_FORCE_ON_V 0x00000001U
#define HUK_MEM_CG_FORCE_ON_S 1
/** HUK_INT_RAW_REG register
* HUK Generator interrupt raw register, valid in level.
*/
#define HUK_INT_RAW_REG (DR_REG_HUK_BASE + 0x8)
/** HUK_PREP_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
* The raw interrupt status bit for the huk_prep_done_int interrupt
*/
#define HUK_PREP_DONE_INT_RAW (BIT(0))
#define HUK_PREP_DONE_INT_RAW_M (HUK_PREP_DONE_INT_RAW_V << HUK_PREP_DONE_INT_RAW_S)
#define HUK_PREP_DONE_INT_RAW_V 0x00000001U
#define HUK_PREP_DONE_INT_RAW_S 0
/** HUK_PROC_DONE_INT_RAW : RO/WTC/SS; bitpos: [1]; default: 0;
* The raw interrupt status bit for the huk_proc_done_int interrupt
*/
#define HUK_PROC_DONE_INT_RAW (BIT(1))
#define HUK_PROC_DONE_INT_RAW_M (HUK_PROC_DONE_INT_RAW_V << HUK_PROC_DONE_INT_RAW_S)
#define HUK_PROC_DONE_INT_RAW_V 0x00000001U
#define HUK_PROC_DONE_INT_RAW_S 1
/** HUK_POST_DONE_INT_RAW : RO/WTC/SS; bitpos: [2]; default: 0;
* The raw interrupt status bit for the huk_post_done_int interrupt
*/
#define HUK_POST_DONE_INT_RAW (BIT(2))
#define HUK_POST_DONE_INT_RAW_M (HUK_POST_DONE_INT_RAW_V << HUK_POST_DONE_INT_RAW_S)
#define HUK_POST_DONE_INT_RAW_V 0x00000001U
#define HUK_POST_DONE_INT_RAW_S 2
/** HUK_INT_ST_REG register
* HUK Generator interrupt status register.
*/
#define HUK_INT_ST_REG (DR_REG_HUK_BASE + 0xc)
/** HUK_PREP_DONE_INT_ST : RO; bitpos: [0]; default: 0;
* The masked interrupt status bit for the huk_prep_done_int interrupt
*/
#define HUK_PREP_DONE_INT_ST (BIT(0))
#define HUK_PREP_DONE_INT_ST_M (HUK_PREP_DONE_INT_ST_V << HUK_PREP_DONE_INT_ST_S)
#define HUK_PREP_DONE_INT_ST_V 0x00000001U
#define HUK_PREP_DONE_INT_ST_S 0
/** HUK_PROC_DONE_INT_ST : RO; bitpos: [1]; default: 0;
* The masked interrupt status bit for the huk_proc_done_int interrupt
*/
#define HUK_PROC_DONE_INT_ST (BIT(1))
#define HUK_PROC_DONE_INT_ST_M (HUK_PROC_DONE_INT_ST_V << HUK_PROC_DONE_INT_ST_S)
#define HUK_PROC_DONE_INT_ST_V 0x00000001U
#define HUK_PROC_DONE_INT_ST_S 1
/** HUK_POST_DONE_INT_ST : RO; bitpos: [2]; default: 0;
* The masked interrupt status bit for the huk_post_done_int interrupt
*/
#define HUK_POST_DONE_INT_ST (BIT(2))
#define HUK_POST_DONE_INT_ST_M (HUK_POST_DONE_INT_ST_V << HUK_POST_DONE_INT_ST_S)
#define HUK_POST_DONE_INT_ST_V 0x00000001U
#define HUK_POST_DONE_INT_ST_S 2
/** HUK_INT_ENA_REG register
* HUK Generator interrupt enable register.
*/
#define HUK_INT_ENA_REG (DR_REG_HUK_BASE + 0x10)
/** HUK_PREP_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
* The interrupt enable bit for the huk_prep_done_int interrupt
*/
#define HUK_PREP_DONE_INT_ENA (BIT(0))
#define HUK_PREP_DONE_INT_ENA_M (HUK_PREP_DONE_INT_ENA_V << HUK_PREP_DONE_INT_ENA_S)
#define HUK_PREP_DONE_INT_ENA_V 0x00000001U
#define HUK_PREP_DONE_INT_ENA_S 0
/** HUK_PROC_DONE_INT_ENA : R/W; bitpos: [1]; default: 0;
* The interrupt enable bit for the huk_proc_done_int interrupt
*/
#define HUK_PROC_DONE_INT_ENA (BIT(1))
#define HUK_PROC_DONE_INT_ENA_M (HUK_PROC_DONE_INT_ENA_V << HUK_PROC_DONE_INT_ENA_S)
#define HUK_PROC_DONE_INT_ENA_V 0x00000001U
#define HUK_PROC_DONE_INT_ENA_S 1
/** HUK_POST_DONE_INT_ENA : R/W; bitpos: [2]; default: 0;
* The interrupt enable bit for the huk_post_done_int interrupt
*/
#define HUK_POST_DONE_INT_ENA (BIT(2))
#define HUK_POST_DONE_INT_ENA_M (HUK_POST_DONE_INT_ENA_V << HUK_POST_DONE_INT_ENA_S)
#define HUK_POST_DONE_INT_ENA_V 0x00000001U
#define HUK_POST_DONE_INT_ENA_S 2
/** HUK_INT_CLR_REG register
* HUK Generator interrupt clear register.
*/
#define HUK_INT_CLR_REG (DR_REG_HUK_BASE + 0x14)
/** HUK_PREP_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
* Set this bit to clear the huk_prep_done_int interrupt
*/
#define HUK_PREP_DONE_INT_CLR (BIT(0))
#define HUK_PREP_DONE_INT_CLR_M (HUK_PREP_DONE_INT_CLR_V << HUK_PREP_DONE_INT_CLR_S)
#define HUK_PREP_DONE_INT_CLR_V 0x00000001U
#define HUK_PREP_DONE_INT_CLR_S 0
/** HUK_PROC_DONE_INT_CLR : WT; bitpos: [1]; default: 0;
* Set this bit to clear the huk_proc_done_int interrupt
*/
#define HUK_PROC_DONE_INT_CLR (BIT(1))
#define HUK_PROC_DONE_INT_CLR_M (HUK_PROC_DONE_INT_CLR_V << HUK_PROC_DONE_INT_CLR_S)
#define HUK_PROC_DONE_INT_CLR_V 0x00000001U
#define HUK_PROC_DONE_INT_CLR_S 1
/** HUK_POST_DONE_INT_CLR : WT; bitpos: [2]; default: 0;
* Set this bit to clear the huk_post_done_int interrupt
*/
#define HUK_POST_DONE_INT_CLR (BIT(2))
#define HUK_POST_DONE_INT_CLR_M (HUK_POST_DONE_INT_CLR_V << HUK_POST_DONE_INT_CLR_S)
#define HUK_POST_DONE_INT_CLR_V 0x00000001U
#define HUK_POST_DONE_INT_CLR_S 2
/** HUK_CONF_REG register
* HUK Generator configuration register
*/
#define HUK_CONF_REG (DR_REG_HUK_BASE + 0x20)
/** HUK_MODE : R/W; bitpos: [0]; default: 0;
* Set this field to choose the huk process. 1: process huk generate mode. 0: process
* huk recovery mode.
*/
#define HUK_MODE (BIT(0))
#define HUK_MODE_M (HUK_MODE_V << HUK_MODE_S)
#define HUK_MODE_V 0x00000001U
#define HUK_MODE_S 0
/** HUK_START_REG register
* HUK Generator control register
*/
#define HUK_START_REG (DR_REG_HUK_BASE + 0x24)
/** HUK_START : WT; bitpos: [0]; default: 0;
* Write 1 to continue HUK Generator operation at LOAD/GAIN state.
*/
#define HUK_START (BIT(0))
#define HUK_START_M (HUK_START_V << HUK_START_S)
#define HUK_START_V 0x00000001U
#define HUK_START_S 0
/** HUK_CONTINUE : WT; bitpos: [1]; default: 0;
* Write 1 to start HUK Generator at IDLE state.
*/
#define HUK_CONTINUE (BIT(1))
#define HUK_CONTINUE_M (HUK_CONTINUE_V << HUK_CONTINUE_S)
#define HUK_CONTINUE_V 0x00000001U
#define HUK_CONTINUE_S 1
/** HUK_STATE_REG register
* HUK Generator state register
*/
#define HUK_STATE_REG (DR_REG_HUK_BASE + 0x28)
/** HUK_STATE : RO; bitpos: [1:0]; default: 0;
* The state of HUK Generator. 0: IDLE. 1: LOAD. 2: GAIN. 3: BUSY.
*/
#define HUK_STATE 0x00000003U
#define HUK_STATE_M (HUK_STATE_V << HUK_STATE_S)
#define HUK_STATE_V 0x00000003U
#define HUK_STATE_S 0
/** HUK_STATUS_REG register
* HUK Generator HUK status register
*/
#define HUK_STATUS_REG (DR_REG_HUK_BASE + 0x34)
/** HUK_STATUS : RO; bitpos: [1:0]; default: 0;
* The HUK generation status. 0: HUK is not generated. 1: HUK is generated and valid.
* 2: HUK is generated but invalid. 3: reserved.
*/
#define HUK_STATUS 0x00000003U
#define HUK_STATUS_M (HUK_STATUS_V << HUK_STATUS_S)
#define HUK_STATUS_V 0x00000003U
#define HUK_STATUS_S 0
/** HUK_RISK_LEVEL : RO; bitpos: [4:2]; default: 0;
* The risk level of HUK. 0-6: the higher the risk level is, the more error bits there
* are in the PUF SRAM. 7: Error Level, HUK is invalid.
*/
#define HUK_RISK_LEVEL 0x00000007U
#define HUK_RISK_LEVEL_M (HUK_RISK_LEVEL_V << HUK_RISK_LEVEL_S)
#define HUK_RISK_LEVEL_V 0x00000007U
#define HUK_RISK_LEVEL_S 2
/** HUK_DATE_REG register
* Version control register
*/
#define HUK_DATE_REG (DR_REG_HUK_BASE + 0xfc)
/** HUK_DATE : R/W; bitpos: [27:0]; default: 36720704;
* HUK Generator version control register.
*/
#define HUK_DATE 0x0FFFFFFFU
#define HUK_DATE_M (HUK_DATE_V << HUK_DATE_S)
#define HUK_DATE_V 0x0FFFFFFFU
#define HUK_DATE_S 0
/** HUK_INFO_MEM register
* The memory that stores HUK info.
*/
#define HUK_INFO_MEM (DR_REG_HUK_BASE + 0x100)
#define HUK_INFO_MEM_SIZE_BYTES 384
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Memory data */
/** Group: Clock gate register */
/** Type of clk register
* HUK Generator clock gate control register
*/
typedef union {
struct {
/** clk_en : R/W; bitpos: [0]; default: 1;
* Write 1 to force on register clock gate.
*/
uint32_t clk_en:1;
/** mem_cg_force_on : R/W; bitpos: [1]; default: 0;
* Write 1 to force on memory clock gate.
*/
uint32_t mem_cg_force_on:1;
uint32_t reserved_2:30;
};
uint32_t val;
} huk_clk_reg_t;
/** Group: Interrupt registers */
/** Type of int_raw register
* HUK Generator interrupt raw register, valid in level.
*/
typedef union {
struct {
/** prep_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0;
* The raw interrupt status bit for the huk_prep_done_int interrupt
*/
uint32_t prep_done_int_raw:1;
/** proc_done_int_raw : RO/WTC/SS; bitpos: [1]; default: 0;
* The raw interrupt status bit for the huk_proc_done_int interrupt
*/
uint32_t proc_done_int_raw:1;
/** post_done_int_raw : RO/WTC/SS; bitpos: [2]; default: 0;
* The raw interrupt status bit for the huk_post_done_int interrupt
*/
uint32_t post_done_int_raw:1;
uint32_t reserved_3:29;
};
uint32_t val;
} huk_int_raw_reg_t;
/** Type of int_st register
* HUK Generator interrupt status register.
*/
typedef union {
struct {
/** prep_done_int_st : RO; bitpos: [0]; default: 0;
* The masked interrupt status bit for the huk_prep_done_int interrupt
*/
uint32_t prep_done_int_st:1;
/** proc_done_int_st : RO; bitpos: [1]; default: 0;
* The masked interrupt status bit for the huk_proc_done_int interrupt
*/
uint32_t proc_done_int_st:1;
/** post_done_int_st : RO; bitpos: [2]; default: 0;
* The masked interrupt status bit for the huk_post_done_int interrupt
*/
uint32_t post_done_int_st:1;
uint32_t reserved_3:29;
};
uint32_t val;
} huk_int_st_reg_t;
/** Type of int_ena register
* HUK Generator interrupt enable register.
*/
typedef union {
struct {
/** prep_done_int_ena : R/W; bitpos: [0]; default: 0;
* The interrupt enable bit for the huk_prep_done_int interrupt
*/
uint32_t prep_done_int_ena:1;
/** proc_done_int_ena : R/W; bitpos: [1]; default: 0;
* The interrupt enable bit for the huk_proc_done_int interrupt
*/
uint32_t proc_done_int_ena:1;
/** post_done_int_ena : R/W; bitpos: [2]; default: 0;
* The interrupt enable bit for the huk_post_done_int interrupt
*/
uint32_t post_done_int_ena:1;
uint32_t reserved_3:29;
};
uint32_t val;
} huk_int_ena_reg_t;
/** Type of int_clr register
* HUK Generator interrupt clear register.
*/
typedef union {
struct {
/** prep_done_int_clr : WT; bitpos: [0]; default: 0;
* Set this bit to clear the huk_prep_done_int interrupt
*/
uint32_t prep_done_int_clr:1;
/** proc_done_int_clr : WT; bitpos: [1]; default: 0;
* Set this bit to clear the huk_proc_done_int interrupt
*/
uint32_t proc_done_int_clr:1;
/** post_done_int_clr : WT; bitpos: [2]; default: 0;
* Set this bit to clear the huk_post_done_int interrupt
*/
uint32_t post_done_int_clr:1;
uint32_t reserved_3:29;
};
uint32_t val;
} huk_int_clr_reg_t;
/** Group: Configuration registers */
/** Type of conf register
* HUK Generator configuration register
*/
typedef union {
struct {
/** mode : R/W; bitpos: [0]; default: 0;
* Set this field to choose the huk process. 1: process huk generate mode. 0: process
* huk recovery mode.
*/
uint32_t mode:1;
uint32_t reserved_1:31;
};
uint32_t val;
} huk_conf_reg_t;
/** Group: Control registers */
/** Type of start register
* HUK Generator control register
*/
typedef union {
struct {
/** start : WT; bitpos: [0]; default: 0;
* Write 1 to continue HUK Generator operation at LOAD/GAIN state.
*/
uint32_t start:1;
/** continue : WT; bitpos: [1]; default: 0;
* Write 1 to start HUK Generator at IDLE state.
*/
uint32_t conti:1;
uint32_t reserved_2:30;
};
uint32_t val;
} huk_start_reg_t;
/** Group: State registers */
/** Type of state register
* HUK Generator state register
*/
typedef union {
struct {
/** state : RO; bitpos: [1:0]; default: 0;
* The state of HUK Generator. 0: IDLE. 1: LOAD. 2: GAIN. 3: BUSY.
*/
uint32_t state:2;
uint32_t reserved_2:30;
};
uint32_t val;
} huk_state_reg_t;
/** Group: Result registers */
/** Type of status register
* HUK Generator HUK status register
*/
typedef union {
struct {
/** status : RO; bitpos: [1:0]; default: 0;
* The HUK generation status. 0: HUK is not generated. 1: HUK is generated and valid.
* 2: HUK is generated but invalid. 3: reserved.
*/
uint32_t status:2;
/** risk_level : RO; bitpos: [4:2]; default: 0;
* The risk level of HUK. 0-6: the higher the risk level is, the more error bits there
* are in the PUF SRAM. 7: Error Level, HUK is invalid.
*/
uint32_t risk_level:3;
uint32_t reserved_5:27;
};
uint32_t val;
} huk_status_reg_t;
/** Group: Version register */
/** Type of date register
* Version control register
*/
typedef union {
struct {
/** date : R/W; bitpos: [27:0]; default: 36720704;
* HUK Generator version control register.
*/
uint32_t date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} huk_date_reg_t;
typedef struct {
uint32_t reserved_000;
volatile huk_clk_reg_t clk;
volatile huk_int_raw_reg_t int_raw;
volatile huk_int_st_reg_t int_st;
volatile huk_int_ena_reg_t int_ena;
volatile huk_int_clr_reg_t int_clr;
uint32_t reserved_018[2];
volatile huk_conf_reg_t conf;
volatile huk_start_reg_t start;
volatile huk_state_reg_t state;
uint32_t reserved_02c[2];
volatile huk_status_reg_t status;
uint32_t reserved_038[49];
volatile huk_date_reg_t date;
volatile uint32_t info[96];
} huk_dev_t;
#ifndef __cplusplus
_Static_assert(sizeof(huk_dev_t) == 0x280, "Invalid size of huk_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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components/soc/esp32p4/include/soc/i2c_ana_mst_reg.h Normal file
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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** I2C_ANA_MST_I2C0_CTRL_REG register
* need des
*/
#define I2C_ANA_MST_I2C0_CTRL_REG (DR_REG_I2C_ANA_MST_BASE + 0x0)
/** I2C_ANA_MST_I2C0_CTRL : R/W; bitpos: [24:0]; default: 0;
* need des
*/
#define I2C_ANA_MST_I2C0_CTRL 0x01FFFFFFU
#define I2C_ANA_MST_I2C0_CTRL_M (I2C_ANA_MST_I2C0_CTRL_V << I2C_ANA_MST_I2C0_CTRL_S)
#define I2C_ANA_MST_I2C0_CTRL_V 0x01FFFFFFU
#define I2C_ANA_MST_I2C0_CTRL_S 0
/** I2C_ANA_MST_I2C0_BUSY : RO; bitpos: [25]; default: 0;
* need des
*/
#define I2C_ANA_MST_I2C0_BUSY (BIT(25))
#define I2C_ANA_MST_I2C0_BUSY_M (I2C_ANA_MST_I2C0_BUSY_V << I2C_ANA_MST_I2C0_BUSY_S)
#define I2C_ANA_MST_I2C0_BUSY_V 0x00000001U
#define I2C_ANA_MST_I2C0_BUSY_S 25
/** I2C_ANA_MST_I2C1_CTRL_REG register
* need des
*/
#define I2C_ANA_MST_I2C1_CTRL_REG (DR_REG_I2C_ANA_MST_BASE + 0x4)
/** I2C_ANA_MST_I2C1_CTRL : R/W; bitpos: [24:0]; default: 0;
* need des
*/
#define I2C_ANA_MST_I2C1_CTRL 0x01FFFFFFU
#define I2C_ANA_MST_I2C1_CTRL_M (I2C_ANA_MST_I2C1_CTRL_V << I2C_ANA_MST_I2C1_CTRL_S)
#define I2C_ANA_MST_I2C1_CTRL_V 0x01FFFFFFU
#define I2C_ANA_MST_I2C1_CTRL_S 0
/** I2C_ANA_MST_I2C1_BUSY : RO; bitpos: [25]; default: 0;
* need des
*/
#define I2C_ANA_MST_I2C1_BUSY (BIT(25))
#define I2C_ANA_MST_I2C1_BUSY_M (I2C_ANA_MST_I2C1_BUSY_V << I2C_ANA_MST_I2C1_BUSY_S)
#define I2C_ANA_MST_I2C1_BUSY_V 0x00000001U
#define I2C_ANA_MST_I2C1_BUSY_S 25
/** I2C_ANA_MST_I2C0_CONF_REG register
* need des
*/
#define I2C_ANA_MST_I2C0_CONF_REG (DR_REG_I2C_ANA_MST_BASE + 0x8)
/** I2C_ANA_MST_I2C0_CONF : R/W; bitpos: [23:0]; default: 0;
* need des
*/
#define I2C_ANA_MST_I2C0_CONF 0x00FFFFFFU
#define I2C_ANA_MST_I2C0_CONF_M (I2C_ANA_MST_I2C0_CONF_V << I2C_ANA_MST_I2C0_CONF_S)
#define I2C_ANA_MST_I2C0_CONF_V 0x00FFFFFFU
#define I2C_ANA_MST_I2C0_CONF_S 0
/** I2C_ANA_MST_I2C0_STATUS : RO; bitpos: [31:24]; default: 0;
* need des
*/
#define I2C_ANA_MST_I2C0_STATUS 0x000000FFU
#define I2C_ANA_MST_I2C0_STATUS_M (I2C_ANA_MST_I2C0_STATUS_V << I2C_ANA_MST_I2C0_STATUS_S)
#define I2C_ANA_MST_I2C0_STATUS_V 0x000000FFU
#define I2C_ANA_MST_I2C0_STATUS_S 24
/** I2C_ANA_MST_I2C1_CONF_REG register
* need des
*/
#define I2C_ANA_MST_I2C1_CONF_REG (DR_REG_I2C_ANA_MST_BASE + 0xc)
/** I2C_ANA_MST_I2C1_CONF : R/W; bitpos: [23:0]; default: 0;
* need des
*/
#define I2C_ANA_MST_I2C1_CONF 0x00FFFFFFU
#define I2C_ANA_MST_I2C1_CONF_M (I2C_ANA_MST_I2C1_CONF_V << I2C_ANA_MST_I2C1_CONF_S)
#define I2C_ANA_MST_I2C1_CONF_V 0x00FFFFFFU
#define I2C_ANA_MST_I2C1_CONF_S 0
/** I2C_ANA_MST_I2C1_STATUS : RO; bitpos: [31:24]; default: 0;
* need des
*/
#define I2C_ANA_MST_I2C1_STATUS 0x000000FFU
#define I2C_ANA_MST_I2C1_STATUS_M (I2C_ANA_MST_I2C1_STATUS_V << I2C_ANA_MST_I2C1_STATUS_S)
#define I2C_ANA_MST_I2C1_STATUS_V 0x000000FFU
#define I2C_ANA_MST_I2C1_STATUS_S 24
/** I2C_ANA_MST_I2C_BURST_CONF_REG register
* need des
*/
#define I2C_ANA_MST_I2C_BURST_CONF_REG (DR_REG_I2C_ANA_MST_BASE + 0x10)
/** I2C_ANA_MST_I2C_MST_BURST_CTRL : R/W; bitpos: [31:0]; default: 0;
* need des
*/
#define I2C_ANA_MST_I2C_MST_BURST_CTRL 0xFFFFFFFFU
#define I2C_ANA_MST_I2C_MST_BURST_CTRL_M (I2C_ANA_MST_I2C_MST_BURST_CTRL_V << I2C_ANA_MST_I2C_MST_BURST_CTRL_S)
#define I2C_ANA_MST_I2C_MST_BURST_CTRL_V 0xFFFFFFFFU
#define I2C_ANA_MST_I2C_MST_BURST_CTRL_S 0
/** I2C_ANA_MST_I2C_BURST_STATUS_REG register
* need des
*/
#define I2C_ANA_MST_I2C_BURST_STATUS_REG (DR_REG_I2C_ANA_MST_BASE + 0x14)
/** I2C_ANA_MST_I2C_MST_BURST_DONE : RO; bitpos: [0]; default: 0;
* need des
*/
#define I2C_ANA_MST_I2C_MST_BURST_DONE (BIT(0))
#define I2C_ANA_MST_I2C_MST_BURST_DONE_M (I2C_ANA_MST_I2C_MST_BURST_DONE_V << I2C_ANA_MST_I2C_MST_BURST_DONE_S)
#define I2C_ANA_MST_I2C_MST_BURST_DONE_V 0x00000001U
#define I2C_ANA_MST_I2C_MST_BURST_DONE_S 0
/** I2C_ANA_MST_I2C_MST0_BURST_ERR_FLAG : RO; bitpos: [1]; default: 0;
* need des
*/
#define I2C_ANA_MST_I2C_MST0_BURST_ERR_FLAG (BIT(1))
#define I2C_ANA_MST_I2C_MST0_BURST_ERR_FLAG_M (I2C_ANA_MST_I2C_MST0_BURST_ERR_FLAG_V << I2C_ANA_MST_I2C_MST0_BURST_ERR_FLAG_S)
#define I2C_ANA_MST_I2C_MST0_BURST_ERR_FLAG_V 0x00000001U
#define I2C_ANA_MST_I2C_MST0_BURST_ERR_FLAG_S 1
/** I2C_ANA_MST_I2C_MST1_BURST_ERR_FLAG : RO; bitpos: [2]; default: 0;
* need des
*/
#define I2C_ANA_MST_I2C_MST1_BURST_ERR_FLAG (BIT(2))
#define I2C_ANA_MST_I2C_MST1_BURST_ERR_FLAG_M (I2C_ANA_MST_I2C_MST1_BURST_ERR_FLAG_V << I2C_ANA_MST_I2C_MST1_BURST_ERR_FLAG_S)
#define I2C_ANA_MST_I2C_MST1_BURST_ERR_FLAG_V 0x00000001U
#define I2C_ANA_MST_I2C_MST1_BURST_ERR_FLAG_S 2
/** I2C_ANA_MST_I2C_MST_BURST_TIMEOUT_CNT : R/W; bitpos: [31:20]; default: 1024;
* need des
*/
#define I2C_ANA_MST_I2C_MST_BURST_TIMEOUT_CNT 0x00000FFFU
#define I2C_ANA_MST_I2C_MST_BURST_TIMEOUT_CNT_M (I2C_ANA_MST_I2C_MST_BURST_TIMEOUT_CNT_V << I2C_ANA_MST_I2C_MST_BURST_TIMEOUT_CNT_S)
#define I2C_ANA_MST_I2C_MST_BURST_TIMEOUT_CNT_V 0x00000FFFU
#define I2C_ANA_MST_I2C_MST_BURST_TIMEOUT_CNT_S 20
/** I2C_ANA_MST_ANA_CONF0_REG register
* need des
*/
#define I2C_ANA_MST_ANA_CONF0_REG (DR_REG_I2C_ANA_MST_BASE + 0x18)
/** I2C_ANA_MST_ANA_CONF0 : R/W; bitpos: [23:0]; default: 0;
* need des
*/
#define I2C_ANA_MST_ANA_CONF0 0x00FFFFFFU
#define I2C_ANA_MST_ANA_CONF0_M (I2C_ANA_MST_ANA_CONF0_V << I2C_ANA_MST_ANA_CONF0_S)
#define I2C_ANA_MST_ANA_CONF0_V 0x00FFFFFFU
#define I2C_ANA_MST_ANA_CONF0_S 0
/** I2C_ANA_MST_ANA_STATUS0 : RO; bitpos: [31:24]; default: 0;
* need des
*/
#define I2C_ANA_MST_ANA_STATUS0 0x000000FFU
#define I2C_ANA_MST_ANA_STATUS0_M (I2C_ANA_MST_ANA_STATUS0_V << I2C_ANA_MST_ANA_STATUS0_S)
#define I2C_ANA_MST_ANA_STATUS0_V 0x000000FFU
#define I2C_ANA_MST_ANA_STATUS0_S 24
/** I2C_ANA_MST_ANA_CONF1_REG register
* need des
*/
#define I2C_ANA_MST_ANA_CONF1_REG (DR_REG_I2C_ANA_MST_BASE + 0x1c)
/** I2C_ANA_MST_ANA_CONF1 : R/W; bitpos: [23:0]; default: 0;
* need des
*/
#define I2C_ANA_MST_ANA_CONF1 0x00FFFFFFU
#define I2C_ANA_MST_ANA_CONF1_M (I2C_ANA_MST_ANA_CONF1_V << I2C_ANA_MST_ANA_CONF1_S)
#define I2C_ANA_MST_ANA_CONF1_V 0x00FFFFFFU
#define I2C_ANA_MST_ANA_CONF1_S 0
/** I2C_ANA_MST_ANA_STATUS1 : RO; bitpos: [31:24]; default: 0;
* need des
*/
#define I2C_ANA_MST_ANA_STATUS1 0x000000FFU
#define I2C_ANA_MST_ANA_STATUS1_M (I2C_ANA_MST_ANA_STATUS1_V << I2C_ANA_MST_ANA_STATUS1_S)
#define I2C_ANA_MST_ANA_STATUS1_V 0x000000FFU
#define I2C_ANA_MST_ANA_STATUS1_S 24
/** I2C_ANA_MST_ANA_CONF2_REG register
* need des
*/
#define I2C_ANA_MST_ANA_CONF2_REG (DR_REG_I2C_ANA_MST_BASE + 0x20)
/** I2C_ANA_MST_ANA_CONF2 : R/W; bitpos: [23:0]; default: 0;
* need des
*/
#define I2C_ANA_MST_ANA_CONF2 0x00FFFFFFU
#define I2C_ANA_MST_ANA_CONF2_M (I2C_ANA_MST_ANA_CONF2_V << I2C_ANA_MST_ANA_CONF2_S)
#define I2C_ANA_MST_ANA_CONF2_V 0x00FFFFFFU
#define I2C_ANA_MST_ANA_CONF2_S 0
/** I2C_ANA_MST_ANA_STATUS2 : RO; bitpos: [31:24]; default: 0;
* need des
*/
#define I2C_ANA_MST_ANA_STATUS2 0x000000FFU
#define I2C_ANA_MST_ANA_STATUS2_M (I2C_ANA_MST_ANA_STATUS2_V << I2C_ANA_MST_ANA_STATUS2_S)
#define I2C_ANA_MST_ANA_STATUS2_V 0x000000FFU
#define I2C_ANA_MST_ANA_STATUS2_S 24
/** I2C_ANA_MST_I2C0_CTRL1_REG register
* need des
*/
#define I2C_ANA_MST_I2C0_CTRL1_REG (DR_REG_I2C_ANA_MST_BASE + 0x24)
/** I2C_ANA_MST_I2C0_SCL_PULSE_DUR : R/W; bitpos: [5:0]; default: 2;
* need des
*/
#define I2C_ANA_MST_I2C0_SCL_PULSE_DUR 0x0000003FU
#define I2C_ANA_MST_I2C0_SCL_PULSE_DUR_M (I2C_ANA_MST_I2C0_SCL_PULSE_DUR_V << I2C_ANA_MST_I2C0_SCL_PULSE_DUR_S)
#define I2C_ANA_MST_I2C0_SCL_PULSE_DUR_V 0x0000003FU
#define I2C_ANA_MST_I2C0_SCL_PULSE_DUR_S 0
/** I2C_ANA_MST_I2C0_SDA_SIDE_GUARD : R/W; bitpos: [10:6]; default: 1;
* need des
*/
#define I2C_ANA_MST_I2C0_SDA_SIDE_GUARD 0x0000001FU
#define I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_M (I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_V << I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_S)
#define I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_V 0x0000001FU
#define I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_S 6
/** I2C_ANA_MST_I2C1_CTRL1_REG register
* need des
*/
#define I2C_ANA_MST_I2C1_CTRL1_REG (DR_REG_I2C_ANA_MST_BASE + 0x28)
/** I2C_ANA_MST_I2C1_SCL_PULSE_DUR : R/W; bitpos: [5:0]; default: 2;
* need des
*/
#define I2C_ANA_MST_I2C1_SCL_PULSE_DUR 0x0000003FU
#define I2C_ANA_MST_I2C1_SCL_PULSE_DUR_M (I2C_ANA_MST_I2C1_SCL_PULSE_DUR_V << I2C_ANA_MST_I2C1_SCL_PULSE_DUR_S)
#define I2C_ANA_MST_I2C1_SCL_PULSE_DUR_V 0x0000003FU
#define I2C_ANA_MST_I2C1_SCL_PULSE_DUR_S 0
/** I2C_ANA_MST_I2C1_SDA_SIDE_GUARD : R/W; bitpos: [10:6]; default: 1;
* need des
*/
#define I2C_ANA_MST_I2C1_SDA_SIDE_GUARD 0x0000001FU
#define I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_M (I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_V << I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_S)
#define I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_V 0x0000001FU
#define I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_S 6
/** I2C_ANA_MST_HW_I2C_CTRL_REG register
* need des
*/
#define I2C_ANA_MST_HW_I2C_CTRL_REG (DR_REG_I2C_ANA_MST_BASE + 0x2c)
/** I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR : R/W; bitpos: [5:0]; default: 2;
* need des
*/
#define I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR 0x0000003FU
#define I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_M (I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_V << I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_S)
#define I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_V 0x0000003FU
#define I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_S 0
/** I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD : R/W; bitpos: [10:6]; default: 1;
* need des
*/
#define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD 0x0000001FU
#define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_M (I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_V << I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_S)
#define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_V 0x0000001FU
#define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_S 6
/** I2C_ANA_MST_ARBITER_DIS : R/W; bitpos: [11]; default: 0;
* need des
*/
#define I2C_ANA_MST_ARBITER_DIS (BIT(11))
#define I2C_ANA_MST_ARBITER_DIS_M (I2C_ANA_MST_ARBITER_DIS_V << I2C_ANA_MST_ARBITER_DIS_S)
#define I2C_ANA_MST_ARBITER_DIS_V 0x00000001U
#define I2C_ANA_MST_ARBITER_DIS_S 11
/** I2C_ANA_MST_NOUSE_REG register
* need des
*/
#define I2C_ANA_MST_NOUSE_REG (DR_REG_I2C_ANA_MST_BASE + 0x30)
/** I2C_ANA_MST_I2C_MST_NOUSE : R/W; bitpos: [31:0]; default: 0;
* need des
*/
#define I2C_ANA_MST_I2C_MST_NOUSE 0xFFFFFFFFU
#define I2C_ANA_MST_I2C_MST_NOUSE_M (I2C_ANA_MST_I2C_MST_NOUSE_V << I2C_ANA_MST_I2C_MST_NOUSE_S)
#define I2C_ANA_MST_I2C_MST_NOUSE_V 0xFFFFFFFFU
#define I2C_ANA_MST_I2C_MST_NOUSE_S 0
/** I2C_ANA_MST_CLK160M_REG register
* need des
*/
#define I2C_ANA_MST_CLK160M_REG (DR_REG_I2C_ANA_MST_BASE + 0x34)
/** I2C_ANA_MST_CLK_I2C_MST_SEL_160M : R/W; bitpos: [0]; default: 0;
* need des
*/
#define I2C_ANA_MST_CLK_I2C_MST_SEL_160M (BIT(0))
#define I2C_ANA_MST_CLK_I2C_MST_SEL_160M_M (I2C_ANA_MST_CLK_I2C_MST_SEL_160M_V << I2C_ANA_MST_CLK_I2C_MST_SEL_160M_S)
#define I2C_ANA_MST_CLK_I2C_MST_SEL_160M_V 0x00000001U
#define I2C_ANA_MST_CLK_I2C_MST_SEL_160M_S 0
/** I2C_ANA_MST_DATE_REG register
* need des
*/
#define I2C_ANA_MST_DATE_REG (DR_REG_I2C_ANA_MST_BASE + 0x38)
/** I2C_ANA_MST_DATE : R/W; bitpos: [27:0]; default: 35656448;
* need des
*/
#define I2C_ANA_MST_DATE 0x0FFFFFFFU
#define I2C_ANA_MST_DATE_M (I2C_ANA_MST_DATE_V << I2C_ANA_MST_DATE_S)
#define I2C_ANA_MST_DATE_V 0x0FFFFFFFU
#define I2C_ANA_MST_DATE_S 0
/** I2C_ANA_MST_I2C_MST_CLK_EN : R/W; bitpos: [28]; default: 0;
* need des
*/
#define I2C_ANA_MST_I2C_MST_CLK_EN (BIT(28))
#define I2C_ANA_MST_I2C_MST_CLK_EN_M (I2C_ANA_MST_I2C_MST_CLK_EN_V << I2C_ANA_MST_I2C_MST_CLK_EN_S)
#define I2C_ANA_MST_I2C_MST_CLK_EN_V 0x00000001U
#define I2C_ANA_MST_I2C_MST_CLK_EN_S 28
#ifdef __cplusplus
}
#endif

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components/soc/esp32p4/include/soc/i2c_ana_mst_struct.h Normal file
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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Configure Register */
/** Type of i2c0_ctrl register
* need des
*/
typedef union {
struct {
/** i2c0_ctrl : R/W; bitpos: [24:0]; default: 0;
* need des
*/
uint32_t i2c0_ctrl:25;
/** i2c0_busy : RO; bitpos: [25]; default: 0;
* need des
*/
uint32_t i2c0_busy:1;
uint32_t reserved_26:6;
};
uint32_t val;
} i2c_ana_mst_i2c0_ctrl_reg_t;
/** Type of i2c1_ctrl register
* need des
*/
typedef union {
struct {
/** i2c1_ctrl : R/W; bitpos: [24:0]; default: 0;
* need des
*/
uint32_t i2c1_ctrl:25;
/** i2c1_busy : RO; bitpos: [25]; default: 0;
* need des
*/
uint32_t i2c1_busy:1;
uint32_t reserved_26:6;
};
uint32_t val;
} i2c_ana_mst_i2c1_ctrl_reg_t;
/** Type of i2c0_conf register
* need des
*/
typedef union {
struct {
/** i2c0_conf : R/W; bitpos: [23:0]; default: 0;
* need des
*/
uint32_t i2c0_conf:24;
/** i2c0_status : RO; bitpos: [31:24]; default: 0;
* need des
*/
uint32_t i2c0_status:8;
};
uint32_t val;
} i2c_ana_mst_i2c0_conf_reg_t;
/** Type of i2c1_conf register
* need des
*/
typedef union {
struct {
/** i2c1_conf : R/W; bitpos: [23:0]; default: 0;
* need des
*/
uint32_t i2c1_conf:24;
/** i2c1_status : RO; bitpos: [31:24]; default: 0;
* need des
*/
uint32_t i2c1_status:8;
};
uint32_t val;
} i2c_ana_mst_i2c1_conf_reg_t;
/** Type of i2c_burst_conf register
* need des
*/
typedef union {
struct {
/** i2c_mst_burst_ctrl : R/W; bitpos: [31:0]; default: 0;
* need des
*/
uint32_t i2c_mst_burst_ctrl:32;
};
uint32_t val;
} i2c_ana_mst_i2c_burst_conf_reg_t;
/** Type of i2c_burst_status register
* need des
*/
typedef union {
struct {
/** i2c_mst_burst_done : RO; bitpos: [0]; default: 0;
* need des
*/
uint32_t i2c_mst_burst_done:1;
/** i2c_mst0_burst_err_flag : RO; bitpos: [1]; default: 0;
* need des
*/
uint32_t i2c_mst0_burst_err_flag:1;
/** i2c_mst1_burst_err_flag : RO; bitpos: [2]; default: 0;
* need des
*/
uint32_t i2c_mst1_burst_err_flag:1;
uint32_t reserved_3:17;
/** i2c_mst_burst_timeout_cnt : R/W; bitpos: [31:20]; default: 1024;
* need des
*/
uint32_t i2c_mst_burst_timeout_cnt:12;
};
uint32_t val;
} i2c_ana_mst_i2c_burst_status_reg_t;
/** Type of ana_conf0 register
* need des
*/
typedef union {
struct {
/** ana_conf0 : R/W; bitpos: [23:0]; default: 0;
* need des
*/
uint32_t ana_conf0:24;
/** ana_status0 : RO; bitpos: [31:24]; default: 0;
* need des
*/
uint32_t ana_status0:8;
};
uint32_t val;
} i2c_ana_mst_ana_conf0_reg_t;
/** Type of ana_conf1 register
* need des
*/
typedef union {
struct {
/** ana_conf1 : R/W; bitpos: [23:0]; default: 0;
* need des
*/
uint32_t ana_conf1:24;
/** ana_status1 : RO; bitpos: [31:24]; default: 0;
* need des
*/
uint32_t ana_status1:8;
};
uint32_t val;
} i2c_ana_mst_ana_conf1_reg_t;
/** Type of ana_conf2 register
* need des
*/
typedef union {
struct {
/** ana_conf2 : R/W; bitpos: [23:0]; default: 0;
* need des
*/
uint32_t ana_conf2:24;
/** ana_status2 : RO; bitpos: [31:24]; default: 0;
* need des
*/
uint32_t ana_status2:8;
};
uint32_t val;
} i2c_ana_mst_ana_conf2_reg_t;
/** Type of i2c0_ctrl1 register
* need des
*/
typedef union {
struct {
/** i2c0_scl_pulse_dur : R/W; bitpos: [5:0]; default: 2;
* need des
*/
uint32_t i2c0_scl_pulse_dur:6;
/** i2c0_sda_side_guard : R/W; bitpos: [10:6]; default: 1;
* need des
*/
uint32_t i2c0_sda_side_guard:5;
uint32_t reserved_11:21;
};
uint32_t val;
} i2c_ana_mst_i2c0_ctrl1_reg_t;
/** Type of i2c1_ctrl1 register
* need des
*/
typedef union {
struct {
/** i2c1_scl_pulse_dur : R/W; bitpos: [5:0]; default: 2;
* need des
*/
uint32_t i2c1_scl_pulse_dur:6;
/** i2c1_sda_side_guard : R/W; bitpos: [10:6]; default: 1;
* need des
*/
uint32_t i2c1_sda_side_guard:5;
uint32_t reserved_11:21;
};
uint32_t val;
} i2c_ana_mst_i2c1_ctrl1_reg_t;
/** Type of hw_i2c_ctrl register
* need des
*/
typedef union {
struct {
/** hw_i2c_scl_pulse_dur : R/W; bitpos: [5:0]; default: 2;
* need des
*/
uint32_t hw_i2c_scl_pulse_dur:6;
/** hw_i2c_sda_side_guard : R/W; bitpos: [10:6]; default: 1;
* need des
*/
uint32_t hw_i2c_sda_side_guard:5;
/** arbiter_dis : R/W; bitpos: [11]; default: 0;
* need des
*/
uint32_t arbiter_dis:1;
uint32_t reserved_12:20;
};
uint32_t val;
} i2c_ana_mst_hw_i2c_ctrl_reg_t;
/** Type of nouse register
* need des
*/
typedef union {
struct {
/** i2c_mst_nouse : R/W; bitpos: [31:0]; default: 0;
* need des
*/
uint32_t i2c_mst_nouse:32;
};
uint32_t val;
} i2c_ana_mst_nouse_reg_t;
/** Type of clk160m register
* need des
*/
typedef union {
struct {
/** clk_i2c_mst_sel_160m : R/W; bitpos: [0]; default: 0;
* need des
*/
uint32_t clk_i2c_mst_sel_160m:1;
uint32_t reserved_1:31;
};
uint32_t val;
} i2c_ana_mst_clk160m_reg_t;
/** Type of date register
* need des
*/
typedef union {
struct {
/** date : R/W; bitpos: [27:0]; default: 35656448;
* need des
*/
uint32_t date:28;
/** i2c_mst_clk_en : R/W; bitpos: [28]; default: 0;
* need des
*/
uint32_t i2c_mst_clk_en:1;
uint32_t reserved_29:3;
};
uint32_t val;
} i2c_ana_mst_date_reg_t;
typedef struct {
volatile i2c_ana_mst_i2c0_ctrl_reg_t i2c0_ctrl;
volatile i2c_ana_mst_i2c1_ctrl_reg_t i2c1_ctrl;
volatile i2c_ana_mst_i2c0_conf_reg_t i2c0_conf;
volatile i2c_ana_mst_i2c1_conf_reg_t i2c1_conf;
volatile i2c_ana_mst_i2c_burst_conf_reg_t i2c_burst_conf;
volatile i2c_ana_mst_i2c_burst_status_reg_t i2c_burst_status;
volatile i2c_ana_mst_ana_conf0_reg_t ana_conf0;
volatile i2c_ana_mst_ana_conf1_reg_t ana_conf1;
volatile i2c_ana_mst_ana_conf2_reg_t ana_conf2;
volatile i2c_ana_mst_i2c0_ctrl1_reg_t i2c0_ctrl1;
volatile i2c_ana_mst_i2c1_ctrl1_reg_t i2c1_ctrl1;
volatile i2c_ana_mst_hw_i2c_ctrl_reg_t hw_i2c_ctrl;
volatile i2c_ana_mst_nouse_reg_t nouse;
volatile i2c_ana_mst_clk160m_reg_t clk160m;
volatile i2c_ana_mst_date_reg_t date;
} i2c_ana_mst_dev_t;
#ifndef __cplusplus
_Static_assert(sizeof(i2c_ana_mst_dev_t) == 0x3c, "Invalid size of i2c_ana_mst_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** I3C_SLV_CONFIG_REG register
* NA
*/
#define I3C_SLV_CONFIG_REG (DR_REG_I3C_SLV_BASE + 0x4)
/** I3C_SLV_SLVENA : R/W; bitpos: [0]; default: 1;
* 1: allow the slave to operate on i2c or i3c bus. 0: the slave will ignore the bus.
* This should be not set until registers such as PARTNO, IDEXT and the like are set
* 1st -if used- since they impact data to the master
*/
#define I3C_SLV_SLVENA (BIT(0))
#define I3C_SLV_SLVENA_M (I3C_SLV_SLVENA_V << I3C_SLV_SLVENA_S)
#define I3C_SLV_SLVENA_V 0x00000001U
#define I3C_SLV_SLVENA_S 0
/** I3C_SLV_NACK : R/W; bitpos: [1]; default: 0;
* 1:the slave will NACK all requests to it except CCC broadcast. This should be used
* with caution as the Master may determine the slave is missing if overused.
*/
#define I3C_SLV_NACK (BIT(1))
#define I3C_SLV_NACK_M (I3C_SLV_NACK_V << I3C_SLV_NACK_S)
#define I3C_SLV_NACK_V 0x00000001U
#define I3C_SLV_NACK_S 1
/** I3C_SLV_MATCHSS : R/W; bitpos: [2]; default: 0;
* 1: the START and STOP sticky STATUS bits will only be set if MATCHED is set..This
* allows START and STOP to be used to detect end of a message to /from this slave.
*/
#define I3C_SLV_MATCHSS (BIT(2))
#define I3C_SLV_MATCHSS_M (I3C_SLV_MATCHSS_V << I3C_SLV_MATCHSS_S)
#define I3C_SLV_MATCHSS_V 0x00000001U
#define I3C_SLV_MATCHSS_S 2
/** I3C_SLV_S0IGNORE : R/W; bitpos: [3]; default: 0;
* If 1, the Slave will not detect S0 or S1 errors and so not lock up waiting on an
* Exit Pattern. This should only be used when the bus will not use HDR.
*/
#define I3C_SLV_S0IGNORE (BIT(3))
#define I3C_SLV_S0IGNORE_M (I3C_SLV_S0IGNORE_V << I3C_SLV_S0IGNORE_S)
#define I3C_SLV_S0IGNORE_V 0x00000001U
#define I3C_SLV_S0IGNORE_S 3
/** I3C_SLV_DDROK : R/W; bitpos: [4]; default: 0;
* NA
*/
#define I3C_SLV_DDROK (BIT(4))
#define I3C_SLV_DDROK_M (I3C_SLV_DDROK_V << I3C_SLV_DDROK_S)
#define I3C_SLV_DDROK_V 0x00000001U
#define I3C_SLV_DDROK_S 4
/** I3C_SLV_IDRAND : R/W; bitpos: [8]; default: 0;
* NA
*/
#define I3C_SLV_IDRAND (BIT(8))
#define I3C_SLV_IDRAND_M (I3C_SLV_IDRAND_V << I3C_SLV_IDRAND_S)
#define I3C_SLV_IDRAND_V 0x00000001U
#define I3C_SLV_IDRAND_S 8
/** I3C_SLV_OFFLINE : R/W; bitpos: [9]; default: 0;
* NA
*/
#define I3C_SLV_OFFLINE (BIT(9))
#define I3C_SLV_OFFLINE_M (I3C_SLV_OFFLINE_V << I3C_SLV_OFFLINE_S)
#define I3C_SLV_OFFLINE_V 0x00000001U
#define I3C_SLV_OFFLINE_S 9
/** I3C_SLV_BAMATCH : R/W; bitpos: [23:16]; default: 47;
* Bus Available condition match value for current ???Slow clock???. This provides the
* count of the slow clock to count out 1us (or more) to allow an IBI to drive SDA Low
* when the Master is not doing so. The max width , and so max value, is controlled by
* the block. Only if enabled for events such IBI or MR or HJ, and if enabled to
* provide this as a register. With is limited to CLK_SLOW_BITS
*/
#define I3C_SLV_BAMATCH 0x000000FFU
#define I3C_SLV_BAMATCH_M (I3C_SLV_BAMATCH_V << I3C_SLV_BAMATCH_S)
#define I3C_SLV_BAMATCH_V 0x000000FFU
#define I3C_SLV_BAMATCH_S 16
/** I3C_SLV_SADDR : R/W; bitpos: [31:25]; default: 0;
* If allowed by the block:sets i2c 7 bits static address,else should be 0. If enabled
* to use one and to be provided by SW. Block may provide in HW as well.
*/
#define I3C_SLV_SADDR 0x0000007FU
#define I3C_SLV_SADDR_M (I3C_SLV_SADDR_V << I3C_SLV_SADDR_S)
#define I3C_SLV_SADDR_V 0x0000007FU
#define I3C_SLV_SADDR_S 25
/** I3C_SLV_STATUS_REG register
* NA
*/
#define I3C_SLV_STATUS_REG (DR_REG_I3C_SLV_BASE + 0x8)
/** I3C_SLV_STNOTSTOP : RO; bitpos: [0]; default: 0;
* Is 1 if bus is busy(activity) and 0 when in a STOP condition. Other bits may also
* set when busy. Note that this can also be true from an S0 or S1 error, which waits
* for an Exit Pattern.
*/
#define I3C_SLV_STNOTSTOP (BIT(0))
#define I3C_SLV_STNOTSTOP_M (I3C_SLV_STNOTSTOP_V << I3C_SLV_STNOTSTOP_S)
#define I3C_SLV_STNOTSTOP_V 0x00000001U
#define I3C_SLV_STNOTSTOP_S 0
/** I3C_SLV_STMSG : RO; bitpos: [1]; default: 0;
* Is 1 if this bus Slave is listening to the bus traffic or repsonding, If
* STNOSTOP=1, then this will be 0 when a non-matching address seen until next
* respeated START it STOP.
*/
#define I3C_SLV_STMSG (BIT(1))
#define I3C_SLV_STMSG_M (I3C_SLV_STMSG_V << I3C_SLV_STMSG_S)
#define I3C_SLV_STMSG_V 0x00000001U
#define I3C_SLV_STMSG_S 1
/** I3C_SLV_STCCCH : RO; bitpos: [2]; default: 0;
* Is 1 if a CCC message is being handled automatically.
*/
#define I3C_SLV_STCCCH (BIT(2))
#define I3C_SLV_STCCCH_M (I3C_SLV_STCCCH_V << I3C_SLV_STCCCH_S)
#define I3C_SLV_STCCCH_V 0x00000001U
#define I3C_SLV_STCCCH_S 2
/** I3C_SLV_STREQRD : RO; bitpos: [3]; default: 0;
* 1 if the req in process is an sdr read from this slave or an IBI is being pushed
* out,
*/
#define I3C_SLV_STREQRD (BIT(3))
#define I3C_SLV_STREQRD_M (I3C_SLV_STREQRD_V << I3C_SLV_STREQRD_S)
#define I3C_SLV_STREQRD_V 0x00000001U
#define I3C_SLV_STREQRD_S 3
/** I3C_SLV_STREQWR : RO; bitpos: [4]; default: 0;
* NA
*/
#define I3C_SLV_STREQWR (BIT(4))
#define I3C_SLV_STREQWR_M (I3C_SLV_STREQWR_V << I3C_SLV_STREQWR_S)
#define I3C_SLV_STREQWR_V 0x00000001U
#define I3C_SLV_STREQWR_S 4
/** I3C_SLV_STDAA : RO; bitpos: [5]; default: 0;
* NA
*/
#define I3C_SLV_STDAA (BIT(5))
#define I3C_SLV_STDAA_M (I3C_SLV_STDAA_V << I3C_SLV_STDAA_S)
#define I3C_SLV_STDAA_V 0x00000001U
#define I3C_SLV_STDAA_S 5
/** I3C_SLV_STHDR : RO; bitpos: [6]; default: 0;
* NA
*/
#define I3C_SLV_STHDR (BIT(6))
#define I3C_SLV_STHDR_M (I3C_SLV_STHDR_V << I3C_SLV_STHDR_S)
#define I3C_SLV_STHDR_V 0x00000001U
#define I3C_SLV_STHDR_S 6
/** I3C_SLV_START : R/W; bitpos: [8]; default: 0;
* NA
*/
#define I3C_SLV_START (BIT(8))
#define I3C_SLV_START_M (I3C_SLV_START_V << I3C_SLV_START_S)
#define I3C_SLV_START_V 0x00000001U
#define I3C_SLV_START_S 8
/** I3C_SLV_MATCHED : R/W; bitpos: [9]; default: 0;
* NA
*/
#define I3C_SLV_MATCHED (BIT(9))
#define I3C_SLV_MATCHED_M (I3C_SLV_MATCHED_V << I3C_SLV_MATCHED_S)
#define I3C_SLV_MATCHED_V 0x00000001U
#define I3C_SLV_MATCHED_S 9
/** I3C_SLV_STOP : R/W; bitpos: [10]; default: 0;
* NA
*/
#define I3C_SLV_STOP (BIT(10))
#define I3C_SLV_STOP_M (I3C_SLV_STOP_V << I3C_SLV_STOP_S)
#define I3C_SLV_STOP_V 0x00000001U
#define I3C_SLV_STOP_S 10
/** I3C_SLV_RXPEND : RO; bitpos: [11]; default: 0;
* Receiving a message from master,which is not being handled by block(not a CCC
* internally processed). For all but External FIFO, this uses DATACTRL RXTRIG, which
* defaults to not-empty. If DMA is enabled for RX, DMA will be signaled as well. Will
* self-clear if data is read(FIFO and non-FIFO)
*/
#define I3C_SLV_RXPEND (BIT(11))
#define I3C_SLV_RXPEND_M (I3C_SLV_RXPEND_V << I3C_SLV_RXPEND_S)
#define I3C_SLV_RXPEND_V 0x00000001U
#define I3C_SLV_RXPEND_S 11
/** I3C_SLV_TXNOTFULL : RO; bitpos: [12]; default: 0;
* Is 1 when the To-bus buffer/FIFO can accept more data to go out. Defau:1. For all
* but External FIFO, this uses DATACTRL TXTRIG,which defaults to not-full. If DMA is
* enabled for TX, it will also be signaled to provide more.
*/
#define I3C_SLV_TXNOTFULL (BIT(12))
#define I3C_SLV_TXNOTFULL_M (I3C_SLV_TXNOTFULL_V << I3C_SLV_TXNOTFULL_S)
#define I3C_SLV_TXNOTFULL_V 0x00000001U
#define I3C_SLV_TXNOTFULL_S 12
/** I3C_SLV_DACHG : R/W; bitpos: [13]; default: 0;
* The Slv Dynamic Address has been assigned, reassigned, or reset(lost) and is now in
* that state of being valid or none. Actual DA can be seen in the DYNADDR register.
* Note that this will also be used when MAP Auto feature is configured. This will be
* changing one or more MAP items. See DYNADDR and/or MAPCTRLn. DYNAADDR for the main
* DA(0) will indicate if last change was due to Auto MAP.
*/
#define I3C_SLV_DACHG (BIT(13))
#define I3C_SLV_DACHG_M (I3C_SLV_DACHG_V << I3C_SLV_DACHG_S)
#define I3C_SLV_DACHG_V 0x00000001U
#define I3C_SLV_DACHG_S 13
/** I3C_SLV_CCC : R/W; bitpos: [14]; default: 0;
* A common -command-code(CCC), not handled by block, has been received. This acts
* differently between: *Broadcasted ones, which will then also correspond with RXPEND
* and the 1st byte will be the CCC(command) . *Direct ones, which may never be
* directed to this device. If it is, then the TXSEND or RXPEND will be triggered
* with this end the RXPEND will contain the command.
*/
#define I3C_SLV_CCC (BIT(14))
#define I3C_SLV_CCC_M (I3C_SLV_CCC_V << I3C_SLV_CCC_S)
#define I3C_SLV_CCC_V 0x00000001U
#define I3C_SLV_CCC_S 14
/** I3C_SLV_ERRWARN : RO; bitpos: [15]; default: 0;
* NA
*/
#define I3C_SLV_ERRWARN (BIT(15))
#define I3C_SLV_ERRWARN_M (I3C_SLV_ERRWARN_V << I3C_SLV_ERRWARN_S)
#define I3C_SLV_ERRWARN_V 0x00000001U
#define I3C_SLV_ERRWARN_S 15
/** I3C_SLV_HDRMATCH : R/W; bitpos: [16]; default: 0;
* NA
*/
#define I3C_SLV_HDRMATCH (BIT(16))
#define I3C_SLV_HDRMATCH_M (I3C_SLV_HDRMATCH_V << I3C_SLV_HDRMATCH_S)
#define I3C_SLV_HDRMATCH_V 0x00000001U
#define I3C_SLV_HDRMATCH_S 16
/** I3C_SLV_CTRL_REG register
* NA
*/
#define I3C_SLV_CTRL_REG (DR_REG_I3C_SLV_BASE + 0xc)
/** I3C_SLV_SLV_EVENT : R/W; bitpos: [1:0]; default: 0;
* If set to non-0, will request an event. Once requested, STATUS.EVENT and EVDET will
* show the status as it progresses. Once completed, the field will automatically
* return to 0. Once non-0, only 0 can be written(to cancel) until done. 0: Normal
* mode. If set to 0 after was a non-0 value, will cancel if not already in flight. 1:
* start an IBI. This will try to push through an IBI on the bus. If data associate
* with the IBI, it will be drawn from the IBIDATA field. Note that if Time control is
* enabled, this will include anytime control related bytes further, the IBIDATA byte
* will have bit7 set to 1.
*/
#define I3C_SLV_SLV_EVENT 0x00000003U
#define I3C_SLV_SLV_EVENT_M (I3C_SLV_SLV_EVENT_V << I3C_SLV_SLV_EVENT_S)
#define I3C_SLV_SLV_EVENT_V 0x00000003U
#define I3C_SLV_SLV_EVENT_S 0
/** I3C_SLV_EXTDATA : R/W; bitpos: [3]; default: 0;
* reserved
*/
#define I3C_SLV_EXTDATA (BIT(3))
#define I3C_SLV_EXTDATA_M (I3C_SLV_EXTDATA_V << I3C_SLV_EXTDATA_S)
#define I3C_SLV_EXTDATA_V 0x00000001U
#define I3C_SLV_EXTDATA_S 3
/** I3C_SLV_MAPIDX : R/W; bitpos: [7:4]; default: 0;
* Index of Dynamic Address that IBI is for. This is 0 for the main or base Dynamic
* Address, or can be any valid index.
*/
#define I3C_SLV_MAPIDX 0x0000000FU
#define I3C_SLV_MAPIDX_M (I3C_SLV_MAPIDX_V << I3C_SLV_MAPIDX_S)
#define I3C_SLV_MAPIDX_V 0x0000000FU
#define I3C_SLV_MAPIDX_S 4
/** I3C_SLV_IBIDATA : R/W; bitpos: [15:8]; default: 0;
* Data byte to go with an IBI, if enabled for it. If enabled (was in BCR), then it is
* required.
*/
#define I3C_SLV_IBIDATA 0x000000FFU
#define I3C_SLV_IBIDATA_M (I3C_SLV_IBIDATA_V << I3C_SLV_IBIDATA_S)
#define I3C_SLV_IBIDATA_V 0x000000FFU
#define I3C_SLV_IBIDATA_S 8
/** I3C_SLV_PENDINT : R/W; bitpos: [19:16]; default: 0;
* Should be set to the pending interrupt that GETSTATUS CCC will return. This should
* be maintained by the application if used and configured, as the Master will read
* this. If not configured, the GETSTATUS field will return 1 if an IBI is pending,
* and 0 otherwise.
*/
#define I3C_SLV_PENDINT 0x0000000FU
#define I3C_SLV_PENDINT_M (I3C_SLV_PENDINT_V << I3C_SLV_PENDINT_S)
#define I3C_SLV_PENDINT_V 0x0000000FU
#define I3C_SLV_PENDINT_S 16
/** I3C_SLV_ACTSTATE : R/W; bitpos: [21:20]; default: 0;
* NA
*/
#define I3C_SLV_ACTSTATE 0x00000003U
#define I3C_SLV_ACTSTATE_M (I3C_SLV_ACTSTATE_V << I3C_SLV_ACTSTATE_S)
#define I3C_SLV_ACTSTATE_V 0x00000003U
#define I3C_SLV_ACTSTATE_S 20
/** I3C_SLV_VENDINFO : R/W; bitpos: [31:24]; default: 0;
* NA
*/
#define I3C_SLV_VENDINFO 0x000000FFU
#define I3C_SLV_VENDINFO_M (I3C_SLV_VENDINFO_V << I3C_SLV_VENDINFO_S)
#define I3C_SLV_VENDINFO_V 0x000000FFU
#define I3C_SLV_VENDINFO_S 24
/** I3C_SLV_INTSET_REG register
* INSET allows setting enables for interrupts(connecting the corresponding STATUS
* source to causing an IRQ to the processor)
*/
#define I3C_SLV_INTSET_REG (DR_REG_I3C_SLV_BASE + 0x10)
/** I3C_SLV_STOP_ENA : R/W; bitpos: [10]; default: 0;
* Interrupt on STOP state on the bus. See Start as the preferred interrupt when
* needed. This interrupt may not trigger for quick STOP/START combination, as it
* relates to the state of being stopped.
*/
#define I3C_SLV_STOP_ENA (BIT(10))
#define I3C_SLV_STOP_ENA_M (I3C_SLV_STOP_ENA_V << I3C_SLV_STOP_ENA_S)
#define I3C_SLV_STOP_ENA_V 0x00000001U
#define I3C_SLV_STOP_ENA_S 10
/** I3C_SLV_RXPEND_ENA : R/W; bitpos: [11]; default: 0;
* Interrupt when receiving a message from Master, which is not being handled by the
* block (excludes CCCs being handled automatically). If FIFO, then RX fullness
* trigger. If DMA, then message end.
*/
#define I3C_SLV_RXPEND_ENA (BIT(11))
#define I3C_SLV_RXPEND_ENA_M (I3C_SLV_RXPEND_ENA_V << I3C_SLV_RXPEND_ENA_S)
#define I3C_SLV_RXPEND_ENA_V 0x00000001U
#define I3C_SLV_RXPEND_ENA_S 11
/** I3C_SLV_TXSEND_ENA : R/W; bitpos: [12]; default: 0;
* NA
*/
#define I3C_SLV_TXSEND_ENA (BIT(12))
#define I3C_SLV_TXSEND_ENA_M (I3C_SLV_TXSEND_ENA_V << I3C_SLV_TXSEND_ENA_S)
#define I3C_SLV_TXSEND_ENA_V 0x00000001U
#define I3C_SLV_TXSEND_ENA_S 12
/** I3C_SLV_INTCLR_REG register
* NA
*/
#define I3C_SLV_INTCLR_REG (DR_REG_I3C_SLV_BASE + 0x14)
/** I3C_SLV_STOP_CLR : WO; bitpos: [10]; default: 0;
* Interrupt on STOP state on the bus. See Start as the preferred interrupt when
* needed. This interrupt may not trigger for quick STOP/START combination, as it
* relates to the state of being stopped.
*/
#define I3C_SLV_STOP_CLR (BIT(10))
#define I3C_SLV_STOP_CLR_M (I3C_SLV_STOP_CLR_V << I3C_SLV_STOP_CLR_S)
#define I3C_SLV_STOP_CLR_V 0x00000001U
#define I3C_SLV_STOP_CLR_S 10
/** I3C_SLV_RXPEND_CLR : WO; bitpos: [11]; default: 0;
* Interrupt when receiving a message from Master, which is not being handled by the
* block (excludes CCCs being handled automatically). If FIFO, then RX fullness
* trigger. If DMA, then message end.
*/
#define I3C_SLV_RXPEND_CLR (BIT(11))
#define I3C_SLV_RXPEND_CLR_M (I3C_SLV_RXPEND_CLR_V << I3C_SLV_RXPEND_CLR_S)
#define I3C_SLV_RXPEND_CLR_V 0x00000001U
#define I3C_SLV_RXPEND_CLR_S 11
/** I3C_SLV_TXSEND_CLR : WO; bitpos: [12]; default: 0;
* NA
*/
#define I3C_SLV_TXSEND_CLR (BIT(12))
#define I3C_SLV_TXSEND_CLR_M (I3C_SLV_TXSEND_CLR_V << I3C_SLV_TXSEND_CLR_S)
#define I3C_SLV_TXSEND_CLR_V 0x00000001U
#define I3C_SLV_TXSEND_CLR_S 12
/** I3C_SLV_INTMASKED_REG register
* NA
*/
#define I3C_SLV_INTMASKED_REG (DR_REG_I3C_SLV_BASE + 0x18)
/** I3C_SLV_STOP_MASK : RO; bitpos: [10]; default: 0;
* Interrupt on STOP state on the bus. See Start as the preferred interrupt when
* needed. This interrupt may not trigger for quick STOP/START combination, as it
* relates to the state of being stopped.
*/
#define I3C_SLV_STOP_MASK (BIT(10))
#define I3C_SLV_STOP_MASK_M (I3C_SLV_STOP_MASK_V << I3C_SLV_STOP_MASK_S)
#define I3C_SLV_STOP_MASK_V 0x00000001U
#define I3C_SLV_STOP_MASK_S 10
/** I3C_SLV_RXPEND_MASK : RO; bitpos: [11]; default: 0;
* Interrupt when receiving a message from Master, which is not being handled by the
* block (excludes CCCs being handled automatically). If FIFO, then RX fullness
* trigger. If DMA, then message end.
*/
#define I3C_SLV_RXPEND_MASK (BIT(11))
#define I3C_SLV_RXPEND_MASK_M (I3C_SLV_RXPEND_MASK_V << I3C_SLV_RXPEND_MASK_S)
#define I3C_SLV_RXPEND_MASK_V 0x00000001U
#define I3C_SLV_RXPEND_MASK_S 11
/** I3C_SLV_TXSEND_MASK : RO; bitpos: [12]; default: 0;
* NA
*/
#define I3C_SLV_TXSEND_MASK (BIT(12))
#define I3C_SLV_TXSEND_MASK_M (I3C_SLV_TXSEND_MASK_V << I3C_SLV_TXSEND_MASK_S)
#define I3C_SLV_TXSEND_MASK_V 0x00000001U
#define I3C_SLV_TXSEND_MASK_S 12
/** I3C_SLV_DATACTRL_REG register
* NA
*/
#define I3C_SLV_DATACTRL_REG (DR_REG_I3C_SLV_BASE + 0x2c)
/** I3C_SLV_FLUSHTB : WO; bitpos: [0]; default: 0;
* Flushes the from-bus buffer/FIFO. Not normally used
*/
#define I3C_SLV_FLUSHTB (BIT(0))
#define I3C_SLV_FLUSHTB_M (I3C_SLV_FLUSHTB_V << I3C_SLV_FLUSHTB_S)
#define I3C_SLV_FLUSHTB_V 0x00000001U
#define I3C_SLV_FLUSHTB_S 0
/** I3C_SLV_FLUSHFB : WO; bitpos: [1]; default: 0;
* Flushes the to-bus buffer/FIFO. Used when Master terminates a to-bus (read) message
* prematurely
*/
#define I3C_SLV_FLUSHFB (BIT(1))
#define I3C_SLV_FLUSHFB_M (I3C_SLV_FLUSHFB_V << I3C_SLV_FLUSHFB_S)
#define I3C_SLV_FLUSHFB_V 0x00000001U
#define I3C_SLV_FLUSHFB_S 1
/** I3C_SLV_UNLOCK : WO; bitpos: [3]; default: 0;
* If this bit is not written 1, the register bits from 7 to 4 are not changed on
* write.
*/
#define I3C_SLV_UNLOCK (BIT(3))
#define I3C_SLV_UNLOCK_M (I3C_SLV_UNLOCK_V << I3C_SLV_UNLOCK_S)
#define I3C_SLV_UNLOCK_V 0x00000001U
#define I3C_SLV_UNLOCK_S 3
/** I3C_SLV_TXTRIG : R/W; bitpos: [5:4]; default: 3;
* Trigger level for tx emptiness when FIFOed, Affects interrupt and DMA(if enabled).
* The defaults is 3
*/
#define I3C_SLV_TXTRIG 0x00000003U
#define I3C_SLV_TXTRIG_M (I3C_SLV_TXTRIG_V << I3C_SLV_TXTRIG_S)
#define I3C_SLV_TXTRIG_V 0x00000003U
#define I3C_SLV_TXTRIG_S 4
/** I3C_SLV_RXTRIG : R/W; bitpos: [7:6]; default: 2;
* Trigger level for rx fulless when FIFOed, Affects interrupt and DMA(if enabled).
* The defaults is 3
*/
#define I3C_SLV_RXTRIG 0x00000003U
#define I3C_SLV_RXTRIG_M (I3C_SLV_RXTRIG_V << I3C_SLV_RXTRIG_S)
#define I3C_SLV_RXTRIG_V 0x00000003U
#define I3C_SLV_RXTRIG_S 6
/** I3C_SLV_TXCOUNT : RO; bitpos: [20:16]; default: 0;
* NA
*/
#define I3C_SLV_TXCOUNT 0x0000001FU
#define I3C_SLV_TXCOUNT_M (I3C_SLV_TXCOUNT_V << I3C_SLV_TXCOUNT_S)
#define I3C_SLV_TXCOUNT_V 0x0000001FU
#define I3C_SLV_TXCOUNT_S 16
/** I3C_SLV_RXCOUNT : RO; bitpos: [28:24]; default: 0;
* NA
*/
#define I3C_SLV_RXCOUNT 0x0000001FU
#define I3C_SLV_RXCOUNT_M (I3C_SLV_RXCOUNT_V << I3C_SLV_RXCOUNT_S)
#define I3C_SLV_RXCOUNT_V 0x0000001FU
#define I3C_SLV_RXCOUNT_S 24
/** I3C_SLV_TXFULL : RO; bitpos: [30]; default: 0;
* NA
*/
#define I3C_SLV_TXFULL (BIT(30))
#define I3C_SLV_TXFULL_M (I3C_SLV_TXFULL_V << I3C_SLV_TXFULL_S)
#define I3C_SLV_TXFULL_V 0x00000001U
#define I3C_SLV_TXFULL_S 30
/** I3C_SLV_RXEMPTY : RO; bitpos: [31]; default: 0;
* NA
*/
#define I3C_SLV_RXEMPTY (BIT(31))
#define I3C_SLV_RXEMPTY_M (I3C_SLV_RXEMPTY_V << I3C_SLV_RXEMPTY_S)
#define I3C_SLV_RXEMPTY_V 0x00000001U
#define I3C_SLV_RXEMPTY_S 31
/** I3C_SLV_WDATAB_REG register
* NA
*/
#define I3C_SLV_WDATAB_REG (DR_REG_I3C_SLV_BASE + 0x30)
/** I3C_SLV_WDATAB : WO; bitpos: [7:0]; default: 0;
* NA
*/
#define I3C_SLV_WDATAB 0x000000FFU
#define I3C_SLV_WDATAB_M (I3C_SLV_WDATAB_V << I3C_SLV_WDATAB_S)
#define I3C_SLV_WDATAB_V 0x000000FFU
#define I3C_SLV_WDATAB_S 0
/** I3C_SLV_WDATA_END : WO; bitpos: [8]; default: 0;
* NA
*/
#define I3C_SLV_WDATA_END (BIT(8))
#define I3C_SLV_WDATA_END_M (I3C_SLV_WDATA_END_V << I3C_SLV_WDATA_END_S)
#define I3C_SLV_WDATA_END_V 0x00000001U
#define I3C_SLV_WDATA_END_S 8
/** I3C_SLV_WDATABE_REG register
* NA
*/
#define I3C_SLV_WDATABE_REG (DR_REG_I3C_SLV_BASE + 0x34)
/** I3C_SLV_WDATABE : WO; bitpos: [7:0]; default: 0;
* NA
*/
#define I3C_SLV_WDATABE 0x000000FFU
#define I3C_SLV_WDATABE_M (I3C_SLV_WDATABE_V << I3C_SLV_WDATABE_S)
#define I3C_SLV_WDATABE_V 0x000000FFU
#define I3C_SLV_WDATABE_S 0
/** I3C_SLV_RDARAB_REG register
* Read Byte Data (from-bus) register
*/
#define I3C_SLV_RDARAB_REG (DR_REG_I3C_SLV_BASE + 0x40)
/** I3C_SLV_DATA0 : RO; bitpos: [7:0]; default: 0;
* This register allows reading a byte from the bus unless external FIFO is used. A
* byte should not be read unless there is data waiting, as indicated by the RXPEND
* bit being set in the STATUS register
*/
#define I3C_SLV_DATA0 0x000000FFU
#define I3C_SLV_DATA0_M (I3C_SLV_DATA0_V << I3C_SLV_DATA0_S)
#define I3C_SLV_DATA0_V 0x000000FFU
#define I3C_SLV_DATA0_S 0
/** I3C_SLV_RDATAH_REG register
* Read Half-word Data (from-bus) register
*/
#define I3C_SLV_RDATAH_REG (DR_REG_I3C_SLV_BASE + 0x48)
/** I3C_SLV_DATA_LSB : RO; bitpos: [7:0]; default: 0;
* NA
*/
#define I3C_SLV_DATA_LSB 0x000000FFU
#define I3C_SLV_DATA_LSB_M (I3C_SLV_DATA_LSB_V << I3C_SLV_DATA_LSB_S)
#define I3C_SLV_DATA_LSB_V 0x000000FFU
#define I3C_SLV_DATA_LSB_S 0
/** I3C_SLV_DATA_MSB : RO; bitpos: [15:8]; default: 0;
* This register allows reading a Half-word (byte pair) from the bus unless external
* FIFO is used. A Half-word should not be read unless there is at least 2 bytes of
* data waiting, as indicated by the RX FIFO level trigger or RXCOUNT available space
* in the DATACTRL register
*/
#define I3C_SLV_DATA_MSB 0x000000FFU
#define I3C_SLV_DATA_MSB_M (I3C_SLV_DATA_MSB_V << I3C_SLV_DATA_MSB_S)
#define I3C_SLV_DATA_MSB_V 0x000000FFU
#define I3C_SLV_DATA_MSB_S 8
/** I3C_SLV_CAPABILITIES2_REG register
* NA
*/
#define I3C_SLV_CAPABILITIES2_REG (DR_REG_I3C_SLV_BASE + 0x5c)
/** I3C_SLV_CAPABLITIES2 : RO; bitpos: [31:0]; default: 256;
* NA
*/
#define I3C_SLV_CAPABLITIES2 0xFFFFFFFFU
#define I3C_SLV_CAPABLITIES2_M (I3C_SLV_CAPABLITIES2_V << I3C_SLV_CAPABLITIES2_S)
#define I3C_SLV_CAPABLITIES2_V 0xFFFFFFFFU
#define I3C_SLV_CAPABLITIES2_S 0
/** I3C_SLV_CAPABILITIES_REG register
* NA
*/
#define I3C_SLV_CAPABILITIES_REG (DR_REG_I3C_SLV_BASE + 0x60)
/** I3C_SLV_CAPABLITIES : RO; bitpos: [31:0]; default: 2081684508;
* NA
*/
#define I3C_SLV_CAPABLITIES 0xFFFFFFFFU
#define I3C_SLV_CAPABLITIES_M (I3C_SLV_CAPABLITIES_V << I3C_SLV_CAPABLITIES_S)
#define I3C_SLV_CAPABLITIES_V 0xFFFFFFFFU
#define I3C_SLV_CAPABLITIES_S 0
/** I3C_SLV_IDPARTNO_REG register
* NA
*/
#define I3C_SLV_IDPARTNO_REG (DR_REG_I3C_SLV_BASE + 0x6c)
/** I3C_SLV_PARTNO : R/W; bitpos: [31:0]; default: 0;
* NA
*/
#define I3C_SLV_PARTNO 0xFFFFFFFFU
#define I3C_SLV_PARTNO_M (I3C_SLV_PARTNO_V << I3C_SLV_PARTNO_S)
#define I3C_SLV_PARTNO_V 0xFFFFFFFFU
#define I3C_SLV_PARTNO_S 0
/** I3C_SLV_IDEXT_REG register
* NA
*/
#define I3C_SLV_IDEXT_REG (DR_REG_I3C_SLV_BASE + 0x70)
/** I3C_SLV_IDEXT : R/W; bitpos: [31:0]; default: 0;
* NA
*/
#define I3C_SLV_IDEXT 0xFFFFFFFFU
#define I3C_SLV_IDEXT_M (I3C_SLV_IDEXT_V << I3C_SLV_IDEXT_S)
#define I3C_SLV_IDEXT_V 0xFFFFFFFFU
#define I3C_SLV_IDEXT_S 0
/** I3C_SLV_VENDORID_REG register
* NA
*/
#define I3C_SLV_VENDORID_REG (DR_REG_I3C_SLV_BASE + 0x74)
/** I3C_SLV_VID : R/W; bitpos: [14:0]; default: 21840;
* NA
*/
#define I3C_SLV_VID 0x00007FFFU
#define I3C_SLV_VID_M (I3C_SLV_VID_V << I3C_SLV_VID_S)
#define I3C_SLV_VID_V 0x00007FFFU
#define I3C_SLV_VID_S 0
#ifdef __cplusplus
}
#endif

549
components/soc/esp32p4/include/soc/i3c_slv_struct.h Normal file
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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: I3C_SLV CONFIG REG */
/** Type of config register
* NA
*/
typedef union {
struct {
/** slvena : R/W; bitpos: [0]; default: 1;
* 1: allow the slave to operate on i2c or i3c bus. 0: the slave will ignore the bus.
* This should be not set until registers such as PARTNO, IDEXT and the like are set
* 1st -if used- since they impact data to the master
*/
uint32_t slvena:1;
/** nack : R/W; bitpos: [1]; default: 0;
* 1:the slave will NACK all requests to it except CCC broadcast. This should be used
* with caution as the Master may determine the slave is missing if overused.
*/
uint32_t nack:1;
/** matchss : R/W; bitpos: [2]; default: 0;
* 1: the START and STOP sticky STATUS bits will only be set if MATCHED is set..This
* allows START and STOP to be used to detect end of a message to /from this slave.
*/
uint32_t matchss:1;
/** s0ignore : R/W; bitpos: [3]; default: 0;
* If 1, the Slave will not detect S0 or S1 errors and so not lock up waiting on an
* Exit Pattern. This should only be used when the bus will not use HDR.
*/
uint32_t s0ignore:1;
/** ddrok : R/W; bitpos: [4]; default: 0;
* NA
*/
uint32_t ddrok:1;
uint32_t reserved_5:3;
/** idrand : R/W; bitpos: [8]; default: 0;
* NA
*/
uint32_t idrand:1;
/** offline : R/W; bitpos: [9]; default: 0;
* NA
*/
uint32_t offline:1;
uint32_t reserved_10:6;
/** bamatch : R/W; bitpos: [23:16]; default: 47;
* Bus Available condition match value for current ???Slow clock???. This provides the
* count of the slow clock to count out 1us (or more) to allow an IBI to drive SDA Low
* when the Master is not doing so. The max width , and so max value, is controlled by
* the block. Only if enabled for events such IBI or MR or HJ, and if enabled to
* provide this as a register. With is limited to CLK_SLOW_BITS
*/
uint32_t bamatch:8;
uint32_t reserved_24:1;
/** saddr : R/W; bitpos: [31:25]; default: 0;
* If allowed by the block:sets i2c 7 bits static address,else should be 0. If enabled
* to use one and to be provided by SW. Block may provide in HW as well.
*/
uint32_t saddr:7;
};
uint32_t val;
} i3c_slv_config_reg_t;
/** Group: I3C_SLV STATUS REG */
/** Type of status register
* NA
*/
typedef union {
struct {
/** stnotstop : RO; bitpos: [0]; default: 0;
* Is 1 if bus is busy(activity) and 0 when in a STOP condition. Other bits may also
* set when busy. Note that this can also be true from an S0 or S1 error, which waits
* for an Exit Pattern.
*/
uint32_t stnotstop:1;
/** stmsg : RO; bitpos: [1]; default: 0;
* Is 1 if this bus Slave is listening to the bus traffic or repsonding, If
* STNOSTOP=1, then this will be 0 when a non-matching address seen until next
* respeated START it STOP.
*/
uint32_t stmsg:1;
/** stccch : RO; bitpos: [2]; default: 0;
* Is 1 if a CCC message is being handled automatically.
*/
uint32_t stccch:1;
/** streqrd : RO; bitpos: [3]; default: 0;
* 1 if the req in process is an sdr read from this slave or an IBI is being pushed
* out,
*/
uint32_t streqrd:1;
/** streqwr : RO; bitpos: [4]; default: 0;
* NA
*/
uint32_t streqwr:1;
/** stdaa : RO; bitpos: [5]; default: 0;
* NA
*/
uint32_t stdaa:1;
/** sthdr : RO; bitpos: [6]; default: 0;
* NA
*/
uint32_t sthdr:1;
uint32_t reserved_7:1;
/** start : R/W; bitpos: [8]; default: 0;
* NA
*/
uint32_t start:1;
/** matched : R/W; bitpos: [9]; default: 0;
* NA
*/
uint32_t matched:1;
/** stop : R/W; bitpos: [10]; default: 0;
* NA
*/
uint32_t stop:1;
/** rxpend : RO; bitpos: [11]; default: 0;
* Receiving a message from master,which is not being handled by block(not a CCC
* internally processed). For all but External FIFO, this uses DATACTRL RXTRIG, which
* defaults to not-empty. If DMA is enabled for RX, DMA will be signaled as well. Will
* self-clear if data is read(FIFO and non-FIFO)
*/
uint32_t rxpend:1;
/** txnotfull : RO; bitpos: [12]; default: 0;
* Is 1 when the To-bus buffer/FIFO can accept more data to go out. Defau:1. For all
* but External FIFO, this uses DATACTRL TXTRIG,which defaults to not-full. If DMA is
* enabled for TX, it will also be signaled to provide more.
*/
uint32_t txnotfull:1;
/** dachg : R/W; bitpos: [13]; default: 0;
* The Slv Dynamic Address has been assigned, reassigned, or reset(lost) and is now in
* that state of being valid or none. Actual DA can be seen in the DYNADDR register.
* Note that this will also be used when MAP Auto feature is configured. This will be
* changing one or more MAP items. See DYNADDR and/or MAPCTRLn. DYNAADDR for the main
* DA(0) will indicate if last change was due to Auto MAP.
*/
uint32_t dachg:1;
/** ccc : R/W; bitpos: [14]; default: 0;
* A common -command-code(CCC), not handled by block, has been received. This acts
* differently between: *Broadcasted ones, which will then also correspond with RXPEND
* and the 1st byte will be the CCC(command) . *Direct ones, which may never be
* directed to this device. If it is, then the TXSEND or RXPEND will be triggered
* with this end the RXPEND will contain the command.
*/
uint32_t ccc:1;
/** errwarn : RO; bitpos: [15]; default: 0;
* NA
*/
uint32_t errwarn:1;
/** hdrmatch : R/W; bitpos: [16]; default: 0;
* NA
*/
uint32_t hdrmatch:1;
uint32_t reserved_17:15;
};
uint32_t val;
} i3c_slv_status_reg_t;
/** Group: I3C_SLV CTRL REG */
/** Type of ctrl register
* NA
*/
typedef union {
struct {
/** slv_event : R/W; bitpos: [1:0]; default: 0;
* If set to non-0, will request an event. Once requested, STATUS.EVENT and EVDET will
* show the status as it progresses. Once completed, the field will automatically
* return to 0. Once non-0, only 0 can be written(to cancel) until done. 0: Normal
* mode. If set to 0 after was a non-0 value, will cancel if not already in flight. 1:
* start an IBI. This will try to push through an IBI on the bus. If data associate
* with the IBI, it will be drawn from the IBIDATA field. Note that if Time control is
* enabled, this will include anytime control related bytes further, the IBIDATA byte
* will have bit7 set to 1.
*/
uint32_t slv_event:2;
uint32_t reserved_2:1;
/** extdata : R/W; bitpos: [3]; default: 0;
* reserved
*/
uint32_t extdata:1;
/** mapidx : R/W; bitpos: [7:4]; default: 0;
* Index of Dynamic Address that IBI is for. This is 0 for the main or base Dynamic
* Address, or can be any valid index.
*/
uint32_t mapidx:4;
/** ibidata : R/W; bitpos: [15:8]; default: 0;
* Data byte to go with an IBI, if enabled for it. If enabled (was in BCR), then it is
* required.
*/
uint32_t ibidata:8;
/** pendint : R/W; bitpos: [19:16]; default: 0;
* Should be set to the pending interrupt that GETSTATUS CCC will return. This should
* be maintained by the application if used and configured, as the Master will read
* this. If not configured, the GETSTATUS field will return 1 if an IBI is pending,
* and 0 otherwise.
*/
uint32_t pendint:4;
/** actstate : R/W; bitpos: [21:20]; default: 0;
* NA
*/
uint32_t actstate:2;
uint32_t reserved_22:2;
/** vendinfo : R/W; bitpos: [31:24]; default: 0;
* NA
*/
uint32_t vendinfo:8;
};
uint32_t val;
} i3c_slv_ctrl_reg_t;
/** Group: I3C_SLV INTSET REG */
/** Type of intset register
* INSET allows setting enables for interrupts(connecting the corresponding STATUS
* source to causing an IRQ to the processor)
*/
typedef union {
struct {
uint32_t reserved_0:10;
/** stop_ena : R/W; bitpos: [10]; default: 0;
* Interrupt on STOP state on the bus. See Start as the preferred interrupt when
* needed. This interrupt may not trigger for quick STOP/START combination, as it
* relates to the state of being stopped.
*/
uint32_t stop_ena:1;
/** rxpend_ena : R/W; bitpos: [11]; default: 0;
* Interrupt when receiving a message from Master, which is not being handled by the
* block (excludes CCCs being handled automatically). If FIFO, then RX fullness
* trigger. If DMA, then message end.
*/
uint32_t rxpend_ena:1;
/** txsend_ena : R/W; bitpos: [12]; default: 0;
* NA
*/
uint32_t txsend_ena:1;
uint32_t reserved_13:19;
};
uint32_t val;
} i3c_slv_intset_reg_t;
/** Group: I3C_SLV INTCLR REG */
/** Type of intclr register
* NA
*/
typedef union {
struct {
uint32_t reserved_0:10;
/** stop_clr : WO; bitpos: [10]; default: 0;
* Interrupt on STOP state on the bus. See Start as the preferred interrupt when
* needed. This interrupt may not trigger for quick STOP/START combination, as it
* relates to the state of being stopped.
*/
uint32_t stop_clr:1;
/** rxpend_clr : WO; bitpos: [11]; default: 0;
* Interrupt when receiving a message from Master, which is not being handled by the
* block (excludes CCCs being handled automatically). If FIFO, then RX fullness
* trigger. If DMA, then message end.
*/
uint32_t rxpend_clr:1;
/** txsend_clr : WO; bitpos: [12]; default: 0;
* NA
*/
uint32_t txsend_clr:1;
uint32_t reserved_13:19;
};
uint32_t val;
} i3c_slv_intclr_reg_t;
/** Group: I3C_SLV INTMASKED REG */
/** Type of intmasked register
* NA
*/
typedef union {
struct {
uint32_t reserved_0:10;
/** stop_mask : RO; bitpos: [10]; default: 0;
* Interrupt on STOP state on the bus. See Start as the preferred interrupt when
* needed. This interrupt may not trigger for quick STOP/START combination, as it
* relates to the state of being stopped.
*/
uint32_t stop_mask:1;
/** rxpend_mask : RO; bitpos: [11]; default: 0;
* Interrupt when receiving a message from Master, which is not being handled by the
* block (excludes CCCs being handled automatically). If FIFO, then RX fullness
* trigger. If DMA, then message end.
*/
uint32_t rxpend_mask:1;
/** txsend_mask : RO; bitpos: [12]; default: 0;
* NA
*/
uint32_t txsend_mask:1;
uint32_t reserved_13:19;
};
uint32_t val;
} i3c_slv_intmasked_reg_t;
/** Group: I3C_SLV DATACTRL REG */
/** Type of datactrl register
* NA
*/
typedef union {
struct {
/** flushtb : WO; bitpos: [0]; default: 0;
* Flushes the from-bus buffer/FIFO. Not normally used
*/
uint32_t flushtb:1;
/** flushfb : WO; bitpos: [1]; default: 0;
* Flushes the to-bus buffer/FIFO. Used when Master terminates a to-bus (read) message
* prematurely
*/
uint32_t flushfb:1;
uint32_t reserved_2:1;
/** unlock : WO; bitpos: [3]; default: 0;
* If this bit is not written 1, the register bits from 7 to 4 are not changed on
* write.
*/
uint32_t unlock:1;
/** txtrig : R/W; bitpos: [5:4]; default: 3;
* Trigger level for tx emptiness when FIFOed, Affects interrupt and DMA(if enabled).
* The defaults is 3
*/
uint32_t txtrig:2;
/** rxtrig : R/W; bitpos: [7:6]; default: 2;
* Trigger level for rx fulless when FIFOed, Affects interrupt and DMA(if enabled).
* The defaults is 3
*/
uint32_t rxtrig:2;
uint32_t reserved_8:8;
/** txcount : RO; bitpos: [20:16]; default: 0;
* NA
*/
uint32_t txcount:5;
uint32_t reserved_21:3;
/** rxcount : RO; bitpos: [28:24]; default: 0;
* NA
*/
uint32_t rxcount:5;
uint32_t reserved_29:1;
/** txfull : RO; bitpos: [30]; default: 0;
* NA
*/
uint32_t txfull:1;
/** rxempty : RO; bitpos: [31]; default: 0;
* NA
*/
uint32_t rxempty:1;
};
uint32_t val;
} i3c_slv_datactrl_reg_t;
/** Group: I3C_SLV WDATAB REG */
/** Type of wdatab register
* NA
*/
typedef union {
struct {
/** wdatab : WO; bitpos: [7:0]; default: 0;
* NA
*/
uint32_t wdatab:8;
/** wdata_end : WO; bitpos: [8]; default: 0;
* NA
*/
uint32_t wdata_end:1;
uint32_t reserved_9:23;
};
uint32_t val;
} i3c_slv_wdatab_reg_t;
/** Group: I3C_SLV WDATABE REG */
/** Type of wdatabe register
* NA
*/
typedef union {
struct {
/** wdatabe : WO; bitpos: [7:0]; default: 0;
* NA
*/
uint32_t wdatabe:8;
uint32_t reserved_8:24;
};
uint32_t val;
} i3c_slv_wdatabe_reg_t;
/** Group: I3C_SLV RDARAB REG */
/** Type of rdarab register
* Read Byte Data (from-bus) register
*/
typedef union {
struct {
/** data0 : RO; bitpos: [7:0]; default: 0;
* This register allows reading a byte from the bus unless external FIFO is used. A
* byte should not be read unless there is data waiting, as indicated by the RXPEND
* bit being set in the STATUS register
*/
uint32_t data0:8;
uint32_t reserved_8:24;
};
uint32_t val;
} i3c_slv_rdarab_reg_t;
/** Group: I3C_SLV RDATAH REG */
/** Type of rdatah register
* Read Half-word Data (from-bus) register
*/
typedef union {
struct {
/** data_lsb : RO; bitpos: [7:0]; default: 0;
* NA
*/
uint32_t data_lsb:8;
/** data_msb : RO; bitpos: [15:8]; default: 0;
* This register allows reading a Half-word (byte pair) from the bus unless external
* FIFO is used. A Half-word should not be read unless there is at least 2 bytes of
* data waiting, as indicated by the RX FIFO level trigger or RXCOUNT available space
* in the DATACTRL register
*/
uint32_t data_msb:8;
uint32_t reserved_16:16;
};
uint32_t val;
} i3c_slv_rdatah_reg_t;
/** Group: I3C_SLV CAPABILITIES2 REG */
/** Type of capabilities2 register
* NA
*/
typedef union {
struct {
/** capablities2 : RO; bitpos: [31:0]; default: 256;
* NA
*/
uint32_t capablities2:32;
};
uint32_t val;
} i3c_slv_capabilities2_reg_t;
/** Group: I3C_SLV CAPABILITIES REG */
/** Type of capabilities register
* NA
*/
typedef union {
struct {
/** capablities : RO; bitpos: [31:0]; default: 2081684508;
* NA
*/
uint32_t capablities:32;
};
uint32_t val;
} i3c_slv_capabilities_reg_t;
/** Group: I3C_SLV IDPARTNO REG */
/** Type of idpartno register
* NA
*/
typedef union {
struct {
/** partno : R/W; bitpos: [31:0]; default: 0;
* NA
*/
uint32_t partno:32;
};
uint32_t val;
} i3c_slv_idpartno_reg_t;
/** Group: I3C_SLV IDEXT REG */
/** Type of idext register
* NA
*/
typedef union {
struct {
/** idext : R/W; bitpos: [31:0]; default: 0;
* NA
*/
uint32_t idext:32;
};
uint32_t val;
} i3c_slv_idext_reg_t;
/** Group: I3C_SLV VENDORID REG */
/** Type of vendorid register
* NA
*/
typedef union {
struct {
/** vid : R/W; bitpos: [14:0]; default: 21840;
* NA
*/
uint32_t vid:15;
uint32_t reserved_15:17;
};
uint32_t val;
} i3c_slv_vendorid_reg_t;
typedef struct {
uint32_t reserved_000;
volatile i3c_slv_config_reg_t config;
volatile i3c_slv_status_reg_t status;
volatile i3c_slv_ctrl_reg_t ctrl;
volatile i3c_slv_intset_reg_t intset;
volatile i3c_slv_intclr_reg_t intclr;
volatile i3c_slv_intmasked_reg_t intmasked;
uint32_t reserved_01c[4];
volatile i3c_slv_datactrl_reg_t datactrl;
volatile i3c_slv_wdatab_reg_t wdatab;
volatile i3c_slv_wdatabe_reg_t wdatabe;
uint32_t reserved_038[2];
volatile i3c_slv_rdarab_reg_t rdarab;
uint32_t reserved_044;
volatile i3c_slv_rdatah_reg_t rdatah;
uint32_t reserved_04c[4];
volatile i3c_slv_capabilities2_reg_t capabilities2;
volatile i3c_slv_capabilities_reg_t capabilities;
uint32_t reserved_064[2];
volatile i3c_slv_idpartno_reg_t idpartno;
volatile i3c_slv_idext_reg_t idext;
volatile i3c_slv_vendorid_reg_t vendorid;
} i3c_slv_dev_t;
#ifndef __cplusplus
_Static_assert(sizeof(i3c_slv_dev_t) == 0x78, "Invalid size of i3c_slv_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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components/soc/esp32p4/include/soc/icm_sys_qos_reg.h Normal file
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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** ICM_VERID_FILEDS_REG register
* NA
*/
#define ICM_VERID_FILEDS_REG (DR_REG_ICM_BASE + 0x0)
/** ICM_REG_VERID : RO; bitpos: [31:0]; default: 875574314;
* NA
*/
#define ICM_REG_VERID 0xFFFFFFFFU
#define ICM_REG_VERID_M (ICM_REG_VERID_V << ICM_REG_VERID_S)
#define ICM_REG_VERID_V 0xFFFFFFFFU
#define ICM_REG_VERID_S 0
/** ICM_HW_CFG_REG_REG register
* NA
*/
#define ICM_HW_CFG_REG_REG (DR_REG_ICM_BASE + 0x4)
/** ICM_REG_AXI_HWCFG_QOS_SUPPORT : RO; bitpos: [0]; default: 1;
* NA
*/
#define ICM_REG_AXI_HWCFG_QOS_SUPPORT (BIT(0))
#define ICM_REG_AXI_HWCFG_QOS_SUPPORT_M (ICM_REG_AXI_HWCFG_QOS_SUPPORT_V << ICM_REG_AXI_HWCFG_QOS_SUPPORT_S)
#define ICM_REG_AXI_HWCFG_QOS_SUPPORT_V 0x00000001U
#define ICM_REG_AXI_HWCFG_QOS_SUPPORT_S 0
/** ICM_REG_AXI_HWCFG_APB3_SUPPORT : RO; bitpos: [1]; default: 0;
* NA
*/
#define ICM_REG_AXI_HWCFG_APB3_SUPPORT (BIT(1))
#define ICM_REG_AXI_HWCFG_APB3_SUPPORT_M (ICM_REG_AXI_HWCFG_APB3_SUPPORT_V << ICM_REG_AXI_HWCFG_APB3_SUPPORT_S)
#define ICM_REG_AXI_HWCFG_APB3_SUPPORT_V 0x00000001U
#define ICM_REG_AXI_HWCFG_APB3_SUPPORT_S 1
/** ICM_REG_AXI_HWCFG_AXI4_SUPPORT : RO; bitpos: [2]; default: 0;
* NA
*/
#define ICM_REG_AXI_HWCFG_AXI4_SUPPORT (BIT(2))
#define ICM_REG_AXI_HWCFG_AXI4_SUPPORT_M (ICM_REG_AXI_HWCFG_AXI4_SUPPORT_V << ICM_REG_AXI_HWCFG_AXI4_SUPPORT_S)
#define ICM_REG_AXI_HWCFG_AXI4_SUPPORT_V 0x00000001U
#define ICM_REG_AXI_HWCFG_AXI4_SUPPORT_S 2
/** ICM_REG_AXI_HWCFG_LOCK_EN : RO; bitpos: [3]; default: 0;
* NA
*/
#define ICM_REG_AXI_HWCFG_LOCK_EN (BIT(3))
#define ICM_REG_AXI_HWCFG_LOCK_EN_M (ICM_REG_AXI_HWCFG_LOCK_EN_V << ICM_REG_AXI_HWCFG_LOCK_EN_S)
#define ICM_REG_AXI_HWCFG_LOCK_EN_V 0x00000001U
#define ICM_REG_AXI_HWCFG_LOCK_EN_S 3
/** ICM_REG_AXI_HWCFG_TRUST_ZONE_EN : RO; bitpos: [4]; default: 1;
* NA
*/
#define ICM_REG_AXI_HWCFG_TRUST_ZONE_EN (BIT(4))
#define ICM_REG_AXI_HWCFG_TRUST_ZONE_EN_M (ICM_REG_AXI_HWCFG_TRUST_ZONE_EN_V << ICM_REG_AXI_HWCFG_TRUST_ZONE_EN_S)
#define ICM_REG_AXI_HWCFG_TRUST_ZONE_EN_V 0x00000001U
#define ICM_REG_AXI_HWCFG_TRUST_ZONE_EN_S 4
/** ICM_REG_AXI_HWCFG_DECODER_TYPE : RO; bitpos: [5]; default: 0;
* NA
*/
#define ICM_REG_AXI_HWCFG_DECODER_TYPE (BIT(5))
#define ICM_REG_AXI_HWCFG_DECODER_TYPE_M (ICM_REG_AXI_HWCFG_DECODER_TYPE_V << ICM_REG_AXI_HWCFG_DECODER_TYPE_S)
#define ICM_REG_AXI_HWCFG_DECODER_TYPE_V 0x00000001U
#define ICM_REG_AXI_HWCFG_DECODER_TYPE_S 5
/** ICM_REG_AXI_HWCFG_REMAP_EN : RO; bitpos: [6]; default: 1;
* NA
*/
#define ICM_REG_AXI_HWCFG_REMAP_EN (BIT(6))
#define ICM_REG_AXI_HWCFG_REMAP_EN_M (ICM_REG_AXI_HWCFG_REMAP_EN_V << ICM_REG_AXI_HWCFG_REMAP_EN_S)
#define ICM_REG_AXI_HWCFG_REMAP_EN_V 0x00000001U
#define ICM_REG_AXI_HWCFG_REMAP_EN_S 6
/** ICM_REG_AXI_HWCFG_BI_DIR_CMD_EN : RO; bitpos: [7]; default: 0;
* NA
*/
#define ICM_REG_AXI_HWCFG_BI_DIR_CMD_EN (BIT(7))
#define ICM_REG_AXI_HWCFG_BI_DIR_CMD_EN_M (ICM_REG_AXI_HWCFG_BI_DIR_CMD_EN_V << ICM_REG_AXI_HWCFG_BI_DIR_CMD_EN_S)
#define ICM_REG_AXI_HWCFG_BI_DIR_CMD_EN_V 0x00000001U
#define ICM_REG_AXI_HWCFG_BI_DIR_CMD_EN_S 7
/** ICM_REG_AXI_HWCFG_LOW_POWER_INF_EN : RO; bitpos: [8]; default: 1;
* NA
*/
#define ICM_REG_AXI_HWCFG_LOW_POWER_INF_EN (BIT(8))
#define ICM_REG_AXI_HWCFG_LOW_POWER_INF_EN_M (ICM_REG_AXI_HWCFG_LOW_POWER_INF_EN_V << ICM_REG_AXI_HWCFG_LOW_POWER_INF_EN_S)
#define ICM_REG_AXI_HWCFG_LOW_POWER_INF_EN_V 0x00000001U
#define ICM_REG_AXI_HWCFG_LOW_POWER_INF_EN_S 8
/** ICM_REG_AXI_HWCFG_AXI_NUM_MASTERS : RO; bitpos: [16:12]; default: 13;
* NA
*/
#define ICM_REG_AXI_HWCFG_AXI_NUM_MASTERS 0x0000001FU
#define ICM_REG_AXI_HWCFG_AXI_NUM_MASTERS_M (ICM_REG_AXI_HWCFG_AXI_NUM_MASTERS_V << ICM_REG_AXI_HWCFG_AXI_NUM_MASTERS_S)
#define ICM_REG_AXI_HWCFG_AXI_NUM_MASTERS_V 0x0000001FU
#define ICM_REG_AXI_HWCFG_AXI_NUM_MASTERS_S 12
/** ICM_REG_AXI_HWCFG_AXI_NUM_SLAVES : RO; bitpos: [24:20]; default: 7;
* NA
*/
#define ICM_REG_AXI_HWCFG_AXI_NUM_SLAVES 0x0000001FU
#define ICM_REG_AXI_HWCFG_AXI_NUM_SLAVES_M (ICM_REG_AXI_HWCFG_AXI_NUM_SLAVES_V << ICM_REG_AXI_HWCFG_AXI_NUM_SLAVES_S)
#define ICM_REG_AXI_HWCFG_AXI_NUM_SLAVES_V 0x0000001FU
#define ICM_REG_AXI_HWCFG_AXI_NUM_SLAVES_S 20
/** ICM_CMD_REG register
* NA
*/
#define ICM_CMD_REG (DR_REG_ICM_BASE + 0x8)
/** ICM_REG_AXI_CMD : R/W; bitpos: [2:0]; default: 0;
* NA
*/
#define ICM_REG_AXI_CMD 0x00000007U
#define ICM_REG_AXI_CMD_M (ICM_REG_AXI_CMD_V << ICM_REG_AXI_CMD_S)
#define ICM_REG_AXI_CMD_V 0x00000007U
#define ICM_REG_AXI_CMD_S 0
/** ICM_REG_RD_WR_CHAN : R/W; bitpos: [7]; default: 0;
* NA
*/
#define ICM_REG_RD_WR_CHAN (BIT(7))
#define ICM_REG_RD_WR_CHAN_M (ICM_REG_RD_WR_CHAN_V << ICM_REG_RD_WR_CHAN_S)
#define ICM_REG_RD_WR_CHAN_V 0x00000001U
#define ICM_REG_RD_WR_CHAN_S 7
/** ICM_REG_AXI_MASTER_PORT : R/W; bitpos: [11:8]; default: 0;
* NA
*/
#define ICM_REG_AXI_MASTER_PORT 0x0000000FU
#define ICM_REG_AXI_MASTER_PORT_M (ICM_REG_AXI_MASTER_PORT_V << ICM_REG_AXI_MASTER_PORT_S)
#define ICM_REG_AXI_MASTER_PORT_V 0x0000000FU
#define ICM_REG_AXI_MASTER_PORT_S 8
/** ICM_REG_AXI_ERR_BIT : RO; bitpos: [28]; default: 0;
* NA
*/
#define ICM_REG_AXI_ERR_BIT (BIT(28))
#define ICM_REG_AXI_ERR_BIT_M (ICM_REG_AXI_ERR_BIT_V << ICM_REG_AXI_ERR_BIT_S)
#define ICM_REG_AXI_ERR_BIT_V 0x00000001U
#define ICM_REG_AXI_ERR_BIT_S 28
/** ICM_REG_AXI_SOFT_RESET_BIT : R/W; bitpos: [29]; default: 0;
* NA
*/
#define ICM_REG_AXI_SOFT_RESET_BIT (BIT(29))
#define ICM_REG_AXI_SOFT_RESET_BIT_M (ICM_REG_AXI_SOFT_RESET_BIT_V << ICM_REG_AXI_SOFT_RESET_BIT_S)
#define ICM_REG_AXI_SOFT_RESET_BIT_V 0x00000001U
#define ICM_REG_AXI_SOFT_RESET_BIT_S 29
/** ICM_REG_AXI_RD_WR_CMD : R/W; bitpos: [30]; default: 0;
* NA
*/
#define ICM_REG_AXI_RD_WR_CMD (BIT(30))
#define ICM_REG_AXI_RD_WR_CMD_M (ICM_REG_AXI_RD_WR_CMD_V << ICM_REG_AXI_RD_WR_CMD_S)
#define ICM_REG_AXI_RD_WR_CMD_V 0x00000001U
#define ICM_REG_AXI_RD_WR_CMD_S 30
/** ICM_REG_AXI_CMD_EN : R/W; bitpos: [31]; default: 0;
* NA
*/
#define ICM_REG_AXI_CMD_EN (BIT(31))
#define ICM_REG_AXI_CMD_EN_M (ICM_REG_AXI_CMD_EN_V << ICM_REG_AXI_CMD_EN_S)
#define ICM_REG_AXI_CMD_EN_V 0x00000001U
#define ICM_REG_AXI_CMD_EN_S 31
/** ICM_DATA_REG register
* NA
*/
#define ICM_DATA_REG (DR_REG_ICM_BASE + 0xc)
/** ICM_REG_DATA : R/W; bitpos: [31:0]; default: 0;
* NA
*/
#define ICM_REG_DATA 0xFFFFFFFFU
#define ICM_REG_DATA_M (ICM_REG_DATA_V << ICM_REG_DATA_S)
#define ICM_REG_DATA_V 0xFFFFFFFFU
#define ICM_REG_DATA_S 0
#ifdef __cplusplus
}
#endif

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components/soc/esp32p4/include/soc/icm_sys_qos_struct.h Normal file
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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: ICM AXI VERID FILEDS REG */
/** Type of verid_fileds register
* NA
*/
typedef union {
struct {
/** reg_verid : RO; bitpos: [31:0]; default: 875574314;
* NA
*/
uint32_t reg_verid:32;
};
uint32_t val;
} icm_verid_fileds_reg_t;
/** Group: ICM AXI HW CFG REG REG */
/** Type of hw_cfg_reg register
* NA
*/
typedef union {
struct {
/** reg_axi_hwcfg_qos_support : RO; bitpos: [0]; default: 1;
* NA
*/
uint32_t reg_axi_hwcfg_qos_support:1;
/** reg_axi_hwcfg_apb3_support : RO; bitpos: [1]; default: 0;
* NA
*/
uint32_t reg_axi_hwcfg_apb3_support:1;
/** reg_axi_hwcfg_axi4_support : RO; bitpos: [2]; default: 0;
* NA
*/
uint32_t reg_axi_hwcfg_axi4_support:1;
/** reg_axi_hwcfg_lock_en : RO; bitpos: [3]; default: 0;
* NA
*/
uint32_t reg_axi_hwcfg_lock_en:1;
/** reg_axi_hwcfg_trust_zone_en : RO; bitpos: [4]; default: 1;
* NA
*/
uint32_t reg_axi_hwcfg_trust_zone_en:1;
/** reg_axi_hwcfg_decoder_type : RO; bitpos: [5]; default: 0;
* NA
*/
uint32_t reg_axi_hwcfg_decoder_type:1;
/** reg_axi_hwcfg_remap_en : RO; bitpos: [6]; default: 1;
* NA
*/
uint32_t reg_axi_hwcfg_remap_en:1;
/** reg_axi_hwcfg_bi_dir_cmd_en : RO; bitpos: [7]; default: 0;
* NA
*/
uint32_t reg_axi_hwcfg_bi_dir_cmd_en:1;
/** reg_axi_hwcfg_low_power_inf_en : RO; bitpos: [8]; default: 1;
* NA
*/
uint32_t reg_axi_hwcfg_low_power_inf_en:1;
uint32_t reserved_9:3;
/** reg_axi_hwcfg_axi_num_masters : RO; bitpos: [16:12]; default: 13;
* NA
*/
uint32_t reg_axi_hwcfg_axi_num_masters:5;
uint32_t reserved_17:3;
/** reg_axi_hwcfg_axi_num_slaves : RO; bitpos: [24:20]; default: 7;
* NA
*/
uint32_t reg_axi_hwcfg_axi_num_slaves:5;
uint32_t reserved_25:7;
};
uint32_t val;
} icm_hw_cfg_reg_reg_t;
/** Group: ICM AXI CMD REG */
/** Type of cmd register
* NA
*/
typedef union {
struct {
/** reg_axi_cmd : R/W; bitpos: [2:0]; default: 0;
* NA
*/
uint32_t reg_axi_cmd:3;
uint32_t reserved_3:4;
/** reg_rd_wr_chan : R/W; bitpos: [7]; default: 0;
* NA
*/
uint32_t reg_rd_wr_chan:1;
/** reg_axi_master_port : R/W; bitpos: [11:8]; default: 0;
* NA
*/
uint32_t reg_axi_master_port:4;
uint32_t reserved_12:16;
/** reg_axi_err_bit : RO; bitpos: [28]; default: 0;
* NA
*/
uint32_t reg_axi_err_bit:1;
/** reg_axi_soft_reset_bit : R/W; bitpos: [29]; default: 0;
* NA
*/
uint32_t reg_axi_soft_reset_bit:1;
/** reg_axi_rd_wr_cmd : R/W; bitpos: [30]; default: 0;
* NA
*/
uint32_t reg_axi_rd_wr_cmd:1;
/** reg_axi_cmd_en : R/W; bitpos: [31]; default: 0;
* NA
*/
uint32_t reg_axi_cmd_en:1;
};
uint32_t val;
} icm_cmd_reg_t;
/** Group: ICM AXI DATA REG */
/** Type of data register
* NA
*/
typedef union {
struct {
/** reg_data : R/W; bitpos: [31:0]; default: 0;
* NA
*/
uint32_t reg_data:32;
};
uint32_t val;
} icm_data_reg_t;
typedef struct {
volatile icm_verid_fileds_reg_t verid_fileds;
volatile icm_hw_cfg_reg_reg_t hw_cfg_reg;
volatile icm_cmd_reg_t cmd;
volatile icm_data_reg_t data;
} icm_dev_t;
#ifndef __cplusplus
_Static_assert(sizeof(icm_dev_t) == 0x10, "Invalid size of icm_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

546
components/soc/esp32p4/include/soc/icm_sys_reg.h Normal file
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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** ICM_VER_DATE_REG register
* NA
*/
#define ICM_VER_DATE_REG (DR_REG_ICM_BASE + 0x0)
/** ICM_REG_VER_DATE : R/W; bitpos: [31:0]; default: 539165204;
* NA
*/
#define ICM_REG_VER_DATE 0xFFFFFFFFU
#define ICM_REG_VER_DATE_M (ICM_REG_VER_DATE_V << ICM_REG_VER_DATE_S)
#define ICM_REG_VER_DATE_V 0xFFFFFFFFU
#define ICM_REG_VER_DATE_S 0
/** ICM_CLK_EN_REG register
* NA
*/
#define ICM_CLK_EN_REG (DR_REG_ICM_BASE + 0x4)
/** ICM_REG_CLK_EN : R/W; bitpos: [0]; default: 0;
* NA
*/
#define ICM_REG_CLK_EN (BIT(0))
#define ICM_REG_CLK_EN_M (ICM_REG_CLK_EN_V << ICM_REG_CLK_EN_S)
#define ICM_REG_CLK_EN_V 0x00000001U
#define ICM_REG_CLK_EN_S 0
/** ICM_DLOCK_STATUS_REG register
* NA
*/
#define ICM_DLOCK_STATUS_REG (DR_REG_ICM_BASE + 0x8)
/** ICM_REG_DLOCK_MST : RO; bitpos: [3:0]; default: 0;
* Lowest numbered deadlocked master
*/
#define ICM_REG_DLOCK_MST 0x0000000FU
#define ICM_REG_DLOCK_MST_M (ICM_REG_DLOCK_MST_V << ICM_REG_DLOCK_MST_S)
#define ICM_REG_DLOCK_MST_V 0x0000000FU
#define ICM_REG_DLOCK_MST_S 0
/** ICM_REG_DLOCK_SLV : RO; bitpos: [6:4]; default: 0;
* Slave with which dlock_mst is deadlocked
*/
#define ICM_REG_DLOCK_SLV 0x00000007U
#define ICM_REG_DLOCK_SLV_M (ICM_REG_DLOCK_SLV_V << ICM_REG_DLOCK_SLV_S)
#define ICM_REG_DLOCK_SLV_V 0x00000007U
#define ICM_REG_DLOCK_SLV_S 4
/** ICM_REG_DLOCK_ID : RO; bitpos: [10:7]; default: 0;
* AXI ID of deadlocked transaction
*/
#define ICM_REG_DLOCK_ID 0x0000000FU
#define ICM_REG_DLOCK_ID_M (ICM_REG_DLOCK_ID_V << ICM_REG_DLOCK_ID_S)
#define ICM_REG_DLOCK_ID_V 0x0000000FU
#define ICM_REG_DLOCK_ID_S 7
/** ICM_REG_DLOCK_WR : RO; bitpos: [11]; default: 0;
* Asserted if deadlocked transaction is a write
*/
#define ICM_REG_DLOCK_WR (BIT(11))
#define ICM_REG_DLOCK_WR_M (ICM_REG_DLOCK_WR_V << ICM_REG_DLOCK_WR_S)
#define ICM_REG_DLOCK_WR_V 0x00000001U
#define ICM_REG_DLOCK_WR_S 11
/** ICM_INT_RAW_REG register
* NA
*/
#define ICM_INT_RAW_REG (DR_REG_ICM_BASE + 0xc)
/** ICM_REG_DLOCK_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
* NA
*/
#define ICM_REG_DLOCK_INT_RAW (BIT(0))
#define ICM_REG_DLOCK_INT_RAW_M (ICM_REG_DLOCK_INT_RAW_V << ICM_REG_DLOCK_INT_RAW_S)
#define ICM_REG_DLOCK_INT_RAW_V 0x00000001U
#define ICM_REG_DLOCK_INT_RAW_S 0
/** ICM_REG_ICM_SYS_ADDRHOLE_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
* NA
*/
#define ICM_REG_ICM_SYS_ADDRHOLE_INT_RAW (BIT(1))
#define ICM_REG_ICM_SYS_ADDRHOLE_INT_RAW_M (ICM_REG_ICM_SYS_ADDRHOLE_INT_RAW_V << ICM_REG_ICM_SYS_ADDRHOLE_INT_RAW_S)
#define ICM_REG_ICM_SYS_ADDRHOLE_INT_RAW_V 0x00000001U
#define ICM_REG_ICM_SYS_ADDRHOLE_INT_RAW_S 1
/** ICM_REG_ICM_CPU_ADDRHOLE_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
* NA
*/
#define ICM_REG_ICM_CPU_ADDRHOLE_INT_RAW (BIT(2))
#define ICM_REG_ICM_CPU_ADDRHOLE_INT_RAW_M (ICM_REG_ICM_CPU_ADDRHOLE_INT_RAW_V << ICM_REG_ICM_CPU_ADDRHOLE_INT_RAW_S)
#define ICM_REG_ICM_CPU_ADDRHOLE_INT_RAW_V 0x00000001U
#define ICM_REG_ICM_CPU_ADDRHOLE_INT_RAW_S 2
/** ICM_INT_ST_REG register
* NA
*/
#define ICM_INT_ST_REG (DR_REG_ICM_BASE + 0x10)
/** ICM_REG_DLOCK_INT_ST : RO; bitpos: [0]; default: 0;
* NA
*/
#define ICM_REG_DLOCK_INT_ST (BIT(0))
#define ICM_REG_DLOCK_INT_ST_M (ICM_REG_DLOCK_INT_ST_V << ICM_REG_DLOCK_INT_ST_S)
#define ICM_REG_DLOCK_INT_ST_V 0x00000001U
#define ICM_REG_DLOCK_INT_ST_S 0
/** ICM_REG_ICM_SYS_ADDRHOLE_INT_ST : RO; bitpos: [1]; default: 0;
* NA
*/
#define ICM_REG_ICM_SYS_ADDRHOLE_INT_ST (BIT(1))
#define ICM_REG_ICM_SYS_ADDRHOLE_INT_ST_M (ICM_REG_ICM_SYS_ADDRHOLE_INT_ST_V << ICM_REG_ICM_SYS_ADDRHOLE_INT_ST_S)
#define ICM_REG_ICM_SYS_ADDRHOLE_INT_ST_V 0x00000001U
#define ICM_REG_ICM_SYS_ADDRHOLE_INT_ST_S 1
/** ICM_REG_ICM_CPU_ADDRHOLE_INT_ST : RO; bitpos: [2]; default: 0;
* NA
*/
#define ICM_REG_ICM_CPU_ADDRHOLE_INT_ST (BIT(2))
#define ICM_REG_ICM_CPU_ADDRHOLE_INT_ST_M (ICM_REG_ICM_CPU_ADDRHOLE_INT_ST_V << ICM_REG_ICM_CPU_ADDRHOLE_INT_ST_S)
#define ICM_REG_ICM_CPU_ADDRHOLE_INT_ST_V 0x00000001U
#define ICM_REG_ICM_CPU_ADDRHOLE_INT_ST_S 2
/** ICM_INT_ENA_REG register
* NA
*/
#define ICM_INT_ENA_REG (DR_REG_ICM_BASE + 0x14)
/** ICM_REG_DLOCK_INT_ENA : R/W; bitpos: [0]; default: 1;
* NA
*/
#define ICM_REG_DLOCK_INT_ENA (BIT(0))
#define ICM_REG_DLOCK_INT_ENA_M (ICM_REG_DLOCK_INT_ENA_V << ICM_REG_DLOCK_INT_ENA_S)
#define ICM_REG_DLOCK_INT_ENA_V 0x00000001U
#define ICM_REG_DLOCK_INT_ENA_S 0
/** ICM_REG_ICM_SYS_ADDRHOLE_INT_ENA : R/W; bitpos: [1]; default: 1;
* NA
*/
#define ICM_REG_ICM_SYS_ADDRHOLE_INT_ENA (BIT(1))
#define ICM_REG_ICM_SYS_ADDRHOLE_INT_ENA_M (ICM_REG_ICM_SYS_ADDRHOLE_INT_ENA_V << ICM_REG_ICM_SYS_ADDRHOLE_INT_ENA_S)
#define ICM_REG_ICM_SYS_ADDRHOLE_INT_ENA_V 0x00000001U
#define ICM_REG_ICM_SYS_ADDRHOLE_INT_ENA_S 1
/** ICM_REG_ICM_CPU_ADDRHOLE_INT_ENA : R/W; bitpos: [2]; default: 1;
* NA
*/
#define ICM_REG_ICM_CPU_ADDRHOLE_INT_ENA (BIT(2))
#define ICM_REG_ICM_CPU_ADDRHOLE_INT_ENA_M (ICM_REG_ICM_CPU_ADDRHOLE_INT_ENA_V << ICM_REG_ICM_CPU_ADDRHOLE_INT_ENA_S)
#define ICM_REG_ICM_CPU_ADDRHOLE_INT_ENA_V 0x00000001U
#define ICM_REG_ICM_CPU_ADDRHOLE_INT_ENA_S 2
/** ICM_INT_CLR_REG register
* NA
*/
#define ICM_INT_CLR_REG (DR_REG_ICM_BASE + 0x18)
/** ICM_REG_DLOCK_INT_CLR : WT; bitpos: [0]; default: 0;
* NA
*/
#define ICM_REG_DLOCK_INT_CLR (BIT(0))
#define ICM_REG_DLOCK_INT_CLR_M (ICM_REG_DLOCK_INT_CLR_V << ICM_REG_DLOCK_INT_CLR_S)
#define ICM_REG_DLOCK_INT_CLR_V 0x00000001U
#define ICM_REG_DLOCK_INT_CLR_S 0
/** ICM_REG_ICM_SYS_ADDRHOLE_INT_CLR : WT; bitpos: [1]; default: 0;
* NA
*/
#define ICM_REG_ICM_SYS_ADDRHOLE_INT_CLR (BIT(1))
#define ICM_REG_ICM_SYS_ADDRHOLE_INT_CLR_M (ICM_REG_ICM_SYS_ADDRHOLE_INT_CLR_V << ICM_REG_ICM_SYS_ADDRHOLE_INT_CLR_S)
#define ICM_REG_ICM_SYS_ADDRHOLE_INT_CLR_V 0x00000001U
#define ICM_REG_ICM_SYS_ADDRHOLE_INT_CLR_S 1
/** ICM_REG_ICM_CPU_ADDRHOLE_INT_CLR : WT; bitpos: [2]; default: 0;
* NA
*/
#define ICM_REG_ICM_CPU_ADDRHOLE_INT_CLR (BIT(2))
#define ICM_REG_ICM_CPU_ADDRHOLE_INT_CLR_M (ICM_REG_ICM_CPU_ADDRHOLE_INT_CLR_V << ICM_REG_ICM_CPU_ADDRHOLE_INT_CLR_S)
#define ICM_REG_ICM_CPU_ADDRHOLE_INT_CLR_V 0x00000001U
#define ICM_REG_ICM_CPU_ADDRHOLE_INT_CLR_S 2
/** ICM_MST_ARB_PRIORITY_REG0_REG register
* NA
*/
#define ICM_MST_ARB_PRIORITY_REG0_REG (DR_REG_ICM_BASE + 0x1c)
/** ICM_REG_CPU_PRIORITY : R/W; bitpos: [3:0]; default: 0;
* CPU arbitration priority for command channels between masters connected to sys_icm
*/
#define ICM_REG_CPU_PRIORITY 0x0000000FU
#define ICM_REG_CPU_PRIORITY_M (ICM_REG_CPU_PRIORITY_V << ICM_REG_CPU_PRIORITY_S)
#define ICM_REG_CPU_PRIORITY_V 0x0000000FU
#define ICM_REG_CPU_PRIORITY_S 0
/** ICM_REG_CACHE_PRIORITY : R/W; bitpos: [7:4]; default: 0;
* CACHE arbitration priority for command channels between masters connected to sys_icm
*/
#define ICM_REG_CACHE_PRIORITY 0x0000000FU
#define ICM_REG_CACHE_PRIORITY_M (ICM_REG_CACHE_PRIORITY_V << ICM_REG_CACHE_PRIORITY_S)
#define ICM_REG_CACHE_PRIORITY_V 0x0000000FU
#define ICM_REG_CACHE_PRIORITY_S 4
/** ICM_REG_DMA2D_PRIORITY : R/W; bitpos: [11:8]; default: 0;
* GFX arbitration priority for command channels between masters connected to sys_icm
*/
#define ICM_REG_DMA2D_PRIORITY 0x0000000FU
#define ICM_REG_DMA2D_PRIORITY_M (ICM_REG_DMA2D_PRIORITY_V << ICM_REG_DMA2D_PRIORITY_S)
#define ICM_REG_DMA2D_PRIORITY_V 0x0000000FU
#define ICM_REG_DMA2D_PRIORITY_S 8
/** ICM_REG_GDMA_MST1_PRIORITY : R/W; bitpos: [15:12]; default: 0;
* GDMA mst1 arbitration priority for command channels between masters connected to
* sys_icm
*/
#define ICM_REG_GDMA_MST1_PRIORITY 0x0000000FU
#define ICM_REG_GDMA_MST1_PRIORITY_M (ICM_REG_GDMA_MST1_PRIORITY_V << ICM_REG_GDMA_MST1_PRIORITY_S)
#define ICM_REG_GDMA_MST1_PRIORITY_V 0x0000000FU
#define ICM_REG_GDMA_MST1_PRIORITY_S 12
/** ICM_REG_GDMA_MST2_PRIORITY : R/W; bitpos: [19:16]; default: 0;
* GDMA mst2 arbitration priority for command channels between masters connected to
* sys_icm
*/
#define ICM_REG_GDMA_MST2_PRIORITY 0x0000000FU
#define ICM_REG_GDMA_MST2_PRIORITY_M (ICM_REG_GDMA_MST2_PRIORITY_V << ICM_REG_GDMA_MST2_PRIORITY_S)
#define ICM_REG_GDMA_MST2_PRIORITY_V 0x0000000FU
#define ICM_REG_GDMA_MST2_PRIORITY_S 16
/** ICM_REG_H264_M1_PRIORITY : R/W; bitpos: [23:20]; default: 0;
* H264 mst1 arbitration priority for command channels between masters connected to
* sys_icm
*/
#define ICM_REG_H264_M1_PRIORITY 0x0000000FU
#define ICM_REG_H264_M1_PRIORITY_M (ICM_REG_H264_M1_PRIORITY_V << ICM_REG_H264_M1_PRIORITY_S)
#define ICM_REG_H264_M1_PRIORITY_V 0x0000000FU
#define ICM_REG_H264_M1_PRIORITY_S 20
/** ICM_REG_H264_M2_PRIORITY : R/W; bitpos: [27:24]; default: 0;
* H264 mst2 arbitration priority for command channels between masters connected to
* sys_icm
*/
#define ICM_REG_H264_M2_PRIORITY 0x0000000FU
#define ICM_REG_H264_M2_PRIORITY_M (ICM_REG_H264_M2_PRIORITY_V << ICM_REG_H264_M2_PRIORITY_S)
#define ICM_REG_H264_M2_PRIORITY_V 0x0000000FU
#define ICM_REG_H264_M2_PRIORITY_S 24
/** ICM_REG_AXI_PDMA_PRIORITY : R/W; bitpos: [31:28]; default: 0;
* AXI PDMA arbitration priority for command channels between masters connected to
* sys_icm
*/
#define ICM_REG_AXI_PDMA_PRIORITY 0x0000000FU
#define ICM_REG_AXI_PDMA_PRIORITY_M (ICM_REG_AXI_PDMA_PRIORITY_V << ICM_REG_AXI_PDMA_PRIORITY_S)
#define ICM_REG_AXI_PDMA_PRIORITY_V 0x0000000FU
#define ICM_REG_AXI_PDMA_PRIORITY_S 28
/** ICM_SLV_ARB_PRIORITY_REG register
* NA
*/
#define ICM_SLV_ARB_PRIORITY_REG (DR_REG_ICM_BASE + 0x24)
/** ICM_REG_L2MEM_PRIORITY : R/W; bitpos: [5:3]; default: 0;
* L2MEM arbitration priority for response channels between slaves connected to sys_icm
*/
#define ICM_REG_L2MEM_PRIORITY 0x00000007U
#define ICM_REG_L2MEM_PRIORITY_M (ICM_REG_L2MEM_PRIORITY_V << ICM_REG_L2MEM_PRIORITY_S)
#define ICM_REG_L2MEM_PRIORITY_V 0x00000007U
#define ICM_REG_L2MEM_PRIORITY_S 3
/** ICM_REG_FLASH_MSPI_PRIORITY : R/W; bitpos: [14:12]; default: 0;
* FLASH MSPI arbitration priority for response channels between slaves connected to
* sys_icm
*/
#define ICM_REG_FLASH_MSPI_PRIORITY 0x00000007U
#define ICM_REG_FLASH_MSPI_PRIORITY_M (ICM_REG_FLASH_MSPI_PRIORITY_V << ICM_REG_FLASH_MSPI_PRIORITY_S)
#define ICM_REG_FLASH_MSPI_PRIORITY_V 0x00000007U
#define ICM_REG_FLASH_MSPI_PRIORITY_S 12
/** ICM_REG_PSRAM_MSPI_PRIORITY : R/W; bitpos: [17:15]; default: 0;
* PSRAM MSPI arbitration priority for response channels between slaves connected to
* sys_icm
*/
#define ICM_REG_PSRAM_MSPI_PRIORITY 0x00000007U
#define ICM_REG_PSRAM_MSPI_PRIORITY_M (ICM_REG_PSRAM_MSPI_PRIORITY_V << ICM_REG_PSRAM_MSPI_PRIORITY_S)
#define ICM_REG_PSRAM_MSPI_PRIORITY_V 0x00000007U
#define ICM_REG_PSRAM_MSPI_PRIORITY_S 15
/** ICM_REG_LCD_PRIORITY : R/W; bitpos: [20:18]; default: 0;
* MIPI_LCD registers arbitration priority for response channels between slaves
* connected to sys_icm
*/
#define ICM_REG_LCD_PRIORITY 0x00000007U
#define ICM_REG_LCD_PRIORITY_M (ICM_REG_LCD_PRIORITY_V << ICM_REG_LCD_PRIORITY_S)
#define ICM_REG_LCD_PRIORITY_V 0x00000007U
#define ICM_REG_LCD_PRIORITY_S 18
/** ICM_REG_CAM_PRIORITY : R/W; bitpos: [23:21]; default: 0;
* MIPI_CAM registers arbitration priority for response channels between slaves
* connected to sys_icm
*/
#define ICM_REG_CAM_PRIORITY 0x00000007U
#define ICM_REG_CAM_PRIORITY_M (ICM_REG_CAM_PRIORITY_V << ICM_REG_CAM_PRIORITY_S)
#define ICM_REG_CAM_PRIORITY_V 0x00000007U
#define ICM_REG_CAM_PRIORITY_S 21
/** ICM_MST_ARQOS_REG0_REG register
* NA
*/
#define ICM_MST_ARQOS_REG0_REG (DR_REG_ICM_BASE + 0x28)
/** ICM_REG_CPU_ARQOS : R/W; bitpos: [3:0]; default: 0;
* NA
*/
#define ICM_REG_CPU_ARQOS 0x0000000FU
#define ICM_REG_CPU_ARQOS_M (ICM_REG_CPU_ARQOS_V << ICM_REG_CPU_ARQOS_S)
#define ICM_REG_CPU_ARQOS_V 0x0000000FU
#define ICM_REG_CPU_ARQOS_S 0
/** ICM_REG_CACHE_ARQOS : R/W; bitpos: [7:4]; default: 0;
* NA
*/
#define ICM_REG_CACHE_ARQOS 0x0000000FU
#define ICM_REG_CACHE_ARQOS_M (ICM_REG_CACHE_ARQOS_V << ICM_REG_CACHE_ARQOS_S)
#define ICM_REG_CACHE_ARQOS_V 0x0000000FU
#define ICM_REG_CACHE_ARQOS_S 4
/** ICM_REG_DMA2D_ARQOS : R/W; bitpos: [11:8]; default: 0;
* NA
*/
#define ICM_REG_DMA2D_ARQOS 0x0000000FU
#define ICM_REG_DMA2D_ARQOS_M (ICM_REG_DMA2D_ARQOS_V << ICM_REG_DMA2D_ARQOS_S)
#define ICM_REG_DMA2D_ARQOS_V 0x0000000FU
#define ICM_REG_DMA2D_ARQOS_S 8
/** ICM_REG_GDMA_MST1_ARQOS : R/W; bitpos: [15:12]; default: 0;
* NA
*/
#define ICM_REG_GDMA_MST1_ARQOS 0x0000000FU
#define ICM_REG_GDMA_MST1_ARQOS_M (ICM_REG_GDMA_MST1_ARQOS_V << ICM_REG_GDMA_MST1_ARQOS_S)
#define ICM_REG_GDMA_MST1_ARQOS_V 0x0000000FU
#define ICM_REG_GDMA_MST1_ARQOS_S 12
/** ICM_REG_GDMA_MST2_ARQOS : R/W; bitpos: [19:16]; default: 0;
* NA
*/
#define ICM_REG_GDMA_MST2_ARQOS 0x0000000FU
#define ICM_REG_GDMA_MST2_ARQOS_M (ICM_REG_GDMA_MST2_ARQOS_V << ICM_REG_GDMA_MST2_ARQOS_S)
#define ICM_REG_GDMA_MST2_ARQOS_V 0x0000000FU
#define ICM_REG_GDMA_MST2_ARQOS_S 16
/** ICM_REG_H264_DMA2D_M1_ARQOS : R/W; bitpos: [23:20]; default: 0;
* NA
*/
#define ICM_REG_H264_DMA2D_M1_ARQOS 0x0000000FU
#define ICM_REG_H264_DMA2D_M1_ARQOS_M (ICM_REG_H264_DMA2D_M1_ARQOS_V << ICM_REG_H264_DMA2D_M1_ARQOS_S)
#define ICM_REG_H264_DMA2D_M1_ARQOS_V 0x0000000FU
#define ICM_REG_H264_DMA2D_M1_ARQOS_S 20
/** ICM_REG_H264_DMA2D_M2_ARQOS : R/W; bitpos: [27:24]; default: 0;
* NA
*/
#define ICM_REG_H264_DMA2D_M2_ARQOS 0x0000000FU
#define ICM_REG_H264_DMA2D_M2_ARQOS_M (ICM_REG_H264_DMA2D_M2_ARQOS_V << ICM_REG_H264_DMA2D_M2_ARQOS_S)
#define ICM_REG_H264_DMA2D_M2_ARQOS_V 0x0000000FU
#define ICM_REG_H264_DMA2D_M2_ARQOS_S 24
/** ICM_REG_AXI_PDMA_INT_ARQOS : R/W; bitpos: [31:28]; default: 0;
* NA
*/
#define ICM_REG_AXI_PDMA_INT_ARQOS 0x0000000FU
#define ICM_REG_AXI_PDMA_INT_ARQOS_M (ICM_REG_AXI_PDMA_INT_ARQOS_V << ICM_REG_AXI_PDMA_INT_ARQOS_S)
#define ICM_REG_AXI_PDMA_INT_ARQOS_V 0x0000000FU
#define ICM_REG_AXI_PDMA_INT_ARQOS_S 28
/** ICM_MST_AWQOS_REG0_REG register
* NA
*/
#define ICM_MST_AWQOS_REG0_REG (DR_REG_ICM_BASE + 0x30)
/** ICM_REG_CPU_AWQOS : R/W; bitpos: [3:0]; default: 0;
* NA
*/
#define ICM_REG_CPU_AWQOS 0x0000000FU
#define ICM_REG_CPU_AWQOS_M (ICM_REG_CPU_AWQOS_V << ICM_REG_CPU_AWQOS_S)
#define ICM_REG_CPU_AWQOS_V 0x0000000FU
#define ICM_REG_CPU_AWQOS_S 0
/** ICM_REG_CACHE_AWQOS : R/W; bitpos: [7:4]; default: 0;
* NA
*/
#define ICM_REG_CACHE_AWQOS 0x0000000FU
#define ICM_REG_CACHE_AWQOS_M (ICM_REG_CACHE_AWQOS_V << ICM_REG_CACHE_AWQOS_S)
#define ICM_REG_CACHE_AWQOS_V 0x0000000FU
#define ICM_REG_CACHE_AWQOS_S 4
/** ICM_REG_DMA2D_AWQOS : R/W; bitpos: [11:8]; default: 0;
* NA
*/
#define ICM_REG_DMA2D_AWQOS 0x0000000FU
#define ICM_REG_DMA2D_AWQOS_M (ICM_REG_DMA2D_AWQOS_V << ICM_REG_DMA2D_AWQOS_S)
#define ICM_REG_DMA2D_AWQOS_V 0x0000000FU
#define ICM_REG_DMA2D_AWQOS_S 8
/** ICM_REG_GDMA_MST1_AWQOS : R/W; bitpos: [15:12]; default: 0;
* NA
*/
#define ICM_REG_GDMA_MST1_AWQOS 0x0000000FU
#define ICM_REG_GDMA_MST1_AWQOS_M (ICM_REG_GDMA_MST1_AWQOS_V << ICM_REG_GDMA_MST1_AWQOS_S)
#define ICM_REG_GDMA_MST1_AWQOS_V 0x0000000FU
#define ICM_REG_GDMA_MST1_AWQOS_S 12
/** ICM_REG_GDMA_MST2_AWQOS : R/W; bitpos: [19:16]; default: 0;
* NA
*/
#define ICM_REG_GDMA_MST2_AWQOS 0x0000000FU
#define ICM_REG_GDMA_MST2_AWQOS_M (ICM_REG_GDMA_MST2_AWQOS_V << ICM_REG_GDMA_MST2_AWQOS_S)
#define ICM_REG_GDMA_MST2_AWQOS_V 0x0000000FU
#define ICM_REG_GDMA_MST2_AWQOS_S 16
/** ICM_REG_H264_DMA2D_M1_AWQOS : R/W; bitpos: [23:20]; default: 0;
* NA
*/
#define ICM_REG_H264_DMA2D_M1_AWQOS 0x0000000FU
#define ICM_REG_H264_DMA2D_M1_AWQOS_M (ICM_REG_H264_DMA2D_M1_AWQOS_V << ICM_REG_H264_DMA2D_M1_AWQOS_S)
#define ICM_REG_H264_DMA2D_M1_AWQOS_V 0x0000000FU
#define ICM_REG_H264_DMA2D_M1_AWQOS_S 20
/** ICM_REG_H264_DMA2D_M2_AWQOS : R/W; bitpos: [27:24]; default: 0;
* NA
*/
#define ICM_REG_H264_DMA2D_M2_AWQOS 0x0000000FU
#define ICM_REG_H264_DMA2D_M2_AWQOS_M (ICM_REG_H264_DMA2D_M2_AWQOS_V << ICM_REG_H264_DMA2D_M2_AWQOS_S)
#define ICM_REG_H264_DMA2D_M2_AWQOS_V 0x0000000FU
#define ICM_REG_H264_DMA2D_M2_AWQOS_S 24
/** ICM_REG_PDMA_INT_AWQOS : R/W; bitpos: [31:28]; default: 0;
* NA
*/
#define ICM_REG_PDMA_INT_AWQOS 0x0000000FU
#define ICM_REG_PDMA_INT_AWQOS_M (ICM_REG_PDMA_INT_AWQOS_V << ICM_REG_PDMA_INT_AWQOS_S)
#define ICM_REG_PDMA_INT_AWQOS_V 0x0000000FU
#define ICM_REG_PDMA_INT_AWQOS_S 28
/** ICM_SYS_ADDRHOLE_ADDR_REG register
* icm sys addr hole address registers
*/
#define ICM_SYS_ADDRHOLE_ADDR_REG (DR_REG_ICM_BASE + 0x38)
/** ICM_REG_ICM_SYS_ADDRHOLE_ADDR : RO; bitpos: [31:0]; default: 0;
* NA
*/
#define ICM_REG_ICM_SYS_ADDRHOLE_ADDR 0xFFFFFFFFU
#define ICM_REG_ICM_SYS_ADDRHOLE_ADDR_M (ICM_REG_ICM_SYS_ADDRHOLE_ADDR_V << ICM_REG_ICM_SYS_ADDRHOLE_ADDR_S)
#define ICM_REG_ICM_SYS_ADDRHOLE_ADDR_V 0xFFFFFFFFU
#define ICM_REG_ICM_SYS_ADDRHOLE_ADDR_S 0
/** ICM_SYS_ADDRHOLE_INFO_REG register
* NA
*/
#define ICM_SYS_ADDRHOLE_INFO_REG (DR_REG_ICM_BASE + 0x3c)
/** ICM_REG_ICM_SYS_ADDRHOLE_ID : RO; bitpos: [7:0]; default: 0;
* master id = 4-bit CID + 4-bit UID(refer to related IP) . CID is used to verfiy
* master in icm. CID: 4'h1: cache, 4'h5 gdma mst1, 4'h6: gdma mst2, 4'h8: axi pdma,
* 4'ha: dma2d, 4'hb: h264 mst1, 4'hc: h264 mst2.
*/
#define ICM_REG_ICM_SYS_ADDRHOLE_ID 0x000000FFU
#define ICM_REG_ICM_SYS_ADDRHOLE_ID_M (ICM_REG_ICM_SYS_ADDRHOLE_ID_V << ICM_REG_ICM_SYS_ADDRHOLE_ID_S)
#define ICM_REG_ICM_SYS_ADDRHOLE_ID_V 0x000000FFU
#define ICM_REG_ICM_SYS_ADDRHOLE_ID_S 0
/** ICM_REG_ICM_SYS_ADDRHOLE_WR : RO; bitpos: [8]; default: 0;
* 1: illegal address access, 0: access without permission
*/
#define ICM_REG_ICM_SYS_ADDRHOLE_WR (BIT(8))
#define ICM_REG_ICM_SYS_ADDRHOLE_WR_M (ICM_REG_ICM_SYS_ADDRHOLE_WR_V << ICM_REG_ICM_SYS_ADDRHOLE_WR_S)
#define ICM_REG_ICM_SYS_ADDRHOLE_WR_V 0x00000001U
#define ICM_REG_ICM_SYS_ADDRHOLE_WR_S 8
/** ICM_REG_ICM_SYS_ADDRHOLE_SECURE : RO; bitpos: [9]; default: 0;
* It is illegall access address if reg_icm_cpu_addrhole_secure is 1, Otherwise, it
* the address without permission to access.
*/
#define ICM_REG_ICM_SYS_ADDRHOLE_SECURE (BIT(9))
#define ICM_REG_ICM_SYS_ADDRHOLE_SECURE_M (ICM_REG_ICM_SYS_ADDRHOLE_SECURE_V << ICM_REG_ICM_SYS_ADDRHOLE_SECURE_S)
#define ICM_REG_ICM_SYS_ADDRHOLE_SECURE_V 0x00000001U
#define ICM_REG_ICM_SYS_ADDRHOLE_SECURE_S 9
/** ICM_CPU_ADDRHOLE_ADDR_REG register
* icm cpu addr hole address registers
*/
#define ICM_CPU_ADDRHOLE_ADDR_REG (DR_REG_ICM_BASE + 0x40)
/** ICM_REG_ICM_CPU_ADDRHOLE_ADDR : RO; bitpos: [31:0]; default: 0;
* It is illegall access address if reg_icm_cpu_addrhole_secure is 1. Otherwise, it
* the address without permission to access.
*/
#define ICM_REG_ICM_CPU_ADDRHOLE_ADDR 0xFFFFFFFFU
#define ICM_REG_ICM_CPU_ADDRHOLE_ADDR_M (ICM_REG_ICM_CPU_ADDRHOLE_ADDR_V << ICM_REG_ICM_CPU_ADDRHOLE_ADDR_S)
#define ICM_REG_ICM_CPU_ADDRHOLE_ADDR_V 0xFFFFFFFFU
#define ICM_REG_ICM_CPU_ADDRHOLE_ADDR_S 0
/** ICM_CPU_ADDRHOLE_INFO_REG register
* NA
*/
#define ICM_CPU_ADDRHOLE_INFO_REG (DR_REG_ICM_BASE + 0x44)
/** ICM_REG_ICM_CPU_ADDRHOLE_ID : RO; bitpos: [4:0]; default: 0;
* master id: 5'h0: hp core0, 5'h1:hp core1, 5'h2:lp core, 5'h3:usb otg11, 5'h4:
* regdma, 5'h5: gmac, 5'h5 sdmmc, 5'h7: usbotg20, 5'h8: trace0, 5'h9: trace1, 5'ha
* tcm monitor, 5'hb: l2mem monitor. 5'h10~5'h1f: ahb pdma.
*/
#define ICM_REG_ICM_CPU_ADDRHOLE_ID 0x0000001FU
#define ICM_REG_ICM_CPU_ADDRHOLE_ID_M (ICM_REG_ICM_CPU_ADDRHOLE_ID_V << ICM_REG_ICM_CPU_ADDRHOLE_ID_S)
#define ICM_REG_ICM_CPU_ADDRHOLE_ID_V 0x0000001FU
#define ICM_REG_ICM_CPU_ADDRHOLE_ID_S 0
/** ICM_REG_ICM_CPU_ADDRHOLE_WR : RO; bitpos: [8]; default: 0;
* 1:write trans, 0: read trans.
*/
#define ICM_REG_ICM_CPU_ADDRHOLE_WR (BIT(8))
#define ICM_REG_ICM_CPU_ADDRHOLE_WR_M (ICM_REG_ICM_CPU_ADDRHOLE_WR_V << ICM_REG_ICM_CPU_ADDRHOLE_WR_S)
#define ICM_REG_ICM_CPU_ADDRHOLE_WR_V 0x00000001U
#define ICM_REG_ICM_CPU_ADDRHOLE_WR_S 8
/** ICM_REG_ICM_CPU_ADDRHOLE_SECURE : RO; bitpos: [9]; default: 0;
* 1: illegal address access, 0: access without permission
*/
#define ICM_REG_ICM_CPU_ADDRHOLE_SECURE (BIT(9))
#define ICM_REG_ICM_CPU_ADDRHOLE_SECURE_M (ICM_REG_ICM_CPU_ADDRHOLE_SECURE_V << ICM_REG_ICM_CPU_ADDRHOLE_SECURE_S)
#define ICM_REG_ICM_CPU_ADDRHOLE_SECURE_V 0x00000001U
#define ICM_REG_ICM_CPU_ADDRHOLE_SECURE_S 9
/** ICM_DLOCK_TIMEOUT_REG register
* NA
*/
#define ICM_DLOCK_TIMEOUT_REG (DR_REG_ICM_BASE + 0x48)
/** ICM_REG_DLOCK_TIMEOUT : R/W; bitpos: [12:0]; default: 2048;
* if no response until reg_dlock_timeout bus clock cycle, deadlock will happen
*/
#define ICM_REG_DLOCK_TIMEOUT 0x00001FFFU
#define ICM_REG_DLOCK_TIMEOUT_M (ICM_REG_DLOCK_TIMEOUT_V << ICM_REG_DLOCK_TIMEOUT_S)
#define ICM_REG_DLOCK_TIMEOUT_V 0x00001FFFU
#define ICM_REG_DLOCK_TIMEOUT_S 0
/** ICM_RDN_ECO_CS_REG register
* NA
*/
#define ICM_RDN_ECO_CS_REG (DR_REG_ICM_BASE + 0x50)
/** ICM_REG_RDN_ECO_EN : R/W; bitpos: [0]; default: 0;
* NA
*/
#define ICM_REG_RDN_ECO_EN (BIT(0))
#define ICM_REG_RDN_ECO_EN_M (ICM_REG_RDN_ECO_EN_V << ICM_REG_RDN_ECO_EN_S)
#define ICM_REG_RDN_ECO_EN_V 0x00000001U
#define ICM_REG_RDN_ECO_EN_S 0
/** ICM_REG_RDN_ECO_RESULT : RO; bitpos: [1]; default: 0;
* NA
*/
#define ICM_REG_RDN_ECO_RESULT (BIT(1))
#define ICM_REG_RDN_ECO_RESULT_M (ICM_REG_RDN_ECO_RESULT_V << ICM_REG_RDN_ECO_RESULT_S)
#define ICM_REG_RDN_ECO_RESULT_V 0x00000001U
#define ICM_REG_RDN_ECO_RESULT_S 1
/** ICM_RDN_ECO_LOW_REG register
* NA
*/
#define ICM_RDN_ECO_LOW_REG (DR_REG_ICM_BASE + 0x54)
/** ICM_RDN_ECO_LOW : R/W; bitpos: [31:0]; default: 0;
* NA
*/
#define ICM_RDN_ECO_LOW 0xFFFFFFFFU
#define ICM_RDN_ECO_LOW_M (ICM_RDN_ECO_LOW_V << ICM_RDN_ECO_LOW_S)
#define ICM_RDN_ECO_LOW_V 0xFFFFFFFFU
#define ICM_RDN_ECO_LOW_S 0
/** ICM_RDN_ECO_HIGH_REG register
* NA
*/
#define ICM_RDN_ECO_HIGH_REG (DR_REG_ICM_BASE + 0x58)
/** ICM_RDN_ECO_HIGH : R/W; bitpos: [31:0]; default: 4294967295;
* NA
*/
#define ICM_RDN_ECO_HIGH 0xFFFFFFFFU
#define ICM_RDN_ECO_HIGH_M (ICM_RDN_ECO_HIGH_V << ICM_RDN_ECO_HIGH_S)
#define ICM_RDN_ECO_HIGH_V 0xFFFFFFFFU
#define ICM_RDN_ECO_HIGH_S 0
#ifdef __cplusplus
}
#endif

520
components/soc/esp32p4/include/soc/icm_sys_struct.h Normal file
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@@ -0,0 +1,520 @@
/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: ICM VER DATE REG */
/** Type of ver_date register
* NA
*/
typedef union {
struct {
/** reg_ver_date : R/W; bitpos: [31:0]; default: 539165204;
* NA
*/
uint32_t reg_ver_date:32;
};
uint32_t val;
} icm_ver_date_reg_t;
/** Group: ICM CLK EN REG */
/** Type of clk_en register
* NA
*/
typedef union {
struct {
/** reg_clk_en : R/W; bitpos: [0]; default: 0;
* NA
*/
uint32_t reg_clk_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} icm_clk_en_reg_t;
/** Group: ICM DLOCK STATUS REG */
/** Type of dlock_status register
* NA
*/
typedef union {
struct {
/** reg_dlock_mst : RO; bitpos: [3:0]; default: 0;
* Lowest numbered deadlocked master
*/
uint32_t reg_dlock_mst:4;
/** reg_dlock_slv : RO; bitpos: [6:4]; default: 0;
* Slave with which dlock_mst is deadlocked
*/
uint32_t reg_dlock_slv:3;
/** reg_dlock_id : RO; bitpos: [10:7]; default: 0;
* AXI ID of deadlocked transaction
*/
uint32_t reg_dlock_id:4;
/** reg_dlock_wr : RO; bitpos: [11]; default: 0;
* Asserted if deadlocked transaction is a write
*/
uint32_t reg_dlock_wr:1;
uint32_t reserved_12:20;
};
uint32_t val;
} icm_dlock_status_reg_t;
/** Group: ICM INT RAW REG */
/** Type of int_raw register
* NA
*/
typedef union {
struct {
/** reg_dlock_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
* NA
*/
uint32_t reg_dlock_int_raw:1;
/** reg_icm_sys_addrhole_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
* NA
*/
uint32_t reg_icm_sys_addrhole_int_raw:1;
/** reg_icm_cpu_addrhole_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
* NA
*/
uint32_t reg_icm_cpu_addrhole_int_raw:1;
uint32_t reserved_3:29;
};
uint32_t val;
} icm_int_raw_reg_t;
/** Group: ICM INT ST REG */
/** Type of int_st register
* NA
*/
typedef union {
struct {
/** reg_dlock_int_st : RO; bitpos: [0]; default: 0;
* NA
*/
uint32_t reg_dlock_int_st:1;
/** reg_icm_sys_addrhole_int_st : RO; bitpos: [1]; default: 0;
* NA
*/
uint32_t reg_icm_sys_addrhole_int_st:1;
/** reg_icm_cpu_addrhole_int_st : RO; bitpos: [2]; default: 0;
* NA
*/
uint32_t reg_icm_cpu_addrhole_int_st:1;
uint32_t reserved_3:29;
};
uint32_t val;
} icm_int_st_reg_t;
/** Group: ICM INT ENA REG */
/** Type of int_ena register
* NA
*/
typedef union {
struct {
/** reg_dlock_int_ena : R/W; bitpos: [0]; default: 1;
* NA
*/
uint32_t reg_dlock_int_ena:1;
/** reg_icm_sys_addrhole_int_ena : R/W; bitpos: [1]; default: 1;
* NA
*/
uint32_t reg_icm_sys_addrhole_int_ena:1;
/** reg_icm_cpu_addrhole_int_ena : R/W; bitpos: [2]; default: 1;
* NA
*/
uint32_t reg_icm_cpu_addrhole_int_ena:1;
uint32_t reserved_3:29;
};
uint32_t val;
} icm_int_ena_reg_t;
/** Group: ICM INT CLR REG */
/** Type of int_clr register
* NA
*/
typedef union {
struct {
/** reg_dlock_int_clr : WT; bitpos: [0]; default: 0;
* NA
*/
uint32_t reg_dlock_int_clr:1;
/** reg_icm_sys_addrhole_int_clr : WT; bitpos: [1]; default: 0;
* NA
*/
uint32_t reg_icm_sys_addrhole_int_clr:1;
/** reg_icm_cpu_addrhole_int_clr : WT; bitpos: [2]; default: 0;
* NA
*/
uint32_t reg_icm_cpu_addrhole_int_clr:1;
uint32_t reserved_3:29;
};
uint32_t val;
} icm_int_clr_reg_t;
/** Group: ICM MST ARB PRIORITY REG0 REG */
/** Type of mst_arb_priority_reg0 register
* NA
*/
typedef union {
struct {
/** reg_cpu_priority : R/W; bitpos: [3:0]; default: 0;
* CPU arbitration priority for command channels between masters connected to sys_icm
*/
uint32_t reg_cpu_priority:4;
/** reg_cache_priority : R/W; bitpos: [7:4]; default: 0;
* CACHE arbitration priority for command channels between masters connected to sys_icm
*/
uint32_t reg_cache_priority:4;
/** reg_dma2d_priority : R/W; bitpos: [11:8]; default: 0;
* GFX arbitration priority for command channels between masters connected to sys_icm
*/
uint32_t reg_dma2d_priority:4;
/** reg_gdma_mst1_priority : R/W; bitpos: [15:12]; default: 0;
* GDMA mst1 arbitration priority for command channels between masters connected to
* sys_icm
*/
uint32_t reg_gdma_mst1_priority:4;
/** reg_gdma_mst2_priority : R/W; bitpos: [19:16]; default: 0;
* GDMA mst2 arbitration priority for command channels between masters connected to
* sys_icm
*/
uint32_t reg_gdma_mst2_priority:4;
/** reg_h264_m1_priority : R/W; bitpos: [23:20]; default: 0;
* H264 mst1 arbitration priority for command channels between masters connected to
* sys_icm
*/
uint32_t reg_h264_m1_priority:4;
/** reg_h264_m2_priority : R/W; bitpos: [27:24]; default: 0;
* H264 mst2 arbitration priority for command channels between masters connected to
* sys_icm
*/
uint32_t reg_h264_m2_priority:4;
/** reg_axi_pdma_priority : R/W; bitpos: [31:28]; default: 0;
* AXI PDMA arbitration priority for command channels between masters connected to
* sys_icm
*/
uint32_t reg_axi_pdma_priority:4;
};
uint32_t val;
} icm_mst_arb_priority_reg0_reg_t;
/** Group: ICM SLV ARB PRIORITY REG */
/** Type of slv_arb_priority register
* NA
*/
typedef union {
struct {
uint32_t reserved_0:3;
/** reg_l2mem_priority : R/W; bitpos: [5:3]; default: 0;
* L2MEM arbitration priority for response channels between slaves connected to sys_icm
*/
uint32_t reg_l2mem_priority:3;
uint32_t reserved_6:6;
/** reg_flash_mspi_priority : R/W; bitpos: [14:12]; default: 0;
* FLASH MSPI arbitration priority for response channels between slaves connected to
* sys_icm
*/
uint32_t reg_flash_mspi_priority:3;
/** reg_psram_mspi_priority : R/W; bitpos: [17:15]; default: 0;
* PSRAM MSPI arbitration priority for response channels between slaves connected to
* sys_icm
*/
uint32_t reg_psram_mspi_priority:3;
/** reg_lcd_priority : R/W; bitpos: [20:18]; default: 0;
* MIPI_LCD registers arbitration priority for response channels between slaves
* connected to sys_icm
*/
uint32_t reg_lcd_priority:3;
/** reg_cam_priority : R/W; bitpos: [23:21]; default: 0;
* MIPI_CAM registers arbitration priority for response channels between slaves
* connected to sys_icm
*/
uint32_t reg_cam_priority:3;
uint32_t reserved_24:8;
};
uint32_t val;
} icm_slv_arb_priority_reg_t;
/** Group: ICM MST ARQOS REG0 REG */
/** Type of mst_arqos_reg0 register
* NA
*/
typedef union {
struct {
/** reg_cpu_arqos : R/W; bitpos: [3:0]; default: 0;
* NA
*/
uint32_t reg_cpu_arqos:4;
/** reg_cache_arqos : R/W; bitpos: [7:4]; default: 0;
* NA
*/
uint32_t reg_cache_arqos:4;
/** reg_dma2d_arqos : R/W; bitpos: [11:8]; default: 0;
* NA
*/
uint32_t reg_dma2d_arqos:4;
/** reg_gdma_mst1_arqos : R/W; bitpos: [15:12]; default: 0;
* NA
*/
uint32_t reg_gdma_mst1_arqos:4;
/** reg_gdma_mst2_arqos : R/W; bitpos: [19:16]; default: 0;
* NA
*/
uint32_t reg_gdma_mst2_arqos:4;
/** reg_h264_dma2d_m1_arqos : R/W; bitpos: [23:20]; default: 0;
* NA
*/
uint32_t reg_h264_dma2d_m1_arqos:4;
/** reg_h264_dma2d_m2_arqos : R/W; bitpos: [27:24]; default: 0;
* NA
*/
uint32_t reg_h264_dma2d_m2_arqos:4;
/** reg_axi_pdma_int_arqos : R/W; bitpos: [31:28]; default: 0;
* NA
*/
uint32_t reg_axi_pdma_int_arqos:4;
};
uint32_t val;
} icm_mst_arqos_reg0_reg_t;
/** Group: ICM MST AWQOS REG0 REG */
/** Type of mst_awqos_reg0 register
* NA
*/
typedef union {
struct {
/** reg_cpu_awqos : R/W; bitpos: [3:0]; default: 0;
* NA
*/
uint32_t reg_cpu_awqos:4;
/** reg_cache_awqos : R/W; bitpos: [7:4]; default: 0;
* NA
*/
uint32_t reg_cache_awqos:4;
/** reg_dma2d_awqos : R/W; bitpos: [11:8]; default: 0;
* NA
*/
uint32_t reg_dma2d_awqos:4;
/** reg_gdma_mst1_awqos : R/W; bitpos: [15:12]; default: 0;
* NA
*/
uint32_t reg_gdma_mst1_awqos:4;
/** reg_gdma_mst2_awqos : R/W; bitpos: [19:16]; default: 0;
* NA
*/
uint32_t reg_gdma_mst2_awqos:4;
/** reg_h264_dma2d_m1_awqos : R/W; bitpos: [23:20]; default: 0;
* NA
*/
uint32_t reg_h264_dma2d_m1_awqos:4;
/** reg_h264_dma2d_m2_awqos : R/W; bitpos: [27:24]; default: 0;
* NA
*/
uint32_t reg_h264_dma2d_m2_awqos:4;
/** reg_pdma_int_awqos : R/W; bitpos: [31:28]; default: 0;
* NA
*/
uint32_t reg_pdma_int_awqos:4;
};
uint32_t val;
} icm_mst_awqos_reg0_reg_t;
/** Group: ICM ADDRHOLE ADDR REG */
/** Type of sys_addrhole_addr register
* icm sys addr hole address registers
*/
typedef union {
struct {
/** reg_icm_sys_addrhole_addr : RO; bitpos: [31:0]; default: 0;
* NA
*/
uint32_t reg_icm_sys_addrhole_addr:32;
};
uint32_t val;
} icm_sys_addrhole_addr_reg_t;
/** Type of cpu_addrhole_addr register
* icm cpu addr hole address registers
*/
typedef union {
struct {
/** reg_icm_cpu_addrhole_addr : RO; bitpos: [31:0]; default: 0;
* It is illegall access address if reg_icm_cpu_addrhole_secure is 1. Otherwise, it
* the address without permission to access.
*/
uint32_t reg_icm_cpu_addrhole_addr:32;
};
uint32_t val;
} icm_cpu_addrhole_addr_reg_t;
/** Group: ICM ADDRHOLE INFO REG */
/** Type of sys_addrhole_info register
* NA
*/
typedef union {
struct {
/** reg_icm_sys_addrhole_id : RO; bitpos: [7:0]; default: 0;
* master id = 4-bit CID + 4-bit UID(refer to related IP) . CID is used to verfiy
* master in icm. CID: 4'h1: cache, 4'h5 gdma mst1, 4'h6: gdma mst2, 4'h8: axi pdma,
* 4'ha: dma2d, 4'hb: h264 mst1, 4'hc: h264 mst2.
*/
uint32_t reg_icm_sys_addrhole_id:8;
/** reg_icm_sys_addrhole_wr : RO; bitpos: [8]; default: 0;
* 1: illegal address access, 0: access without permission
*/
uint32_t reg_icm_sys_addrhole_wr:1;
/** reg_icm_sys_addrhole_secure : RO; bitpos: [9]; default: 0;
* It is illegall access address if reg_icm_cpu_addrhole_secure is 1, Otherwise, it
* the address without permission to access.
*/
uint32_t reg_icm_sys_addrhole_secure:1;
uint32_t reserved_10:22;
};
uint32_t val;
} icm_sys_addrhole_info_reg_t;
/** Type of cpu_addrhole_info register
* NA
*/
typedef union {
struct {
/** reg_icm_cpu_addrhole_id : RO; bitpos: [4:0]; default: 0;
* master id: 5'h0: hp core0, 5'h1:hp core1, 5'h2:lp core, 5'h3:usb otg11, 5'h4:
* regdma, 5'h5: gmac, 5'h5 sdmmc, 5'h7: usbotg20, 5'h8: trace0, 5'h9: trace1, 5'ha
* tcm monitor, 5'hb: l2mem monitor. 5'h10~5'h1f: ahb pdma.
*/
uint32_t reg_icm_cpu_addrhole_id:5;
uint32_t reserved_5:3;
/** reg_icm_cpu_addrhole_wr : RO; bitpos: [8]; default: 0;
* 1:write trans, 0: read trans.
*/
uint32_t reg_icm_cpu_addrhole_wr:1;
/** reg_icm_cpu_addrhole_secure : RO; bitpos: [9]; default: 0;
* 1: illegal address access, 0: access without permission
*/
uint32_t reg_icm_cpu_addrhole_secure:1;
uint32_t reserved_10:22;
};
uint32_t val;
} icm_cpu_addrhole_info_reg_t;
/** Group: ICM DLOCK TIMEOUT REG */
/** Type of dlock_timeout register
* NA
*/
typedef union {
struct {
/** reg_dlock_timeout : R/W; bitpos: [12:0]; default: 2048;
* if no response until reg_dlock_timeout bus clock cycle, deadlock will happen
*/
uint32_t reg_dlock_timeout:13;
uint32_t reserved_13:19;
};
uint32_t val;
} icm_dlock_timeout_reg_t;
/** Group: ICM RDN ECO CS REG */
/** Type of rdn_eco_cs register
* NA
*/
typedef union {
struct {
/** reg_rdn_eco_en : R/W; bitpos: [0]; default: 0;
* NA
*/
uint32_t reg_rdn_eco_en:1;
/** reg_rdn_eco_result : RO; bitpos: [1]; default: 0;
* NA
*/
uint32_t reg_rdn_eco_result:1;
uint32_t reserved_2:30;
};
uint32_t val;
} icm_rdn_eco_cs_reg_t;
/** Group: ICM RDN ECO LOW REG */
/** Type of rdn_eco_low register
* NA
*/
typedef union {
struct {
/** rdn_eco_low : R/W; bitpos: [31:0]; default: 0;
* NA
*/
uint32_t rdn_eco_low:32;
};
uint32_t val;
} icm_rdn_eco_low_reg_t;
/** Group: ICM RDN ECO HIGH REG */
/** Type of rdn_eco_high register
* NA
*/
typedef union {
struct {
/** rdn_eco_high : R/W; bitpos: [31:0]; default: 4294967295;
* NA
*/
uint32_t rdn_eco_high:32;
};
uint32_t val;
} icm_rdn_eco_high_reg_t;
typedef struct {
volatile icm_ver_date_reg_t ver_date;
volatile icm_clk_en_reg_t clk_en;
volatile icm_dlock_status_reg_t dlock_status;
volatile icm_int_raw_reg_t int_raw;
volatile icm_int_st_reg_t int_st;
volatile icm_int_ena_reg_t int_ena;
volatile icm_int_clr_reg_t int_clr;
volatile icm_mst_arb_priority_reg0_reg_t mst_arb_priority_reg0;
uint32_t reserved_020;
volatile icm_slv_arb_priority_reg_t slv_arb_priority;
volatile icm_mst_arqos_reg0_reg_t mst_arqos_reg0;
uint32_t reserved_02c;
volatile icm_mst_awqos_reg0_reg_t mst_awqos_reg0;
uint32_t reserved_034;
volatile icm_sys_addrhole_addr_reg_t sys_addrhole_addr;
volatile icm_sys_addrhole_info_reg_t sys_addrhole_info;
volatile icm_cpu_addrhole_addr_reg_t cpu_addrhole_addr;
volatile icm_cpu_addrhole_info_reg_t cpu_addrhole_info;
volatile icm_dlock_timeout_reg_t dlock_timeout;
uint32_t reserved_04c;
volatile icm_rdn_eco_cs_reg_t rdn_eco_cs;
volatile icm_rdn_eco_low_reg_t rdn_eco_low;
volatile icm_rdn_eco_high_reg_t rdn_eco_high;
} icm_dev_t;
#ifndef __cplusplus
_Static_assert(sizeof(icm_dev_t) == 0x5c, "Invalid size of icm_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

493
components/soc/esp32p4/include/soc/io_mux_reg.h Normal file
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@@ -0,0 +1,493 @@
/*
* SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include "soc.h"
/* The following are the bit fields for PERIPHS_IO_MUX_x_U registers */
/* Output enable in sleep mode */
#define SLP_OE (BIT(0))
#define SLP_OE_M (BIT(0))
#define SLP_OE_V 1
#define SLP_OE_S 0
/* Pin used for wakeup from sleep */
#define SLP_SEL (BIT(1))
#define SLP_SEL_M (BIT(1))
#define SLP_SEL_V 1
#define SLP_SEL_S 1
/* Pulldown enable in sleep mode */
#define SLP_PD (BIT(2))
#define SLP_PD_M (BIT(2))
#define SLP_PD_V 1
#define SLP_PD_S 2
/* Pullup enable in sleep mode */
#define SLP_PU (BIT(3))
#define SLP_PU_M (BIT(3))
#define SLP_PU_V 1
#define SLP_PU_S 3
/* Input enable in sleep mode */
#define SLP_IE (BIT(4))
#define SLP_IE_M (BIT(4))
#define SLP_IE_V 1
#define SLP_IE_S 4
/* Drive strength in sleep mode */
#define SLP_DRV 0x3
#define SLP_DRV_M (SLP_DRV_V << SLP_DRV_S)
#define SLP_DRV_V 0x3
#define SLP_DRV_S 5
/* Pulldown enable */
#define FUN_PD (BIT(7))
#define FUN_PD_M (BIT(7))
#define FUN_PD_V 1
#define FUN_PD_S 7
/* Pullup enable */
#define FUN_PU (BIT(8))
#define FUN_PU_M (BIT(8))
#define FUN_PU_V 1
#define FUN_PU_S 8
/* Input enable */
#define FUN_IE (BIT(9))
#define FUN_IE_M (FUN_IE_V << FUN_IE_S)
#define FUN_IE_V 1
#define FUN_IE_S 9
/* Drive strength */
#define FUN_DRV 0x3
#define FUN_DRV_M (FUN_DRV_V << FUN_DRV_S)
#define FUN_DRV_V 0x3
#define FUN_DRV_S 10
/* Function select (possible values are defined for each pin as FUNC_pinname_function below) */
#define MCU_SEL 0x7
#define MCU_SEL_M (MCU_SEL_V << MCU_SEL_S)
#define MCU_SEL_V 0x7
#define MCU_SEL_S 12
#define PIN_INPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,FUN_IE)
#define PIN_INPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,FUN_IE)
#define PIN_SET_DRV(PIN_NAME, drv) REG_SET_FIELD(PIN_NAME, FUN_DRV, (drv));
#define PIN_PULLUP_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FUN_PU)
#define PIN_PULLUP_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PU)
#define PIN_PULLDWN_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FUN_PD)
#define PIN_PULLDWN_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PD)
#define PIN_FUNC_SELECT(PIN_NAME, FUNC) REG_SET_FIELD(PIN_NAME, MCU_SEL, FUNC)
#define IO_MUX_GPIO0_REG PERIPHS_IO_MUX_U_PAD_GPIO0
#define IO_MUX_GPIO1_REG PERIPHS_IO_MUX_U_PAD_GPIO1
#define IO_MUX_GPIO2_REG PERIPHS_IO_MUX_U_PAD_GPIO2
#define IO_MUX_GPIO3_REG PERIPHS_IO_MUX_U_PAD_GPIO3
#define IO_MUX_GPIO4_REG PERIPHS_IO_MUX_U_PAD_GPIO4
#define IO_MUX_GPIO5_REG PERIPHS_IO_MUX_U_PAD_GPIO5
#define IO_MUX_GPIO6_REG PERIPHS_IO_MUX_U_PAD_GPIO6
#define IO_MUX_GPIO7_REG PERIPHS_IO_MUX_U_PAD_GPIO7
#define IO_MUX_GPIO8_REG PERIPHS_IO_MUX_U_PAD_GPIO8
#define IO_MUX_GPIO9_REG PERIPHS_IO_MUX_U_PAD_GPIO9
#define IO_MUX_GPIO10_REG PERIPHS_IO_MUX_U_PAD_GPIO10
#define IO_MUX_GPIO11_REG PERIPHS_IO_MUX_U_PAD_GPIO11
#define IO_MUX_GPIO12_REG PERIPHS_IO_MUX_U_PAD_GPIO12
#define IO_MUX_GPIO13_REG PERIPHS_IO_MUX_U_PAD_GPIO13
#define IO_MUX_GPIO14_REG PERIPHS_IO_MUX_U_PAD_GPIO14
#define IO_MUX_GPIO15_REG PERIPHS_IO_MUX_U_PAD_GPIO15
#define IO_MUX_GPIO16_REG PERIPHS_IO_MUX_U_PAD_GPIO16
#define IO_MUX_GPIO17_REG PERIPHS_IO_MUX_U_PAD_GPIO17
#define IO_MUX_GPIO18_REG PERIPHS_IO_MUX_U_PAD_GPIO18
#define IO_MUX_GPIO19_REG PERIPHS_IO_MUX_U_PAD_GPIO19
#define IO_MUX_GPIO20_REG PERIPHS_IO_MUX_U_PAD_GPIO20
#define IO_MUX_GPIO21_REG PERIPHS_IO_MUX_U_PAD_GPIO21
#define IO_MUX_GPIO22_REG PERIPHS_IO_MUX_U_PAD_GPIO22
#define IO_MUX_GPIO23_REG PERIPHS_IO_MUX_U_PAD_GPIO23
#define IO_MUX_GPIO24_REG PERIPHS_IO_MUX_U_PAD_GPIO24
#define IO_MUX_GPIO25_REG PERIPHS_IO_MUX_U_PAD_GPIO25
#define IO_MUX_GPIO26_REG PERIPHS_IO_MUX_U_PAD_GPIO26
#define IO_MUX_GPIO27_REG PERIPHS_IO_MUX_U_PAD_GPIO27
#define IO_MUX_GPIO28_REG PERIPHS_IO_MUX_U_PAD_GPIO28
#define IO_MUX_GPIO29_REG PERIPHS_IO_MUX_U_PAD_GPIO29
#define IO_MUX_GPIO30_REG PERIPHS_IO_MUX_U_PAD_GPIO30
#define IO_MUX_GPIO31_REG PERIPHS_IO_MUX_U_PAD_GPIO31
#define IO_MUX_GPIO32_REG PERIPHS_IO_MUX_U_PAD_GPIO32
#define IO_MUX_GPIO33_REG PERIPHS_IO_MUX_U_PAD_GPIO33
#define IO_MUX_GPIO34_REG PERIPHS_IO_MUX_U_PAD_GPIO34
#define IO_MUX_GPIO35_REG PERIPHS_IO_MUX_U_PAD_GPIO35
#define IO_MUX_GPIO36_REG PERIPHS_IO_MUX_U_PAD_GPIO36
#define IO_MUX_GPIO37_REG PERIPHS_IO_MUX_U_PAD_GPIO37
#define IO_MUX_GPIO38_REG PERIPHS_IO_MUX_U_PAD_GPIO38
#define IO_MUX_GPIO39_REG PERIPHS_IO_MUX_U_PAD_GPIO39
#define IO_MUX_GPIO40_REG PERIPHS_IO_MUX_U_PAD_GPIO40
#define IO_MUX_GPIO41_REG PERIPHS_IO_MUX_U_PAD_GPIO41
#define IO_MUX_GPIO42_REG PERIPHS_IO_MUX_U_PAD_GPIO42
#define IO_MUX_GPIO43_REG PERIPHS_IO_MUX_U_PAD_GPIO43
#define IO_MUX_GPIO44_REG PERIPHS_IO_MUX_U_PAD_GPIO44
#define IO_MUX_GPIO45_REG PERIPHS_IO_MUX_U_PAD_GPIO45
#define IO_MUX_GPIO46_REG PERIPHS_IO_MUX_U_PAD_GPIO46
#define IO_MUX_GPIO47_REG PERIPHS_IO_MUX_U_PAD_GPIO47
#define IO_MUX_GPIO48_REG PERIPHS_IO_MUX_U_PAD_GPIO48
#define IO_MUX_GPIO49_REG PERIPHS_IO_MUX_U_PAD_GPIO49
#define IO_MUX_GPIO50_REG PERIPHS_IO_MUX_U_PAD_GPIO50
#define IO_MUX_GPIO51_REG PERIPHS_IO_MUX_U_PAD_GPIO51
#define IO_MUX_GPIO52_REG PERIPHS_IO_MUX_U_PAD_GPIO52
#define IO_MUX_GPIO53_REG PERIPHS_IO_MUX_U_PAD_GPIO53
#define IO_MUX_GPIO54_REG PERIPHS_IO_MUX_U_PAD_GPIO54
#define IO_MUX_GPIO55_REG PERIPHS_IO_MUX_U_PAD_GPIO55
#define IO_MUX_GPIO56_REG PERIPHS_IO_MUX_U_PAD_GPIO56
#define FUNC_GPIO_GPIO 1
#define PIN_FUNC_GPIO 1
#define GPIO_PAD_PULLUP(num) do{PIN_PULLDWN_DIS(IOMUX_REG_GPIO##num);PIN_PULLUP_EN(IOMUX_REG_GPIO##num);}while(0)
#define GPIO_PAD_PULLDOWN(num) do{PIN_PULLUP_DIS(IOMUX_REG_GPIO##num);PIN_PULLDWN_EN(IOMUX_REG_GPIO##num);}while(0)
#define GPIO_PAD_SET_DRV(num, drv) PIN_SET_DRV(IOMUX_REG_GPIO##num, drv)
#define MAX_RTC_GPIO_NUM 15
#define MAX_PAD_GPIO_NUM 56
#define MAX_GPIO_NUM 56
#define HIGH_IO_HOLD_BIT_SHIFT 32
#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE
#define PIN_CTRL (REG_IO_MUX_BASE +0x00)
#define PAD_POWER_SEL BIT(15)
#define PAD_POWER_SEL_V 0x1
#define PAD_POWER_SEL_M BIT(15)
#define PAD_POWER_SEL_S 15
#define PAD_POWER_SWITCH_DELAY 0x7
#define PAD_POWER_SWITCH_DELAY_V 0x7
#define PAD_POWER_SWITCH_DELAY_M (PAD_POWER_SWITCH_DELAY_V << PAD_POWER_SWITCH_DELAY_S)
#define PAD_POWER_SWITCH_DELAY_S 12
#define CLK_OUT3 IO_MUX_CLK_OUT3
#define CLK_OUT3_V IO_MUX_CLK_OUT3_V
#define CLK_OUT3_S IO_MUX_CLK_OUT3_S
#define CLK_OUT3_M IO_MUX_CLK_OUT3_M
#define CLK_OUT2 IO_MUX_CLK_OUT2
#define CLK_OUT2_V IO_MUX_CLK_OUT2_V
#define CLK_OUT2_S IO_MUX_CLK_OUT2_S
#define CLK_OUT2_M IO_MUX_CLK_OUT2_M
#define CLK_OUT1 IO_MUX_CLK_OUT1
#define CLK_OUT1_V IO_MUX_CLK_OUT1_V
#define CLK_OUT1_S IO_MUX_CLK_OUT1_S
#define CLK_OUT1_M IO_MUX_CLK_OUT1_M
// definitions above are inherited from previous version of code, should double check
// definitions below are generated from pin_txt.csv
#define PERIPHS_IO_MUX_U_PAD_GPIO0 (REG_IO_MUX_BASE + 0x4)
#define FUNC_GPIO0_GPIO0 1
#define FUNC_GPIO0_GPIO0_0 0
#define PERIPHS_IO_MUX_U_PAD_GPIO1 (REG_IO_MUX_BASE + 0x8)
#define FUNC_GPIO1_GPIO1 1
#define FUNC_GPIO1_GPIO1_0 0
#define PERIPHS_IO_MUX_U_PAD_GPIO2 (REG_IO_MUX_BASE + 0xC)
#define FUNC_GPIO2_GPIO2 1
#define FUNC_GPIO2_MTCK 0
#define PERIPHS_IO_MUX_U_PAD_GPIO3 (REG_IO_MUX_BASE + 0x10)
#define FUNC_GPIO3_GPIO3 1
#define FUNC_GPIO3_MTDI 0
#define PERIPHS_IO_MUX_U_PAD_GPIO4 (REG_IO_MUX_BASE + 0x14)
#define FUNC_GPIO4_GPIO4 1
#define FUNC_GPIO4_MTMS 0
#define PERIPHS_IO_MUX_U_PAD_GPIO5 (REG_IO_MUX_BASE + 0x18)
#define FUNC_GPIO5_GPIO5 1
#define FUNC_GPIO5_MTDO 0
#define PERIPHS_IO_MUX_U_PAD_GPIO6 (REG_IO_MUX_BASE + 0x1C)
#define FUNC_GPIO6_SPI2_HOLD_PAD 3
#define FUNC_GPIO6_GPIO6 1
#define FUNC_GPIO6_GPIO6_0 0
#define PERIPHS_IO_MUX_U_PAD_GPIO7 (REG_IO_MUX_BASE + 0x20)
#define FUNC_GPIO7_SPI2_CS_PAD 3
#define FUNC_GPIO7_GPIO7 1
#define FUNC_GPIO7_GPIO7_0 0
#define PERIPHS_IO_MUX_U_PAD_GPIO8 (REG_IO_MUX_BASE + 0x24)
#define FUNC_GPIO8_SPI2_D_PAD 3
#define FUNC_GPIO8_UART0_RTS_PAD 2
#define FUNC_GPIO8_GPIO8 1
#define FUNC_GPIO8_GPIO8_0 0
#define PERIPHS_IO_MUX_U_PAD_GPIO9 (REG_IO_MUX_BASE + 0x28)
#define FUNC_GPIO9_SPI2_CK_PAD 3
#define FUNC_GPIO9_UART0_CTS_PAD 2
#define FUNC_GPIO9_GPIO9 1
#define FUNC_GPIO9_GPIO9_0 0
#define PERIPHS_IO_MUX_U_PAD_GPIO10 (REG_IO_MUX_BASE + 0x2C)
#define FUNC_GPIO10_SPI2_Q_PAD 3
#define FUNC_GPIO10_UART1_TXD_PAD 2
#define FUNC_GPIO10_GPIO10 1
#define FUNC_GPIO10_GPIO10_0 0
#define PERIPHS_IO_MUX_U_PAD_GPIO11 (REG_IO_MUX_BASE + 0x30)
#define FUNC_GPIO11_SPI2_WP_PAD 3
#define FUNC_GPIO11_UART1_RXD_PAD 2
#define FUNC_GPIO11_GPIO11 1
#define FUNC_GPIO11_GPIO11_0 0
#define PERIPHS_IO_MUX_U_PAD_GPIO12 (REG_IO_MUX_BASE + 0x34)
#define FUNC_GPIO12_UART1_RTS_PAD 2
#define FUNC_GPIO12_GPIO12 1
#define FUNC_GPIO12_GPIO12_0 0
#define PERIPHS_IO_MUX_U_PAD_GPIO13 (REG_IO_MUX_BASE + 0x38)
#define FUNC_GPIO13_UART1_CTS_PAD 2
#define FUNC_GPIO13_GPIO13 1
#define FUNC_GPIO13_GPIO13_0 0
#define PERIPHS_IO_MUX_U_PAD_GPIO14 (REG_IO_MUX_BASE + 0x3C)
#define FUNC_GPIO14_GPIO14 1
#define FUNC_GPIO14_GPIO14_0 0
#define PERIPHS_IO_MUX_U_PAD_GPIO15 (REG_IO_MUX_BASE + 0x40)
#define FUNC_GPIO15_GPIO15 1
#define FUNC_GPIO15_GPIO15_0 0
#define PERIPHS_IO_MUX_U_PAD_GPIO16 (REG_IO_MUX_BASE + 0x44)
#define FUNC_GPIO16_GPIO16 1
#define FUNC_GPIO16_GPIO16_0 0
#define PERIPHS_IO_MUX_U_PAD_GPIO17 (REG_IO_MUX_BASE + 0x48)
#define FUNC_GPIO17_GPIO17 1
#define FUNC_GPIO17_GPIO17_0 0
#define PERIPHS_IO_MUX_U_PAD_GPIO18 (REG_IO_MUX_BASE + 0x4C)
#define FUNC_GPIO18_GPIO18 1
#define FUNC_GPIO18_GPIO18_0 0
#define PERIPHS_IO_MUX_U_PAD_GPIO19 (REG_IO_MUX_BASE + 0x50)
#define FUNC_GPIO19_GPIO19 1
#define FUNC_GPIO19_GPIO19_0 0
#define PERIPHS_IO_MUX_U_PAD_GPIO20 (REG_IO_MUX_BASE + 0x54)
#define FUNC_GPIO20_GPIO20 1
#define FUNC_GPIO20_GPIO20_0 0
#define PERIPHS_IO_MUX_U_PAD_GPIO21 (REG_IO_MUX_BASE + 0x58)
#define FUNC_GPIO21_GPIO21 1
#define FUNC_GPIO21_GPIO21_0 0
#define PERIPHS_IO_MUX_U_PAD_GPIO22 (REG_IO_MUX_BASE + 0x5C)
#define FUNC_GPIO22_DBG_PSRAM_CK_PAD 4
#define FUNC_GPIO22_GPIO22 1
#define FUNC_GPIO22_GPIO22_0 0
#define PERIPHS_IO_MUX_U_PAD_GPIO23 (REG_IO_MUX_BASE + 0x60)
#define FUNC_GPIO23_DBG_PSRAM_CS_PAD 4
#define FUNC_GPIO23_REF_50M_CLK_PAD 3
#define FUNC_GPIO23_GPIO23 1
#define FUNC_GPIO23_GPIO23_0 0
#define PERIPHS_IO_MUX_U_PAD_GPIO24 (REG_IO_MUX_BASE + 0x64)
#define FUNC_GPIO24_GPIO24 1
#define FUNC_GPIO24_GPIO24_0 0
#define PERIPHS_IO_MUX_U_PAD_GPIO25 (REG_IO_MUX_BASE + 0x68)
#define FUNC_GPIO25_GPIO25 1
#define FUNC_GPIO25_GPIO25_0 0
#define PERIPHS_IO_MUX_U_PAD_GPIO26 (REG_IO_MUX_BASE + 0x6C)
#define FUNC_GPIO26_GPIO26 1
#define FUNC_GPIO26_GPIO26_0 0
#define PERIPHS_IO_MUX_U_PAD_GPIO27 (REG_IO_MUX_BASE + 0x70)
#define FUNC_GPIO27_GPIO27 1
#define FUNC_GPIO27_GPIO27_0 0
#define PERIPHS_IO_MUX_U_PAD_GPIO28 (REG_IO_MUX_BASE + 0x74)
#define FUNC_GPIO28_DBG_PSRAM_D_PAD 4
#define FUNC_GPIO28_GMAC_PHY_RXDV_PAD 3
#define FUNC_GPIO28_SPI2_CS_PAD 2
#define FUNC_GPIO28_GPIO28 1
#define FUNC_GPIO28_GPIO28_0 0
#define PERIPHS_IO_MUX_U_PAD_GPIO29 (REG_IO_MUX_BASE + 0x78)
#define FUNC_GPIO29_DBG_PSRAM_Q_PAD 4
#define FUNC_GPIO29_GMAC_PHY_RXD0_PAD 3
#define FUNC_GPIO29_SPI2_D_PAD 2
#define FUNC_GPIO29_GPIO29 1
#define FUNC_GPIO29_GPIO29_0 0
#define PERIPHS_IO_MUX_U_PAD_GPIO30 (REG_IO_MUX_BASE + 0x7C)
#define FUNC_GPIO30_DBG_PSRAM_WP_PAD 4
#define FUNC_GPIO30_GMAC_PHY_RXD1_PAD 3
#define FUNC_GPIO30_SPI2_CK_PAD 2
#define FUNC_GPIO30_GPIO30 1
#define FUNC_GPIO30_GPIO30_0 0
#define PERIPHS_IO_MUX_U_PAD_GPIO31 (REG_IO_MUX_BASE + 0x80)
#define FUNC_GPIO31_DBG_PSRAM_HOLD_PAD 4
#define FUNC_GPIO31_GMAC_PHY_RXER_PAD 3
#define FUNC_GPIO31_SPI2_Q_PAD 2
#define FUNC_GPIO31_GPIO31 1
#define FUNC_GPIO31_GPIO31_0 0
#define PERIPHS_IO_MUX_U_PAD_GPIO32 (REG_IO_MUX_BASE + 0x84)
#define FUNC_GPIO32_DBG_PSRAM_DQ4_PAD 4
#define FUNC_GPIO32_GMAC_RMII_CLK_PAD 3
#define FUNC_GPIO32_SPI2_HOLD_PAD 2
#define FUNC_GPIO32_GPIO32 1
#define FUNC_GPIO32_GPIO32_0 0
#define PERIPHS_IO_MUX_U_PAD_GPIO33 (REG_IO_MUX_BASE + 0x88)
#define FUNC_GPIO33_DBG_PSRAM_DQ5_PAD 4
#define FUNC_GPIO33_GMAC_PHY_TXEN_PAD 3
#define FUNC_GPIO33_SPI2_WP_PAD 2
#define FUNC_GPIO33_GPIO33 1
#define FUNC_GPIO33_GPIO33_0 0
#define PERIPHS_IO_MUX_U_PAD_GPIO34 (REG_IO_MUX_BASE + 0x8C)
#define FUNC_GPIO34_DBG_PSRAM_DQ6_PAD 4
#define FUNC_GPIO34_GMAC_PHY_TXD0_PAD 3
#define FUNC_GPIO34_SPI2_IO4_PAD 2
#define FUNC_GPIO34_GPIO34 1
#define FUNC_GPIO34_GPIO34_0 0
#define PERIPHS_IO_MUX_U_PAD_GPIO35 (REG_IO_MUX_BASE + 0x90)
#define FUNC_GPIO35_DBG_PSRAM_DQ7_PAD 4
#define FUNC_GPIO35_GMAC_PHY_TXD1_PAD 3
#define FUNC_GPIO35_SPI2_IO5_PAD 2
#define FUNC_GPIO35_GPIO35 1
#define FUNC_GPIO35_GPIO35_0 0
#define PERIPHS_IO_MUX_U_PAD_GPIO36 (REG_IO_MUX_BASE + 0x94)
#define FUNC_GPIO36_DBG_PSRAM_DQS_0_PAD 4
#define FUNC_GPIO36_GMAC_PHY_TXER_PAD 3
#define FUNC_GPIO36_SPI2_IO6_PAD 2
#define FUNC_GPIO36_GPIO36 1
#define FUNC_GPIO36_GPIO36_0 0
#define PERIPHS_IO_MUX_U_PAD_GPIO37 (REG_IO_MUX_BASE + 0x98)
#define FUNC_GPIO37_SPI2_IO7_PAD 2
#define FUNC_GPIO37_GPIO37 1
#define FUNC_GPIO37_UART0_TXD_PAD 0
#define PERIPHS_IO_MUX_U_PAD_GPIO38 (REG_IO_MUX_BASE + 0x9C)
#define FUNC_GPIO38_SPI2_DQS_PAD 2
#define FUNC_GPIO38_GPIO38 1
#define FUNC_GPIO38_UART0_RXD_PAD 0
#define PERIPHS_IO_MUX_U_PAD_GPIO39 (REG_IO_MUX_BASE + 0xA0)
#define FUNC_GPIO39_DBG_PSRAM_DQ8_PAD 4
#define FUNC_GPIO39_REF_50M_CLK_PAD 3
#define FUNC_GPIO39_BIST_PAD 2
#define FUNC_GPIO39_GPIO39 1
#define FUNC_GPIO39_SD1_CDATA0_PAD 0
#define PERIPHS_IO_MUX_U_PAD_GPIO40 (REG_IO_MUX_BASE + 0xA4)
#define FUNC_GPIO40_DBG_PSRAM_DQ9_PAD 4
#define FUNC_GPIO40_GMAC_PHY_TXEN_PAD 3
#define FUNC_GPIO40_BIST_PAD 2
#define FUNC_GPIO40_GPIO40 1
#define FUNC_GPIO40_SD1_CDATA1_PAD 0
#define PERIPHS_IO_MUX_U_PAD_GPIO41 (REG_IO_MUX_BASE + 0xA8)
#define FUNC_GPIO41_DBG_PSRAM_DQ10_PAD 4
#define FUNC_GPIO41_GMAC_PHY_TXD0_PAD 3
#define FUNC_GPIO41_BIST_PAD 2
#define FUNC_GPIO41_GPIO41 1
#define FUNC_GPIO41_SD1_CDATA2_PAD 0
#define PERIPHS_IO_MUX_U_PAD_GPIO42 (REG_IO_MUX_BASE + 0xAC)
#define FUNC_GPIO42_DBG_PSRAM_DQ11_PAD 4
#define FUNC_GPIO42_GMAC_PHY_TXD1_PAD 3
#define FUNC_GPIO42_BIST_PAD 2
#define FUNC_GPIO42_GPIO42 1
#define FUNC_GPIO42_SD1_CDATA3_PAD 0
#define PERIPHS_IO_MUX_U_PAD_GPIO43 (REG_IO_MUX_BASE + 0xB0)
#define FUNC_GPIO43_DBG_PSRAM_DQ12_PAD 4
#define FUNC_GPIO43_GMAC_PHY_TXER_PAD 3
#define FUNC_GPIO43_BIST_PAD 2
#define FUNC_GPIO43_GPIO43 1
#define FUNC_GPIO43_SD1_CCLK_PAD 0
#define PERIPHS_IO_MUX_U_PAD_GPIO44 (REG_IO_MUX_BASE + 0xB4)
#define FUNC_GPIO44_DBG_PSRAM_DQ13_PAD 4
#define FUNC_GPIO44_GMAC_RMII_CLK_PAD 3
#define FUNC_GPIO44_BIST_PAD 2
#define FUNC_GPIO44_GPIO44 1
#define FUNC_GPIO44_SD1_CCMD_PAD 0
#define PERIPHS_IO_MUX_U_PAD_GPIO45 (REG_IO_MUX_BASE + 0xB8)
#define FUNC_GPIO45_DBG_PSRAM_DQ14_PAD 4
#define FUNC_GPIO45_GMAC_PHY_RXDV_PAD 3
#define FUNC_GPIO45_BIST_PAD 2
#define FUNC_GPIO45_GPIO45 1
#define FUNC_GPIO45_SD1_CDATA4_PAD 0
#define PERIPHS_IO_MUX_U_PAD_GPIO46 (REG_IO_MUX_BASE + 0xBC)
#define FUNC_GPIO46_DBG_PSRAM_DQ15_PAD 4
#define FUNC_GPIO46_GMAC_PHY_RXD0_PAD 3
#define FUNC_GPIO46_BIST_PAD 2
#define FUNC_GPIO46_GPIO46 1
#define FUNC_GPIO46_SD1_CDATA5_PAD 0
#define PERIPHS_IO_MUX_U_PAD_GPIO47 (REG_IO_MUX_BASE + 0xC0)
#define FUNC_GPIO47_DBG_PSRAM_DQS_1_PAD 4
#define FUNC_GPIO47_GMAC_PHY_RXD1_PAD 3
#define FUNC_GPIO47_BIST_PAD 2
#define FUNC_GPIO47_GPIO47 1
#define FUNC_GPIO47_SD1_CDATA6_PAD 0
#define PERIPHS_IO_MUX_U_PAD_GPIO48 (REG_IO_MUX_BASE + 0xC4)
#define FUNC_GPIO48_GMAC_PHY_RXER_PAD 3
#define FUNC_GPIO48_BIST_PAD 2
#define FUNC_GPIO48_GPIO48 1
#define FUNC_GPIO48_SD1_CDATA7_PAD 0
#define PERIPHS_IO_MUX_U_PAD_GPIO49 (REG_IO_MUX_BASE + 0xC8)
#define FUNC_GPIO49_DBG_FLASH_CS_PAD 4
#define FUNC_GPIO49_GMAC_PHY_TXEN_PAD 3
#define FUNC_GPIO49_GPIO49 1
#define FUNC_GPIO49_GPIO49_0 0
#define PERIPHS_IO_MUX_U_PAD_GPIO50 (REG_IO_MUX_BASE + 0xCC)
#define FUNC_GPIO50_DBG_FLASH_Q_PAD 4
#define FUNC_GPIO50_GMAC_RMII_CLK_PAD 3
#define FUNC_GPIO50_GPIO50 1
#define FUNC_GPIO50_GPIO50_0 0
#define PERIPHS_IO_MUX_U_PAD_GPIO51 (REG_IO_MUX_BASE + 0xD0)
#define FUNC_GPIO51_DBG_FLASH_WP_PAD 4
#define FUNC_GPIO51_GMAC_PHY_RXDV_PAD 3
#define FUNC_GPIO51_GPIO51 1
#define FUNC_GPIO51_GPIO51_0 0
#define PERIPHS_IO_MUX_U_PAD_GPIO52 (REG_IO_MUX_BASE + 0xD4)
#define FUNC_GPIO52_DBG_FLASH_HOLD_PAD 4
#define FUNC_GPIO52_GMAC_PHY_RXD0_PAD 3
#define FUNC_GPIO52_GPIO52 1
#define FUNC_GPIO52_GPIO52_0 0
#define PERIPHS_IO_MUX_U_PAD_GPIO53 (REG_IO_MUX_BASE + 0xD8)
#define FUNC_GPIO53_DBG_FLASH_CK_PAD 4
#define FUNC_GPIO53_GMAC_PHY_RXD1_PAD 3
#define FUNC_GPIO53_GPIO53 1
#define FUNC_GPIO53_GPIO53_0 0
#define PERIPHS_IO_MUX_U_PAD_GPIO54 (REG_IO_MUX_BASE + 0xDC)
#define FUNC_GPIO54_DBG_FLASH_D_PAD 4
#define FUNC_GPIO54_GMAC_PHY_RXER_PAD 3
#define FUNC_GPIO54_GPIO54 1
#define FUNC_GPIO54_GPIO54_0 0
#define PERIPHS_IO_MUX_U_PAD_GPIO55 (REG_IO_MUX_BASE + 0xE0)
#define FUNC_GPIO55_GPIO55 1
#define FUNC_GPIO55_GPIO55_0 0
#define PERIPHS_IO_MUX_U_PAD_GPIO56 (REG_IO_MUX_BASE + 0xE4)
#define FUNC_GPIO56_GPIO56 1
#define FUNC_GPIO56_GPIO56_0 0
#define IO_MUX_DATE_REG (REG_IO_MUX_BASE + 0x104)
/* IO_MUX_DATE : R/W ;bitpos:[27:0] ;default: 27'h0201222 ; */
/*description: csv date.*/
#define IO_MUX_DATE 0x0FFFFFFF
#define IO_MUX_DATE_M ((IO_MUX_DATE_V)<<(IO_MUX_DATE_S))
#define IO_MUX_DATE_V 0xFFFFFFF
#define IO_MUX_DATE_S 0

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/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
typedef volatile struct iomux_dev_s {
uint32_t reserved_0;
union {
struct {
uint32_t mcu_oe : 1; /*output enable on sleep mode*/
uint32_t slp_sel : 1; /*io sleep mode enable. set 1 to enable sleep mode.*/
uint32_t mcu_wpd : 1; /*pull-down enable on sleep mode*/
uint32_t mcu_wpu : 1; /*pull-up enable on sleep mode*/
uint32_t mcu_ie : 1; /*input enable on sleep mode*/
uint32_t mcu_drv : 2; /*select drive strenth on sleep mode*/
uint32_t fun_wpd : 1; /*pull-down enable*/
uint32_t fun_wpu : 1; /*pull-up enable*/
uint32_t fun_ie : 1; /*input enable*/
uint32_t fun_drv : 2; /*select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA*/
uint32_t mcu_sel : 3; /*0:select function0, 1:select function1 ...*/
uint32_t filter_en : 1; /*input filter enable*/
uint32_t reserved16 : 16;
};
uint32_t val;
} gpio[57];
uint32_t reserved_e8;
uint32_t reserved_ec;
uint32_t reserved_f0;
uint32_t reserved_f4;
uint32_t reserved_f8;
uint32_t reserved_fc;
uint32_t reserved_100;
union {
struct {
uint32_t reg_date : 28; /*csv date*/
uint32_t reserved28 : 4;
};
uint32_t val;
} io_mux_date;
} iomux_dev_t;
extern iomux_dev_t IOMUX;
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** KEYMNG_CLK_REG register
* Key Manager clock gate control register
*/
#define KEYMNG_CLK_REG (DR_REG_KEYMNG_BASE + 0x4)
/** KEYMNG_CLK_EN : R/W; bitpos: [0]; default: 1;
* Write 1 to force on register clock gate.
*/
#define KEYMNG_CLK_EN (BIT(0))
#define KEYMNG_CLK_EN_M (KEYMNG_CLK_EN_V << KEYMNG_CLK_EN_S)
#define KEYMNG_CLK_EN_V 0x00000001U
#define KEYMNG_CLK_EN_S 0
/** KEYMNG_MEM_CG_FORCE_ON : R/W; bitpos: [1]; default: 0;
* Write 1 to force on memory clock gate.
*/
#define KEYMNG_MEM_CG_FORCE_ON (BIT(1))
#define KEYMNG_MEM_CG_FORCE_ON_M (KEYMNG_MEM_CG_FORCE_ON_V << KEYMNG_MEM_CG_FORCE_ON_S)
#define KEYMNG_MEM_CG_FORCE_ON_V 0x00000001U
#define KEYMNG_MEM_CG_FORCE_ON_S 1
/** KEYMNG_INT_RAW_REG register
* Key Manager interrupt raw register, valid in level.
*/
#define KEYMNG_INT_RAW_REG (DR_REG_KEYMNG_BASE + 0x8)
/** KEYMNG_PREP_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
* The raw interrupt status bit for the km_prep_done_int interrupt
*/
#define KEYMNG_PREP_DONE_INT_RAW (BIT(0))
#define KEYMNG_PREP_DONE_INT_RAW_M (KEYMNG_PREP_DONE_INT_RAW_V << KEYMNG_PREP_DONE_INT_RAW_S)
#define KEYMNG_PREP_DONE_INT_RAW_V 0x00000001U
#define KEYMNG_PREP_DONE_INT_RAW_S 0
/** KEYMNG_PROC_DONE_INT_RAW : RO/WTC/SS; bitpos: [1]; default: 0;
* The raw interrupt status bit for the km_proc_done_int interrupt
*/
#define KEYMNG_PROC_DONE_INT_RAW (BIT(1))
#define KEYMNG_PROC_DONE_INT_RAW_M (KEYMNG_PROC_DONE_INT_RAW_V << KEYMNG_PROC_DONE_INT_RAW_S)
#define KEYMNG_PROC_DONE_INT_RAW_V 0x00000001U
#define KEYMNG_PROC_DONE_INT_RAW_S 1
/** KEYMNG_POST_DONE_INT_RAW : RO/WTC/SS; bitpos: [2]; default: 0;
* The raw interrupt status bit for the km_post_done_int interrupt
*/
#define KEYMNG_POST_DONE_INT_RAW (BIT(2))
#define KEYMNG_POST_DONE_INT_RAW_M (KEYMNG_POST_DONE_INT_RAW_V << KEYMNG_POST_DONE_INT_RAW_S)
#define KEYMNG_POST_DONE_INT_RAW_V 0x00000001U
#define KEYMNG_POST_DONE_INT_RAW_S 2
/** KEYMNG_INT_ST_REG register
* Key Manager interrupt status register.
*/
#define KEYMNG_INT_ST_REG (DR_REG_KEYMNG_BASE + 0xc)
/** KEYMNG_PREP_DONE_INT_ST : RO; bitpos: [0]; default: 0;
* The masked interrupt status bit for the km_prep_done_int interrupt
*/
#define KEYMNG_PREP_DONE_INT_ST (BIT(0))
#define KEYMNG_PREP_DONE_INT_ST_M (KEYMNG_PREP_DONE_INT_ST_V << KEYMNG_PREP_DONE_INT_ST_S)
#define KEYMNG_PREP_DONE_INT_ST_V 0x00000001U
#define KEYMNG_PREP_DONE_INT_ST_S 0
/** KEYMNG_PROC_DONE_INT_ST : RO; bitpos: [1]; default: 0;
* The masked interrupt status bit for the km_proc_done_int interrupt
*/
#define KEYMNG_PROC_DONE_INT_ST (BIT(1))
#define KEYMNG_PROC_DONE_INT_ST_M (KEYMNG_PROC_DONE_INT_ST_V << KEYMNG_PROC_DONE_INT_ST_S)
#define KEYMNG_PROC_DONE_INT_ST_V 0x00000001U
#define KEYMNG_PROC_DONE_INT_ST_S 1
/** KEYMNG_POST_DONE_INT_ST : RO; bitpos: [2]; default: 0;
* The masked interrupt status bit for the km_post_done_int interrupt
*/
#define KEYMNG_POST_DONE_INT_ST (BIT(2))
#define KEYMNG_POST_DONE_INT_ST_M (KEYMNG_POST_DONE_INT_ST_V << KEYMNG_POST_DONE_INT_ST_S)
#define KEYMNG_POST_DONE_INT_ST_V 0x00000001U
#define KEYMNG_POST_DONE_INT_ST_S 2
/** KEYMNG_INT_ENA_REG register
* Key Manager interrupt enable register.
*/
#define KEYMNG_INT_ENA_REG (DR_REG_KEYMNG_BASE + 0x10)
/** KEYMNG_PREP_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
* The interrupt enable bit for the km_prep_done_int interrupt
*/
#define KEYMNG_PREP_DONE_INT_ENA (BIT(0))
#define KEYMNG_PREP_DONE_INT_ENA_M (KEYMNG_PREP_DONE_INT_ENA_V << KEYMNG_PREP_DONE_INT_ENA_S)
#define KEYMNG_PREP_DONE_INT_ENA_V 0x00000001U
#define KEYMNG_PREP_DONE_INT_ENA_S 0
/** KEYMNG_PROC_DONE_INT_ENA : R/W; bitpos: [1]; default: 0;
* The interrupt enable bit for the km_proc_done_int interrupt
*/
#define KEYMNG_PROC_DONE_INT_ENA (BIT(1))
#define KEYMNG_PROC_DONE_INT_ENA_M (KEYMNG_PROC_DONE_INT_ENA_V << KEYMNG_PROC_DONE_INT_ENA_S)
#define KEYMNG_PROC_DONE_INT_ENA_V 0x00000001U
#define KEYMNG_PROC_DONE_INT_ENA_S 1
/** KEYMNG_POST_DONE_INT_ENA : R/W; bitpos: [2]; default: 0;
* The interrupt enable bit for the km_post_done_int interrupt
*/
#define KEYMNG_POST_DONE_INT_ENA (BIT(2))
#define KEYMNG_POST_DONE_INT_ENA_M (KEYMNG_POST_DONE_INT_ENA_V << KEYMNG_POST_DONE_INT_ENA_S)
#define KEYMNG_POST_DONE_INT_ENA_V 0x00000001U
#define KEYMNG_POST_DONE_INT_ENA_S 2
/** KEYMNG_INT_CLR_REG register
* Key Manager interrupt clear register.
*/
#define KEYMNG_INT_CLR_REG (DR_REG_KEYMNG_BASE + 0x14)
/** KEYMNG_PREP_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
* Set this bit to clear the km_prep_done_int interrupt
*/
#define KEYMNG_PREP_DONE_INT_CLR (BIT(0))
#define KEYMNG_PREP_DONE_INT_CLR_M (KEYMNG_PREP_DONE_INT_CLR_V << KEYMNG_PREP_DONE_INT_CLR_S)
#define KEYMNG_PREP_DONE_INT_CLR_V 0x00000001U
#define KEYMNG_PREP_DONE_INT_CLR_S 0
/** KEYMNG_PROC_DONE_INT_CLR : WT; bitpos: [1]; default: 0;
* Set this bit to clear the km_proc_done_int interrupt
*/
#define KEYMNG_PROC_DONE_INT_CLR (BIT(1))
#define KEYMNG_PROC_DONE_INT_CLR_M (KEYMNG_PROC_DONE_INT_CLR_V << KEYMNG_PROC_DONE_INT_CLR_S)
#define KEYMNG_PROC_DONE_INT_CLR_V 0x00000001U
#define KEYMNG_PROC_DONE_INT_CLR_S 1
/** KEYMNG_POST_DONE_INT_CLR : WT; bitpos: [2]; default: 0;
* Set this bit to clear the km_post_done_int interrupt
*/
#define KEYMNG_POST_DONE_INT_CLR (BIT(2))
#define KEYMNG_POST_DONE_INT_CLR_M (KEYMNG_POST_DONE_INT_CLR_V << KEYMNG_POST_DONE_INT_CLR_S)
#define KEYMNG_POST_DONE_INT_CLR_V 0x00000001U
#define KEYMNG_POST_DONE_INT_CLR_S 2
/** KEYMNG_STATIC_REG register
* Key Manager static configuration register
*/
#define KEYMNG_STATIC_REG (DR_REG_KEYMNG_BASE + 0x18)
/** KEYMNG_USE_EFUSE_KEY : R/W; bitpos: [1:0]; default: 0;
* Set each bit to choose efuse key instead of key manager deployed key. Each bit
* stands for a key type: bit 1 for xts_key; bit 0 for ecdsa_key
*/
#define KEYMNG_USE_EFUSE_KEY 0x00000003U
#define KEYMNG_USE_EFUSE_KEY_M (KEYMNG_USE_EFUSE_KEY_V << KEYMNG_USE_EFUSE_KEY_S)
#define KEYMNG_USE_EFUSE_KEY_V 0x00000003U
#define KEYMNG_USE_EFUSE_KEY_S 0
/** KEYMNG_RND_SWITCH_CYCLE : R/W; bitpos: [8:4]; default: 15;
* The core clock cycle number to sample one rng input data. Please set it bigger than
* the clock cycle ratio: T_rng/T_km
*/
#define KEYMNG_RND_SWITCH_CYCLE 0x0000001FU
#define KEYMNG_RND_SWITCH_CYCLE_M (KEYMNG_RND_SWITCH_CYCLE_V << KEYMNG_RND_SWITCH_CYCLE_S)
#define KEYMNG_RND_SWITCH_CYCLE_V 0x0000001FU
#define KEYMNG_RND_SWITCH_CYCLE_S 4
/** KEYMNG_USE_SW_INIT_KEY : R/W; bitpos: [9]; default: 0;
* Set this bit to use software written init key instead of efuse_init_key.
*/
#define KEYMNG_USE_SW_INIT_KEY (BIT(9))
#define KEYMNG_USE_SW_INIT_KEY_M (KEYMNG_USE_SW_INIT_KEY_V << KEYMNG_USE_SW_INIT_KEY_S)
#define KEYMNG_USE_SW_INIT_KEY_V 0x00000001U
#define KEYMNG_USE_SW_INIT_KEY_S 9
/** KEYMNG_XTS_AES_KEY_LEN : R/W; bitpos: [10]; default: 0;
* Set this bit to choose using xts-aes-256 or xts-aes-128. 1: use xts-aes-256. 0: use
* xts-aes-128.
*/
#define KEYMNG_XTS_AES_KEY_LEN (BIT(10))
#define KEYMNG_XTS_AES_KEY_LEN_M (KEYMNG_XTS_AES_KEY_LEN_V << KEYMNG_XTS_AES_KEY_LEN_S)
#define KEYMNG_XTS_AES_KEY_LEN_V 0x00000001U
#define KEYMNG_XTS_AES_KEY_LEN_S 10
/** KEYMNG_LOCK_REG register
* Key Manager static configuration locker register
*/
#define KEYMNG_LOCK_REG (DR_REG_KEYMNG_BASE + 0x1c)
/** KEYMNG_USE_EFUSE_KEY_LOCK : R/W1; bitpos: [1:0]; default: 0;
* Write 1 to lock reg_use_efuse_key. Each bit locks the corresponding bit of
* reg_use_efuse_key.
*/
#define KEYMNG_USE_EFUSE_KEY_LOCK 0x00000003U
#define KEYMNG_USE_EFUSE_KEY_LOCK_M (KEYMNG_USE_EFUSE_KEY_LOCK_V << KEYMNG_USE_EFUSE_KEY_LOCK_S)
#define KEYMNG_USE_EFUSE_KEY_LOCK_V 0x00000003U
#define KEYMNG_USE_EFUSE_KEY_LOCK_S 0
/** KEYMNG_RND_SWITCH_CYCLE_LOCK : R/W1; bitpos: [4]; default: 0;
* Write 1 to lock reg_rnd_switch_cycle.
*/
#define KEYMNG_RND_SWITCH_CYCLE_LOCK (BIT(4))
#define KEYMNG_RND_SWITCH_CYCLE_LOCK_M (KEYMNG_RND_SWITCH_CYCLE_LOCK_V << KEYMNG_RND_SWITCH_CYCLE_LOCK_S)
#define KEYMNG_RND_SWITCH_CYCLE_LOCK_V 0x00000001U
#define KEYMNG_RND_SWITCH_CYCLE_LOCK_S 4
/** KEYMNG_USE_SW_INIT_KEY_LOCK : R/W1; bitpos: [5]; default: 0;
* Write 1 to lock reg_use_sw_init_key.
*/
#define KEYMNG_USE_SW_INIT_KEY_LOCK (BIT(5))
#define KEYMNG_USE_SW_INIT_KEY_LOCK_M (KEYMNG_USE_SW_INIT_KEY_LOCK_V << KEYMNG_USE_SW_INIT_KEY_LOCK_S)
#define KEYMNG_USE_SW_INIT_KEY_LOCK_V 0x00000001U
#define KEYMNG_USE_SW_INIT_KEY_LOCK_S 5
/** KEYMNG_XTS_AES_KEY_LEN_LOCK : R/W1; bitpos: [6]; default: 0;
* Write 1 to lock reg_xts_aes_key_len.
*/
#define KEYMNG_XTS_AES_KEY_LEN_LOCK (BIT(6))
#define KEYMNG_XTS_AES_KEY_LEN_LOCK_M (KEYMNG_XTS_AES_KEY_LEN_LOCK_V << KEYMNG_XTS_AES_KEY_LEN_LOCK_S)
#define KEYMNG_XTS_AES_KEY_LEN_LOCK_V 0x00000001U
#define KEYMNG_XTS_AES_KEY_LEN_LOCK_S 6
/** KEYMNG_CONF_REG register
* Key Manager configuration register
*/
#define KEYMNG_CONF_REG (DR_REG_KEYMNG_BASE + 0x20)
/** KEYMNG_KGEN_MODE : R/W; bitpos: [2:0]; default: 0;
* Set this field to choose the key generator deployment mode. 0: random mode. 1: AES
* mode. 2: ECDH0 mode. 3: ECDH1 mode. 4: recover mode. 5: export mode. 6-7: reserved.
*/
#define KEYMNG_KGEN_MODE 0x00000007U
#define KEYMNG_KGEN_MODE_M (KEYMNG_KGEN_MODE_V << KEYMNG_KGEN_MODE_S)
#define KEYMNG_KGEN_MODE_V 0x00000007U
#define KEYMNG_KGEN_MODE_S 0
/** KEYMNG_KEY_PURPOSE : R/W; bitpos: [6:3]; default: 0;
* Set this field to choose the key purpose. 1: ecdsa_key 2: xts_256_1_key. 3:
* xts_256_2_key. 4. xts_128_key. others: reserved.
*/
#define KEYMNG_KEY_PURPOSE 0x0000000FU
#define KEYMNG_KEY_PURPOSE_M (KEYMNG_KEY_PURPOSE_V << KEYMNG_KEY_PURPOSE_S)
#define KEYMNG_KEY_PURPOSE_V 0x0000000FU
#define KEYMNG_KEY_PURPOSE_S 3
/** KEYMNG_START_REG register
* Key Manager control register
*/
#define KEYMNG_START_REG (DR_REG_KEYMNG_BASE + 0x24)
/** KEYMNG_START : WT; bitpos: [0]; default: 0;
* Write 1 to continue Key Manager operation at LOAD/GAIN state.
*/
#define KEYMNG_START (BIT(0))
#define KEYMNG_START_M (KEYMNG_START_V << KEYMNG_START_S)
#define KEYMNG_START_V 0x00000001U
#define KEYMNG_START_S 0
/** KEYMNG_CONTINUE : WT; bitpos: [1]; default: 0;
* Write 1 to start Key Manager at IDLE state.
*/
#define KEYMNG_CONTINUE (BIT(1))
#define KEYMNG_CONTINUE_M (KEYMNG_CONTINUE_V << KEYMNG_CONTINUE_S)
#define KEYMNG_CONTINUE_V 0x00000001U
#define KEYMNG_CONTINUE_S 1
/** KEYMNG_STATE_REG register
* Key Manager state register
*/
#define KEYMNG_STATE_REG (DR_REG_KEYMNG_BASE + 0x28)
/** KEYMNG_STATE : RO; bitpos: [1:0]; default: 0;
* The state of Key Manager. 0: IDLE. 1: LOAD. 2: GAIN. 3: BUSY.
*/
#define KEYMNG_STATE 0x00000003U
#define KEYMNG_STATE_M (KEYMNG_STATE_V << KEYMNG_STATE_S)
#define KEYMNG_STATE_V 0x00000003U
#define KEYMNG_STATE_S 0
/** KEYMNG_RESULT_REG register
* Key Manager operation result register
*/
#define KEYMNG_RESULT_REG (DR_REG_KEYMNG_BASE + 0x2c)
/** KEYMNG_PROC_RESULT : RO/SS; bitpos: [0]; default: 0;
* The procedure result bit of Key Manager, only valid when Key Manager procedure is
* done. 1: Key Manager procedure succeeded. 0: Key Manager procedure failed.
*/
#define KEYMNG_PROC_RESULT (BIT(0))
#define KEYMNG_PROC_RESULT_M (KEYMNG_PROC_RESULT_V << KEYMNG_PROC_RESULT_S)
#define KEYMNG_PROC_RESULT_V 0x00000001U
#define KEYMNG_PROC_RESULT_S 0
/** KEYMNG_KEY_VLD_REG register
* Key Manager key status register
*/
#define KEYMNG_KEY_VLD_REG (DR_REG_KEYMNG_BASE + 0x30)
/** KEYMNG_KEY_ECDSA_VLD : RO; bitpos: [0]; default: 0;
* The status bit for key_ecdsa. 1: The key has been deployed correctly. 0: The key
* has not been deployed yet.
*/
#define KEYMNG_KEY_ECDSA_VLD (BIT(0))
#define KEYMNG_KEY_ECDSA_VLD_M (KEYMNG_KEY_ECDSA_VLD_V << KEYMNG_KEY_ECDSA_VLD_S)
#define KEYMNG_KEY_ECDSA_VLD_V 0x00000001U
#define KEYMNG_KEY_ECDSA_VLD_S 0
/** KEYMNG_KEY_XTS_VLD : RO; bitpos: [1]; default: 0;
* The status bit for key_xts. 1: The key has been deployed correctly. 0: The
* key has not been deployed yet.
*/
#define KEYMNG_KEY_XTS_VLD (BIT(1))
#define KEYMNG_KEY_XTS_VLD_M (KEYMNG_KEY_XTS_VLD_V << KEYMNG_KEY_XTS_VLD_S)
#define KEYMNG_KEY_XTS_VLD_V 0x00000001U
#define KEYMNG_KEY_XTS_VLD_S 1
/** KEYMNG_HUK_VLD_REG register
* Key Manager HUK status register
*/
#define KEYMNG_HUK_VLD_REG (DR_REG_KEYMNG_BASE + 0x34)
/** KEYMNG_HUK_VALID : RO; bitpos: [0]; default: 0;
* The HUK status. 0: HUK is not valid. 1: HUK is valid.
*/
#define KEYMNG_HUK_VALID (BIT(0))
#define KEYMNG_HUK_VALID_M (KEYMNG_HUK_VALID_V << KEYMNG_HUK_VALID_S)
#define KEYMNG_HUK_VALID_V 0x00000001U
#define KEYMNG_HUK_VALID_S 0
/** KEYMNG_DATE_REG register
* Version control register
*/
#define KEYMNG_DATE_REG (DR_REG_KEYMNG_BASE + 0xfc)
/** KEYMNG_DATE : R/W; bitpos: [27:0]; default: 36720704;
* Key Manager version control register.
*/
#define KEYMNG_DATE 0x0FFFFFFFU
#define KEYMNG_DATE_M (KEYMNG_DATE_V << KEYMNG_DATE_S)
#define KEYMNG_DATE_V 0x0FFFFFFFU
#define KEYMNG_DATE_S 0
/** KEYMNG_ASSIST_INFO_MEM register
* The memory that stores assist key info.
*/
#define KEYMNG_ASSIST_INFO_MEM (DR_REG_KEYMNG_BASE + 0x100)
#define KEYMNG_ASSIST_INFO_MEM_SIZE_BYTES 64
/** KEYMNG_PUBLIC_INFO_MEM register
* The memory that stores public key info.
*/
#define KEYMNG_PUBLIC_INFO_MEM (DR_REG_KEYMNG_BASE + 0x140)
#define KEYMNG_PUBLIC_INFO_MEM_SIZE_BYTES 64
/** KEYMNG_SW_INIT_KEY_MEM register
* The memory that stores software written init key.
*/
#define KEYMNG_SW_INIT_KEY_MEM (DR_REG_KEYMNG_BASE + 0x180)
#define KEYMNG_SW_INIT_KEY_MEM_SIZE_BYTES 32
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Memory data */
/** Group: Clock gate register */
/** Type of clk register
* Key Manager clock gate control register
*/
typedef union {
struct {
/** clk_en : R/W; bitpos: [0]; default: 1;
* Write 1 to force on register clock gate.
*/
uint32_t clk_en:1;
/** mem_cg_force_on : R/W; bitpos: [1]; default: 0;
* Write 1 to force on memory clock gate.
*/
uint32_t mem_cg_force_on:1;
uint32_t reserved_2:30;
};
uint32_t val;
} keymng_clk_reg_t;
/** Group: Interrupt registers */
/** Type of int_raw register
* Key Manager interrupt raw register, valid in level.
*/
typedef union {
struct {
/** prep_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0;
* The raw interrupt status bit for the km_prep_done_int interrupt
*/
uint32_t prep_done_int_raw:1;
/** proc_done_int_raw : RO/WTC/SS; bitpos: [1]; default: 0;
* The raw interrupt status bit for the km_proc_done_int interrupt
*/
uint32_t proc_done_int_raw:1;
/** post_done_int_raw : RO/WTC/SS; bitpos: [2]; default: 0;
* The raw interrupt status bit for the km_post_done_int interrupt
*/
uint32_t post_done_int_raw:1;
uint32_t reserved_3:29;
};
uint32_t val;
} keymng_int_raw_reg_t;
/** Type of int_st register
* Key Manager interrupt status register.
*/
typedef union {
struct {
/** prep_done_int_st : RO; bitpos: [0]; default: 0;
* The masked interrupt status bit for the km_prep_done_int interrupt
*/
uint32_t prep_done_int_st:1;
/** proc_done_int_st : RO; bitpos: [1]; default: 0;
* The masked interrupt status bit for the km_proc_done_int interrupt
*/
uint32_t proc_done_int_st:1;
/** post_done_int_st : RO; bitpos: [2]; default: 0;
* The masked interrupt status bit for the km_post_done_int interrupt
*/
uint32_t post_done_int_st:1;
uint32_t reserved_3:29;
};
uint32_t val;
} keymng_int_st_reg_t;
/** Type of int_ena register
* Key Manager interrupt enable register.
*/
typedef union {
struct {
/** prep_done_int_ena : R/W; bitpos: [0]; default: 0;
* The interrupt enable bit for the km_prep_done_int interrupt
*/
uint32_t prep_done_int_ena:1;
/** proc_done_int_ena : R/W; bitpos: [1]; default: 0;
* The interrupt enable bit for the km_proc_done_int interrupt
*/
uint32_t proc_done_int_ena:1;
/** post_done_int_ena : R/W; bitpos: [2]; default: 0;
* The interrupt enable bit for the km_post_done_int interrupt
*/
uint32_t post_done_int_ena:1;
uint32_t reserved_3:29;
};
uint32_t val;
} keymng_int_ena_reg_t;
/** Type of int_clr register
* Key Manager interrupt clear register.
*/
typedef union {
struct {
/** prep_done_int_clr : WT; bitpos: [0]; default: 0;
* Set this bit to clear the km_prep_done_int interrupt
*/
uint32_t prep_done_int_clr:1;
/** proc_done_int_clr : WT; bitpos: [1]; default: 0;
* Set this bit to clear the km_proc_done_int interrupt
*/
uint32_t proc_done_int_clr:1;
/** post_done_int_clr : WT; bitpos: [2]; default: 0;
* Set this bit to clear the km_post_done_int interrupt
*/
uint32_t post_done_int_clr:1;
uint32_t reserved_3:29;
};
uint32_t val;
} keymng_int_clr_reg_t;
/** Group: Static configuration registers */
/** Type of static register
* Key Manager static configuration register
*/
typedef union {
struct {
/** use_efuse_key : R/W; bitpos: [1:0]; default: 0;
* Set each bit to choose efuse key instead of key manager deployed key. Each bit
* stands for a key type: bit 1 for xts_key; bit 0 for ecdsa_key
*/
uint32_t use_efuse_key:2;
uint32_t reserved_2:2;
/** rnd_switch_cycle : R/W; bitpos: [8:4]; default: 15;
* The core clock cycle number to sample one rng input data. Please set it bigger than
* the clock cycle ratio: T_rng/T_km
*/
uint32_t rnd_switch_cycle:5;
/** use_sw_init_key : R/W; bitpos: [9]; default: 0;
* Set this bit to use software written init key instead of efuse_init_key.
*/
uint32_t use_sw_init_key:1;
/** xts_aes_key_len : R/W; bitpos: [10]; default: 0;
* Set this bit to choose using xts-aes-256 or xts-aes-128. 1: use xts-aes-256. 0: use
* xts-aes-128.
*/
uint32_t xts_aes_key_len:1;
uint32_t reserved_11:21;
};
uint32_t val;
} keymng_static_reg_t;
/** Type of lock register
* Key Manager static configuration locker register
*/
typedef union {
struct {
/** use_efuse_key_lock : R/W1; bitpos: [1:0]; default: 0;
* Write 1 to lock reg_use_efuse_key. Each bit locks the corresponding bit of
* reg_use_efuse_key.
*/
uint32_t use_efuse_key_lock:2;
uint32_t reserved_2:2;
/** rnd_switch_cycle_lock : R/W1; bitpos: [4]; default: 0;
* Write 1 to lock reg_rnd_switch_cycle.
*/
uint32_t rnd_switch_cycle_lock:1;
/** use_sw_init_key_lock : R/W1; bitpos: [5]; default: 0;
* Write 1 to lock reg_use_sw_init_key.
*/
uint32_t use_sw_init_key_lock:1;
/** xts_aes_key_len_lock : R/W1; bitpos: [6]; default: 0;
* Write 1 to lock reg_xts_aes_key_len.
*/
uint32_t xts_aes_key_len_lock:1;
uint32_t reserved_7:25;
};
uint32_t val;
} keymng_lock_reg_t;
/** Group: Configuration registers */
/** Type of conf register
* Key Manager configuration register
*/
typedef union {
struct {
/** kgen_mode : R/W; bitpos: [2:0]; default: 0;
* Set this field to choose the key generator deployment mode. 0: random mode. 1: AES
* mode. 2: ECDH0 mode. 3: ECDH1 mode. 4: recover mode. 5: export mode. 6-7: reserved.
*/
uint32_t kgen_mode:3;
/** key_purpose : R/W; bitpos: [6:3]; default: 0;
* Set this field to choose the key purpose. 1: ecdsa_key 2: xts_256_1_key. 3:
* xts_256_2_key. 4. xts_128_key. others: reserved.
*/
uint32_t key_purpose:4;
uint32_t reserved_7:25;
};
uint32_t val;
} keymng_conf_reg_t;
/** Group: Control registers */
/** Type of start register
* Key Manager control register
*/
typedef union {
struct {
/** start : WT; bitpos: [0]; default: 0;
* Write 1 to continue Key Manager operation at LOAD/GAIN state.
*/
uint32_t start:1;
/** continue : WT; bitpos: [1]; default: 0;
* Write 1 to start Key Manager at IDLE state.
*/
uint32_t conti:1;
uint32_t reserved_2:30;
};
uint32_t val;
} keymng_start_reg_t;
/** Group: State registers */
/** Type of state register
* Key Manager state register
*/
typedef union {
struct {
/** state : RO; bitpos: [1:0]; default: 0;
* The state of Key Manager. 0: IDLE. 1: LOAD. 2: GAIN. 3: BUSY.
*/
uint32_t state:2;
uint32_t reserved_2:30;
};
uint32_t val;
} keymng_state_reg_t;
/** Group: Result registers */
/** Type of result register
* Key Manager operation result register
*/
typedef union {
struct {
/** proc_result : RO/SS; bitpos: [0]; default: 0;
* The procedure result bit of Key Manager, only valid when Key Manager procedure is
* done. 1: Key Manager procedure succeeded. 0: Key Manager procedure failed.
*/
uint32_t proc_result:1;
uint32_t reserved_1:31;
};
uint32_t val;
} keymng_result_reg_t;
/** Type of key_vld register
* Key Manager key status register
*/
typedef union {
struct {
/** key_ecdsa_vld : RO; bitpos: [0]; default: 0;
* The status bit for key_ecdsa. 1: The key has been deployed correctly. 0: The key
* has not been deployed yet.
*/
uint32_t key_ecdsa_vld:1;
/** key_xts_vld : RO; bitpos: [1]; default: 0;
* The status bit for key_xts. 1: The key has been deployed correctly. 0: The
* key has not been deployed yet.
*/
uint32_t key_xts_vld:1;
uint32_t reserved_2:30;
};
uint32_t val;
} keymng_key_vld_reg_t;
/** Type of huk_vld register
* Key Manager HUK status register
*/
typedef union {
struct {
/** huk_valid : RO; bitpos: [0]; default: 0;
* The HUK status. 0: HUK is not valid. 1: HUK is valid.
*/
uint32_t huk_valid:1;
uint32_t reserved_1:31;
};
uint32_t val;
} keymng_huk_vld_reg_t;
/** Group: Version register */
/** Type of date register
* Version control register
*/
typedef union {
struct {
/** date : R/W; bitpos: [27:0]; default: 36720704;
* Key Manager version control register.
*/
uint32_t date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} keymng_date_reg_t;
typedef struct {
uint32_t reserved_000;
volatile keymng_clk_reg_t clk;
volatile keymng_int_raw_reg_t int_raw;
volatile keymng_int_st_reg_t int_st;
volatile keymng_int_ena_reg_t int_ena;
volatile keymng_int_clr_reg_t int_clr;
volatile keymng_static_reg_t static_conf;
volatile keymng_lock_reg_t lock;
volatile keymng_conf_reg_t conf;
volatile keymng_start_reg_t start;
volatile keymng_state_reg_t state;
volatile keymng_result_reg_t result;
volatile keymng_key_vld_reg_t key_vld;
volatile keymng_huk_vld_reg_t huk_vld;
uint32_t reserved_038[49];
volatile keymng_date_reg_t date;
volatile uint32_t assist_info[16];
volatile uint32_t public_info[16];
volatile uint32_t sw_init_key[8];
} keymng_dev_t;
#ifndef __cplusplus
_Static_assert(sizeof(keymng_dev_t) == 0x1a0, "Invalid size of keymng_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** MEM_MONITOR_LOG_SETTING_REG register
* log config register
*/
#define MEM_MONITOR_LOG_SETTING_REG (DR_REG_MEM_MONITOR_BASE + 0x0)
/** MEM_MONITOR_LOG_MODE : R/W; bitpos: [3:0]; default: 0;
* Bit[0] : WR monitor, BIT[1]: WORD monitor, BIT[2]: HALFWORD monitor, BIT[3]: BYTE
* monitor
*/
#define MEM_MONITOR_LOG_MODE 0x0000000FU
#define MEM_MONITOR_LOG_MODE_M (MEM_MONITOR_LOG_MODE_V << MEM_MONITOR_LOG_MODE_S)
#define MEM_MONITOR_LOG_MODE_V 0x0000000FU
#define MEM_MONITOR_LOG_MODE_S 0
/** MEM_MONITOR_LOG_MEM_LOOP_ENABLE : R/W; bitpos: [4]; default: 1;
* Set 1 enable mem_loop, it will loop write at the range of MEM_START and MEM_END
*/
#define MEM_MONITOR_LOG_MEM_LOOP_ENABLE (BIT(4))
#define MEM_MONITOR_LOG_MEM_LOOP_ENABLE_M (MEM_MONITOR_LOG_MEM_LOOP_ENABLE_V << MEM_MONITOR_LOG_MEM_LOOP_ENABLE_S)
#define MEM_MONITOR_LOG_MEM_LOOP_ENABLE_V 0x00000001U
#define MEM_MONITOR_LOG_MEM_LOOP_ENABLE_S 4
/** MEM_MONITOR_LOG_CORE_ENA : R/W; bitpos: [15:8]; default: 0;
* enable core log
*/
#define MEM_MONITOR_LOG_CORE_ENA 0x000000FFU
#define MEM_MONITOR_LOG_CORE_ENA_M (MEM_MONITOR_LOG_CORE_ENA_V << MEM_MONITOR_LOG_CORE_ENA_S)
#define MEM_MONITOR_LOG_CORE_ENA_V 0x000000FFU
#define MEM_MONITOR_LOG_CORE_ENA_S 8
/** MEM_MONITOR_LOG_DMA_0_ENA : R/W; bitpos: [23:16]; default: 0;
* enable dma_0 log
*/
#define MEM_MONITOR_LOG_DMA_0_ENA 0x000000FFU
#define MEM_MONITOR_LOG_DMA_0_ENA_M (MEM_MONITOR_LOG_DMA_0_ENA_V << MEM_MONITOR_LOG_DMA_0_ENA_S)
#define MEM_MONITOR_LOG_DMA_0_ENA_V 0x000000FFU
#define MEM_MONITOR_LOG_DMA_0_ENA_S 16
/** MEM_MONITOR_LOG_DMA_1_ENA : R/W; bitpos: [31:24]; default: 0;
* enable dma_1 log
*/
#define MEM_MONITOR_LOG_DMA_1_ENA 0x000000FFU
#define MEM_MONITOR_LOG_DMA_1_ENA_M (MEM_MONITOR_LOG_DMA_1_ENA_V << MEM_MONITOR_LOG_DMA_1_ENA_S)
#define MEM_MONITOR_LOG_DMA_1_ENA_V 0x000000FFU
#define MEM_MONITOR_LOG_DMA_1_ENA_S 24
/** MEM_MONITOR_LOG_SETTING1_REG register
* log config register
*/
#define MEM_MONITOR_LOG_SETTING1_REG (DR_REG_MEM_MONITOR_BASE + 0x4)
/** MEM_MONITOR_LOG_DMA_2_ENA : R/W; bitpos: [7:0]; default: 0;
* enable dma_2 log
*/
#define MEM_MONITOR_LOG_DMA_2_ENA 0x000000FFU
#define MEM_MONITOR_LOG_DMA_2_ENA_M (MEM_MONITOR_LOG_DMA_2_ENA_V << MEM_MONITOR_LOG_DMA_2_ENA_S)
#define MEM_MONITOR_LOG_DMA_2_ENA_V 0x000000FFU
#define MEM_MONITOR_LOG_DMA_2_ENA_S 0
/** MEM_MONITOR_LOG_DMA_3_ENA : R/W; bitpos: [15:8]; default: 0;
* enable dma_3 log
*/
#define MEM_MONITOR_LOG_DMA_3_ENA 0x000000FFU
#define MEM_MONITOR_LOG_DMA_3_ENA_M (MEM_MONITOR_LOG_DMA_3_ENA_V << MEM_MONITOR_LOG_DMA_3_ENA_S)
#define MEM_MONITOR_LOG_DMA_3_ENA_V 0x000000FFU
#define MEM_MONITOR_LOG_DMA_3_ENA_S 8
/** MEM_MONITOR_LOG_CHECK_DATA_REG register
* check data register
*/
#define MEM_MONITOR_LOG_CHECK_DATA_REG (DR_REG_MEM_MONITOR_BASE + 0x8)
/** MEM_MONITOR_LOG_CHECK_DATA : R/W; bitpos: [31:0]; default: 0;
* The special check data, when write this special data, it will trigger logging.
*/
#define MEM_MONITOR_LOG_CHECK_DATA 0xFFFFFFFFU
#define MEM_MONITOR_LOG_CHECK_DATA_M (MEM_MONITOR_LOG_CHECK_DATA_V << MEM_MONITOR_LOG_CHECK_DATA_S)
#define MEM_MONITOR_LOG_CHECK_DATA_V 0xFFFFFFFFU
#define MEM_MONITOR_LOG_CHECK_DATA_S 0
/** MEM_MONITOR_LOG_DATA_MASK_REG register
* check data mask register
*/
#define MEM_MONITOR_LOG_DATA_MASK_REG (DR_REG_MEM_MONITOR_BASE + 0xc)
/** MEM_MONITOR_LOG_DATA_MASK : R/W; bitpos: [3:0]; default: 0;
* byte mask enable, BIT0 mask the first byte of MEM_MONITOR_LOG_CHECK_DATA, and BIT1
* mask second byte, and so on.
*/
#define MEM_MONITOR_LOG_DATA_MASK 0x0000000FU
#define MEM_MONITOR_LOG_DATA_MASK_M (MEM_MONITOR_LOG_DATA_MASK_V << MEM_MONITOR_LOG_DATA_MASK_S)
#define MEM_MONITOR_LOG_DATA_MASK_V 0x0000000FU
#define MEM_MONITOR_LOG_DATA_MASK_S 0
/** MEM_MONITOR_LOG_MIN_REG register
* log boundary register
*/
#define MEM_MONITOR_LOG_MIN_REG (DR_REG_MEM_MONITOR_BASE + 0x10)
/** MEM_MONITOR_LOG_MIN : R/W; bitpos: [31:0]; default: 0;
* the min address of log range
*/
#define MEM_MONITOR_LOG_MIN 0xFFFFFFFFU
#define MEM_MONITOR_LOG_MIN_M (MEM_MONITOR_LOG_MIN_V << MEM_MONITOR_LOG_MIN_S)
#define MEM_MONITOR_LOG_MIN_V 0xFFFFFFFFU
#define MEM_MONITOR_LOG_MIN_S 0
/** MEM_MONITOR_LOG_MAX_REG register
* log boundary register
*/
#define MEM_MONITOR_LOG_MAX_REG (DR_REG_MEM_MONITOR_BASE + 0x14)
/** MEM_MONITOR_LOG_MAX : R/W; bitpos: [31:0]; default: 0;
* the max address of log range
*/
#define MEM_MONITOR_LOG_MAX 0xFFFFFFFFU
#define MEM_MONITOR_LOG_MAX_M (MEM_MONITOR_LOG_MAX_V << MEM_MONITOR_LOG_MAX_S)
#define MEM_MONITOR_LOG_MAX_V 0xFFFFFFFFU
#define MEM_MONITOR_LOG_MAX_S 0
/** MEM_MONITOR_LOG_MEM_START_REG register
* log message store range register
*/
#define MEM_MONITOR_LOG_MEM_START_REG (DR_REG_MEM_MONITOR_BASE + 0x18)
/** MEM_MONITOR_LOG_MEM_START : R/W; bitpos: [31:0]; default: 0;
* the start address of writing logging message
*/
#define MEM_MONITOR_LOG_MEM_START 0xFFFFFFFFU
#define MEM_MONITOR_LOG_MEM_START_M (MEM_MONITOR_LOG_MEM_START_V << MEM_MONITOR_LOG_MEM_START_S)
#define MEM_MONITOR_LOG_MEM_START_V 0xFFFFFFFFU
#define MEM_MONITOR_LOG_MEM_START_S 0
/** MEM_MONITOR_LOG_MEM_END_REG register
* log message store range register
*/
#define MEM_MONITOR_LOG_MEM_END_REG (DR_REG_MEM_MONITOR_BASE + 0x1c)
/** MEM_MONITOR_LOG_MEM_END : R/W; bitpos: [31:0]; default: 0;
* the end address of writing logging message
*/
#define MEM_MONITOR_LOG_MEM_END 0xFFFFFFFFU
#define MEM_MONITOR_LOG_MEM_END_M (MEM_MONITOR_LOG_MEM_END_V << MEM_MONITOR_LOG_MEM_END_S)
#define MEM_MONITOR_LOG_MEM_END_V 0xFFFFFFFFU
#define MEM_MONITOR_LOG_MEM_END_S 0
/** MEM_MONITOR_LOG_MEM_CURRENT_ADDR_REG register
* current writing address.
*/
#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR_REG (DR_REG_MEM_MONITOR_BASE + 0x20)
/** MEM_MONITOR_LOG_MEM_CURRENT_ADDR : RO; bitpos: [31:0]; default: 0;
* means next writing address
*/
#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR 0xFFFFFFFFU
#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR_M (MEM_MONITOR_LOG_MEM_CURRENT_ADDR_V << MEM_MONITOR_LOG_MEM_CURRENT_ADDR_S)
#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR_V 0xFFFFFFFFU
#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR_S 0
/** MEM_MONITOR_LOG_MEM_ADDR_UPDATE_REG register
* writing address update
*/
#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_REG (DR_REG_MEM_MONITOR_BASE + 0x24)
/** MEM_MONITOR_LOG_MEM_ADDR_UPDATE : WT; bitpos: [0]; default: 0;
* Set 1 to updata MEM_MONITOR_LOG_MEM_CURRENT_ADDR, when set 1,
* MEM_MONITOR_LOG_MEM_CURRENT_ADDR will update to MEM_MONITOR_LOG_MEM_START
*/
#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE (BIT(0))
#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_M (MEM_MONITOR_LOG_MEM_ADDR_UPDATE_V << MEM_MONITOR_LOG_MEM_ADDR_UPDATE_S)
#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_V 0x00000001U
#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_S 0
/** MEM_MONITOR_LOG_MEM_FULL_FLAG_REG register
* full flag status register
*/
#define MEM_MONITOR_LOG_MEM_FULL_FLAG_REG (DR_REG_MEM_MONITOR_BASE + 0x28)
/** MEM_MONITOR_LOG_MEM_FULL_FLAG : RO; bitpos: [0]; default: 0;
* 1 means memory write loop at least one time at the range of MEM_START and MEM_END
*/
#define MEM_MONITOR_LOG_MEM_FULL_FLAG (BIT(0))
#define MEM_MONITOR_LOG_MEM_FULL_FLAG_M (MEM_MONITOR_LOG_MEM_FULL_FLAG_V << MEM_MONITOR_LOG_MEM_FULL_FLAG_S)
#define MEM_MONITOR_LOG_MEM_FULL_FLAG_V 0x00000001U
#define MEM_MONITOR_LOG_MEM_FULL_FLAG_S 0
/** MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG : WT; bitpos: [1]; default: 0;
* Set 1 to clr MEM_MONITOR_LOG_MEM_FULL_FLAG
*/
#define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG (BIT(1))
#define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_M (MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_V << MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_S)
#define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_V 0x00000001U
#define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_S 1
/** MEM_MONITOR_CLOCK_GATE_REG register
* clock gate force on register
*/
#define MEM_MONITOR_CLOCK_GATE_REG (DR_REG_MEM_MONITOR_BASE + 0x2c)
/** MEM_MONITOR_CLK_EN : R/W; bitpos: [0]; default: 0;
* Set 1 to force on the clk of mem_monitor register
*/
#define MEM_MONITOR_CLK_EN (BIT(0))
#define MEM_MONITOR_CLK_EN_M (MEM_MONITOR_CLK_EN_V << MEM_MONITOR_CLK_EN_S)
#define MEM_MONITOR_CLK_EN_V 0x00000001U
#define MEM_MONITOR_CLK_EN_S 0
/** MEM_MONITOR_DATE_REG register
* version register
*/
#define MEM_MONITOR_DATE_REG (DR_REG_MEM_MONITOR_BASE + 0x3fc)
/** MEM_MONITOR_DATE : R/W; bitpos: [27:0]; default: 36708896;
* version register
*/
#define MEM_MONITOR_DATE 0x0FFFFFFFU
#define MEM_MONITOR_DATE_M (MEM_MONITOR_DATE_V << MEM_MONITOR_DATE_S)
#define MEM_MONITOR_DATE_V 0x0FFFFFFFU
#define MEM_MONITOR_DATE_S 0
#ifdef __cplusplus
}
#endif

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components/soc/esp32p4/include/soc/l2mem_monitor_struct.h Normal file
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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: configuration registers */
/** Type of log_setting register
* log config regsiter
*/
typedef union {
struct {
/** log_mode : R/W; bitpos: [3:0]; default: 0;
* Bit[0] : WR monitor, BIT[1]: WORD monitor, BIT[2]: HALFWORD monitor, BIT[3]: BYTE
* monitor
*/
uint32_t log_mode:4;
/** log_mem_loop_enable : R/W; bitpos: [4]; default: 1;
* Set 1 enable mem_loop, it will loop write at the range of MEM_START and MEM_END
*/
uint32_t log_mem_loop_enable:1;
uint32_t reserved_5:3;
/** log_core_ena : R/W; bitpos: [15:8]; default: 0;
* enable core log
*/
uint32_t log_core_ena:8;
/** log_dma_0_ena : R/W; bitpos: [23:16]; default: 0;
* enable dma_0 log
*/
uint32_t log_dma_0_ena:8;
/** log_dma_1_ena : R/W; bitpos: [31:24]; default: 0;
* enable dma_1 log
*/
uint32_t log_dma_1_ena:8;
};
uint32_t val;
} mem_monitor_log_setting_reg_t;
/** Type of log_setting1 register
* log config regsiter
*/
typedef union {
struct {
/** log_dma_2_ena : R/W; bitpos: [7:0]; default: 0;
* enable dma_2 log
*/
uint32_t log_dma_2_ena:8;
/** log_dma_3_ena : R/W; bitpos: [15:8]; default: 0;
* enable dma_3 log
*/
uint32_t log_dma_3_ena:8;
uint32_t reserved_16:16;
};
uint32_t val;
} mem_monitor_log_setting1_reg_t;
/** Type of log_check_data register
* check data regsiter
*/
typedef union {
struct {
/** log_check_data : R/W; bitpos: [31:0]; default: 0;
* The special check data, when write this special data, it will trigger logging.
*/
uint32_t log_check_data:32;
};
uint32_t val;
} mem_monitor_log_check_data_reg_t;
/** Type of log_data_mask register
* check data mask register
*/
typedef union {
struct {
/** log_data_mask : R/W; bitpos: [3:0]; default: 0;
* byte mask enable, BIT0 mask the first byte of MEM_MONITOR_LOG_CHECK_DATA, and BIT1
* mask second byte, and so on.
*/
uint32_t log_data_mask:4;
uint32_t reserved_4:28;
};
uint32_t val;
} mem_monitor_log_data_mask_reg_t;
/** Type of log_min register
* log boundary regsiter
*/
typedef union {
struct {
/** log_min : R/W; bitpos: [31:0]; default: 0;
* the min address of log range
*/
uint32_t log_min:32;
};
uint32_t val;
} mem_monitor_log_min_reg_t;
/** Type of log_max register
* log boundary regsiter
*/
typedef union {
struct {
/** log_max : R/W; bitpos: [31:0]; default: 0;
* the max address of log range
*/
uint32_t log_max:32;
};
uint32_t val;
} mem_monitor_log_max_reg_t;
/** Type of log_mem_start register
* log message store range register
*/
typedef union {
struct {
/** log_mem_start : R/W; bitpos: [31:0]; default: 0;
* the start address of writing logging message
*/
uint32_t log_mem_start:32;
};
uint32_t val;
} mem_monitor_log_mem_start_reg_t;
/** Type of log_mem_end register
* log message store range register
*/
typedef union {
struct {
/** log_mem_end : R/W; bitpos: [31:0]; default: 0;
* the end address of writing logging message
*/
uint32_t log_mem_end:32;
};
uint32_t val;
} mem_monitor_log_mem_end_reg_t;
/** Type of log_mem_current_addr register
* current writing address.
*/
typedef union {
struct {
/** log_mem_current_addr : RO; bitpos: [31:0]; default: 0;
* means next writing address
*/
uint32_t log_mem_current_addr:32;
};
uint32_t val;
} mem_monitor_log_mem_current_addr_reg_t;
/** Type of log_mem_addr_update register
* writing address update
*/
typedef union {
struct {
/** log_mem_addr_update : WT; bitpos: [0]; default: 0;
* Set 1 to updata MEM_MONITOR_LOG_MEM_CURRENT_ADDR, when set 1,
* MEM_MONITOR_LOG_MEM_CURRENT_ADDR will update to MEM_MONITOR_LOG_MEM_START
*/
uint32_t log_mem_addr_update:1;
uint32_t reserved_1:31;
};
uint32_t val;
} mem_monitor_log_mem_addr_update_reg_t;
/** Type of log_mem_full_flag register
* full flag status register
*/
typedef union {
struct {
/** log_mem_full_flag : RO; bitpos: [0]; default: 0;
* 1 means memory write loop at least one time at the range of MEM_START and MEM_END
*/
uint32_t log_mem_full_flag:1;
/** clr_log_mem_full_flag : WT; bitpos: [1]; default: 0;
* Set 1 to clr MEM_MONITOR_LOG_MEM_FULL_FLAG
*/
uint32_t clr_log_mem_full_flag:1;
uint32_t reserved_2:30;
};
uint32_t val;
} mem_monitor_log_mem_full_flag_reg_t;
/** Group: clk register */
/** Type of clock_gate register
* clock gate force on register
*/
typedef union {
struct {
/** clk_en : R/W; bitpos: [0]; default: 0;
* Set 1 to force on the clk of mem_monitor register
*/
uint32_t clk_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} mem_monitor_clock_gate_reg_t;
/** Group: version register */
/** Type of date register
* version register
*/
typedef union {
struct {
/** date : R/W; bitpos: [27:0]; default: 36708896;
* version register
*/
uint32_t date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} mem_monitor_date_reg_t;
typedef struct {
volatile mem_monitor_log_setting_reg_t log_setting;
volatile mem_monitor_log_setting1_reg_t log_setting1;
volatile mem_monitor_log_check_data_reg_t log_check_data;
volatile mem_monitor_log_data_mask_reg_t log_data_mask;
volatile mem_monitor_log_min_reg_t log_min;
volatile mem_monitor_log_max_reg_t log_max;
volatile mem_monitor_log_mem_start_reg_t log_mem_start;
volatile mem_monitor_log_mem_end_reg_t log_mem_end;
volatile mem_monitor_log_mem_current_addr_reg_t log_mem_current_addr;
volatile mem_monitor_log_mem_addr_update_reg_t log_mem_addr_update;
volatile mem_monitor_log_mem_full_flag_reg_t log_mem_full_flag;
volatile mem_monitor_clock_gate_reg_t clock_gate;
uint32_t reserved_030[243];
volatile mem_monitor_date_reg_t date;
} mem_monitor_dev_t;
#ifndef __cplusplus
_Static_assert(sizeof(mem_monitor_dev_t) == 0x400, "Invalid size of mem_monitor_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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components/soc/esp32p4/include/soc/lcdcam_reg.h Normal file
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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: lcd configuration registers */
/** Type of lcd_clock register
* LCD clock config register.
*/
typedef union {
struct {
/** lcd_clkcnt_n : R/W; bitpos: [5:0]; default: 3;
* f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1) when reg_clk_equ_sysclk is 0.
*/
uint32_t lcd_clkcnt_n:6;
/** lcd_clk_equ_sysclk : R/W; bitpos: [6]; default: 1;
* 1: f_LCD_PCLK = f_LCD_CLK. 0: f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1).
*/
uint32_t lcd_clk_equ_sysclk:1;
/** lcd_ck_idle_edge : R/W; bitpos: [7]; default: 0;
* 1: LCD_PCLK line is high when idle 0: LCD_PCLK line is low when idle.
*/
uint32_t lcd_ck_idle_edge:1;
/** lcd_ck_out_edge : R/W; bitpos: [8]; default: 0;
* 1: LCD_PCLK line is high in the first half data cycle. 0: LCD_PCLK line is low
* in the second half data cycle.
*/
uint32_t lcd_ck_out_edge:1;
/** lcd_clkm_div_num : R/W; bitpos: [16:9]; default: 4;
* Integral LCD clock divider value
*/
uint32_t lcd_clkm_div_num:8;
/** lcd_clkm_div_b : R/W; bitpos: [22:17]; default: 0;
* Fractional clock divider numerator value
*/
uint32_t lcd_clkm_div_b:6;
/** lcd_clkm_div_a : R/W; bitpos: [28:23]; default: 0;
* Fractional clock divider denominator value
*/
uint32_t lcd_clkm_div_a:6;
/** lcd_clk_sel : R/W; bitpos: [30:29]; default: 0;
* Select LCD module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock.
*/
uint32_t lcd_clk_sel:2;
/** clk_en : R/W; bitpos: [31]; default: 0;
* Set this bit to enable clk gate
*/
uint32_t clk_en:1;
};
uint32_t val;
} lcdcam_lcd_clock_reg_t;
/** Type of lcd_rgb_yuv register
* LCD YUV/RGB converter configuration register.
*/
typedef union {
struct {
uint32_t reserved_0:20;
/** lcd_conv_8bits_data_inv : R/W; bitpos: [20]; default: 0;
* 1:invert every two 8bits input data. 2. disabled.
*/
uint32_t lcd_conv_8bits_data_inv:1;
/** lcd_conv_txtorx : R/W; bitpos: [21]; default: 0;
* 0: txtorx mode off. 1: txtorx mode on.
*/
uint32_t lcd_conv_txtorx:1;
/** lcd_conv_yuv2yuv_mode : R/W; bitpos: [23:22]; default: 3;
* 0: to yuv422. 1: to yuv420. 2: to yuv411. 3: disabled. To enable yuv2yuv mode,
* trans_mode must be set to 1.
*/
uint32_t lcd_conv_yuv2yuv_mode:2;
/** lcd_conv_yuv_mode : R/W; bitpos: [25:24]; default: 0;
* 0: yuv422. 1: yuv420. 2: yuv411. When in yuv2yuv mode, yuv_mode decides the yuv
* mode of Data_in
*/
uint32_t lcd_conv_yuv_mode:2;
/** lcd_conv_protocol_mode : R/W; bitpos: [26]; default: 0;
* 0:BT601. 1:BT709.
*/
uint32_t lcd_conv_protocol_mode:1;
/** lcd_conv_data_out_mode : R/W; bitpos: [27]; default: 0;
* LIMIT or FULL mode of Data out. 0: limit. 1: full
*/
uint32_t lcd_conv_data_out_mode:1;
/** lcd_conv_data_in_mode : R/W; bitpos: [28]; default: 0;
* LIMIT or FULL mode of Data in. 0: limit. 1: full
*/
uint32_t lcd_conv_data_in_mode:1;
/** lcd_conv_mode_8bits_on : R/W; bitpos: [29]; default: 0;
* 0: 16bits mode. 1: 8bits mode.
*/
uint32_t lcd_conv_mode_8bits_on:1;
/** lcd_conv_trans_mode : R/W; bitpos: [30]; default: 0;
* 0: YUV to RGB. 1: RGB to YUV.
*/
uint32_t lcd_conv_trans_mode:1;
/** lcd_conv_enable : R/W; bitpos: [31]; default: 0;
* 0: Bypass converter. 1: Enable converter.
*/
uint32_t lcd_conv_enable:1;
};
uint32_t val;
} lcdcam_lcd_rgb_yuv_reg_t;
/** Type of lcd_user register
* LCD config register.
*/
typedef union {
struct {
/** lcd_dout_cyclelen : R/W; bitpos: [12:0]; default: 1;
* The output data cycles minus 1 of LCD module.
*/
uint32_t lcd_dout_cyclelen:13;
/** lcd_always_out_en : R/W; bitpos: [13]; default: 0;
* LCD always output when LCD is in LCD_DOUT state, unless reg_lcd_start is cleared or
* reg_lcd_reset is set.
*/
uint32_t lcd_always_out_en:1;
/** lcd_dout_byte_swizzle_mode : R/W; bitpos: [16:14]; default: 0;
* 0: ABAB->BABA. 1: ABC->ACB. 2: ABC->BAC. 3: ABC->BCA. 4:ABC->CAB. 5:ABC->CBA
*/
uint32_t lcd_dout_byte_swizzle_mode:3;
/** lcd_dout_byte_swizzle_enable : R/W; bitpos: [17]; default: 0;
* 1: enable byte swizzle 0: disable
*/
uint32_t lcd_dout_byte_swizzle_enable:1;
/** lcd_dout_bit_order : R/W; bitpos: [18]; default: 0;
* 1: change bit order in every byte. 0: Not change.
*/
uint32_t lcd_dout_bit_order:1;
/** lcd_byte_mode : R/W; bitpos: [20:19]; default: 0;
* 2: 24bit mode. 1: 16bit mode. 0: 8bit mode
*/
uint32_t lcd_byte_mode:2;
/** lcd_update_reg : R/W/SC; bitpos: [21]; default: 0;
* 1: Update LCD registers, will be cleared by hardware. 0 : Not care.
*/
uint32_t lcd_update_reg:1;
/** lcd_bit_order : R/W; bitpos: [22]; default: 0;
* 1: Change data bit order, change LCD_DATA_out[7:0] to LCD_DATA_out[0:7] in one byte
* mode, and bits[15:0] to bits[0:15] in two byte mode. 0: Not change.
*/
uint32_t lcd_bit_order:1;
/** lcd_byte_order : R/W; bitpos: [23]; default: 0;
* 1: invert data byte order, only valid in 2 byte mode. 0: Not change.
*/
uint32_t lcd_byte_order:1;
/** lcd_dout : R/W; bitpos: [24]; default: 0;
* 1: Be able to send data out in LCD sequence when LCD starts. 0: Disable.
*/
uint32_t lcd_dout:1;
/** lcd_dummy : R/W; bitpos: [25]; default: 0;
* 1: Enable DUMMY phase in LCD sequence when LCD starts. 0: Disable.
*/
uint32_t lcd_dummy:1;
/** lcd_cmd : R/W; bitpos: [26]; default: 0;
* 1: Be able to send command in LCD sequence when LCD starts. 0: Disable.
*/
uint32_t lcd_cmd:1;
/** lcd_start : R/W/SC; bitpos: [27]; default: 0;
* LCD start sending data enable signal, valid in high level.
*/
uint32_t lcd_start:1;
/** lcd_reset : WT; bitpos: [28]; default: 0;
* The value of command.
*/
uint32_t lcd_reset:1;
/** lcd_dummy_cyclelen : R/W; bitpos: [30:29]; default: 0;
* The dummy cycle length minus 1.
*/
uint32_t lcd_dummy_cyclelen:2;
/** lcd_cmd_2_cycle_en : R/W; bitpos: [31]; default: 0;
* The cycle length of command phase. 1: 2 cycles. 0: 1 cycle.
*/
uint32_t lcd_cmd_2_cycle_en:1;
};
uint32_t val;
} lcdcam_lcd_user_reg_t;
/** Type of lcd_misc register
* LCD config register.
*/
typedef union {
struct {
uint32_t reserved_0:4;
/** lcd_wire_mode : R/W; bitpos: [5:4]; default: 0;
* The wire width of LCD output. 0: 8bit. 1: 16bit 2: 24bit
*/
uint32_t lcd_wire_mode:2;
/** lcd_vfk_cyclelen : R/W; bitpos: [11:6]; default: 3;
* The setup cycle length minus 1 in LCD non-RGB mode.
*/
uint32_t lcd_vfk_cyclelen:6;
/** lcd_vbk_cyclelen : R/W; bitpos: [24:12]; default: 0;
* The vertical back blank region cycle length minus 1 in LCD RGB mode, or the hold
* time cycle length in LCD non-RGB mode.
*/
uint32_t lcd_vbk_cyclelen:13;
/** lcd_next_frame_en : R/W; bitpos: [25]; default: 0;
* 1: Send the next frame data when the current frame is sent out. 0: LCD stops when
* the current frame is sent out.
*/
uint32_t lcd_next_frame_en:1;
/** lcd_bk_en : R/W; bitpos: [26]; default: 0;
* 1: Enable blank region when LCD sends data out. 0: No blank region.
*/
uint32_t lcd_bk_en:1;
/** lcd_afifo_reset : WT; bitpos: [27]; default: 0;
* LCD AFIFO reset signal.
*/
uint32_t lcd_afifo_reset:1;
/** lcd_cd_data_set : R/W; bitpos: [28]; default: 0;
* 1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_DOUT state. 0: LCD_CD =
* reg_cd_idle_edge.
*/
uint32_t lcd_cd_data_set:1;
/** lcd_cd_dummy_set : R/W; bitpos: [29]; default: 0;
* 1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_DUMMY state. 0: LCD_CD =
* reg_cd_idle_edge.
*/
uint32_t lcd_cd_dummy_set:1;
/** lcd_cd_cmd_set : R/W; bitpos: [30]; default: 0;
* 1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_CMD state. 0: LCD_CD =
* reg_cd_idle_edge.
*/
uint32_t lcd_cd_cmd_set:1;
/** lcd_cd_idle_edge : R/W; bitpos: [31]; default: 0;
* The default value of LCD_CD.
*/
uint32_t lcd_cd_idle_edge:1;
};
uint32_t val;
} lcdcam_lcd_misc_reg_t;
/** Type of lcd_ctrl register
* LCD config register.
*/
typedef union {
struct {
/** lcd_hb_front : R/W; bitpos: [10:0]; default: 0;
* It is the horizontal blank front porch of a frame.
*/
uint32_t lcd_hb_front:11;
/** lcd_va_height : R/W; bitpos: [20:11]; default: 0;
* It is the vertical active height of a frame.
*/
uint32_t lcd_va_height:10;
/** lcd_vt_height : R/W; bitpos: [30:21]; default: 0;
* It is the vertical total height of a frame.
*/
uint32_t lcd_vt_height:10;
/** lcd_rgb_mode_en : R/W; bitpos: [31]; default: 0;
* 1: Enable LCD RGB mode. 0: Disable LCD RGB mode.
*/
uint32_t lcd_rgb_mode_en:1;
};
uint32_t val;
} lcdcam_lcd_ctrl_reg_t;
/** Type of lcd_ctrl1 register
* LCD config register.
*/
typedef union {
struct {
/** lcd_vb_front : R/W; bitpos: [7:0]; default: 0;
* It is the vertical blank front porch of a frame.
*/
uint32_t lcd_vb_front:8;
/** lcd_ha_width : R/W; bitpos: [19:8]; default: 0;
* It is the horizontal active width of a frame.
*/
uint32_t lcd_ha_width:12;
/** lcd_ht_width : R/W; bitpos: [31:20]; default: 0;
* It is the horizontal total width of a frame.
*/
uint32_t lcd_ht_width:12;
};
uint32_t val;
} lcdcam_lcd_ctrl1_reg_t;
/** Type of lcd_ctrl2 register
* LCD config register.
*/
typedef union {
struct {
/** lcd_vsync_width : R/W; bitpos: [6:0]; default: 1;
* It is the position of LCD_VSYNC active pulse in a line.
*/
uint32_t lcd_vsync_width:7;
/** lcd_vsync_idle_pol : R/W; bitpos: [7]; default: 0;
* It is the idle value of LCD_VSYNC.
*/
uint32_t lcd_vsync_idle_pol:1;
/** lcd_de_idle_pol : R/W; bitpos: [8]; default: 0;
* It is the idle value of LCD_DE.
*/
uint32_t lcd_de_idle_pol:1;
/** lcd_hs_blank_en : R/W; bitpos: [9]; default: 0;
* 1: The pulse of LCD_HSYNC is out in vertical blanking lines RGB mode. 0: LCD_HSYNC
* pulse is valid only in active region lines in RGB mode.
*/
uint32_t lcd_hs_blank_en:1;
uint32_t reserved_10:6;
/** lcd_hsync_width : R/W; bitpos: [22:16]; default: 1;
* It is the position of LCD_HSYNC active pulse in a line.
*/
uint32_t lcd_hsync_width:7;
/** lcd_hsync_idle_pol : R/W; bitpos: [23]; default: 0;
* It is the idle value of LCD_HSYNC.
*/
uint32_t lcd_hsync_idle_pol:1;
/** lcd_hsync_position : R/W; bitpos: [31:24]; default: 0;
* It is the position of LCD_HSYNC active pulse in a line.
*/
uint32_t lcd_hsync_position:8;
};
uint32_t val;
} lcdcam_lcd_ctrl2_reg_t;
/** Type of lcd_first_cmd_val register
* LCD config register.
*/
typedef union {
struct {
/** lcd_first_cmd_value : R/W; bitpos: [31:0]; default: 0;
* The LCD write command value of first cmd cycle.
*/
uint32_t lcd_first_cmd_value:32;
};
uint32_t val;
} lcdcam_lcd_first_cmd_val_reg_t;
/** Type of lcd_latter_cmd_val register
* LCD config register.
*/
typedef union {
struct {
/** lcd_latter_cmd_value : R/W; bitpos: [31:0]; default: 0;
* The LCD write command value of latter cmd cycle.
*/
uint32_t lcd_latter_cmd_value:32;
};
uint32_t val;
} lcdcam_lcd_latter_cmd_val_reg_t;
/** Type of lcd_dly_mode_cfg1 register
* LCD config register.
*/
typedef union {
struct {
/** dout16_mode : R/W; bitpos: [1:0]; default: 0;
* The output data bit $n is delayed by module clock LCD_CLK. 0: output without
* delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
* LCD_CLK.
*/
uint32_t dout16_mode:2;
/** dout17_mode : R/W; bitpos: [3:2]; default: 0;
* The output data bit $n is delayed by module clock LCD_CLK. 0: output without
* delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
* LCD_CLK.
*/
uint32_t dout17_mode:2;
/** dout18_mode : R/W; bitpos: [5:4]; default: 0;
* The output data bit $n is delayed by module clock LCD_CLK. 0: output without
* delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
* LCD_CLK.
*/
uint32_t dout18_mode:2;
/** dout19_mode : R/W; bitpos: [7:6]; default: 0;
* The output data bit $n is delayed by module clock LCD_CLK. 0: output without
* delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
* LCD_CLK.
*/
uint32_t dout19_mode:2;
/** dout20_mode : R/W; bitpos: [9:8]; default: 0;
* The output data bit $n is delayed by module clock LCD_CLK. 0: output without
* delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
* LCD_CLK.
*/
uint32_t dout20_mode:2;
/** dout21_mode : R/W; bitpos: [11:10]; default: 0;
* The output data bit $n is delayed by module clock LCD_CLK. 0: output without
* delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
* LCD_CLK.
*/
uint32_t dout21_mode:2;
/** dout22_mode : R/W; bitpos: [13:12]; default: 0;
* The output data bit $n is delayed by module clock LCD_CLK. 0: output without
* delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
* LCD_CLK.
*/
uint32_t dout22_mode:2;
/** dout23_mode : R/W; bitpos: [15:14]; default: 0;
* The output data bit $n is delayed by module clock LCD_CLK. 0: output without
* delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
* LCD_CLK.
*/
uint32_t dout23_mode:2;
/** lcd_cd_mode : R/W; bitpos: [17:16]; default: 0;
* The output LCD_CD is delayed by module clock LCD_CLK. 0: output without delayed. 1:
* delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.
*/
uint32_t lcd_cd_mode:2;
/** lcd_de_mode : R/W; bitpos: [19:18]; default: 0;
* The output LCD_DE is delayed by module clock LCD_CLK. 0: output without delayed. 1:
* delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.
*/
uint32_t lcd_de_mode:2;
/** lcd_hsync_mode : R/W; bitpos: [21:20]; default: 0;
* The output LCD_HSYNC is delayed by module clock LCD_CLK. 0: output without delayed.
* 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.
*/
uint32_t lcd_hsync_mode:2;
/** lcd_vsync_mode : R/W; bitpos: [23:22]; default: 0;
* The output LCD_VSYNC is delayed by module clock LCD_CLK. 0: output without delayed.
* 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.
*/
uint32_t lcd_vsync_mode:2;
uint32_t reserved_24:8;
};
uint32_t val;
} lcdcam_lcd_dly_mode_cfg1_reg_t;
/** Type of lcd_dly_mode_cfg2 register
* LCD config register.
*/
typedef union {
struct {
/** dout0_mode : R/W; bitpos: [1:0]; default: 0;
* The output data bit $n is delayed by module clock LCD_CLK. 0: output without
* delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
* LCD_CLK.
*/
uint32_t dout0_mode:2;
/** dout1_mode : R/W; bitpos: [3:2]; default: 0;
* The output data bit $n is delayed by module clock LCD_CLK. 0: output without
* delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
* LCD_CLK.
*/
uint32_t dout1_mode:2;
/** dout2_mode : R/W; bitpos: [5:4]; default: 0;
* The output data bit $n is delayed by module clock LCD_CLK. 0: output without
* delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
* LCD_CLK.
*/
uint32_t dout2_mode:2;
/** dout3_mode : R/W; bitpos: [7:6]; default: 0;
* The output data bit $n is delayed by module clock LCD_CLK. 0: output without
* delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
* LCD_CLK.
*/
uint32_t dout3_mode:2;
/** dout4_mode : R/W; bitpos: [9:8]; default: 0;
* The output data bit $n is delayed by module clock LCD_CLK. 0: output without
* delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
* LCD_CLK.
*/
uint32_t dout4_mode:2;
/** dout5_mode : R/W; bitpos: [11:10]; default: 0;
* The output data bit $n is delayed by module clock LCD_CLK. 0: output without
* delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
* LCD_CLK.
*/
uint32_t dout5_mode:2;
/** dout6_mode : R/W; bitpos: [13:12]; default: 0;
* The output data bit $n is delayed by module clock LCD_CLK. 0: output without
* delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
* LCD_CLK.
*/
uint32_t dout6_mode:2;
/** dout7_mode : R/W; bitpos: [15:14]; default: 0;
* The output data bit $n is delayed by module clock LCD_CLK. 0: output without
* delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
* LCD_CLK.
*/
uint32_t dout7_mode:2;
/** dout8_mode : R/W; bitpos: [17:16]; default: 0;
* The output data bit $n is delayed by module clock LCD_CLK. 0: output without
* delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
* LCD_CLK.
*/
uint32_t dout8_mode:2;
/** dout9_mode : R/W; bitpos: [19:18]; default: 0;
* The output data bit $n is delayed by module clock LCD_CLK. 0: output without
* delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
* LCD_CLK.
*/
uint32_t dout9_mode:2;
/** dout10_mode : R/W; bitpos: [21:20]; default: 0;
* The output data bit $n is delayed by module clock LCD_CLK. 0: output without
* delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
* LCD_CLK.
*/
uint32_t dout10_mode:2;
/** dout11_mode : R/W; bitpos: [23:22]; default: 0;
* The output data bit $n is delayed by module clock LCD_CLK. 0: output without
* delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
* LCD_CLK.
*/
uint32_t dout11_mode:2;
/** dout12_mode : R/W; bitpos: [25:24]; default: 0;
* The output data bit $n is delayed by module clock LCD_CLK. 0: output without
* delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
* LCD_CLK.
*/
uint32_t dout12_mode:2;
/** dout13_mode : R/W; bitpos: [27:26]; default: 0;
* The output data bit $n is delayed by module clock LCD_CLK. 0: output without
* delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
* LCD_CLK.
*/
uint32_t dout13_mode:2;
/** dout14_mode : R/W; bitpos: [29:28]; default: 0;
* The output data bit $n is delayed by module clock LCD_CLK. 0: output without
* delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
* LCD_CLK.
*/
uint32_t dout14_mode:2;
/** dout15_mode : R/W; bitpos: [31:30]; default: 0;
* The output data bit $n is delayed by module clock LCD_CLK. 0: output without
* delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
* LCD_CLK.
*/
uint32_t dout15_mode:2;
};
uint32_t val;
} lcdcam_lcd_dly_mode_cfg2_reg_t;
/** Group: cam configuration registers */
/** Type of cam_ctrl register
* CAM config register.
*/
typedef union {
struct {
/** cam_stop_en : R/W; bitpos: [0]; default: 0;
* Camera stop enable signal, 1: camera stops when DMA Rx FIFO is full. 0: Not stop.
*/
uint32_t cam_stop_en:1;
/** cam_vsync_filter_thres : R/W; bitpos: [3:1]; default: 0;
* Filter threshold value for CAM_VSYNC signal.
*/
uint32_t cam_vsync_filter_thres:3;
/** cam_update_reg : R/W/SC; bitpos: [4]; default: 0;
* 1: Update Camera registers, will be cleared by hardware. 0 : Not care.
*/
uint32_t cam_update_reg:1;
/** cam_byte_order : R/W; bitpos: [5]; default: 0;
* 1: Change data bit order, change CAM_DATA_in[7:0] to CAM_DATA_in[0:7] in one byte
* mode, and bits[15:0] to bits[0:15] in two byte mode. 0: Not change.
*/
uint32_t cam_byte_order:1;
/** cam_bit_order : R/W; bitpos: [6]; default: 0;
* 1: invert data byte order, only valid in 2 byte mode. 0: Not change.
*/
uint32_t cam_bit_order:1;
/** cam_line_int_en : R/W; bitpos: [7]; default: 0;
* 1: Enable to generate CAM_HS_INT. 0: Disable.
*/
uint32_t cam_line_int_en:1;
/** cam_vs_eof_en : R/W; bitpos: [8]; default: 0;
* 1: CAM_VSYNC to generate in_suc_eof. 0: in_suc_eof is controlled by
* reg_cam_rec_data_cyclelen.
*/
uint32_t cam_vs_eof_en:1;
/** cam_clkm_div_num : R/W; bitpos: [16:9]; default: 4;
* Integral Camera clock divider value
*/
uint32_t cam_clkm_div_num:8;
/** cam_clkm_div_b : R/W; bitpos: [22:17]; default: 0;
* Fractional clock divider numerator value
*/
uint32_t cam_clkm_div_b:6;
/** cam_clkm_div_a : R/W; bitpos: [28:23]; default: 0;
* Fractional clock divider denominator value
*/
uint32_t cam_clkm_div_a:6;
/** cam_clk_sel : R/W; bitpos: [30:29]; default: 0;
* Select Camera module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock.
*/
uint32_t cam_clk_sel:2;
uint32_t reserved_31:1;
};
uint32_t val;
} lcdcam_cam_ctrl_reg_t;
/** Type of cam_ctrl1 register
* CAM config register.
*/
typedef union {
struct {
/** cam_rec_data_bytelen : R/W; bitpos: [15:0]; default: 0;
* Camera receive data byte length minus 1 to set DMA in_suc_eof_int.
*/
uint32_t cam_rec_data_bytelen:16;
/** cam_line_int_num : R/W; bitpos: [21:16]; default: 0;
* The line number minus 1 to generate cam_hs_int.
*/
uint32_t cam_line_int_num:6;
/** cam_clk_inv : R/W; bitpos: [22]; default: 0;
* 1: Invert the input signal CAM_PCLK. 0: Not invert.
*/
uint32_t cam_clk_inv:1;
/** cam_vsync_filter_en : R/W; bitpos: [23]; default: 0;
* 1: Enable CAM_VSYNC filter function. 0: bypass.
*/
uint32_t cam_vsync_filter_en:1;
/** cam_2byte_en : R/W; bitpos: [24]; default: 0;
* 1: The bit number of input data is 9~16. 0: The bit number of input data is 0~8.
*/
uint32_t cam_2byte_en:1;
/** cam_de_inv : R/W; bitpos: [25]; default: 0;
* CAM_DE invert enable signal, valid in high level.
*/
uint32_t cam_de_inv:1;
/** cam_hsync_inv : R/W; bitpos: [26]; default: 0;
* CAM_HSYNC invert enable signal, valid in high level.
*/
uint32_t cam_hsync_inv:1;
/** cam_vsync_inv : R/W; bitpos: [27]; default: 0;
* CAM_VSYNC invert enable signal, valid in high level.
*/
uint32_t cam_vsync_inv:1;
/** cam_vh_de_mode_en : R/W; bitpos: [28]; default: 0;
* 1: Input control signals are CAM_DE CAM_HSYNC and CAM_VSYNC. 0: Input control
* signals are CAM_DE and CAM_VSYNC.
*/
uint32_t cam_vh_de_mode_en:1;
/** cam_start : R/W/SC; bitpos: [29]; default: 0;
* Camera module start signal.
*/
uint32_t cam_start:1;
/** cam_reset : WT; bitpos: [30]; default: 0;
* Camera module reset signal.
*/
uint32_t cam_reset:1;
/** cam_afifo_reset : WT; bitpos: [31]; default: 0;
* Camera AFIFO reset signal.
*/
uint32_t cam_afifo_reset:1;
};
uint32_t val;
} lcdcam_cam_ctrl1_reg_t;
/** Type of cam_rgb_yuv register
* CAM YUV/RGB converter configuration register.
*/
typedef union {
struct {
uint32_t reserved_0:21;
/** cam_conv_8bits_data_inv : R/W; bitpos: [21]; default: 0;
* 1:invert every two 8bits input data. 2. disabled.
*/
uint32_t cam_conv_8bits_data_inv:1;
/** cam_conv_yuv2yuv_mode : R/W; bitpos: [23:22]; default: 3;
* 0: to yuv422. 1: to yuv420. 2: to yuv411. 3: disabled. To enable yuv2yuv mode,
* trans_mode must be set to 1.
*/
uint32_t cam_conv_yuv2yuv_mode:2;
/** cam_conv_yuv_mode : R/W; bitpos: [25:24]; default: 0;
* 0: yuv422. 1: yuv420. 2: yuv411. When in yuv2yuv mode, yuv_mode decides the yuv
* mode of Data_in
*/
uint32_t cam_conv_yuv_mode:2;
/** cam_conv_protocol_mode : R/W; bitpos: [26]; default: 0;
* 0:BT601. 1:BT709.
*/
uint32_t cam_conv_protocol_mode:1;
/** cam_conv_data_out_mode : R/W; bitpos: [27]; default: 0;
* LIMIT or FULL mode of Data out. 0: limit. 1: full
*/
uint32_t cam_conv_data_out_mode:1;
/** cam_conv_data_in_mode : R/W; bitpos: [28]; default: 0;
* LIMIT or FULL mode of Data in. 0: limit. 1: full
*/
uint32_t cam_conv_data_in_mode:1;
/** cam_conv_mode_8bits_on : R/W; bitpos: [29]; default: 0;
* 0: 16bits mode. 1: 8bits mode.
*/
uint32_t cam_conv_mode_8bits_on:1;
/** cam_conv_trans_mode : R/W; bitpos: [30]; default: 0;
* 0: YUV to RGB. 1: RGB to YUV.
*/
uint32_t cam_conv_trans_mode:1;
/** cam_conv_enable : R/W; bitpos: [31]; default: 0;
* 0: Bypass converter. 1: Enable converter.
*/
uint32_t cam_conv_enable:1;
};
uint32_t val;
} lcdcam_cam_rgb_yuv_reg_t;
/** Group: Interrupt registers */
/** Type of lc_dma_int_ena register
* LCDCAM interrupt enable register.
*/
typedef union {
struct {
/** lcd_vsync_int_ena : R/W; bitpos: [0]; default: 0;
* The enable bit for LCD frame end interrupt.
*/
uint32_t lcd_vsync_int_ena:1;
/** lcd_trans_done_int_ena : R/W; bitpos: [1]; default: 0;
* The enable bit for lcd transfer end interrupt.
*/
uint32_t lcd_trans_done_int_ena:1;
/** cam_vsync_int_ena : R/W; bitpos: [2]; default: 0;
* The enable bit for Camera frame end interrupt.
*/
uint32_t cam_vsync_int_ena:1;
/** cam_hs_int_ena : R/W; bitpos: [3]; default: 0;
* The enable bit for Camera line interrupt.
*/
uint32_t cam_hs_int_ena:1;
uint32_t reserved_4:28;
};
uint32_t val;
} lcdcam_lc_dma_int_ena_reg_t;
/** Type of lc_dma_int_raw register
* LCDCAM interrupt raw register, valid in level.
*/
typedef union {
struct {
/** lcd_vsync_int_raw : RO/WTC/SS; bitpos: [0]; default: 0;
* The raw bit for LCD frame end interrupt.
*/
uint32_t lcd_vsync_int_raw:1;
/** lcd_trans_done_int_raw : RO/WTC/SS; bitpos: [1]; default: 0;
* The raw bit for lcd transfer end interrupt.
*/
uint32_t lcd_trans_done_int_raw:1;
/** cam_vsync_int_raw : RO/WTC/SS; bitpos: [2]; default: 0;
* The raw bit for Camera frame end interrupt.
*/
uint32_t cam_vsync_int_raw:1;
/** cam_hs_int_raw : RO/WTC/SS; bitpos: [3]; default: 0;
* The raw bit for Camera line interrupt.
*/
uint32_t cam_hs_int_raw:1;
uint32_t reserved_4:28;
};
uint32_t val;
} lcdcam_lc_dma_int_raw_reg_t;
/** Type of lc_dma_int_st register
* LCDCAM interrupt status register.
*/
typedef union {
struct {
/** lcd_vsync_int_st : RO; bitpos: [0]; default: 0;
* The status bit for LCD frame end interrupt.
*/
uint32_t lcd_vsync_int_st:1;
/** lcd_trans_done_int_st : RO; bitpos: [1]; default: 0;
* The status bit for lcd transfer end interrupt.
*/
uint32_t lcd_trans_done_int_st:1;
/** cam_vsync_int_st : RO; bitpos: [2]; default: 0;
* The status bit for Camera frame end interrupt.
*/
uint32_t cam_vsync_int_st:1;
/** cam_hs_int_st : RO; bitpos: [3]; default: 0;
* The status bit for Camera transfer end interrupt.
*/
uint32_t cam_hs_int_st:1;
uint32_t reserved_4:28;
};
uint32_t val;
} lcdcam_lc_dma_int_st_reg_t;
/** Type of lc_dma_int_clr register
* LCDCAM interrupt clear register.
*/
typedef union {
struct {
/** lcd_vsync_int_clr : WT; bitpos: [0]; default: 0;
* The clear bit for LCD frame end interrupt.
*/
uint32_t lcd_vsync_int_clr:1;
/** lcd_trans_done_int_clr : WT; bitpos: [1]; default: 0;
* The clear bit for lcd transfer end interrupt.
*/
uint32_t lcd_trans_done_int_clr:1;
/** cam_vsync_int_clr : WT; bitpos: [2]; default: 0;
* The clear bit for Camera frame end interrupt.
*/
uint32_t cam_vsync_int_clr:1;
/** cam_hs_int_clr : WT; bitpos: [3]; default: 0;
* The clear bit for Camera line interrupt.
*/
uint32_t cam_hs_int_clr:1;
uint32_t reserved_4:28;
};
uint32_t val;
} lcdcam_lc_dma_int_clr_reg_t;
/** Group: Version register */
/** Type of lc_reg_date register
* Version register
*/
typedef union {
struct {
/** lc_date : R/W; bitpos: [27:0]; default: 36712592;
* LCD_CAM version control register
*/
uint32_t lc_date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} lcdcam_lc_reg_date_reg_t;
typedef struct {
volatile lcdcam_lcd_clock_reg_t lcd_clock;
volatile lcdcam_cam_ctrl_reg_t cam_ctrl;
volatile lcdcam_cam_ctrl1_reg_t cam_ctrl1;
volatile lcdcam_cam_rgb_yuv_reg_t cam_rgb_yuv;
volatile lcdcam_lcd_rgb_yuv_reg_t lcd_rgb_yuv;
volatile lcdcam_lcd_user_reg_t lcd_user;
volatile lcdcam_lcd_misc_reg_t lcd_misc;
volatile lcdcam_lcd_ctrl_reg_t lcd_ctrl;
volatile lcdcam_lcd_ctrl1_reg_t lcd_ctrl1;
volatile lcdcam_lcd_ctrl2_reg_t lcd_ctrl2;
volatile lcdcam_lcd_first_cmd_val_reg_t lcd_first_cmd_val;
volatile lcdcam_lcd_latter_cmd_val_reg_t lcd_latter_cmd_val;
volatile lcdcam_lcd_dly_mode_cfg1_reg_t lcd_dly_mode_cfg1;
uint32_t reserved_034;
volatile lcdcam_lcd_dly_mode_cfg2_reg_t lcd_dly_mode_cfg2;
uint32_t reserved_03c[10];
volatile lcdcam_lc_dma_int_ena_reg_t lc_dma_int_ena;
volatile lcdcam_lc_dma_int_raw_reg_t lc_dma_int_raw;
volatile lcdcam_lc_dma_int_st_reg_t lc_dma_int_st;
volatile lcdcam_lc_dma_int_clr_reg_t lc_dma_int_clr;
uint32_t reserved_074[34];
volatile lcdcam_lc_reg_date_reg_t lc_reg_date;
} lcdcam_dev_t;
#ifndef __cplusplus
_Static_assert(sizeof(lcdcam_dev_t) == 0x100, "Invalid size of lcdcam_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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