forked from espressif/esp-idf
components/spi_flash: make spi_flash APIs dual-core-compatible
See esp_spi_flash.c for implementation notes.
This commit is contained in:
Ivan Grokhotkov
@@ -21,6 +21,194 @@
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#include <rom/cache.h>
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#include <rom/cache.h>
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#include <esp_attr.h>
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#include <esp_attr.h>
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#include <soc/dport_reg.h>
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#include <soc/dport_reg.h>
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#include "sdkconfig.h"
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/*
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Driver for SPI flash read/write/erase operations
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In order to perform some flash operations, we need to make sure both CPUs
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are not running any code from flash for the duration of the flash operation.
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In a single-core setup this is easy: we disable interrupts/scheduler and do
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the flash operation. In the dual-core setup this is slightly more complicated.
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We need to make sure that the other CPU doesn't run any code from flash.
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SPI flash driver starts two tasks (spi_flash_op_block_task), one pinned to
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each CPU. Each task is associated with its own semaphore.
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When SPI flash API is called on CPU A (can be PRO or APP), we wake up the task
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on CPU B by "giving" the semaphore associated with it. Tasks resumes, disables
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cache on CPU B, and acknowledges that it has taken the semaphore by setting
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a flag (s_flash_op_can_start). Flash API function running on CPU A waits for
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this flag to be set. Once the flag is set, it disables cache on CPU A and
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starts flash operation.
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While flash operation is running, interrupts can still run on CPU B.
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We assume that all interrupt code is placed into RAM.
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Once flash operation is complete, function on CPU A sets another flag,
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s_flash_op_complete, to let the task on CPU B know that it can re-enable
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cache and release the CPU. Then the function on CPU A re-enables the cache on
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CPU A as well and returns control to the calling code. Task on CPU B returns
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to suspended state by "taking" the semaphore.
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Additionally, all API functions are protected with a mutex (s_flash_op_mutex).
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In a single core environment (CONFIG_FREERTOS_UNICORE enabled), we simply
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disable both caches, no inter-CPU communication takes place.
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*/
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static esp_err_t spi_flash_translate_rc(SpiFlashOpResult rc);
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extern void Cache_Flush(int);
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#ifndef CONFIG_FREERTOS_UNICORE
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static TaskHandle_t s_flash_op_tasks[2];
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static SemaphoreHandle_t s_flash_op_mutex;
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static SemaphoreHandle_t s_flash_op_sem[2];
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static bool s_flash_op_can_start = false;
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static bool s_flash_op_complete = false;
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// Task whose duty is to block other tasks from running on a given CPU
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static void IRAM_ATTR spi_flash_op_block_task(void* arg)
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{
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uint32_t cpuid = (uint32_t) arg;
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while (true) {
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// Wait for flash operation to be initiated.
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// This will be indicated by giving the semaphore corresponding to
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// this CPU.
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if (xSemaphoreTake(s_flash_op_sem[cpuid], portMAX_DELAY) != pdTRUE) {
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// TODO: when can this happen?
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abort();
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}
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// Disable cache on this CPU
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Cache_Read_Disable(cpuid);
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// Signal to the flash API function that flash operation can start
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s_flash_op_can_start = true;
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while (!s_flash_op_complete) {
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// until we have a way to use interrupts for inter-CPU communication,
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// busy loop here and wait for the other CPU to finish flash operation
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}
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// Flash operation is complete, re-enable cache
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Cache_Read_Enable(cpuid);
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}
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// TODO: currently this is unreachable code. Introduce spi_flash_uninit
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// function which will signal to both tasks that they can shut down.
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// Not critical at this point, we don't have a use case for stopping
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// SPI flash driver yet.
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// Also need to delete the semaphore here.
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vTaskDelete(NULL);
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}
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void spi_flash_init()
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{
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s_flash_op_can_start = false;
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s_flash_op_complete = false;
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s_flash_op_sem[0] = xSemaphoreCreateBinary();
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s_flash_op_sem[1] = xSemaphoreCreateBinary();
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s_flash_op_mutex = xSemaphoreCreateMutex();
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// Start two tasks, one on each CPU, with max priorities
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// TODO: optimize stack usage. Stack size 512 is too small.
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xTaskCreatePinnedToCore(spi_flash_op_block_task, "flash_op_pro", 1024, (void*) 0,
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configMAX_PRIORITIES - 1, &s_flash_op_tasks[0], 0);
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xTaskCreatePinnedToCore(spi_flash_op_block_task, "flash_op_app", 1024, (void*) 1,
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configMAX_PRIORITIES - 1, &s_flash_op_tasks[1], 1);
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}
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static void IRAM_ATTR spi_flash_disable_interrupts_caches_and_other_cpu()
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{
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// Take the API lock
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xSemaphoreTake(s_flash_op_mutex, portMAX_DELAY);
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const uint32_t cpuid = xPortGetCoreID();
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uint32_t other_cpuid = !cpuid;
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s_flash_op_can_start = false;
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s_flash_op_complete = false;
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// Signal to the spi_flash_op_block_task on the other CPU that we need it to
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// disable cache there and block other tasks from executing.
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xSemaphoreGive(s_flash_op_sem[other_cpuid]);
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while (!s_flash_op_can_start) {
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// Busy loop and wait for spi_flash_op_block_task to take the semaphore on the
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// other CPU.
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}
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vTaskSuspendAll();
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// Disable cache on this CPU as well
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Cache_Read_Disable(cpuid);
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}
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static void IRAM_ATTR spi_flash_enable_interrupts_caches_and_other_cpu()
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{
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uint32_t cpuid = xPortGetCoreID();
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// Signal to spi_flash_op_block_task that flash operation is complete
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s_flash_op_complete = true;
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// Re-enable cache on this CPU
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Cache_Read_Enable(cpuid);
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// Release API lock
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xSemaphoreGive(s_flash_op_mutex);
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xTaskResumeAll();
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}
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#else // CONFIG_FREERTOS_UNICORE
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void spi_flash_init()
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{
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// No-op in single core mode
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}
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static void IRAM_ATTR spi_flash_disable_interrupts_caches_and_other_cpu()
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{
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vTaskSuspendAll();
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Cache_Read_Disable(0);
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Cache_Read_Disable(1);
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}
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static void IRAM_ATTR spi_flash_enable_interrupts_caches_and_other_cpu()
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{
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Cache_Read_Enable(0);
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Cache_Read_Enable(1);
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xTaskResumeAll();
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}
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#endif // CONFIG_FREERTOS_UNICORE
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esp_err_t IRAM_ATTR spi_flash_erase_sector(uint16_t sec)
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{
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spi_flash_disable_interrupts_caches_and_other_cpu();
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SpiFlashOpResult rc;
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rc = SPIUnlock();
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if (rc == SPI_FLASH_RESULT_OK) {
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rc = SPIEraseSector(sec);
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}
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Cache_Flush(0);
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Cache_Flush(1);
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spi_flash_enable_interrupts_caches_and_other_cpu();
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return spi_flash_translate_rc(rc);
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}
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esp_err_t IRAM_ATTR spi_flash_write(uint32_t dest_addr, const uint32_t *src, uint32_t size)
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{
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spi_flash_disable_interrupts_caches_and_other_cpu();
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SpiFlashOpResult rc;
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rc = SPIUnlock();
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if (rc == SPI_FLASH_RESULT_OK) {
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rc = SPIWrite(dest_addr, src, (int32_t) size);
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}
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Cache_Flush(0);
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Cache_Flush(1);
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spi_flash_enable_interrupts_caches_and_other_cpu();
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return spi_flash_translate_rc(rc);
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}
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esp_err_t IRAM_ATTR spi_flash_read(uint32_t src_addr, uint32_t *dest, uint32_t size)
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{
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spi_flash_disable_interrupts_caches_and_other_cpu();
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SpiFlashOpResult rc;
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rc = SPIRead(src_addr, dest, (int32_t) size);
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Cache_Flush(0);
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Cache_Flush(1);
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spi_flash_enable_interrupts_caches_and_other_cpu();
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return spi_flash_translate_rc(rc);
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}
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static esp_err_t spi_flash_translate_rc(SpiFlashOpResult rc)
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static esp_err_t spi_flash_translate_rc(SpiFlashOpResult rc)
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{
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{
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@@ -34,73 +222,3 @@ static esp_err_t spi_flash_translate_rc(SpiFlashOpResult rc)
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return ESP_ERR_FLASH_OP_FAIL;
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return ESP_ERR_FLASH_OP_FAIL;
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}
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}
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}
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}
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extern void Cache_Flush(int);
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static void IRAM_ATTR spi_flash_disable_interrupts_caches_and_app_cpu()
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{
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vTaskSuspendAll();
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// SET_PERI_REG_MASK(APPCPU_CTRL_REG_C, DPORT_APPCPU_RUNSTALL);
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Cache_Read_Disable(0);
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Cache_Read_Disable(1);
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}
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static void IRAM_ATTR spi_flash_enable_interrupts_caches_and_app_cpu()
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{
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Cache_Read_Enable(0);
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Cache_Read_Enable(1);
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// CLEAR_PERI_REG_MASK(APPCPU_CTRL_REG_C, DPORT_APPCPU_RUNSTALL);
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xTaskResumeAll();
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}
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esp_err_t IRAM_ATTR spi_flash_erase_sector(uint16_t sec)
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{
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spi_flash_disable_interrupts_caches_and_app_cpu();
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SpiFlashOpResult rc;
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if (xPortGetCoreID() == 1) {
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rc = SPI_FLASH_RESULT_ERR;
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}
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else {
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rc = SPIUnlock();
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if (rc == SPI_FLASH_RESULT_OK) {
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rc = SPIEraseSector(sec);
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}
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}
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Cache_Flush(0);
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Cache_Flush(1);
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spi_flash_enable_interrupts_caches_and_app_cpu();
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return spi_flash_translate_rc(rc);
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}
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esp_err_t IRAM_ATTR spi_flash_write(uint32_t dest_addr, const uint32_t *src, uint32_t size)
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{
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spi_flash_disable_interrupts_caches_and_app_cpu();
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SpiFlashOpResult rc;
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if (xPortGetCoreID() == 1) {
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rc = SPI_FLASH_RESULT_ERR;
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}
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else {
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rc = SPIUnlock();
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if (rc == SPI_FLASH_RESULT_OK) {
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rc = SPIWrite(dest_addr, src, (int32_t) size);
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}
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}
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Cache_Flush(0);
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Cache_Flush(1);
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spi_flash_enable_interrupts_caches_and_app_cpu();
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return spi_flash_translate_rc(rc);
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}
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esp_err_t IRAM_ATTR spi_flash_read(uint32_t src_addr, uint32_t *dest, uint32_t size)
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{
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spi_flash_disable_interrupts_caches_and_app_cpu();
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SpiFlashOpResult rc;
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if (xPortGetCoreID() == 1) {
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rc = SPI_FLASH_RESULT_ERR;
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}
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else {
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rc = SPIRead(src_addr, dest, (int32_t) size);
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}
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spi_flash_enable_interrupts_caches_and_app_cpu();
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return spi_flash_translate_rc(rc);
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}
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@@ -28,6 +28,15 @@ extern "C" {
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#define SPI_FLASH_SEC_SIZE 4096 /**< SPI Flash sector size */
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#define SPI_FLASH_SEC_SIZE 4096 /**< SPI Flash sector size */
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/**
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* @brief Initialize SPI flash access driver
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*
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* This function must be called exactly once, before any other
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* spi_flash_* functions are called.
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*
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*/
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void spi_flash_init();
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/**
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/**
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* @brief Erase the Flash sector.
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* @brief Erase the Flash sector.
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*
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*
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Block a user