From 31b3f31ef4b6e5fa3bb48ad7c49f36bec8f524ea Mon Sep 17 00:00:00 2001 From: Armando Date: Mon, 27 Jun 2022 18:48:01 +0800 Subject: [PATCH 1/3] ext_mem: make memory region check strict --- .../include/esp_private/esp_psram_extram.h | 4 ++++ components/hal/esp32/include/hal/cache_ll.h | 6 +++--- components/hal/esp32c2/include/hal/cache_ll.h | 6 +++--- components/hal/esp32c3/include/hal/cache_ll.h | 6 +++--- components/hal/esp32h2/include/hal/cache_ll.h | 6 +++--- components/hal/esp32s2/include/hal/cache_ll.h | 2 +- components/hal/esp32s2/include/hal/mmu_ll.h | 15 ++++++++------- components/hal/esp32s3/include/hal/cache_ll.h | 6 +++--- components/soc/esp32/include/soc/ext_mem_defs.h | 2 +- components/soc/esp32c2/include/soc/ext_mem_defs.h | 2 +- components/soc/esp32c3/include/soc/ext_mem_defs.h | 2 +- components/soc/esp32h2/include/soc/ext_mem_defs.h | 2 +- components/soc/esp32s2/include/soc/ext_mem_defs.h | 2 +- components/soc/esp32s3/include/soc/ext_mem_defs.h | 2 +- 14 files changed, 34 insertions(+), 29 deletions(-) diff --git a/components/esp_psram/include/esp_private/esp_psram_extram.h b/components/esp_psram/include/esp_private/esp_psram_extram.h index 32f8b4ddcf..a05a371c76 100644 --- a/components/esp_psram/include/esp_private/esp_psram_extram.h +++ b/components/esp_psram/include/esp_private/esp_psram_extram.h @@ -20,6 +20,8 @@ extern "C" { * @param[out] out_vstart PSRAM virtual address start * @param[out] out_vend PSRAM virtual address end * + * @note [out_vstart, out_vend), `out_vend` isn't included. + * * @return * - ESP_OK On success * - ESP_ERR_INVALID_STATE PSRAM is not initialized successfully @@ -32,6 +34,8 @@ esp_err_t esp_psram_extram_get_mapped_range(intptr_t *out_vstart, intptr_t *out_ * @param[out] out_vstart PSRAM virtual address start * @param[out] out_vend PSRAM virtual address end * + * @note [out_vstart, out_vend), `out_vend` isn't included. + * * @return * - ESP_OK On success * - ESP_ERR_INVALID_STATE PSRAM is not initialized successfully diff --git a/components/hal/esp32/include/hal/cache_ll.h b/components/hal/esp32/include/hal/cache_ll.h index 2ea6cb75b4..b3443a1c88 100644 --- a/components/hal/esp32/include/hal/cache_ll.h +++ b/components/hal/esp32/include/hal/cache_ll.h @@ -37,7 +37,7 @@ static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t v HAL_ASSERT(cache_id == 0 || cache_id == 1); cache_bus_mask_t mask = 0; - uint32_t vaddr_end = vaddr_start + len; + uint32_t vaddr_end = vaddr_start + len - 1; if (vaddr_start >= IROM0_CACHE_ADDRESS_HIGH) { HAL_ASSERT(false); //out of range } else if (vaddr_start >= IROM0_CACHE_ADDRESS_LOW) { @@ -50,10 +50,10 @@ static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t v mask |= (vaddr_end >= IRAM1_CACHE_ADDRESS_LOW) ? CACHE_BUS_IBUS1 : 0; mask |= (vaddr_end >= IROM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_IBUS2 : 0; } else if (vaddr_start >= DRAM1_CACHE_ADDRESS_LOW) { - HAL_ASSERT(vaddr_end <= DRAM1_CACHE_ADDRESS_HIGH); //out of range, vaddr should be consecutive, see `ext_mem_defs.h` + HAL_ASSERT(vaddr_end < DRAM1_CACHE_ADDRESS_HIGH); //out of range, vaddr should be consecutive, see `ext_mem_defs.h` mask |= CACHE_BUS_DBUS1; } else if (vaddr_start >= DROM0_CACHE_ADDRESS_LOW) { - HAL_ASSERT(vaddr_end <= DROM0_CACHE_ADDRESS_HIGH); //out of range, vaddr should be consecutive, see `ext_mem_defs.h` + HAL_ASSERT(vaddr_end < DROM0_CACHE_ADDRESS_HIGH); //out of range, vaddr should be consecutive, see `ext_mem_defs.h` mask |= CACHE_BUS_DBUS0; } else { HAL_ASSERT(false); diff --git a/components/hal/esp32c2/include/hal/cache_ll.h b/components/hal/esp32c2/include/hal/cache_ll.h index fd3d69a717..c39aa532c8 100644 --- a/components/hal/esp32c2/include/hal/cache_ll.h +++ b/components/hal/esp32c2/include/hal/cache_ll.h @@ -53,10 +53,10 @@ static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t v HAL_ASSERT(cache_id == 0); cache_bus_mask_t mask = 0; - uint32_t vaddr_end = vaddr_start + len; - if (vaddr_start >= IRAM0_CACHE_ADDRESS_LOW && vaddr_end <= IRAM0_CACHE_ADDRESS_HIGH(CONFIG_MMU_PAGE_SIZE)) { + uint32_t vaddr_end = vaddr_start + len - 1; + if (vaddr_start >= IRAM0_CACHE_ADDRESS_LOW && vaddr_end < IRAM0_CACHE_ADDRESS_HIGH(CONFIG_MMU_PAGE_SIZE)) { mask |= CACHE_BUS_IBUS0; - } else if (vaddr_start >= DRAM0_CACHE_ADDRESS_LOW && vaddr_end <= DRAM0_CACHE_ADDRESS_HIGH(CONFIG_MMU_PAGE_SIZE)) { + } else if (vaddr_start >= DRAM0_CACHE_ADDRESS_LOW && vaddr_end < DRAM0_CACHE_ADDRESS_HIGH(CONFIG_MMU_PAGE_SIZE)) { mask |= CACHE_BUS_DBUS0; } else { HAL_ASSERT(0); //Out of region diff --git a/components/hal/esp32c3/include/hal/cache_ll.h b/components/hal/esp32c3/include/hal/cache_ll.h index 659b689fcf..8ba372d3af 100644 --- a/components/hal/esp32c3/include/hal/cache_ll.h +++ b/components/hal/esp32c3/include/hal/cache_ll.h @@ -53,10 +53,10 @@ static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t v HAL_ASSERT(cache_id == 0); cache_bus_mask_t mask = 0; - uint32_t vaddr_end = vaddr_start + len; - if (vaddr_start >= IRAM0_CACHE_ADDRESS_LOW && vaddr_end <= IRAM0_CACHE_ADDRESS_HIGH) { + uint32_t vaddr_end = vaddr_start + len - 1; + if (vaddr_start >= IRAM0_CACHE_ADDRESS_LOW && vaddr_end < IRAM0_CACHE_ADDRESS_HIGH) { mask |= CACHE_BUS_IBUS0; - } else if (vaddr_start >= DRAM0_CACHE_ADDRESS_LOW && vaddr_end <= DRAM0_CACHE_ADDRESS_HIGH) { + } else if (vaddr_start >= DRAM0_CACHE_ADDRESS_LOW && vaddr_end < DRAM0_CACHE_ADDRESS_HIGH) { mask |= CACHE_BUS_DBUS0; } else { HAL_ASSERT(0); //Out of region diff --git a/components/hal/esp32h2/include/hal/cache_ll.h b/components/hal/esp32h2/include/hal/cache_ll.h index 1a7b353ef9..39c930e0a1 100644 --- a/components/hal/esp32h2/include/hal/cache_ll.h +++ b/components/hal/esp32h2/include/hal/cache_ll.h @@ -52,10 +52,10 @@ static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t v HAL_ASSERT(cache_id == 0); cache_bus_mask_t mask = 0; - uint32_t vaddr_end = vaddr_start + len; - if (vaddr_start >= IRAM0_CACHE_ADDRESS_LOW && vaddr_end <= IRAM0_CACHE_ADDRESS_HIGH) { + uint32_t vaddr_end = vaddr_start + len - 1; + if (vaddr_start >= IRAM0_CACHE_ADDRESS_LOW && vaddr_end < IRAM0_CACHE_ADDRESS_HIGH) { mask |= CACHE_BUS_IBUS0; - } else if (vaddr_start >= DRAM0_CACHE_ADDRESS_LOW && vaddr_end <= DRAM0_CACHE_ADDRESS_HIGH) { + } else if (vaddr_start >= DRAM0_CACHE_ADDRESS_LOW && vaddr_end < DRAM0_CACHE_ADDRESS_HIGH) { mask |= CACHE_BUS_DBUS0; } else { HAL_ASSERT(0); //Out of region diff --git a/components/hal/esp32s2/include/hal/cache_ll.h b/components/hal/esp32s2/include/hal/cache_ll.h index a9a094d570..6ef7621c65 100644 --- a/components/hal/esp32s2/include/hal/cache_ll.h +++ b/components/hal/esp32s2/include/hal/cache_ll.h @@ -41,7 +41,7 @@ static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t v HAL_ASSERT(cache_id == 0); cache_bus_mask_t mask = 0; - uint32_t vaddr_end = vaddr_start + len; + uint32_t vaddr_end = vaddr_start + len - 1; if (vaddr_start >= IRAM1_ADDRESS_LOW) { mask |= CACHE_BUS_IBUS1; } else if (vaddr_start >= IRAM0_CACHE_ADDRESS_LOW) { diff --git a/components/hal/esp32s2/include/hal/mmu_ll.h b/components/hal/esp32s2/include/hal/mmu_ll.h index 33f7a8a958..0eed27a4a3 100644 --- a/components/hal/esp32s2/include/hal/mmu_ll.h +++ b/components/hal/esp32s2/include/hal/mmu_ll.h @@ -60,14 +60,15 @@ __attribute__((always_inline)) static inline bool mmu_ll_check_valid_ext_vaddr_region(uint32_t mmu_id, uint32_t vaddr_start, uint32_t len) { (void)mmu_id; - uint32_t vaddr_end = vaddr_start + len; + uint32_t vaddr_end = vaddr_start + len - 1; - return (ADDRESS_IN_DROM0(vaddr_start) && ADDRESS_IN_DROM0(vaddr_end)) || - (ADDRESS_IN_IRAM1(vaddr_start) && ADDRESS_IN_IRAM1(vaddr_end)) || - (ADDRESS_IN_IRAM0_CACHE(vaddr_start) && ADDRESS_IN_IRAM0_CACHE(vaddr_end)) || - (ADDRESS_IN_DPORT_CACHE(vaddr_start) && ADDRESS_IN_DPORT_CACHE(vaddr_end)) || - (ADDRESS_IN_DRAM1(vaddr_start) && ADDRESS_IN_DRAM1(vaddr_end)) || - (ADDRESS_IN_DRAM0_CACHE(vaddr_start) && ADDRESS_IN_DRAM0_CACHE(vaddr_end)); + //DROM0 is an alias of the IBUS2 + bool on_ibus = ((vaddr_start >= DROM0_ADDRESS_LOW) && (vaddr_end < DROM0_ADDRESS_HIGH)) || + ((vaddr_start >= IRAM0_CACHE_ADDRESS_LOW) && (vaddr_end < IRAM1_ADDRESS_HIGH)); + + bool on_dbus = (vaddr_start >= DPORT_CACHE_ADDRESS_LOW) && (vaddr_end < DRAM0_CACHE_ADDRESS_HIGH); + + return (on_ibus || on_dbus); } /** diff --git a/components/hal/esp32s3/include/hal/cache_ll.h b/components/hal/esp32s3/include/hal/cache_ll.h index 89638e1ed0..fa6c6b966e 100644 --- a/components/hal/esp32s3/include/hal/cache_ll.h +++ b/components/hal/esp32s3/include/hal/cache_ll.h @@ -56,10 +56,10 @@ static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t v HAL_ASSERT(cache_id == 0 || cache_id == 1); cache_bus_mask_t mask = 0; - uint32_t vaddr_end = vaddr_start + len; - if (vaddr_start >= IRAM0_CACHE_ADDRESS_LOW && vaddr_end <= IRAM0_CACHE_ADDRESS_HIGH) { + uint32_t vaddr_end = vaddr_start + len - 1; + if (vaddr_start >= IRAM0_CACHE_ADDRESS_LOW && vaddr_end < IRAM0_CACHE_ADDRESS_HIGH) { mask |= CACHE_BUS_IBUS0; //Both cores have their own IBUS0 - } else if (vaddr_start >= DRAM0_CACHE_ADDRESS_LOW && vaddr_end <= DRAM0_CACHE_ADDRESS_HIGH) { + } else if (vaddr_start >= DRAM0_CACHE_ADDRESS_LOW && vaddr_end < DRAM0_CACHE_ADDRESS_HIGH) { mask |= CACHE_BUS_DBUS0; //Both cores have their own DBUS0 } else { HAL_ASSERT(0); //Out of region diff --git a/components/soc/esp32/include/soc/ext_mem_defs.h b/components/soc/esp32/include/soc/ext_mem_defs.h index 428623a1bf..2b5d1e4bb2 100644 --- a/components/soc/esp32/include/soc/ext_mem_defs.h +++ b/components/soc/esp32/include/soc/ext_mem_defs.h @@ -29,7 +29,7 @@ extern "C" { #define DROM0_CACHE_ADDRESS_HIGH 0x3F800000 -#define ADDRESS_IN_BUS(bus_name, vaddr) ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) <= bus_name##_ADDRESS_HIGH) +#define ADDRESS_IN_BUS(bus_name, vaddr) ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name##_ADDRESS_HIGH) #define ADDRESS_IN_IRAM0_CACHE(vaddr) ADDRESS_IN_BUS(IRAM0_CACHE, vaddr) #define ADDRESS_IN_IRAM1_CACHE(vaddr) ADDRESS_IN_BUS(IRAM1_CACHE, vaddr) #define ADDRESS_IN_IROM0_CACHE(vaddr) ADDRESS_IN_BUS(IROM0_CACHE, vaddr) diff --git a/components/soc/esp32c2/include/soc/ext_mem_defs.h b/components/soc/esp32c2/include/soc/ext_mem_defs.h index be7099d9bb..9698bb5f76 100644 --- a/components/soc/esp32c2/include/soc/ext_mem_defs.h +++ b/components/soc/esp32c2/include/soc/ext_mem_defs.h @@ -29,7 +29,7 @@ extern "C" { #define ESP_CACHE_TEMP_ADDR 0x3C000000 #define BUS_SIZE(bus_name, page_size) (bus_name##_ADDRESS_HIGH(page_size) - bus_name##_ADDRESS_LOW) -#define ADDRESS_IN_BUS(bus_name, vaddr, page_size) ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) <= bus_name##_ADDRESS_HIGH(page_size)) +#define ADDRESS_IN_BUS(bus_name, vaddr, page_size) ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name##_ADDRESS_HIGH(page_size)) #define ADDRESS_IN_IRAM0(vaddr, page_size) ADDRESS_IN_BUS(IRAM0, vaddr, page_size) #define ADDRESS_IN_IRAM0_CACHE(vaddr, page_size) ADDRESS_IN_BUS(IRAM0_CACHE, vaddr, page_size) diff --git a/components/soc/esp32c3/include/soc/ext_mem_defs.h b/components/soc/esp32c3/include/soc/ext_mem_defs.h index b769d81e88..f37567bffd 100644 --- a/components/soc/esp32c3/include/soc/ext_mem_defs.h +++ b/components/soc/esp32c3/include/soc/ext_mem_defs.h @@ -27,7 +27,7 @@ extern "C" { #define ESP_CACHE_TEMP_ADDR 0x3C000000 #define BUS_SIZE(bus_name) (bus_name##_ADDRESS_HIGH - bus_name##_ADDRESS_LOW) -#define ADDRESS_IN_BUS(bus_name, vaddr) ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) <= bus_name##_ADDRESS_HIGH) +#define ADDRESS_IN_BUS(bus_name, vaddr) ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name##_ADDRESS_HIGH) #define ADDRESS_IN_IRAM0(vaddr) ADDRESS_IN_BUS(IRAM0, vaddr) #define ADDRESS_IN_IRAM0_CACHE(vaddr) ADDRESS_IN_BUS(IRAM0_CACHE, vaddr) diff --git a/components/soc/esp32h2/include/soc/ext_mem_defs.h b/components/soc/esp32h2/include/soc/ext_mem_defs.h index ce4bcc93af..7189108f9b 100644 --- a/components/soc/esp32h2/include/soc/ext_mem_defs.h +++ b/components/soc/esp32h2/include/soc/ext_mem_defs.h @@ -27,7 +27,7 @@ extern "C" { #define ESP_CACHE_TEMP_ADDR 0x3C000000 #define BUS_SIZE(bus_name) (bus_name##_ADDRESS_HIGH - bus_name##_ADDRESS_LOW) -#define ADDRESS_IN_BUS(bus_name, vaddr) ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) <= bus_name##_ADDRESS_HIGH) +#define ADDRESS_IN_BUS(bus_name, vaddr) ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name##_ADDRESS_HIGH) #define ADDRESS_IN_IRAM0(vaddr) ADDRESS_IN_BUS(IRAM0, vaddr) #define ADDRESS_IN_IRAM0_CACHE(vaddr) ADDRESS_IN_BUS(IRAM0_CACHE, vaddr) diff --git a/components/soc/esp32s2/include/soc/ext_mem_defs.h b/components/soc/esp32s2/include/soc/ext_mem_defs.h index 9452fab2c9..de20e102d1 100644 --- a/components/soc/esp32s2/include/soc/ext_mem_defs.h +++ b/components/soc/esp32s2/include/soc/ext_mem_defs.h @@ -43,7 +43,7 @@ extern "C" { #define DPORT_CACHE_ADDRESS_HIGH 0x3f800000 #define BUS_SIZE(bus_name) (bus_name##_ADDRESS_HIGH - bus_name##_ADDRESS_LOW) -#define ADDRESS_IN_BUS(bus_name, vaddr) ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) <= bus_name##_ADDRESS_HIGH) +#define ADDRESS_IN_BUS(bus_name, vaddr) ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name##_ADDRESS_HIGH) #define ADDRESS_IN_IRAM0(vaddr) ADDRESS_IN_BUS(IRAM0, vaddr) #define ADDRESS_IN_IRAM0_CACHE(vaddr) ADDRESS_IN_BUS(IRAM0_CACHE, vaddr) diff --git a/components/soc/esp32s3/include/soc/ext_mem_defs.h b/components/soc/esp32s3/include/soc/ext_mem_defs.h index aae68b3cbe..b26bbe8db9 100644 --- a/components/soc/esp32s3/include/soc/ext_mem_defs.h +++ b/components/soc/esp32s3/include/soc/ext_mem_defs.h @@ -26,7 +26,7 @@ extern "C" { #define ESP_CACHE_TEMP_ADDR 0x3C800000 #define BUS_SIZE(bus_name) (bus_name##_ADDRESS_HIGH - bus_name##_ADDRESS_LOW) -#define ADDRESS_IN_BUS(bus_name, vaddr) ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) <= bus_name##_ADDRESS_HIGH) +#define ADDRESS_IN_BUS(bus_name, vaddr) ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name##_ADDRESS_HIGH) #define ADDRESS_IN_IRAM0(vaddr) ADDRESS_IN_BUS(IRAM0, vaddr) #define ADDRESS_IN_IRAM0_CACHE(vaddr) ADDRESS_IN_BUS(IRAM0_CACHE, vaddr) From c51c1a86518516200b2eb6ab7f5e8186b0aa8b1c Mon Sep 17 00:00:00 2001 From: Armando Date: Mon, 27 Jun 2022 18:50:19 +0800 Subject: [PATCH 2/3] mmu: fix wrong mmu entry id issue --- components/hal/mmu_hal.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/components/hal/mmu_hal.c b/components/hal/mmu_hal.c index 5cfc8d79c1..44f095521c 100644 --- a/components/hal/mmu_hal.c +++ b/components/hal/mmu_hal.c @@ -91,12 +91,12 @@ void mmu_hal_map_region(uint32_t mmu_id, mmu_target_t mem_type, uint32_t vaddr, uint32_t mmu_val; //This is the physical address in the format that MMU supported *out_len = mmu_hal_pages_to_bytes(mmu_id, page_num); - entry_id = mmu_ll_get_entry_id(mmu_id, vaddr); mmu_val = mmu_ll_format_paddr(mmu_id, paddr); while (page_num) { + entry_id = mmu_ll_get_entry_id(mmu_id, vaddr); mmu_ll_write_entry(mmu_id, entry_id, mmu_val, mem_type); - entry_id++; + vaddr += page_size_in_bytes; mmu_val++; page_num--; } From 63d4b52e21f0d7e1a041b0c38e7e15f1de30f92a Mon Sep 17 00:00:00 2001 From: Armando Date: Mon, 27 Jun 2022 18:50:32 +0800 Subject: [PATCH 3/3] psram: correct psram size log --- components/esp_psram/esp_psram.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/components/esp_psram/esp_psram.c b/components/esp_psram/esp_psram.c index 8b35c7961a..b70f02d916 100644 --- a/components/esp_psram/esp_psram.c +++ b/components/esp_psram/esp_psram.c @@ -105,7 +105,7 @@ esp_err_t esp_psram_init(void) ret = esp_psram_impl_get_physical_size(&psram_physical_size); assert(ret == ESP_OK); - ESP_EARLY_LOGI(TAG, "Found %dMBit SPI RAM device", psram_physical_size / (1024 * 1024)); + ESP_EARLY_LOGI(TAG, "Found %dMB SPI RAM device", psram_physical_size / (1024 * 1024)); ESP_EARLY_LOGI(TAG, "Speed: %dMHz", CONFIG_SPIRAM_SPEED); #if CONFIG_IDF_TARGET_ESP32 ESP_EARLY_LOGI(TAG, "PSRAM initialized, cache is in %s mode.", \