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feat(spi): c5mp gpspi master slave and hd driver support

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This commit is contained in:
wanlei
2024-05-20 19:01:20 +08:00
parent 375a4b878e
commit e2432c1d20
15 changed files with 287 additions and 453 deletions
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9
components/esp_driver_spi/test_apps/components/spi_bench_mark/include/spi_performance.h
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@@ -76,11 +76,12 @@
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING_NO_DMA 1000 #define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING_NO_DMA 1000
#elif CONFIG_IDF_TARGET_ESP32C5 #elif CONFIG_IDF_TARGET_ESP32C5
//TODO: IDF-10002 update after chips back and PLL setup
#define IDF_PERFORMANCE_MAX_SPI_CLK_FREQ 40*1000*1000 #define IDF_PERFORMANCE_MAX_SPI_CLK_FREQ 40*1000*1000
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING 27 #define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING 1000
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING 16 #define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING 1000
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING_NO_DMA 24 #define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING_NO_DMA 1000
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING_NO_DMA 13 #define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING_NO_DMA 1000
#else #else
#endif #endif

2
components/esp_driver_spi/test_apps/master/main/test_spi_master.c
View File

@@ -1568,7 +1568,7 @@ void test_add_device_slave(void)
.spics_io_num = CS_REAL_DEV, .spics_io_num = CS_REAL_DEV,
.queue_size = 3, .queue_size = 3,
}; };
TEST_ESP_OK(spi_slave_initialize(TEST_SPI_HOST, &bus_cfg, &slvcfg, SPI_DMA_DISABLED)); TEST_ESP_OK(spi_slave_initialize(TEST_SPI_HOST, &bus_cfg, &slvcfg, SPI_DMA_CH_AUTO));
spi_slave_transaction_t slave_trans = {}; spi_slave_transaction_t slave_trans = {};
slave_trans.length = sizeof(slave_sendbuf) * 8; slave_trans.length = sizeof(slave_sendbuf) * 8;

295
components/hal/esp32c5/include/hal/gpspi_flash_ll.h
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@@ -45,17 +45,17 @@ typedef typeof(GPSPI2.clock.val) gpspi_flash_ll_clock_reg_t;
*/ */
static inline void gpspi_flash_ll_reset(spi_dev_t *dev) static inline void gpspi_flash_ll_reset(spi_dev_t *dev)
{ {
// TODO: [ESP32C5] IDF-8698, IDF-8699 dev->user.val = 0;
// dev->user.val = 0; dev->ctrl.val = 0;
// dev->ctrl.val = 0;
// // dev->clk_gate.clk_en = 1; dev->clk_gate.clk_en = 1;
// dev->clk_gate.mst_clk_active = 1; dev->clk_gate.mst_clk_active = 1;
// dev->clk_gate.mst_clk_sel = 1; dev->clk_gate.mst_clk_sel = 1;
// // dev->dma_conf.val = 0;
// dev->dma_conf.slv_tx_seg_trans_clr_en = 1; dev->dma_conf.val = 0;
// dev->dma_conf.slv_rx_seg_trans_clr_en = 1; dev->dma_conf.slv_tx_seg_trans_clr_en = 1;
// dev->dma_conf.dma_slv_seg_trans_en = 0; dev->dma_conf.slv_rx_seg_trans_clr_en = 1;
abort(); dev->dma_conf.dma_slv_seg_trans_en = 0;
} }
/** /**
@@ -67,10 +67,7 @@ static inline void gpspi_flash_ll_reset(spi_dev_t *dev)
*/ */
static inline bool gpspi_flash_ll_cmd_is_done(const spi_dev_t *dev) static inline bool gpspi_flash_ll_cmd_is_done(const spi_dev_t *dev)
{ {
// TODO: [ESP32C5] IDF-8698, IDF-8699 return (dev->cmd.usr == 0);
// return (dev->cmd.usr == 0);
abort();
return (bool)0;
} }
/** /**
@@ -82,22 +79,20 @@ static inline bool gpspi_flash_ll_cmd_is_done(const spi_dev_t *dev)
*/ */
static inline void gpspi_flash_ll_get_buffer_data(spi_dev_t *dev, void *buffer, uint32_t read_len) static inline void gpspi_flash_ll_get_buffer_data(spi_dev_t *dev, void *buffer, uint32_t read_len)
{ {
// TODO: [ESP32C5] IDF-8698, IDF-8699 if (((intptr_t)buffer % 4 == 0) && (read_len % 4 == 0)) {
// if (((intptr_t)buffer % 4 == 0) && (read_len % 4 == 0)) { // If everything is word-aligned, do a faster memcpy
// // If everything is word-aligned, do a faster memcpy memcpy(buffer, (void *)dev->data_buf, read_len);
// memcpy(buffer, (void *)dev->data_buf, read_len); } else {
// } else { // Otherwise, slow(er) path copies word by word
// // Otherwise, slow(er) path copies word by word int copy_len = read_len;
// int copy_len = read_len; for (int i = 0; i < (read_len + 3) / 4; i++) {
// for (int i = 0; i < (read_len + 3) / 4; i++) { int word_len = MIN(sizeof(uint32_t), copy_len);
// int word_len = MIN(sizeof(uint32_t), copy_len); uint32_t word = dev->data_buf[i].buf;
// uint32_t word = dev->data_buf[i].buf; memcpy(buffer, &word, word_len);
// memcpy(buffer, &word, word_len); buffer = (void *)((intptr_t)buffer + word_len);
// buffer = (void *)((intptr_t)buffer + word_len); copy_len -= word_len;
// copy_len -= word_len; }
// } }
// }
abort();
} }
/** /**
@@ -108,9 +103,7 @@ static inline void gpspi_flash_ll_get_buffer_data(spi_dev_t *dev, void *buffer,
*/ */
static inline void gpspi_flash_ll_write_word(spi_dev_t *dev, uint32_t word) static inline void gpspi_flash_ll_write_word(spi_dev_t *dev, uint32_t word)
{ {
// TODO: [ESP32C5] IDF-8698, IDF-8699 dev->data_buf[0].buf = word;
// dev->data_buf[0].buf = word;
abort();
} }
/** /**
@@ -122,18 +115,16 @@ static inline void gpspi_flash_ll_write_word(spi_dev_t *dev, uint32_t word)
*/ */
static inline void gpspi_flash_ll_set_buffer_data(spi_dev_t *dev, const void *buffer, uint32_t length) static inline void gpspi_flash_ll_set_buffer_data(spi_dev_t *dev, const void *buffer, uint32_t length)
{ {
// TODO: [ESP32C5] IDF-8698, IDF-8699 // Load data registers, word at a time
// // Load data registers, word at a time int num_words = (length + 3) / 4;
// int num_words = (length + 3) / 4; for (int i = 0; i < num_words; i++) {
// for (int i = 0; i < num_words; i++) { uint32_t word = 0;
// uint32_t word = 0; uint32_t word_len = MIN(length, sizeof(word));
// uint32_t word_len = MIN(length, sizeof(word)); memcpy(&word, buffer, word_len);
// memcpy(&word, buffer, word_len); dev->data_buf[i].buf = word;
// dev->data_buf[i].buf = word; length -= word_len;
// length -= word_len; buffer = (void *)((intptr_t)buffer + word_len);
// buffer = (void *)((intptr_t)buffer + word_len); }
// }
abort();
} }
/** /**
@@ -145,11 +136,9 @@ static inline void gpspi_flash_ll_set_buffer_data(spi_dev_t *dev, const void *bu
*/ */
static inline void gpspi_flash_ll_user_start(spi_dev_t *dev, bool pe_ops) static inline void gpspi_flash_ll_user_start(spi_dev_t *dev, bool pe_ops)
{ {
// TODO: [ESP32C5] IDF-8698, IDF-8699 dev->cmd.update = 1;
// dev->cmd.update = 1; while (dev->cmd.update);
// while (dev->cmd.update); dev->cmd.usr = 1;
// dev->cmd.usr = 1;
abort();
} }
/** /**
@@ -159,9 +148,7 @@ static inline void gpspi_flash_ll_user_start(spi_dev_t *dev, bool pe_ops)
*/ */
static inline void gpspi_flash_ll_set_pe_bit(spi_dev_t *dev) static inline void gpspi_flash_ll_set_pe_bit(spi_dev_t *dev)
{ {
// TODO: [ESP32C5] IDF-8698, IDF-8699 // Not supported on GPSPI
// // Not supported on GPSPI
abort();
} }
/** /**
@@ -171,9 +158,7 @@ static inline void gpspi_flash_ll_set_pe_bit(spi_dev_t *dev)
*/ */
static inline void gpspi_flash_ll_set_hold_pol(spi_dev_t *dev, uint32_t pol_val) static inline void gpspi_flash_ll_set_hold_pol(spi_dev_t *dev, uint32_t pol_val)
{ {
// TODO: [ESP32C5] IDF-8698, IDF-8699 dev->ctrl.hold_pol = pol_val;
// dev->ctrl.hold_pol = pol_val;
abort();
} }
/** /**
@@ -185,10 +170,7 @@ static inline void gpspi_flash_ll_set_hold_pol(spi_dev_t *dev, uint32_t pol_val)
*/ */
static inline bool gpspi_flash_ll_host_idle(const spi_dev_t *dev) static inline bool gpspi_flash_ll_host_idle(const spi_dev_t *dev)
{ {
// TODO: [ESP32C5] IDF-8698, IDF-8699 return dev->cmd.usr == 0;
// return dev->cmd.usr == 0;
abort();
return (bool)0;
} }
/** /**
@@ -198,15 +180,13 @@ static inline bool gpspi_flash_ll_host_idle(const spi_dev_t *dev)
*/ */
static inline void gpspi_flash_ll_read_phase(spi_dev_t *dev) static inline void gpspi_flash_ll_read_phase(spi_dev_t *dev)
{ {
// TODO: [ESP32C5] IDF-8698, IDF-8699 typeof (dev->user) user = {
// typeof (dev->user) user = { .usr_mosi = 0,
// .usr_mosi = 0, .usr_miso = 1,
// .usr_miso = 1, .usr_addr = 1,
// .usr_addr = 1, .usr_command = 1,
// .usr_command = 1, };
// }; dev->user.val = user.val;
// dev->user.val = user.val;
abort();
} }
/*------------------------------------------------------------------------------ /*------------------------------------------------------------------------------
* Configs * Configs
@@ -219,10 +199,8 @@ static inline void gpspi_flash_ll_read_phase(spi_dev_t *dev)
*/ */
static inline void gpspi_flash_ll_set_cs_pin(spi_dev_t *dev, int pin) static inline void gpspi_flash_ll_set_cs_pin(spi_dev_t *dev, int pin)
{ {
// TODO: [ESP32C5] IDF-8698, IDF-8699 dev->misc.cs0_dis = (pin == 0) ? 0 : 1;
// dev->misc.cs0_dis = (pin == 0) ? 0 : 1; dev->misc.cs1_dis = (pin == 1) ? 0 : 1;
// dev->misc.cs1_dis = (pin == 1) ? 0 : 1;
abort();
} }
/** /**
@@ -233,44 +211,45 @@ static inline void gpspi_flash_ll_set_cs_pin(spi_dev_t *dev, int pin)
*/ */
static inline void gpspi_flash_ll_set_read_mode(spi_dev_t *dev, esp_flash_io_mode_t read_mode) static inline void gpspi_flash_ll_set_read_mode(spi_dev_t *dev, esp_flash_io_mode_t read_mode)
{ {
// TODO: [ESP32C5] IDF-8698, IDF-8699 typeof (dev->ctrl) ctrl;
// typeof (dev->ctrl) ctrl; ctrl.val = dev->ctrl.val;
// ctrl.val = dev->ctrl.val; typeof (dev->user) user;
// typeof (dev->user) user; user.val = dev->user.val;
// user.val = dev->user.val;
// // ctrl.val &= ~(SPI_FCMD_QUAD_M | SPI_FADDR_QUAD_M | SPI_FREAD_QUAD_M | SPI_FCMD_DUAL_M | SPI_FADDR_DUAL_M | SPI_FREAD_DUAL_M); ctrl.val &= ~(SPI_FCMD_QUAD_M | SPI_FADDR_QUAD_M | SPI_FREAD_QUAD_M | SPI_FCMD_DUAL_M | SPI_FADDR_DUAL_M | SPI_FREAD_DUAL_M);
// user.val &= ~(SPI_FWRITE_QUAD_M | SPI_FWRITE_DUAL_M); user.val &= ~(SPI_FWRITE_QUAD_M | SPI_FWRITE_DUAL_M);
// // switch (read_mode) {
// case SPI_FLASH_FASTRD: switch (read_mode) {
// //the default option case SPI_FLASH_FASTRD:
// case SPI_FLASH_SLOWRD: //the default option
// break; case SPI_FLASH_SLOWRD:
// case SPI_FLASH_QIO: break;
// ctrl.fread_quad = 1; case SPI_FLASH_QIO:
// ctrl.faddr_quad = 1; ctrl.fread_quad = 1;
// user.fwrite_quad = 1; ctrl.faddr_quad = 1;
// break; user.fwrite_quad = 1;
// case SPI_FLASH_QOUT: break;
// ctrl.fread_quad = 1; case SPI_FLASH_QOUT:
// user.fwrite_quad = 1; ctrl.fread_quad = 1;
// break; user.fwrite_quad = 1;
// case SPI_FLASH_DIO: break;
// ctrl.fread_dual = 1; case SPI_FLASH_DIO:
// ctrl.faddr_dual = 1; ctrl.fread_dual = 1;
// user.fwrite_dual = 1; ctrl.faddr_dual = 1;
// break; user.fwrite_dual = 1;
// case SPI_FLASH_DOUT: break;
// ctrl.fread_dual = 1; case SPI_FLASH_DOUT:
// user.fwrite_dual = 1; ctrl.fread_dual = 1;
// break; user.fwrite_dual = 1;
// default: break;
// abort(); default:
// }
// // dev->ctrl.val = ctrl.val;
// dev->user.val = user.val;
abort(); abort();
} }
dev->ctrl.val = ctrl.val;
dev->user.val = user.val;
}
/** /**
* Set clock frequency to work at. * Set clock frequency to work at.
* *
@@ -279,9 +258,7 @@ static inline void gpspi_flash_ll_set_read_mode(spi_dev_t *dev, esp_flash_io_mod
*/ */
static inline void gpspi_flash_ll_set_clock(spi_dev_t *dev, gpspi_flash_ll_clock_reg_t *clock_val) static inline void gpspi_flash_ll_set_clock(spi_dev_t *dev, gpspi_flash_ll_clock_reg_t *clock_val)
{ {
// TODO: [ESP32C5] IDF-8698, IDF-8699 dev->clock.val = *clock_val;
// dev->clock.val = *clock_val;
abort();
} }
/** /**
@@ -292,12 +269,10 @@ static inline void gpspi_flash_ll_set_clock(spi_dev_t *dev, gpspi_flash_ll_clock
*/ */
static inline void gpspi_flash_ll_set_miso_bitlen(spi_dev_t *dev, uint32_t bitlen) static inline void gpspi_flash_ll_set_miso_bitlen(spi_dev_t *dev, uint32_t bitlen)
{ {
// TODO: [ESP32C5] IDF-8698, IDF-8699 dev->user.usr_miso = bitlen > 0;
// dev->user.usr_miso = bitlen > 0; if (bitlen) {
// if (bitlen) { dev->ms_dlen.ms_data_bitlen = bitlen - 1;
// dev->ms_dlen.ms_data_bitlen = bitlen - 1; }
// }
abort();
} }
/** /**
@@ -309,12 +284,10 @@ static inline void gpspi_flash_ll_set_miso_bitlen(spi_dev_t *dev, uint32_t bitle
*/ */
static inline void gpspi_flash_ll_set_mosi_bitlen(spi_dev_t *dev, uint32_t bitlen) static inline void gpspi_flash_ll_set_mosi_bitlen(spi_dev_t *dev, uint32_t bitlen)
{ {
// TODO: [ESP32C5] IDF-8698, IDF-8699 dev->user.usr_mosi = bitlen > 0;
// dev->user.usr_mosi = bitlen > 0; if (bitlen) {
// if (bitlen) { dev->ms_dlen.ms_data_bitlen = bitlen - 1;
// dev->ms_dlen.ms_data_bitlen = bitlen - 1; }
// }
abort();
} }
/** /**
@@ -326,14 +299,12 @@ static inline void gpspi_flash_ll_set_mosi_bitlen(spi_dev_t *dev, uint32_t bitle
*/ */
static inline void gpspi_flash_ll_set_command(spi_dev_t *dev, uint8_t command, uint32_t bitlen) static inline void gpspi_flash_ll_set_command(spi_dev_t *dev, uint8_t command, uint32_t bitlen)
{ {
// TODO: [ESP32C5] IDF-8698, IDF-8699 dev->user.usr_command = 1;
// dev->user.usr_command = 1; typeof(dev->user2) user2 = {
// typeof(dev->user2) user2 = { .usr_command_value = command,
// .usr_command_value = command, .usr_command_bitlen = (bitlen - 1),
// .usr_command_bitlen = (bitlen - 1), };
// }; dev->user2.val = user2.val;
// dev->user2.val = user2.val;
abort();
} }
/** /**
@@ -344,10 +315,7 @@ static inline void gpspi_flash_ll_set_command(spi_dev_t *dev, uint8_t command, u
*/ */
static inline int gpspi_flash_ll_get_addr_bitlen(spi_dev_t *dev) static inline int gpspi_flash_ll_get_addr_bitlen(spi_dev_t *dev)
{ {
// TODO: [ESP32C5] IDF-8698, IDF-8699 return dev->user.usr_addr ? dev->user1.usr_addr_bitlen + 1 : 0;
// return dev->user.usr_addr ? dev->user1.usr_addr_bitlen + 1 : 0;
abort();
return (int)0;
} }
/** /**
@@ -358,10 +326,8 @@ static inline int gpspi_flash_ll_get_addr_bitlen(spi_dev_t *dev)
*/ */
static inline void gpspi_flash_ll_set_addr_bitlen(spi_dev_t *dev, uint32_t bitlen) static inline void gpspi_flash_ll_set_addr_bitlen(spi_dev_t *dev, uint32_t bitlen)
{ {
// TODO: [ESP32C5] IDF-8698, IDF-8699 dev->user1.usr_addr_bitlen = (bitlen - 1);
// dev->user1.usr_addr_bitlen = (bitlen - 1); dev->user.usr_addr = bitlen ? 1 : 0;
// dev->user.usr_addr = bitlen ? 1 : 0;
abort();
} }
/** /**
@@ -372,11 +338,9 @@ static inline void gpspi_flash_ll_set_addr_bitlen(spi_dev_t *dev, uint32_t bitle
*/ */
static inline void gpspi_flash_ll_set_usr_address(spi_dev_t *dev, uint32_t addr, uint32_t bitlen) static inline void gpspi_flash_ll_set_usr_address(spi_dev_t *dev, uint32_t addr, uint32_t bitlen)
{ {
// TODO: [ESP32C5] IDF-8698, IDF-8699 // The blank region should be all ones
// // The blank region should be all ones uint32_t padding_ones = (bitlen == 32? 0 : UINT32_MAX >> bitlen);
// uint32_t padding_ones = (bitlen == 32? 0 : UINT32_MAX >> bitlen); dev->addr.val = (addr << (32 - bitlen)) | padding_ones;
// dev->addr.val = (addr << (32 - bitlen)) | padding_ones;
abort();
} }
/** /**
@@ -387,9 +351,7 @@ static inline void gpspi_flash_ll_set_usr_address(spi_dev_t *dev, uint32_t addr,
*/ */
static inline void gpspi_flash_ll_set_address(spi_dev_t *dev, uint32_t addr) static inline void gpspi_flash_ll_set_address(spi_dev_t *dev, uint32_t addr)
{ {
// TODO: [ESP32C5] IDF-8698, IDF-8699 dev->addr.val = addr;
// dev->addr.val = addr;
abort();
} }
/** /**
@@ -400,10 +362,8 @@ static inline void gpspi_flash_ll_set_address(spi_dev_t *dev, uint32_t addr)
*/ */
static inline void gpspi_flash_ll_set_dummy(spi_dev_t *dev, uint32_t dummy_n) static inline void gpspi_flash_ll_set_dummy(spi_dev_t *dev, uint32_t dummy_n)
{ {
// TODO: [ESP32C5] IDF-8698, IDF-8699 dev->user.usr_dummy = dummy_n ? 1 : 0;
// dev->user.usr_dummy = dummy_n ? 1 : 0; HAL_FORCE_MODIFY_U32_REG_FIELD(dev->user1, usr_dummy_cyclelen, dummy_n - 1);
// HAL_FORCE_MODIFY_U32_REG_FIELD(dev->user1, usr_dummy_cyclelen, dummy_n - 1);
abort();
} }
/** /**
@@ -414,18 +374,14 @@ static inline void gpspi_flash_ll_set_dummy(spi_dev_t *dev, uint32_t dummy_n)
*/ */
static inline void gpspi_flash_ll_set_hold(spi_dev_t *dev, uint32_t hold_n) static inline void gpspi_flash_ll_set_hold(spi_dev_t *dev, uint32_t hold_n)
{ {
// TODO: [ESP32C5] IDF-8698, IDF-8699 dev->user1.cs_hold_time = hold_n - 1;
// dev->user1.cs_hold_time = hold_n - 1; dev->user.cs_hold = (hold_n > 0? 1: 0);
// dev->user.cs_hold = (hold_n > 0? 1: 0);
abort();
} }
static inline void gpspi_flash_ll_set_cs_setup(spi_dev_t *dev, uint32_t cs_setup_time) static inline void gpspi_flash_ll_set_cs_setup(spi_dev_t *dev, uint32_t cs_setup_time)
{ {
// TODO: [ESP32C5] IDF-8698, IDF-8699 dev->user.cs_setup = (cs_setup_time > 0 ? 1 : 0);
// dev->user.cs_setup = (cs_setup_time > 0 ? 1 : 0); dev->user1.cs_setup_time = cs_setup_time - 1;
// dev->user1.cs_setup_time = cs_setup_time - 1;
abort();
} }
/** /**
@@ -437,17 +393,14 @@ static inline void gpspi_flash_ll_set_cs_setup(spi_dev_t *dev, uint32_t cs_setup
*/ */
static inline uint32_t gpspi_flash_ll_calculate_clock_reg(uint8_t clkdiv) static inline uint32_t gpspi_flash_ll_calculate_clock_reg(uint8_t clkdiv)
{ {
// TODO: [ESP32C5] IDF-8698, IDF-8699 uint32_t div_parameter;
// uint32_t div_parameter; // See comments of `clock` in `spi_struct.h`
// // See comments of `clock` in `spi_struct.h` if (clkdiv == 1) {
// if (clkdiv == 1) { div_parameter = (1 << 31);
// div_parameter = (1 << 31); } else {
// } else { div_parameter = ((clkdiv - 1) | (((clkdiv/2 - 1) & 0xff) << 6 ) | (((clkdiv - 1) & 0xff) << 12));
// div_parameter = ((clkdiv - 1) | (((clkdiv/2 - 1) & 0xff) << 6 ) | (((clkdiv - 1) & 0xff) << 12)); }
// } return div_parameter;
// return div_parameter;
abort();
return (uint32_t)0;
} }
#ifdef __cplusplus #ifdef __cplusplus

29
components/hal/esp32c5/include/hal/spi_ll.h
View File

@@ -16,7 +16,6 @@
#include <stdlib.h> //for abs() #include <stdlib.h> //for abs()
#include <string.h> #include <string.h>
#include "sdkconfig.h" // TODO: [ESP32C5] IDF-8698 remove
#include "esp_types.h" #include "esp_types.h"
#include "soc/spi_periph.h" #include "soc/spi_periph.h"
#include "soc/spi_struct.h" #include "soc/spi_struct.h"
@@ -150,15 +149,12 @@ static inline void spi_ll_set_clk_source(spi_dev_t *hw, spi_clock_source_t clk_s
{ {
uint32_t clk_id = 0; uint32_t clk_id = 0;
switch (clk_source) { switch (clk_source) {
// TODO: [ESP32C5] IDF-8698
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
case SOC_MOD_CLK_PLL_F160M: case SOC_MOD_CLK_PLL_F160M:
clk_id = 1; clk_id = 1;
break; break;
case SOC_MOD_CLK_RC_FAST: case SOC_MOD_CLK_RC_FAST:
clk_id = 2; clk_id = 2;
break; break;
#endif
case SOC_MOD_CLK_XTAL: case SOC_MOD_CLK_XTAL:
clk_id = 0; clk_id = 0;
break; break;
@@ -317,7 +313,7 @@ static inline void spi_ll_slave_reset(spi_dev_t *hw)
/** /**
* Reset SPI CPU TX FIFO * Reset SPI CPU TX FIFO
* *
* On esp32c5, this function is not seperated * On esp32c5, this function is not separated
* *
* @param hw Beginning address of the peripheral registers. * @param hw Beginning address of the peripheral registers.
*/ */
@@ -330,7 +326,7 @@ static inline void spi_ll_cpu_tx_fifo_reset(spi_dev_t *hw)
/** /**
* Reset SPI CPU RX FIFO * Reset SPI CPU RX FIFO
* *
* On esp32c5, this function is not seperated * On esp32c5, this function is not separated
* *
* @param hw Beginning address of the peripheral registers. * @param hw Beginning address of the peripheral registers.
*/ */
@@ -430,15 +426,12 @@ static inline void spi_ll_dma_set_rx_eof_generation(spi_dev_t *hw, bool enable)
*/ */
static inline void spi_ll_write_buffer(spi_dev_t *hw, const uint8_t *buffer_to_send, size_t bitlen) static inline void spi_ll_write_buffer(spi_dev_t *hw, const uint8_t *buffer_to_send, size_t bitlen)
{ {
// TODO: [ESP32C5] IDF-8698
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
for (int x = 0; x < bitlen; x += 32) { for (int x = 0; x < bitlen; x += 32) {
//Use memcpy to get around alignment issues for txdata //Use memcpy to get around alignment issues for txdata
uint32_t word; uint32_t word;
memcpy(&word, &buffer_to_send[x / 8], 4); memcpy(&word, &buffer_to_send[x / 8], 4);
hw->data_buf[(x / 32)].buf = word; hw->data_buf[(x / 32)].buf = word;
} }
#endif
} }
/** /**
@@ -454,8 +447,7 @@ static inline void spi_ll_write_buffer_byte(spi_dev_t *hw, int byte_id, uint8_t
HAL_ASSERT(byte_id + len <= 64); HAL_ASSERT(byte_id + len <= 64);
HAL_ASSERT(len > 0); HAL_ASSERT(len > 0);
HAL_ASSERT(byte_id >= 0); HAL_ASSERT(byte_id >= 0);
// TODO: [ESP32C5] IDF-8698
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
while (len > 0) { while (len > 0) {
uint32_t word; uint32_t word;
int offset = byte_id % 4; int offset = byte_id % 4;
@@ -475,7 +467,6 @@ static inline void spi_ll_write_buffer_byte(spi_dev_t *hw, int byte_id, uint8_t
byte_id += copy_len; byte_id += copy_len;
len -= copy_len; len -= copy_len;
} }
#endif
} }
/** /**
@@ -487,8 +478,6 @@ static inline void spi_ll_write_buffer_byte(spi_dev_t *hw, int byte_id, uint8_t
*/ */
static inline void spi_ll_read_buffer(spi_dev_t *hw, uint8_t *buffer_to_rcv, size_t bitlen) static inline void spi_ll_read_buffer(spi_dev_t *hw, uint8_t *buffer_to_rcv, size_t bitlen)
{ {
// TODO: [ESP32C5] IDF-8698
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
for (int x = 0; x < bitlen; x += 32) { for (int x = 0; x < bitlen; x += 32) {
//Do a memcpy to get around possible alignment issues in rx_buffer //Do a memcpy to get around possible alignment issues in rx_buffer
uint32_t word = hw->data_buf[x / 32].buf; uint32_t word = hw->data_buf[x / 32].buf;
@@ -498,7 +487,6 @@ static inline void spi_ll_read_buffer(spi_dev_t *hw, uint8_t *buffer_to_rcv, siz
} }
memcpy(&buffer_to_rcv[x / 8], &word, (len + 7) / 8); memcpy(&buffer_to_rcv[x / 8], &word, (len + 7) / 8);
} }
#endif
} }
/** /**
@@ -511,8 +499,6 @@ static inline void spi_ll_read_buffer(spi_dev_t *hw, uint8_t *buffer_to_rcv, siz
*/ */
static inline void spi_ll_read_buffer_byte(spi_dev_t *hw, int byte_id, uint8_t *out_data, int len) static inline void spi_ll_read_buffer_byte(spi_dev_t *hw, int byte_id, uint8_t *out_data, int len)
{ {
// TODO: [ESP32C5] IDF-8698
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
while (len > 0) { while (len > 0) {
uint32_t word = hw->data_buf[byte_id / 4].buf; uint32_t word = hw->data_buf[byte_id / 4].buf;
int offset = byte_id % 4; int offset = byte_id % 4;
@@ -526,7 +512,6 @@ static inline void spi_ll_read_buffer_byte(spi_dev_t *hw, int byte_id, uint8_t *
out_data += copy_len; out_data += copy_len;
len -= copy_len; len -= copy_len;
} }
#endif
} }
/*------------------------------------------------------------------------------ /*------------------------------------------------------------------------------
@@ -726,7 +711,7 @@ static inline void spi_ll_master_set_clock_by_reg(spi_dev_t *hw, const spi_ll_cl
* Get the frequency of given dividers. Don't use in app. * Get the frequency of given dividers. Don't use in app.
* *
* @param fapb APB clock of the system. * @param fapb APB clock of the system.
* @param pre Pre devider. * @param pre Pre divider.
* @param n Main divider. * @param n Main divider.
* *
* @return Frequency of given dividers. * @return Frequency of given dividers.
@@ -737,10 +722,10 @@ static inline int spi_ll_freq_for_pre_n(int fapb, int pre, int n)
} }
/** /**
* Calculate the nearest frequency avaliable for master. * Calculate the nearest frequency available for master.
* *
* @param fapb APB clock of the system. * @param fapb APB clock of the system.
* @param hz Frequncy desired. * @param hz Frequency desired.
* @param duty_cycle Duty cycle desired. * @param duty_cycle Duty cycle desired.
* @param out_reg Output address to store the calculated clock configurations for the return frequency. * @param out_reg Output address to store the calculated clock configurations for the return frequency.
* *
@@ -820,7 +805,7 @@ static inline int spi_ll_master_cal_clock(int fapb, int hz, int duty_cycle, spi_
* *
* @param hw Beginning address of the peripheral registers. * @param hw Beginning address of the peripheral registers.
* @param fapb APB clock of the system. * @param fapb APB clock of the system.
* @param hz Frequncy desired. * @param hz Frequency desired.
* @param duty_cycle Duty cycle desired. * @param duty_cycle Duty cycle desired.
* *
* @return Actual frequency that is used. * @return Actual frequency that is used.

2
components/soc/esp32c5/beta3/spi_periph.c
View File

@@ -12,7 +12,7 @@
*/ */
const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = { const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = {
{ {
// MSPI on P4 has dedicated iomux pins // MSPI has dedicated iomux pins
.spiclk_out = -1, .spiclk_out = -1,
.spiclk_in = -1, .spiclk_in = -1,
.spid_out = -1, .spid_out = -1,

40
components/soc/esp32c5/mp/include/soc/Kconfig.soc_caps.in
View File

@@ -43,6 +43,10 @@ config SOC_RTC_MEM_SUPPORTED
bool bool
default y default y
config SOC_GPSPI_SUPPORTED
bool
default y
config SOC_SYSTIMER_SUPPORTED config SOC_SYSTIMER_SUPPORTED
bool bool
default y default y
@@ -307,6 +311,42 @@ config SOC_SPI_MAX_CS_NUM
int int
default 6 default 6
config SOC_SPI_MAXIMUM_BUFFER_SIZE
int
default 64
config SOC_SPI_SUPPORT_DDRCLK
bool
default y
config SOC_SPI_SLAVE_SUPPORT_SEG_TRANS
bool
default y
config SOC_SPI_SUPPORT_CD_SIG
bool
default y
config SOC_SPI_SUPPORT_CONTINUOUS_TRANS
bool
default y
config SOC_SPI_SUPPORT_SLAVE_HD_VER2
bool
default y
config SOC_SPI_SUPPORT_CLK_XTAL
bool
default y
config SOC_MEMSPI_IS_INDEPENDENT
bool
default y
config SOC_SPI_MAX_PRE_DIVIDER
int
default 16
config SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED config SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED
bool bool
default y default y

12
components/soc/esp32c5/mp/include/soc/clk_tree_defs.h
View File

@@ -364,16 +364,20 @@ typedef enum { // TODO: [ESP32C5] IDF-8695 (inherit from C6)
/** /**
* @brief Array initializer for all supported clock sources of SPI * @brief Array initializer for all supported clock sources of SPI
*/ */
#define SOC_SPI_CLKS {SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST} #define SOC_SPI_CLKS {SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST}
/** /**
* @brief Type of SPI clock source. * @brief Type of SPI clock source.
*/ */
typedef enum { // TODO: [ESP32C5] IDF-8698, IDF-8699 (inherit from C6) typedef enum {
SPI_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_80M as SPI source clock */
SPI_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_80M as SPI source clock */
SPI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as SPI source clock */ SPI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as SPI source clock */
SPI_CLK_SRC_PLL_F160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_160M as SPI source clock */
SPI_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as SPI source clock */ SPI_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as SPI source clock */
#if SOC_CLK_TREE_SUPPORTED
SPI_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_80M as SPI source clock */
#else
SPI_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select PLL_80M as SPI source clock */
#endif
} soc_periph_spi_clk_src_t; } soc_periph_spi_clk_src_t;
//////////////////////////////////////////////////SDM////////////////////////////////////////////////////////////// //////////////////////////////////////////////////SDM//////////////////////////////////////////////////////////////

1
components/soc/esp32c5/mp/include/soc/io_mux_reg.h
View File

@@ -131,7 +131,6 @@ extern "C" {
#define GPIO_PAD_PULLDOWN(num) do{PIN_PULLUP_DIS(IOMUX_REG_GPIO##num);PIN_PULLDWN_EN(IOMUX_REG_GPIO##num);}while(0) #define GPIO_PAD_PULLDOWN(num) do{PIN_PULLUP_DIS(IOMUX_REG_GPIO##num);PIN_PULLDWN_EN(IOMUX_REG_GPIO##num);}while(0)
#define GPIO_PAD_SET_DRV(num, drv) PIN_SET_DRV(IOMUX_REG_GPIO##num, drv) #define GPIO_PAD_SET_DRV(num, drv) PIN_SET_DRV(IOMUX_REG_GPIO##num, drv)
// TODO: [ESP32C5] IDF-8698 need check
#define SPI_HD_GPIO_NUM 20 #define SPI_HD_GPIO_NUM 20
#define SPI_WP_GPIO_NUM 18 #define SPI_WP_GPIO_NUM 18
#define SPI_CS0_GPIO_NUM 16 #define SPI_CS0_GPIO_NUM 16

21
components/soc/esp32c5/mp/include/soc/soc_caps.h
View File

@@ -41,7 +41,7 @@
// #define SOC_I2S_SUPPORTED 1 // TODO: [ESP32C5] IDF-8713, IDF-8714 // #define SOC_I2S_SUPPORTED 1 // TODO: [ESP32C5] IDF-8713, IDF-8714
// #define SOC_RMT_SUPPORTED 1 // TODO: [ESP32C5] IDF-8726 // #define SOC_RMT_SUPPORTED 1 // TODO: [ESP32C5] IDF-8726
// #define SOC_SDM_SUPPORTED 1 // TODO: [ESP32C5] IDF-8687 // #define SOC_SDM_SUPPORTED 1 // TODO: [ESP32C5] IDF-8687
// #define SOC_GPSPI_SUPPORTED 1 // TODO: [ESP32C5] IDF-8698, IDF-8699 #define SOC_GPSPI_SUPPORTED 1
// #define SOC_LEDC_SUPPORTED 1 // TODO: [ESP32C5] IDF-8684 // #define SOC_LEDC_SUPPORTED 1 // TODO: [ESP32C5] IDF-8684
// #define SOC_I2C_SUPPORTED 1 // TODO: [ESP32C5] IDF-8694, IDF-8696 // #define SOC_I2C_SUPPORTED 1 // TODO: [ESP32C5] IDF-8694, IDF-8696
#define SOC_SYSTIMER_SUPPORTED 1 // TODO: [ESP32C5] IDF-8707 #define SOC_SYSTIMER_SUPPORTED 1 // TODO: [ESP32C5] IDF-8707
@@ -383,15 +383,14 @@
#define SOC_SPI_PERIPH_NUM 2 #define SOC_SPI_PERIPH_NUM 2
#define SOC_SPI_PERIPH_CS_NUM(i) 6 #define SOC_SPI_PERIPH_CS_NUM(i) 6
#define SOC_SPI_MAX_CS_NUM 6 #define SOC_SPI_MAX_CS_NUM 6
#define SOC_SPI_MAXIMUM_BUFFER_SIZE 64
// #define SOC_SPI_MAXIMUM_BUFFER_SIZE 64 #define SOC_SPI_SUPPORT_DDRCLK 1
#define SOC_SPI_SLAVE_SUPPORT_SEG_TRANS 1
// #define SOC_SPI_SUPPORT_DDRCLK 1 #define SOC_SPI_SUPPORT_CD_SIG 1
// #define SOC_SPI_SLAVE_SUPPORT_SEG_TRANS 1 #define SOC_SPI_SUPPORT_CONTINUOUS_TRANS 1
// #define SOC_SPI_SUPPORT_CD_SIG 1 #define SOC_SPI_SUPPORT_SLAVE_HD_VER2 1
// #define SOC_SPI_SUPPORT_CONTINUOUS_TRANS 1 #define SOC_SPI_SUPPORT_CLK_XTAL 1
// #define SOC_SPI_SUPPORT_SLAVE_HD_VER2 1
// #define SOC_SPI_SUPPORT_CLK_XTAL 1
// #define SOC_SPI_SUPPORT_CLK_PLL_F80M 1 // #define SOC_SPI_SUPPORT_CLK_PLL_F80M 1
// #define SOC_SPI_SUPPORT_CLK_RC_FAST 1 // #define SOC_SPI_SUPPORT_CLK_RC_FAST 1
@@ -399,8 +398,8 @@
// host_id = 0 -> SPI0/SPI1, host_id = 1 -> SPI2, // host_id = 0 -> SPI0/SPI1, host_id = 1 -> SPI2,
#define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(host_id) ({(void)host_id; 1;}) #define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(host_id) ({(void)host_id; 1;})
// #define SOC_MEMSPI_IS_INDEPENDENT 1 #define SOC_MEMSPI_IS_INDEPENDENT 1
// #define SOC_SPI_MAX_PRE_DIVIDER 16 #define SOC_SPI_MAX_PRE_DIVIDER 16
/*-------------------------- SPI MEM CAPS ---------------------------------------*/ /*-------------------------- SPI MEM CAPS ---------------------------------------*/
// #define SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE (1) // #define SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE (1)

18
components/soc/esp32c5/mp/include/soc/spi_pins.h
View File

@@ -5,16 +5,16 @@
*/ */
#pragma once #pragma once
#include "soc/io_mux_reg.h"
// TODO: [ESP32C5] IDF-8698 (inherit from C6) // MSPI IO_MUX pin
#define SPI_FUNC_NUM 0 #define SPI_FUNC_NUM 0
#define SPI_IOMUX_PIN_NUM_CS 24 #define SPI_IOMUX_PIN_NUM_CS SPI_CS0_GPIO_NUM
#define SPI_IOMUX_PIN_NUM_CLK 29 #define SPI_IOMUX_PIN_NUM_CLK SPI_CLK_GPIO_NUM
#define SPI_IOMUX_PIN_NUM_MOSI 30 #define SPI_IOMUX_PIN_NUM_MOSI SPI_D_GPIO_NUM
#define SPI_IOMUX_PIN_NUM_MISO 25 #define SPI_IOMUX_PIN_NUM_MISO SPI_Q_GPIO_NUM
#define SPI_IOMUX_PIN_NUM_WP 26 #define SPI_IOMUX_PIN_NUM_WP SPI_WP_GPIO_NUM
#define SPI_IOMUX_PIN_NUM_HD 28 #define SPI_IOMUX_PIN_NUM_HD SPI_HD_GPIO_NUM
#define SPI2_FUNC_NUM 2 #define SPI2_FUNC_NUM 2
#define SPI2_IOMUX_PIN_NUM_MISO 2 #define SPI2_IOMUX_PIN_NUM_MISO 2
@@ -22,4 +22,4 @@
#define SPI2_IOMUX_PIN_NUM_WP 5 #define SPI2_IOMUX_PIN_NUM_WP 5
#define SPI2_IOMUX_PIN_NUM_CLK 6 #define SPI2_IOMUX_PIN_NUM_CLK 6
#define SPI2_IOMUX_PIN_NUM_MOSI 7 #define SPI2_IOMUX_PIN_NUM_MOSI 7
#define SPI2_IOMUX_PIN_NUM_CS 16 #define SPI2_IOMUX_PIN_NUM_CS 10

223
components/soc/esp32c5/mp/include/soc/spi_struct.h
View File

@@ -819,7 +819,7 @@ typedef union {
/** clk_equ_sysclk : R/W; bitpos: [31]; default: 1; /** clk_equ_sysclk : R/W; bitpos: [31]; default: 1;
* Configures whether or not the SPI_CLK is equal to APB_CLK in master transfer.\\ * Configures whether or not the SPI_CLK is equal to APB_CLK in master transfer.\\
* 0: SPI_CLK is divided from APB_CLK.\\ * 0: SPI_CLK is divided from APB_CLK.\\
* 1: SPI_CLK is eqaul to APB_CLK.\\ * 1: SPI_CLK is equal to APB_CLK.\\
* Can be configured in CONF state. * Can be configured in CONF state.
*/ */
uint32_t clk_equ_sysclk:1; uint32_t clk_equ_sysclk:1;
@@ -1555,7 +1555,7 @@ typedef union {
/** Group: CPU-controlled data buffer */ /** Group: CPU-controlled data buffer */
/** Type of w0 register /** Type of wn register
* SPI CPU-controlled buffer0 * SPI CPU-controlled buffer0
*/ */
typedef union { typedef union {
@@ -1563,206 +1563,10 @@ typedef union {
/** buf0 : R/W/SS; bitpos: [31:0]; default: 0; /** buf0 : R/W/SS; bitpos: [31:0]; default: 0;
* 32-bit data buffer $n. * 32-bit data buffer $n.
*/ */
uint32_t buf0:32; uint32_t buf:32;
}; };
uint32_t val; uint32_t val;
} spi_w0_reg_t; } spi_wn_reg_t;
/** Type of w1 register
* SPI CPU-controlled buffer1
*/
typedef union {
struct {
/** buf1 : R/W/SS; bitpos: [31:0]; default: 0;
* 32-bit data buffer $n.
*/
uint32_t buf1:32;
};
uint32_t val;
} spi_w1_reg_t;
/** Type of w2 register
* SPI CPU-controlled buffer2
*/
typedef union {
struct {
/** buf2 : R/W/SS; bitpos: [31:0]; default: 0;
* 32-bit data buffer $n.
*/
uint32_t buf2:32;
};
uint32_t val;
} spi_w2_reg_t;
/** Type of w3 register
* SPI CPU-controlled buffer3
*/
typedef union {
struct {
/** buf3 : R/W/SS; bitpos: [31:0]; default: 0;
* 32-bit data buffer $n.
*/
uint32_t buf3:32;
};
uint32_t val;
} spi_w3_reg_t;
/** Type of w4 register
* SPI CPU-controlled buffer4
*/
typedef union {
struct {
/** buf4 : R/W/SS; bitpos: [31:0]; default: 0;
* 32-bit data buffer $n.
*/
uint32_t buf4:32;
};
uint32_t val;
} spi_w4_reg_t;
/** Type of w5 register
* SPI CPU-controlled buffer5
*/
typedef union {
struct {
/** buf5 : R/W/SS; bitpos: [31:0]; default: 0;
* 32-bit data buffer $n.
*/
uint32_t buf5:32;
};
uint32_t val;
} spi_w5_reg_t;
/** Type of w6 register
* SPI CPU-controlled buffer6
*/
typedef union {
struct {
/** buf6 : R/W/SS; bitpos: [31:0]; default: 0;
* 32-bit data buffer $n.
*/
uint32_t buf6:32;
};
uint32_t val;
} spi_w6_reg_t;
/** Type of w7 register
* SPI CPU-controlled buffer7
*/
typedef union {
struct {
/** buf7 : R/W/SS; bitpos: [31:0]; default: 0;
* 32-bit data buffer $n.
*/
uint32_t buf7:32;
};
uint32_t val;
} spi_w7_reg_t;
/** Type of w8 register
* SPI CPU-controlled buffer8
*/
typedef union {
struct {
/** buf8 : R/W/SS; bitpos: [31:0]; default: 0;
* 32-bit data buffer $n.
*/
uint32_t buf8:32;
};
uint32_t val;
} spi_w8_reg_t;
/** Type of w9 register
* SPI CPU-controlled buffer9
*/
typedef union {
struct {
/** buf9 : R/W/SS; bitpos: [31:0]; default: 0;
* 32-bit data buffer $n.
*/
uint32_t buf9:32;
};
uint32_t val;
} spi_w9_reg_t;
/** Type of w10 register
* SPI CPU-controlled buffer10
*/
typedef union {
struct {
/** buf10 : R/W/SS; bitpos: [31:0]; default: 0;
* 32-bit data buffer $n.
*/
uint32_t buf10:32;
};
uint32_t val;
} spi_w10_reg_t;
/** Type of w11 register
* SPI CPU-controlled buffer11
*/
typedef union {
struct {
/** buf11 : R/W/SS; bitpos: [31:0]; default: 0;
* 32-bit data buffer $n.
*/
uint32_t buf11:32;
};
uint32_t val;
} spi_w11_reg_t;
/** Type of w12 register
* SPI CPU-controlled buffer12
*/
typedef union {
struct {
/** buf12 : R/W/SS; bitpos: [31:0]; default: 0;
* 32-bit data buffer $n.
*/
uint32_t buf12:32;
};
uint32_t val;
} spi_w12_reg_t;
/** Type of w13 register
* SPI CPU-controlled buffer13
*/
typedef union {
struct {
/** buf13 : R/W/SS; bitpos: [31:0]; default: 0;
* 32-bit data buffer $n.
*/
uint32_t buf13:32;
};
uint32_t val;
} spi_w13_reg_t;
/** Type of w14 register
* SPI CPU-controlled buffer14
*/
typedef union {
struct {
/** buf14 : R/W/SS; bitpos: [31:0]; default: 0;
* 32-bit data buffer $n.
*/
uint32_t buf14:32;
};
uint32_t val;
} spi_w14_reg_t;
/** Type of w15 register
* SPI CPU-controlled buffer15
*/
typedef union {
struct {
/** buf15 : R/W/SS; bitpos: [31:0]; default: 0;
* 32-bit data buffer $n.
*/
uint32_t buf15:32;
};
uint32_t val;
} spi_w15_reg_t;
/** Group: Version register */ /** Group: Version register */
/** Type of date register /** Type of date register
@@ -1797,25 +1601,10 @@ typedef struct {
volatile spi_dma_int_ena_reg_t dma_int_ena; volatile spi_dma_int_ena_reg_t dma_int_ena;
volatile spi_dma_int_clr_reg_t dma_int_clr; volatile spi_dma_int_clr_reg_t dma_int_clr;
volatile spi_dma_int_raw_reg_t dma_int_raw; volatile spi_dma_int_raw_reg_t dma_int_raw;
volatile spi_dma_int_st_reg_t dma_int_st; volatile spi_dma_int_st_reg_t dma_int_sta;
volatile spi_dma_int_set_reg_t dma_int_set; volatile spi_dma_int_set_reg_t dma_int_set;
uint32_t reserved_048[20]; uint32_t reserved_048[20];
volatile spi_w0_reg_t w0; volatile spi_wn_reg_t data_buf[16];
volatile spi_w1_reg_t w1;
volatile spi_w2_reg_t w2;
volatile spi_w3_reg_t w3;
volatile spi_w4_reg_t w4;
volatile spi_w5_reg_t w5;
volatile spi_w6_reg_t w6;
volatile spi_w7_reg_t w7;
volatile spi_w8_reg_t w8;
volatile spi_w9_reg_t w9;
volatile spi_w10_reg_t w10;
volatile spi_w11_reg_t w11;
volatile spi_w12_reg_t w12;
volatile spi_w13_reg_t w13;
volatile spi_w14_reg_t w14;
volatile spi_w15_reg_t w15;
uint32_t reserved_0d8[2]; uint32_t reserved_0d8[2];
volatile spi_slave_reg_t slave; volatile spi_slave_reg_t slave;
volatile spi_slave1_reg_t slave1; volatile spi_slave1_reg_t slave1;

64
components/soc/esp32c5/mp/spi_periph.c Normal file
View File

@@ -0,0 +1,64 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <stddef.h>
#include "soc/spi_periph.h"
/*
Bunch of constants for every SPI peripheral: GPIO signals, irqs, hw addr of registers etc
*/
const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = {
{
// MSPI has dedicated iomux pins
.spiclk_out = -1,
.spiclk_in = -1,
.spid_out = -1,
.spiq_out = -1,
.spiwp_out = -1,
.spihd_out = -1,
.spid_in = -1,
.spiq_in = -1,
.spiwp_in = -1,
.spihd_in = -1,
.spics_out = {-1},
.spics_in = -1,
.spiclk_iomux_pin = -1,
.spid_iomux_pin = -1,
.spiq_iomux_pin = -1,
.spiwp_iomux_pin = -1,
.spihd_iomux_pin = -1,
.spics0_iomux_pin = -1,
.irq = -1,
.irq_dma = -1,
.module = -1,
.hw = NULL,
.func = -1,
}, {
.spiclk_out = FSPICLK_OUT_IDX,
.spiclk_in = FSPICLK_IN_IDX,
.spid_out = FSPID_OUT_IDX,
.spiq_out = FSPIQ_OUT_IDX,
.spiwp_out = FSPIWP_OUT_IDX,
.spihd_out = FSPIHD_OUT_IDX,
.spid_in = FSPID_IN_IDX,
.spiq_in = FSPIQ_IN_IDX,
.spiwp_in = FSPIWP_IN_IDX,
.spihd_in = FSPIHD_IN_IDX,
.spics_out = {FSPICS0_OUT_IDX, FSPICS1_OUT_IDX, FSPICS2_OUT_IDX, FSPICS3_OUT_IDX, FSPICS4_OUT_IDX, FSPICS5_OUT_IDX},
.spics_in = FSPICS0_IN_IDX,
.spiclk_iomux_pin = SPI2_IOMUX_PIN_NUM_CLK,
.spid_iomux_pin = SPI2_IOMUX_PIN_NUM_MOSI,
.spiq_iomux_pin = SPI2_IOMUX_PIN_NUM_MISO,
.spiwp_iomux_pin = SPI2_IOMUX_PIN_NUM_WP,
.spihd_iomux_pin = SPI2_IOMUX_PIN_NUM_HD,
.spics0_iomux_pin = SPI2_IOMUX_PIN_NUM_CS,
.irq = ETS_GPSPI2_INTR_SOURCE,
.irq_dma = -1,
.module = -1,
.hw = &GPSPI2,
.func = SPI2_FUNC_NUM,
},
};

2
components/spi_flash/test_apps/esp_flash/main/test_esp_flash_def.h
View File

@@ -68,7 +68,7 @@
#define HSPI_PIN_NUM_WP FSPI_PIN_NUM_WP #define HSPI_PIN_NUM_WP FSPI_PIN_NUM_WP
#define HSPI_PIN_NUM_CS FSPI_PIN_NUM_CS #define HSPI_PIN_NUM_CS FSPI_PIN_NUM_CS
#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 #elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C5
#define SPI1_CS_IO 26 //the pin which is usually used by the PSRAM cs #define SPI1_CS_IO 26 //the pin which is usually used by the PSRAM cs
#define SPI1_HD_IO 27 //the pin which is usually used by the PSRAM hd #define SPI1_HD_IO 27 //the pin which is usually used by the PSRAM hd
#define SPI1_WP_IO 28 //the pin which is usually used by the PSRAM wp #define SPI1_WP_IO 28 //the pin which is usually used by the PSRAM wp

10
docs/en/api-reference/peripherals/spi_master.rst
View File

@@ -473,7 +473,7 @@ GPIO Matrix and IO_MUX
.. only:: not esp32 .. only:: not esp32
{IDF_TARGET_SPI2_IOMUX_PIN_CS:default="N/A", esp32s2="10", esp32s3="10", esp32c2="10", esp32c3="10", esp32c6="16", esp32h2="1", esp32p4="7", esp32c5="12"} {IDF_TARGET_SPI2_IOMUX_PIN_CS:default="N/A", esp32s2="10", esp32s3="10", esp32c2="10", esp32c3="10", esp32c6="16", esp32h2="1", esp32p4="7", esp32c5="10"}
{IDF_TARGET_SPI2_IOMUX_PIN_CLK:default="N/A", esp32s2="12", esp32s3="12", esp32c2="6", esp32c3="6", esp32c6="6", esp32h2="4", esp32p4="9", esp32c5="6"} {IDF_TARGET_SPI2_IOMUX_PIN_CLK:default="N/A", esp32s2="12", esp32s3="12", esp32c2="6", esp32c3="6", esp32c6="6", esp32h2="4", esp32p4="9", esp32c5="6"}
{IDF_TARGET_SPI2_IOMUX_PIN_MOSI:default="N/A", esp32s2="11" esp32s3="11", esp32c2="7" esp32c3="7", esp32c6="7", esp32h2="5", esp32p4="8", esp32c5="7"} {IDF_TARGET_SPI2_IOMUX_PIN_MOSI:default="N/A", esp32s2="11" esp32s3="11", esp32c2="7" esp32c3="7", esp32c6="7", esp32h2="5", esp32p4="8", esp32c5="7"}
{IDF_TARGET_SPI2_IOMUX_PIN_MISO:default="N/A", esp32s2="13" esp32s3="13", esp32c2="2" esp32c3="2", esp32c6="2", esp32h2="0", esp32p4="10", esp32c5="2"} {IDF_TARGET_SPI2_IOMUX_PIN_MISO:default="N/A", esp32s2="13" esp32s3="13", esp32c2="2" esp32c3="2", esp32c6="2", esp32h2="0", esp32p4="10", esp32c5="2"}
@@ -524,10 +524,10 @@ The main parameter that determines the transfer speed for large transactions is
Transaction Duration Transaction Duration
^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^
{IDF_TARGET_TRANS_TIME_INTR_DMA:default="N/A", esp32="28", esp32s2="23", esp32c3="28", esp32s3="26", esp32c2="42", esp32c6="34", esp32h2="58", esp32c5="27"} {IDF_TARGET_TRANS_TIME_INTR_DMA:default="N/A", esp32="28", esp32s2="23", esp32c3="28", esp32s3="26", esp32c2="42", esp32c6="34", esp32h2="58"}
{IDF_TARGET_TRANS_TIME_POLL_DMA:default="N/A", esp32="10", esp32s2="9", esp32c3="10", esp32s3="11", esp32c2="17", esp32c6="17", esp32h2="28", esp32c5="16"} {IDF_TARGET_TRANS_TIME_POLL_DMA:default="N/A", esp32="10", esp32s2="9", esp32c3="10", esp32s3="11", esp32c2="17", esp32c6="17", esp32h2="28"}
{IDF_TARGET_TRANS_TIME_INTR_CPU:default="N/A", esp32="25", esp32s2="22", esp32c3="27", esp32s3="24", esp32c2="40", esp32c6="32", esp32h2="54", esp32c5="24"} {IDF_TARGET_TRANS_TIME_INTR_CPU:default="N/A", esp32="25", esp32s2="22", esp32c3="27", esp32s3="24", esp32c2="40", esp32c6="32", esp32h2="54"}
{IDF_TARGET_TRANS_TIME_POLL_CPU:default="N/A", esp32="8", esp32s2="8", esp32c3="9", esp32s3="9", esp32c2="15", esp32c6="15", esp32h2="24", esp32c5="13"} {IDF_TARGET_TRANS_TIME_POLL_CPU:default="N/A", esp32="8", esp32s2="8", esp32c3="9", esp32s3="9", esp32c2="15", esp32c6="15", esp32h2="24"}
Transaction duration includes setting up SPI peripheral registers, copying data to FIFOs or setting up DMA links, and the time for SPI transactions. Transaction duration includes setting up SPI peripheral registers, copying data to FIFOs or setting up DMA links, and the time for SPI transactions.

10
docs/zh_CN/api-reference/peripherals/spi_master.rst
View File

@@ -473,7 +473,7 @@ GPIO 矩阵与 IO_MUX 管脚
.. only:: not esp32 .. only:: not esp32
{IDF_TARGET_SPI2_IOMUX_PIN_CS:default="N/A", esp32s2="10", esp32s3="10", esp32c2="10", esp32c3="10", esp32c6="16", esp32h2="1", esp32p4="7", esp32c5="12"} {IDF_TARGET_SPI2_IOMUX_PIN_CS:default="N/A", esp32s2="10", esp32s3="10", esp32c2="10", esp32c3="10", esp32c6="16", esp32h2="1", esp32p4="7", esp32c5="10"}
{IDF_TARGET_SPI2_IOMUX_PIN_CLK:default="N/A", esp32s2="12", esp32s3="12", esp32c2="6", esp32c3="6", esp32c6="6", esp32h2="4", esp32p4="9", esp32c5="6"} {IDF_TARGET_SPI2_IOMUX_PIN_CLK:default="N/A", esp32s2="12", esp32s3="12", esp32c2="6", esp32c3="6", esp32c6="6", esp32h2="4", esp32p4="9", esp32c5="6"}
{IDF_TARGET_SPI2_IOMUX_PIN_MOSI:default="N/A", esp32s2="11" esp32s3="11", esp32c2="7" esp32c3="7", esp32c6="7", esp32h2="5", esp32p4="8", esp32c5="7"} {IDF_TARGET_SPI2_IOMUX_PIN_MOSI:default="N/A", esp32s2="11" esp32s3="11", esp32c2="7" esp32c3="7", esp32c6="7", esp32h2="5", esp32p4="8", esp32c5="7"}
{IDF_TARGET_SPI2_IOMUX_PIN_MISO:default="N/A", esp32s2="13" esp32s3="13", esp32c2="2" esp32c3="2", esp32c6="2", esp32h2="0", esp32p4="10", esp32c5="2"} {IDF_TARGET_SPI2_IOMUX_PIN_MISO:default="N/A", esp32s2="13" esp32s3="13", esp32c2="2" esp32c3="2", esp32c6="2", esp32h2="0", esp32p4="10", esp32c5="2"}
@@ -524,10 +524,10 @@ GPIO 矩阵与 IO_MUX 管脚
传输事务持续时间 传输事务持续时间
^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^
{IDF_TARGET_TRANS_TIME_INTR_DMA:default="N/A", esp32="28", esp32s2="23", esp32c3="28", esp32s3="26", esp32c2="42", esp32c6="34", esp32h2="58", esp32c5="27"} {IDF_TARGET_TRANS_TIME_INTR_DMA:default="N/A", esp32="28", esp32s2="23", esp32c3="28", esp32s3="26", esp32c2="42", esp32c6="34", esp32h2="58"}
{IDF_TARGET_TRANS_TIME_POLL_DMA:default="N/A", esp32="10", esp32s2="9", esp32c3="10", esp32s3="11", esp32c2="17", esp32c6="17", esp32h2="28", esp32c5="16"} {IDF_TARGET_TRANS_TIME_POLL_DMA:default="N/A", esp32="10", esp32s2="9", esp32c3="10", esp32s3="11", esp32c2="17", esp32c6="17", esp32h2="28"}
{IDF_TARGET_TRANS_TIME_INTR_CPU:default="N/A", esp32="25", esp32s2="22", esp32c3="27", esp32s3="24", esp32c2="40", esp32c6="32", esp32h2="54", esp32c5="24"} {IDF_TARGET_TRANS_TIME_INTR_CPU:default="N/A", esp32="25", esp32s2="22", esp32c3="27", esp32s3="24", esp32c2="40", esp32c6="32", esp32h2="54"}
{IDF_TARGET_TRANS_TIME_POLL_CPU:default="N/A", esp32="8", esp32s2="8", esp32c3="9", esp32s3="9", esp32c2="15", esp32c6="15", esp32h2="24", esp32c5="13"} {IDF_TARGET_TRANS_TIME_POLL_CPU:default="N/A", esp32="8", esp32s2="8", esp32c3="9", esp32s3="9", esp32c2="15", esp32c6="15", esp32h2="24"}
传输事务持续时间包括设置 SPI 外设寄存器，将数据复制到 FIFO 或设置 DMA 链接，以及 SPI 传输事务时间。 传输事务持续时间包括设置 SPI 外设寄存器，将数据复制到 FIFO 或设置 DMA 链接，以及 SPI 传输事务时间。