From 5cae5090c2624fa7a15db26a8ed4ac4af58b9790 Mon Sep 17 00:00:00 2001 From: morris Date: Tue, 26 Nov 2024 11:24:50 +0800 Subject: [PATCH 1/2] fix(hal): integer overflow found by coverity actually these "bugs" are harmless from the perspective of the hardware --- components/hal/esp32/include/hal/spi_ll.h | 25 +++--- .../hal/esp32c2/include/hal/gpspi_flash_ll.h | 34 +++++--- components/hal/esp32c2/include/hal/spi_ll.h | 66 ++++++++-------- .../hal/esp32c2/include/hal/spimem_flash_ll.h | 12 +-- .../hal/esp32c3/include/hal/gpspi_flash_ll.h | 34 +++++--- components/hal/esp32c3/include/hal/spi_ll.h | 66 ++++++++-------- .../hal/esp32c3/include/hal/spimem_flash_ll.h | 12 +-- .../hal/esp32c5/include/hal/gpspi_flash_ll.h | 32 +++++--- components/hal/esp32c5/include/hal/spi_ll.h | 21 ++--- .../hal/esp32c5/include/hal/spimem_flash_ll.h | 15 ++-- .../hal/esp32c6/include/hal/gpspi_flash_ll.h | 32 +++++--- components/hal/esp32c6/include/hal/spi_ll.h | 67 ++++++++-------- .../hal/esp32c6/include/hal/spimem_flash_ll.h | 12 +-- .../hal/esp32c61/include/hal/gpspi_flash_ll.h | 32 +++++--- components/hal/esp32c61/include/hal/spi_ll.h | 42 +++++----- .../esp32c61/include/hal/spimem_flash_ll.h | 15 ++-- .../hal/esp32h2/include/hal/gpspi_flash_ll.h | 32 +++++--- components/hal/esp32h2/include/hal/spi_ll.h | 79 +++++++++---------- .../hal/esp32h2/include/hal/spimem_flash_ll.h | 12 +-- .../hal/esp32p4/include/hal/gpspi_flash_ll.h | 32 +++++--- components/hal/esp32p4/include/hal/lcd_ll.h | 16 +++- components/hal/esp32p4/include/hal/spi_ll.h | 24 +++--- .../hal/esp32p4/include/hal/spimem_flash_ll.h | 13 +-- .../hal/esp32s2/include/hal/gpspi_flash_ll.h | 40 +++++++--- components/hal/esp32s2/include/hal/spi_ll.h | 76 +++++++++--------- .../hal/esp32s2/include/hal/spimem_flash_ll.h | 34 ++++---- .../hal/esp32s3/include/hal/gpspi_flash_ll.h | 34 +++++--- components/hal/esp32s3/include/hal/lcd_ll.h | 24 ++++-- components/hal/esp32s3/include/hal/spi_ll.h | 76 +++++++++--------- .../hal/esp32s3/include/hal/spimem_flash_ll.h | 40 +++++----- 30 files changed, 591 insertions(+), 458 deletions(-) diff --git a/components/hal/esp32/include/hal/spi_ll.h b/components/hal/esp32/include/hal/spi_ll.h index 9ab400ee3f..2bf29d19df 100644 --- a/components/hal/esp32/include/hal/spi_ll.h +++ b/components/hal/esp32/include/hal/spi_ll.h @@ -63,10 +63,10 @@ typedef spi_dev_t spi_dma_dev_t; * @param host_id Peripheral index number, see `spi_host_device_t` * @param enable Enable/Disable */ -static inline void spi_ll_enable_bus_clock(spi_host_device_t host_id, bool enable) { +static inline void spi_ll_enable_bus_clock(spi_host_device_t host_id, bool enable) +{ if (enable) { - switch (host_id) - { + switch (host_id) { case SPI1_HOST: DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_SPI01_CLK_EN); break; @@ -79,8 +79,7 @@ static inline void spi_ll_enable_bus_clock(spi_host_device_t host_id, bool enabl default: HAL_ASSERT(false); } } else { - switch (host_id) - { + switch (host_id) { case SPI1_HOST: DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_SPI01_CLK_EN); break; @@ -104,9 +103,9 @@ static inline void spi_ll_enable_bus_clock(spi_host_device_t host_id, bool enabl * * @param host_id Peripheral index number, see `spi_host_device_t` */ -static inline void spi_ll_reset_register(spi_host_device_t host_id) { - switch (host_id) - { +static inline void spi_ll_reset_register(spi_host_device_t host_id) +{ + switch (host_id) { case SPI1_HOST: DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_SPI01_RST); DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_SPI01_RST); @@ -793,7 +792,9 @@ static inline void spi_ll_set_miso_delay(spi_dev_t *hw, int delay_mode, int dela static inline void spi_ll_set_dummy(spi_dev_t *hw, int dummy_n) { hw->user.usr_dummy = dummy_n ? 1 : 0; - HAL_FORCE_MODIFY_U32_REG_FIELD(hw->user1, usr_dummy_cyclelen, dummy_n - 1); + if (dummy_n > 0) { + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->user1, usr_dummy_cyclelen, dummy_n - 1); + } } /** @@ -1061,7 +1062,8 @@ static inline void spi_ll_enable_int(spi_dev_t *hw) * @param host_id Peripheral index number, see `spi_host_device_t` * @param enable Enable/Disable */ -static inline void spi_dma_ll_enable_bus_clock(spi_host_device_t host_id, bool enable) { +static inline void spi_dma_ll_enable_bus_clock(spi_host_device_t host_id, bool enable) +{ (void)host_id; // has only one spi_dma if (enable) { DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_SPI_DMA_CLK_EN); @@ -1080,7 +1082,8 @@ static inline void spi_dma_ll_enable_bus_clock(spi_host_device_t host_id, bool e * @param host_id Peripheral index number, see `spi_host_device_t` */ __attribute__((always_inline)) -static inline void spi_dma_ll_reset_register(spi_host_device_t host_id) { +static inline void spi_dma_ll_reset_register(spi_host_device_t host_id) +{ (void)host_id; // has only one spi_dma DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_SPI_DMA_RST); DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_SPI_DMA_RST); diff --git a/components/hal/esp32c2/include/hal/gpspi_flash_ll.h b/components/hal/esp32c2/include/hal/gpspi_flash_ll.h index bbfca7082a..1364850175 100644 --- a/components/hal/esp32c2/include/hal/gpspi_flash_ll.h +++ b/components/hal/esp32c2/include/hal/gpspi_flash_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -179,7 +179,7 @@ static inline bool gpspi_flash_ll_host_idle(const spi_dev_t *dev) */ static inline void gpspi_flash_ll_read_phase(spi_dev_t *dev) { - typeof (dev->user) user = { + typeof(dev->user) user = { .usr_mosi = 0, .usr_miso = 1, .usr_addr = 1, @@ -210,9 +210,9 @@ static inline void gpspi_flash_ll_set_cs_pin(spi_dev_t *dev, int pin) */ static inline void gpspi_flash_ll_set_read_mode(spi_dev_t *dev, esp_flash_io_mode_t read_mode) { - typeof (dev->ctrl) ctrl; + typeof(dev->ctrl) ctrl; ctrl.val = dev->ctrl.val; - typeof (dev->user) user; + typeof(dev->user) user; user.val = dev->user.val; ctrl.val &= ~(SPI_FCMD_QUAD_M | SPI_FADDR_QUAD_M | SPI_FREAD_QUAD_M | SPI_FCMD_DUAL_M | SPI_FADDR_DUAL_M | SPI_FREAD_DUAL_M); @@ -220,7 +220,7 @@ static inline void gpspi_flash_ll_set_read_mode(spi_dev_t *dev, esp_flash_io_mod switch (read_mode) { case SPI_FLASH_FASTRD: - //the default option + //the default option case SPI_FLASH_SLOWRD: break; case SPI_FLASH_QIO: @@ -338,7 +338,7 @@ static inline void gpspi_flash_ll_set_addr_bitlen(spi_dev_t *dev, uint32_t bitle static inline void gpspi_flash_ll_set_usr_address(spi_dev_t *dev, uint32_t addr, uint32_t bitlen) { // The blank region should be all ones - uint32_t padding_ones = (bitlen == 32? 0 : UINT32_MAX >> bitlen); + uint32_t padding_ones = (bitlen == 32 ? 0 : UINT32_MAX >> bitlen); dev->addr = (addr << (32 - bitlen)) | padding_ones; } @@ -362,7 +362,9 @@ static inline void gpspi_flash_ll_set_address(spi_dev_t *dev, uint32_t addr) static inline void gpspi_flash_ll_set_dummy(spi_dev_t *dev, uint32_t dummy_n) { dev->user.usr_dummy = dummy_n ? 1 : 0; - dev->user1.usr_dummy_cyclelen = dummy_n - 1; + if (dummy_n > 0) { + dev->user1.usr_dummy_cyclelen = dummy_n - 1; + } } /** @@ -387,14 +389,24 @@ static inline void gpspi_flash_ll_set_dummy_out(spi_dev_t *dev, uint32_t out_en, */ static inline void gpspi_flash_ll_set_hold(spi_dev_t *dev, uint32_t hold_n) { - dev->user1.cs_hold_time = hold_n - 1; - dev->user.cs_hold = (hold_n > 0? 1: 0); + dev->user.cs_hold = (hold_n > 0 ? 1 : 0); + if (hold_n > 0) { + dev->user1.cs_hold_time = hold_n - 1; + } } +/** + * Set the delay of SPI clocks before the first SPI clock after the CS active edge. + * + * @param dev Beginning address of the peripheral registers. + * @param cs_setup_time Delay of SPI clocks after the CS active edge, 0 to disable the setup phase. + */ static inline void gpspi_flash_ll_set_cs_setup(spi_dev_t *dev, uint32_t cs_setup_time) { dev->user.cs_setup = (cs_setup_time > 0 ? 1 : 0); - dev->user1.cs_setup_time = cs_setup_time - 1; + if (cs_setup_time > 0) { + dev->user1.cs_setup_time = cs_setup_time - 1; + } } /** @@ -411,7 +423,7 @@ static inline uint32_t gpspi_flash_ll_calculate_clock_reg(uint8_t clkdiv) if (clkdiv == 1) { div_parameter = (1 << 31); } else { - div_parameter = ((clkdiv - 1) | (((clkdiv/2 - 1) & 0xff) << 6 ) | (((clkdiv - 1) & 0xff) << 12)); + div_parameter = ((clkdiv - 1) | (((clkdiv / 2 - 1) & 0xff) << 6) | (((clkdiv - 1) & 0xff) << 12)); } return div_parameter; } diff --git a/components/hal/esp32c2/include/hal/spi_ll.h b/components/hal/esp32c2/include/hal/spi_ll.h index 4acd7b1721..7b83802588 100644 --- a/components/hal/esp32c2/include/hal/spi_ll.h +++ b/components/hal/esp32c2/include/hal/spi_ll.h @@ -75,7 +75,7 @@ typedef enum { // SPI base command in esp32c2 typedef enum { - /* Slave HD Only */ + /* Slave HD Only */ SPI_LL_BASE_CMD_HD_WRBUF = 0x01, SPI_LL_BASE_CMD_HD_RDBUF = 0x02, SPI_LL_BASE_CMD_HD_WRDMA = 0x03, @@ -97,9 +97,9 @@ typedef enum { * @param host_id Peripheral index number, see `spi_host_device_t` * @param enable Enable/Disable */ -static inline void spi_ll_enable_bus_clock(spi_host_device_t host_id, bool enable) { - switch (host_id) - { +static inline void spi_ll_enable_bus_clock(spi_host_device_t host_id, bool enable) +{ + switch (host_id) { case SPI1_HOST: SYSTEM.perip_clk_en0.spi01_clk_en = enable; break; @@ -119,9 +119,9 @@ static inline void spi_ll_enable_bus_clock(spi_host_device_t host_id, bool enabl * * @param host_id Peripheral index number, see `spi_host_device_t` */ -static inline void spi_ll_reset_register(spi_host_device_t host_id) { - switch (host_id) - { +static inline void spi_ll_reset_register(spi_host_device_t host_id) +{ + switch (host_id) { case SPI1_HOST: SYSTEM.perip_rst_en0.spi01_rst = 1; SYSTEM.perip_rst_en0.spi01_rst = 0; @@ -158,15 +158,15 @@ static inline void spi_ll_enable_clock(spi_host_device_t host_id, bool enable) * @param clk_source clock source to select, see valid sources in type `spi_clock_source_t` */ __attribute__((always_inline)) -static inline void spi_ll_set_clk_source(spi_dev_t *hw, spi_clock_source_t clk_source){ - switch (clk_source) - { - case SPI_CLK_SRC_XTAL: - hw->clk_gate.mst_clk_sel = 0; - break; - default: - hw->clk_gate.mst_clk_sel = 1; - break; +static inline void spi_ll_set_clk_source(spi_dev_t *hw, spi_clock_source_t clk_source) +{ + switch (clk_source) { + case SPI_CLK_SRC_XTAL: + hw->clk_gate.mst_clk_sel = 0; + break; + default: + hw->clk_gate.mst_clk_sel = 1; + break; } } @@ -733,7 +733,7 @@ static inline int spi_ll_freq_for_pre_n(int fapb, int pre, int n) */ static inline int spi_ll_master_cal_clock(int fapb, int hz, int duty_cycle, spi_ll_clock_val_t *out_reg) { -typeof(GPSPI2.clock) reg; + typeof(GPSPI2.clock) reg; int eff_clk; //In hw, n, h and l are 1-64, pre is 1-8K. Value written to register is one lower than used value. @@ -1018,7 +1018,9 @@ static inline void spi_ll_set_command(spi_dev_t *hw, uint16_t cmd, int cmdlen, b static inline void spi_ll_set_dummy(spi_dev_t *hw, int dummy_n) { hw->user.usr_dummy = dummy_n ? 1 : 0; - HAL_FORCE_MODIFY_U32_REG_FIELD(hw->user1, usr_dummy_cyclelen, dummy_n - 1); + if (dummy_n > 0) { + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->user1, usr_dummy_cyclelen, dummy_n - 1); + } } /** @@ -1181,8 +1183,7 @@ static inline uint32_t spi_ll_slave_hd_get_last_addr(spi_dev_t *hw) static inline uint8_t spi_ll_get_slave_hd_base_command(spi_command_t cmd_t) { uint8_t cmd_base = 0x00; - switch (cmd_t) - { + switch (cmd_t) { case SPI_CMD_HD_WRBUF: cmd_base = SPI_LL_BASE_CMD_HD_WRBUF; break; @@ -1344,28 +1345,25 @@ static inline void spi_ll_format_line_mode_conf_buff(spi_dev_t *hw, spi_line_mod conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET] &= ~SPI_LL_ONE_LINE_CTRL_MASK; conf_buffer[SPI_LL_USER_REG_POS + SPI_LL_CONF_BUFFER_OFFSET] &= ~SPI_LL_ONE_LINE_USER_MASK; - switch (line_mode.cmd_lines) - { + switch (line_mode.cmd_lines) { case 2: SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FCMD_DUAL_M); break; case 4: SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FCMD_QUAD_M); break; default: break; } - switch (line_mode.addr_lines) - { + switch (line_mode.addr_lines) { case 2: SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FADDR_DUAL_M); break; case 4: SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FADDR_QUAD_M); break; default: break; } - switch (line_mode.data_lines) - { - case 2: SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FREAD_DUAL_M ); - SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_USER_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FWRITE_DUAL_M); - break; - case 4: SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FREAD_QUAD_M ); - SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_USER_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FWRITE_QUAD_M); - break; + switch (line_mode.data_lines) { + case 2: SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FREAD_DUAL_M); + SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_USER_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FWRITE_DUAL_M); + break; + case 4: SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FREAD_QUAD_M); + SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_USER_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FWRITE_QUAD_M); + break; default: break; } } @@ -1380,7 +1378,7 @@ static inline void spi_ll_format_line_mode_conf_buff(spi_dev_t *hw, spi_line_mod static inline void spi_ll_format_prep_phase_conf_buffer(spi_dev_t *hw, uint8_t setup, uint32_t conf_buffer[SOC_SPI_SCT_BUFFER_NUM_MAX]) { //user reg: cs_setup - if(setup) { + if (setup) { SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_USER_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_CS_SETUP_M); } else { SPI_LL_CONF_BUF_CLR_BIT(conf_buffer[SPI_LL_USER_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_CS_SETUP_M); @@ -1526,7 +1524,7 @@ static inline void spi_ll_format_din_phase_conf_buffer(spi_dev_t *hw, int bitlen static inline void spi_ll_format_done_phase_conf_buffer(spi_dev_t *hw, int hold, uint32_t conf_buffer[SOC_SPI_SCT_BUFFER_NUM_MAX]) { //user reg: cs_hold - if(hold) { + if (hold) { SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_USER_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_CS_HOLD_M); } else { SPI_LL_CONF_BUF_CLR_BIT(conf_buffer[SPI_LL_USER_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_CS_HOLD_M); diff --git a/components/hal/esp32c2/include/hal/spimem_flash_ll.h b/components/hal/esp32c2/include/hal/spimem_flash_ll.h index 8c1d1608b1..c1b6343115 100644 --- a/components/hal/esp32c2/include/hal/spimem_flash_ll.h +++ b/components/hal/esp32c2/include/hal/spimem_flash_ll.h @@ -410,7 +410,7 @@ static inline bool spimem_flash_ll_host_idle(const spi_mem_dev_t *dev) */ static inline void spimem_flash_ll_read_phase(spi_mem_dev_t *dev) { - typeof (dev->user) user = { + typeof(dev->user) user = { .usr_mosi = 0, .usr_miso = 1, .usr_addr = 1, @@ -441,7 +441,7 @@ static inline void spimem_flash_ll_set_cs_pin(spi_mem_dev_t *dev, int pin) */ static inline void spimem_flash_ll_set_read_mode(spi_mem_dev_t *dev, esp_flash_io_mode_t read_mode) { - typeof (dev->ctrl) ctrl; + typeof(dev->ctrl) ctrl; ctrl.val = dev->ctrl.val; ctrl.val &= ~(SPI_MEM_FREAD_QIO_M | SPI_MEM_FREAD_QUAD_M | SPI_MEM_FREAD_DIO_M | SPI_MEM_FREAD_DUAL_M); @@ -582,7 +582,9 @@ static inline void spimem_flash_ll_set_usr_address(spi_mem_dev_t *dev, uint32_t static inline void spimem_flash_ll_set_dummy(spi_mem_dev_t *dev, uint32_t dummy_n) { dev->user.usr_dummy = dummy_n ? 1 : 0; - dev->user1.usr_dummy_cyclelen = dummy_n - 1; + if (dummy_n > 0) { + dev->user1.usr_dummy_cyclelen = dummy_n - 1; + } } /** @@ -608,7 +610,7 @@ static inline void spimem_flash_ll_set_dummy_out(spi_mem_dev_t *dev, uint32_t ou static inline void spimem_flash_ll_set_hold(spi_mem_dev_t *dev, uint32_t hold_n) { dev->ctrl2.cs_hold_time = hold_n - 1; - dev->user.cs_hold = (hold_n > 0? 1: 0); + dev->user.cs_hold = (hold_n > 0 ? 1 : 0); } static inline void spimem_flash_ll_set_cs_setup(spi_mem_dev_t *dev, uint32_t cs_setup_time) @@ -647,7 +649,7 @@ static inline uint32_t spimem_flash_ll_calculate_clock_reg(uint8_t clkdiv) if (clkdiv == 1) { div_parameter = (1 << 31); } else { - div_parameter = ((clkdiv - 1) | (((clkdiv - 1) / 2 & 0xff) << 8 ) | (((clkdiv - 1) & 0xff) << 16)); + div_parameter = ((clkdiv - 1) | (((clkdiv - 1) / 2 & 0xff) << 8) | (((clkdiv - 1) & 0xff) << 16)); } return div_parameter; } diff --git a/components/hal/esp32c3/include/hal/gpspi_flash_ll.h b/components/hal/esp32c3/include/hal/gpspi_flash_ll.h index 18465d85f1..26338ba04a 100644 --- a/components/hal/esp32c3/include/hal/gpspi_flash_ll.h +++ b/components/hal/esp32c3/include/hal/gpspi_flash_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -180,7 +180,7 @@ static inline bool gpspi_flash_ll_host_idle(const spi_dev_t *dev) */ static inline void gpspi_flash_ll_read_phase(spi_dev_t *dev) { - typeof (dev->user) user = { + typeof(dev->user) user = { .usr_mosi = 0, .usr_miso = 1, .usr_addr = 1, @@ -211,9 +211,9 @@ static inline void gpspi_flash_ll_set_cs_pin(spi_dev_t *dev, int pin) */ static inline void gpspi_flash_ll_set_read_mode(spi_dev_t *dev, esp_flash_io_mode_t read_mode) { - typeof (dev->ctrl) ctrl; + typeof(dev->ctrl) ctrl; ctrl.val = dev->ctrl.val; - typeof (dev->user) user; + typeof(dev->user) user; user.val = dev->user.val; ctrl.val &= ~(SPI_FCMD_QUAD_M | SPI_FADDR_QUAD_M | SPI_FREAD_QUAD_M | SPI_FCMD_DUAL_M | SPI_FADDR_DUAL_M | SPI_FREAD_DUAL_M); @@ -221,7 +221,7 @@ static inline void gpspi_flash_ll_set_read_mode(spi_dev_t *dev, esp_flash_io_mod switch (read_mode) { case SPI_FLASH_FASTRD: - //the default option + //the default option case SPI_FLASH_SLOWRD: break; case SPI_FLASH_QIO: @@ -339,7 +339,7 @@ static inline void gpspi_flash_ll_set_addr_bitlen(spi_dev_t *dev, uint32_t bitle static inline void gpspi_flash_ll_set_usr_address(spi_dev_t *dev, uint32_t addr, uint32_t bitlen) { // The blank region should be all ones - uint32_t padding_ones = (bitlen == 32? 0 : UINT32_MAX >> bitlen); + uint32_t padding_ones = (bitlen == 32 ? 0 : UINT32_MAX >> bitlen); dev->addr = (addr << (32 - bitlen)) | padding_ones; } @@ -363,7 +363,9 @@ static inline void gpspi_flash_ll_set_address(spi_dev_t *dev, uint32_t addr) static inline void gpspi_flash_ll_set_dummy(spi_dev_t *dev, uint32_t dummy_n) { dev->user.usr_dummy = dummy_n ? 1 : 0; - HAL_FORCE_MODIFY_U32_REG_FIELD(dev->user1, usr_dummy_cyclelen, dummy_n - 1); + if (dummy_n > 0) { + HAL_FORCE_MODIFY_U32_REG_FIELD(dev->user1, usr_dummy_cyclelen, dummy_n - 1); + } } /** @@ -388,14 +390,24 @@ static inline void gpspi_flash_ll_set_dummy_out(spi_dev_t *dev, uint32_t out_en, */ static inline void gpspi_flash_ll_set_hold(spi_dev_t *dev, uint32_t hold_n) { - dev->user1.cs_hold_time = hold_n - 1; - dev->user.cs_hold = (hold_n > 0? 1: 0); + dev->user.cs_hold = (hold_n > 0 ? 1 : 0); + if (hold_n > 0) { + dev->user1.cs_hold_time = hold_n - 1; + } } +/** + * Set the delay of SPI clocks before the first SPI clock after the CS active edge. + * + * @param dev Beginning address of the peripheral registers. + * @param cs_setup_time Delay of SPI clocks after the CS active edge, 0 to disable the setup phase. + */ static inline void gpspi_flash_ll_set_cs_setup(spi_dev_t *dev, uint32_t cs_setup_time) { dev->user.cs_setup = (cs_setup_time > 0 ? 1 : 0); - dev->user1.cs_setup_time = cs_setup_time - 1; + if (cs_setup_time > 0) { + dev->user1.cs_setup_time = cs_setup_time - 1; + } } /** @@ -412,7 +424,7 @@ static inline uint32_t gpspi_flash_ll_calculate_clock_reg(uint8_t clkdiv) if (clkdiv == 1) { div_parameter = (1 << 31); } else { - div_parameter = ((clkdiv - 1) | (((clkdiv/2 - 1) & 0xff) << 6 ) | (((clkdiv - 1) & 0xff) << 12)); + div_parameter = ((clkdiv - 1) | (((clkdiv / 2 - 1) & 0xff) << 6) | (((clkdiv - 1) & 0xff) << 12)); } return div_parameter; } diff --git a/components/hal/esp32c3/include/hal/spi_ll.h b/components/hal/esp32c3/include/hal/spi_ll.h index 2b5ea2346a..ae25e2a7eb 100644 --- a/components/hal/esp32c3/include/hal/spi_ll.h +++ b/components/hal/esp32c3/include/hal/spi_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -77,7 +77,7 @@ typedef enum { // SPI base command in esp32c3 typedef enum { - /* Slave HD Only */ + /* Slave HD Only */ SPI_LL_BASE_CMD_HD_WRBUF = 0x01, SPI_LL_BASE_CMD_HD_RDBUF = 0x02, SPI_LL_BASE_CMD_HD_WRDMA = 0x03, @@ -99,9 +99,9 @@ typedef enum { * @param host_id Peripheral index number, see `spi_host_device_t` * @param enable Enable/Disable */ -static inline void spi_ll_enable_bus_clock(spi_host_device_t host_id, bool enable) { - switch (host_id) - { +static inline void spi_ll_enable_bus_clock(spi_host_device_t host_id, bool enable) +{ + switch (host_id) { case SPI1_HOST: SYSTEM.perip_clk_en0.reg_spi01_clk_en = enable; break; @@ -121,9 +121,9 @@ static inline void spi_ll_enable_bus_clock(spi_host_device_t host_id, bool enabl * * @param host_id Peripheral index number, see `spi_host_device_t` */ -static inline void spi_ll_reset_register(spi_host_device_t host_id) { - switch (host_id) - { +static inline void spi_ll_reset_register(spi_host_device_t host_id) +{ + switch (host_id) { case SPI1_HOST: SYSTEM.perip_rst_en0.reg_spi01_rst = 1; SYSTEM.perip_rst_en0.reg_spi01_rst = 0; @@ -160,15 +160,15 @@ static inline void spi_ll_enable_clock(spi_host_device_t host_id, bool enable) * @param clk_source clock source to select, see valid sources in type `spi_clock_source_t` */ __attribute__((always_inline)) -static inline void spi_ll_set_clk_source(spi_dev_t *hw, spi_clock_source_t clk_source){ - switch (clk_source) - { - case SPI_CLK_SRC_XTAL: - hw->clk_gate.mst_clk_sel = 0; - break; - default: - hw->clk_gate.mst_clk_sel = 1; - break; +static inline void spi_ll_set_clk_source(spi_dev_t *hw, spi_clock_source_t clk_source) +{ + switch (clk_source) { + case SPI_CLK_SRC_XTAL: + hw->clk_gate.mst_clk_sel = 0; + break; + default: + hw->clk_gate.mst_clk_sel = 1; + break; } } @@ -1020,7 +1020,9 @@ static inline void spi_ll_set_command(spi_dev_t *hw, uint16_t cmd, int cmdlen, b static inline void spi_ll_set_dummy(spi_dev_t *hw, int dummy_n) { hw->user.usr_dummy = dummy_n ? 1 : 0; - HAL_FORCE_MODIFY_U32_REG_FIELD(hw->user1, usr_dummy_cyclelen, dummy_n - 1); + if (dummy_n > 0) { + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->user1, usr_dummy_cyclelen, dummy_n - 1); + } } /** @@ -1257,28 +1259,25 @@ static inline void spi_ll_format_line_mode_conf_buff(spi_dev_t *hw, spi_line_mod conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET] &= ~SPI_LL_ONE_LINE_CTRL_MASK; conf_buffer[SPI_LL_USER_REG_POS + SPI_LL_CONF_BUFFER_OFFSET] &= ~SPI_LL_ONE_LINE_USER_MASK; - switch (line_mode.cmd_lines) - { + switch (line_mode.cmd_lines) { case 2: SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FCMD_DUAL_M); break; case 4: SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FCMD_QUAD_M); break; default: break; } - switch (line_mode.addr_lines) - { + switch (line_mode.addr_lines) { case 2: SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FADDR_DUAL_M); break; case 4: SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FADDR_QUAD_M); break; default: break; } - switch (line_mode.data_lines) - { - case 2: SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FREAD_DUAL_M ); - SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_USER_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FWRITE_DUAL_M); - break; - case 4: SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FREAD_QUAD_M ); - SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_USER_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FWRITE_QUAD_M); - break; + switch (line_mode.data_lines) { + case 2: SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FREAD_DUAL_M); + SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_USER_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FWRITE_DUAL_M); + break; + case 4: SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FREAD_QUAD_M); + SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_USER_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FWRITE_QUAD_M); + break; default: break; } } @@ -1293,7 +1292,7 @@ static inline void spi_ll_format_line_mode_conf_buff(spi_dev_t *hw, spi_line_mod static inline void spi_ll_format_prep_phase_conf_buffer(spi_dev_t *hw, uint8_t setup, uint32_t conf_buffer[SOC_SPI_SCT_BUFFER_NUM_MAX]) { //user reg: cs_setup - if(setup) { + if (setup) { SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_USER_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_CS_SETUP_M); } else { SPI_LL_CONF_BUF_CLR_BIT(conf_buffer[SPI_LL_USER_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_CS_SETUP_M); @@ -1439,7 +1438,7 @@ static inline void spi_ll_format_din_phase_conf_buffer(spi_dev_t *hw, int bitlen static inline void spi_ll_format_done_phase_conf_buffer(spi_dev_t *hw, int hold, uint32_t conf_buffer[SOC_SPI_SCT_BUFFER_NUM_MAX]) { //user reg: cs_hold - if(hold) { + if (hold) { SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_USER_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_CS_HOLD_M); } else { SPI_LL_CONF_BUF_CLR_BIT(conf_buffer[SPI_LL_USER_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_CS_HOLD_M); @@ -1511,8 +1510,7 @@ static inline void spi_ll_set_magic_number(spi_dev_t *hw, uint8_t magic_value) static inline uint8_t spi_ll_get_slave_hd_base_command(spi_command_t cmd_t) { uint8_t cmd_base = 0x00; - switch (cmd_t) - { + switch (cmd_t) { case SPI_CMD_HD_WRBUF: cmd_base = SPI_LL_BASE_CMD_HD_WRBUF; break; diff --git a/components/hal/esp32c3/include/hal/spimem_flash_ll.h b/components/hal/esp32c3/include/hal/spimem_flash_ll.h index fd9bc38ed9..f3d0179c02 100644 --- a/components/hal/esp32c3/include/hal/spimem_flash_ll.h +++ b/components/hal/esp32c3/include/hal/spimem_flash_ll.h @@ -412,7 +412,7 @@ static inline bool spimem_flash_ll_host_idle(const spi_mem_dev_t *dev) */ static inline void spimem_flash_ll_read_phase(spi_mem_dev_t *dev) { - typeof (dev->user) user = { + typeof(dev->user) user = { .usr_mosi = 0, .usr_miso = 1, .usr_addr = 1, @@ -443,7 +443,7 @@ static inline void spimem_flash_ll_set_cs_pin(spi_mem_dev_t *dev, int pin) */ static inline void spimem_flash_ll_set_read_mode(spi_mem_dev_t *dev, esp_flash_io_mode_t read_mode) { - typeof (dev->ctrl) ctrl; + typeof(dev->ctrl) ctrl; ctrl.val = dev->ctrl.val; ctrl.val &= ~(SPI_MEM_FREAD_QIO_M | SPI_MEM_FREAD_QUAD_M | SPI_MEM_FREAD_DIO_M | SPI_MEM_FREAD_DUAL_M); @@ -584,7 +584,9 @@ static inline void spimem_flash_ll_set_usr_address(spi_mem_dev_t *dev, uint32_t static inline void spimem_flash_ll_set_dummy(spi_mem_dev_t *dev, uint32_t dummy_n) { dev->user.usr_dummy = dummy_n ? 1 : 0; - dev->user1.usr_dummy_cyclelen = dummy_n - 1; + if (dummy_n > 0) { + dev->user1.usr_dummy_cyclelen = dummy_n - 1; + } } /** @@ -610,7 +612,7 @@ static inline void spimem_flash_ll_set_dummy_out(spi_mem_dev_t *dev, uint32_t ou static inline void spimem_flash_ll_set_hold(spi_mem_dev_t *dev, uint32_t hold_n) { dev->ctrl2.cs_hold_time = hold_n - 1; - dev->user.cs_hold = (hold_n > 0? 1: 0); + dev->user.cs_hold = (hold_n > 0 ? 1 : 0); } static inline void spimem_flash_ll_set_cs_setup(spi_mem_dev_t *dev, uint32_t cs_setup_time) @@ -662,7 +664,7 @@ static inline uint32_t spimem_flash_ll_calculate_clock_reg(uint8_t clkdiv) if (clkdiv == 1) { div_parameter = (1 << 31); } else { - div_parameter = ((clkdiv - 1) | (((clkdiv - 1) / 2 & 0xff) << 8 ) | (((clkdiv - 1) & 0xff) << 16)); + div_parameter = ((clkdiv - 1) | (((clkdiv - 1) / 2 & 0xff) << 8) | (((clkdiv - 1) & 0xff) << 16)); } return div_parameter; } diff --git a/components/hal/esp32c5/include/hal/gpspi_flash_ll.h b/components/hal/esp32c5/include/hal/gpspi_flash_ll.h index 73d64db653..3622702db2 100644 --- a/components/hal/esp32c5/include/hal/gpspi_flash_ll.h +++ b/components/hal/esp32c5/include/hal/gpspi_flash_ll.h @@ -180,7 +180,7 @@ static inline bool gpspi_flash_ll_host_idle(const spi_dev_t *dev) */ static inline void gpspi_flash_ll_read_phase(spi_dev_t *dev) { - typeof (dev->user) user = { + typeof(dev->user) user = { .usr_mosi = 0, .usr_miso = 1, .usr_addr = 1, @@ -211,9 +211,9 @@ static inline void gpspi_flash_ll_set_cs_pin(spi_dev_t *dev, int pin) */ static inline void gpspi_flash_ll_set_read_mode(spi_dev_t *dev, esp_flash_io_mode_t read_mode) { - typeof (dev->ctrl) ctrl; + typeof(dev->ctrl) ctrl; ctrl.val = dev->ctrl.val; - typeof (dev->user) user; + typeof(dev->user) user; user.val = dev->user.val; ctrl.val &= ~(SPI_FCMD_QUAD_M | SPI_FADDR_QUAD_M | SPI_FREAD_QUAD_M | SPI_FCMD_DUAL_M | SPI_FADDR_DUAL_M | SPI_FREAD_DUAL_M); @@ -221,7 +221,7 @@ static inline void gpspi_flash_ll_set_read_mode(spi_dev_t *dev, esp_flash_io_mod switch (read_mode) { case SPI_FLASH_FASTRD: - //the default option + //the default option case SPI_FLASH_SLOWRD: break; case SPI_FLASH_QIO: @@ -339,7 +339,7 @@ static inline void gpspi_flash_ll_set_addr_bitlen(spi_dev_t *dev, uint32_t bitle static inline void gpspi_flash_ll_set_usr_address(spi_dev_t *dev, uint32_t addr, uint32_t bitlen) { // The blank region should be all ones - uint32_t padding_ones = (bitlen == 32? 0 : UINT32_MAX >> bitlen); + uint32_t padding_ones = (bitlen == 32 ? 0 : UINT32_MAX >> bitlen); dev->addr.val = (addr << (32 - bitlen)) | padding_ones; } @@ -363,7 +363,9 @@ static inline void gpspi_flash_ll_set_address(spi_dev_t *dev, uint32_t addr) static inline void gpspi_flash_ll_set_dummy(spi_dev_t *dev, uint32_t dummy_n) { dev->user.usr_dummy = dummy_n ? 1 : 0; - HAL_FORCE_MODIFY_U32_REG_FIELD(dev->user1, usr_dummy_cyclelen, dummy_n - 1); + if (dummy_n > 0) { + HAL_FORCE_MODIFY_U32_REG_FIELD(dev->user1, usr_dummy_cyclelen, dummy_n - 1); + } } /** @@ -388,14 +390,24 @@ static inline void gpspi_flash_ll_set_dummy_out(spi_dev_t *dev, uint32_t out_en, */ static inline void gpspi_flash_ll_set_hold(spi_dev_t *dev, uint32_t hold_n) { - dev->user1.cs_hold_time = hold_n - 1; - dev->user.cs_hold = (hold_n > 0? 1: 0); + dev->user.cs_hold = (hold_n > 0 ? 1 : 0); + if (hold_n > 0) { + dev->user1.cs_hold_time = hold_n - 1; + } } +/** + * Set the delay of SPI clocks before the first SPI clock after the CS active edge. + * + * @param dev Beginning address of the peripheral registers. + * @param cs_setup_time Delay of SPI clocks after the CS active edge, 0 to disable the setup phase. + */ static inline void gpspi_flash_ll_set_cs_setup(spi_dev_t *dev, uint32_t cs_setup_time) { dev->user.cs_setup = (cs_setup_time > 0 ? 1 : 0); - dev->user1.cs_setup_time = cs_setup_time - 1; + if (cs_setup_time > 0) { + dev->user1.cs_setup_time = cs_setup_time - 1; + } } /** @@ -412,7 +424,7 @@ static inline uint32_t gpspi_flash_ll_calculate_clock_reg(uint8_t clkdiv) if (clkdiv == 1) { div_parameter = (1 << 31); } else { - div_parameter = ((clkdiv - 1) | (((clkdiv/2 - 1) & 0xff) << 6 ) | (((clkdiv - 1) & 0xff) << 12)); + div_parameter = ((clkdiv - 1) | (((clkdiv / 2 - 1) & 0xff) << 6) | (((clkdiv - 1) & 0xff) << 12)); } return div_parameter; } diff --git a/components/hal/esp32c5/include/hal/spi_ll.h b/components/hal/esp32c5/include/hal/spi_ll.h index 6af7784d9c..d65a2ae2df 100644 --- a/components/hal/esp32c5/include/hal/spi_ll.h +++ b/components/hal/esp32c5/include/hal/spi_ll.h @@ -77,7 +77,7 @@ typedef enum { // SPI base command typedef enum { - /* Slave HD Only */ + /* Slave HD Only */ SPI_LL_BASE_CMD_HD_WRBUF = 0x01, SPI_LL_BASE_CMD_HD_RDBUF = 0x02, SPI_LL_BASE_CMD_HD_WRDMA = 0x03, @@ -99,9 +99,9 @@ typedef enum { * @param host_id Peripheral index number, see `spi_host_device_t` * @param enable Enable/Disable */ -static inline void spi_ll_enable_bus_clock(spi_host_device_t host_id, bool enable) { - switch (host_id) - { +static inline void spi_ll_enable_bus_clock(spi_host_device_t host_id, bool enable) +{ + switch (host_id) { case SPI2_HOST: PCR.spi2_conf.spi2_clk_en = enable; break; @@ -115,9 +115,9 @@ static inline void spi_ll_enable_bus_clock(spi_host_device_t host_id, bool enabl * * @param host_id Peripheral index number, see `spi_host_device_t` */ -static inline void spi_ll_reset_register(spi_host_device_t host_id) { - switch (host_id) - { +static inline void spi_ll_reset_register(spi_host_device_t host_id) +{ + switch (host_id) { case SPI2_HOST: PCR.spi2_conf.spi2_rst_en = 1; PCR.spi2_conf.spi2_rst_en = 0; @@ -1028,7 +1028,9 @@ static inline void spi_ll_set_command(spi_dev_t *hw, uint16_t cmd, int cmdlen, b static inline void spi_ll_set_dummy(spi_dev_t *hw, int dummy_n) { hw->user.usr_dummy = dummy_n ? 1 : 0; - HAL_FORCE_MODIFY_U32_REG_FIELD(hw->user1, usr_dummy_cyclelen, dummy_n - 1); + if (dummy_n > 0) { + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->user1, usr_dummy_cyclelen, dummy_n - 1); + } } /** @@ -1194,8 +1196,7 @@ static inline uint32_t spi_ll_slave_hd_get_last_addr(spi_dev_t *hw) static inline uint8_t spi_ll_get_slave_hd_base_command(spi_command_t cmd_t) { uint8_t cmd_base = 0x00; - switch (cmd_t) - { + switch (cmd_t) { case SPI_CMD_HD_WRBUF: cmd_base = SPI_LL_BASE_CMD_HD_WRBUF; break; diff --git a/components/hal/esp32c5/include/hal/spimem_flash_ll.h b/components/hal/esp32c5/include/hal/spimem_flash_ll.h index 83f5e6bada..e3211ad70a 100644 --- a/components/hal/esp32c5/include/hal/spimem_flash_ll.h +++ b/components/hal/esp32c5/include/hal/spimem_flash_ll.h @@ -422,7 +422,7 @@ static inline bool spimem_flash_ll_host_idle(const spi_mem_dev_t *dev) */ static inline void spimem_flash_ll_read_phase(spi_mem_dev_t *dev) { - typeof (dev->user) user = { + typeof(dev->user) user = { .usr_mosi = 0, .usr_miso = 1, .usr_addr = 1, @@ -453,7 +453,7 @@ static inline void spimem_flash_ll_set_cs_pin(spi_mem_dev_t *dev, int pin) */ static inline void spimem_flash_ll_set_read_mode(spi_mem_dev_t *dev, esp_flash_io_mode_t read_mode) { - typeof (dev->ctrl) ctrl; + typeof(dev->ctrl) ctrl; ctrl.val = dev->ctrl.val; ctrl.val &= ~(SPI_MEM_FREAD_QIO_M | SPI_MEM_FREAD_QUAD_M | SPI_MEM_FREAD_DIO_M | SPI_MEM_FREAD_DUAL_M); @@ -606,7 +606,9 @@ static inline void spimem_flash_ll_set_usr_address(spi_mem_dev_t *dev, uint32_t static inline void spimem_flash_ll_set_dummy(spi_mem_dev_t *dev, uint32_t dummy_n) { dev->user.usr_dummy = dummy_n ? 1 : 0; - dev->user1.usr_dummy_cyclelen = dummy_n - 1; + if (dummy_n > 0) { + dev->user1.usr_dummy_cyclelen = dummy_n - 1; + } } /** @@ -648,13 +650,12 @@ static inline uint8_t spimem_flash_ll_get_source_freq_mhz(void) { int source_clk_mhz = 0; - switch (PCR.mspi_clk_conf.mspi_func_clk_sel) - { + switch (PCR.mspi_clk_conf.mspi_func_clk_sel) { case 0: source_clk_mhz = clk_ll_xtal_get_freq_mhz(); break; case 1: - source_clk_mhz = (SOC_CLK_RC_FAST_FREQ_APPROX/(1 * 1000 * 1000)); + source_clk_mhz = (SOC_CLK_RC_FAST_FREQ_APPROX / (1 * 1000 * 1000)); break; case 2: source_clk_mhz = clk_ll_bbpll_get_freq_mhz(); @@ -681,7 +682,7 @@ static inline uint32_t spimem_flash_ll_calculate_clock_reg(uint8_t clkdiv) if (clkdiv == 1) { div_parameter = (1 << 31); } else { - div_parameter = ((clkdiv - 1) | (((clkdiv - 1) / 2 & 0xff) << 8 ) | (((clkdiv - 1) & 0xff) << 16)); + div_parameter = ((clkdiv - 1) | (((clkdiv - 1) / 2 & 0xff) << 8) | (((clkdiv - 1) & 0xff) << 16)); } return div_parameter; } diff --git a/components/hal/esp32c6/include/hal/gpspi_flash_ll.h b/components/hal/esp32c6/include/hal/gpspi_flash_ll.h index 73d64db653..3622702db2 100644 --- a/components/hal/esp32c6/include/hal/gpspi_flash_ll.h +++ b/components/hal/esp32c6/include/hal/gpspi_flash_ll.h @@ -180,7 +180,7 @@ static inline bool gpspi_flash_ll_host_idle(const spi_dev_t *dev) */ static inline void gpspi_flash_ll_read_phase(spi_dev_t *dev) { - typeof (dev->user) user = { + typeof(dev->user) user = { .usr_mosi = 0, .usr_miso = 1, .usr_addr = 1, @@ -211,9 +211,9 @@ static inline void gpspi_flash_ll_set_cs_pin(spi_dev_t *dev, int pin) */ static inline void gpspi_flash_ll_set_read_mode(spi_dev_t *dev, esp_flash_io_mode_t read_mode) { - typeof (dev->ctrl) ctrl; + typeof(dev->ctrl) ctrl; ctrl.val = dev->ctrl.val; - typeof (dev->user) user; + typeof(dev->user) user; user.val = dev->user.val; ctrl.val &= ~(SPI_FCMD_QUAD_M | SPI_FADDR_QUAD_M | SPI_FREAD_QUAD_M | SPI_FCMD_DUAL_M | SPI_FADDR_DUAL_M | SPI_FREAD_DUAL_M); @@ -221,7 +221,7 @@ static inline void gpspi_flash_ll_set_read_mode(spi_dev_t *dev, esp_flash_io_mod switch (read_mode) { case SPI_FLASH_FASTRD: - //the default option + //the default option case SPI_FLASH_SLOWRD: break; case SPI_FLASH_QIO: @@ -339,7 +339,7 @@ static inline void gpspi_flash_ll_set_addr_bitlen(spi_dev_t *dev, uint32_t bitle static inline void gpspi_flash_ll_set_usr_address(spi_dev_t *dev, uint32_t addr, uint32_t bitlen) { // The blank region should be all ones - uint32_t padding_ones = (bitlen == 32? 0 : UINT32_MAX >> bitlen); + uint32_t padding_ones = (bitlen == 32 ? 0 : UINT32_MAX >> bitlen); dev->addr.val = (addr << (32 - bitlen)) | padding_ones; } @@ -363,7 +363,9 @@ static inline void gpspi_flash_ll_set_address(spi_dev_t *dev, uint32_t addr) static inline void gpspi_flash_ll_set_dummy(spi_dev_t *dev, uint32_t dummy_n) { dev->user.usr_dummy = dummy_n ? 1 : 0; - HAL_FORCE_MODIFY_U32_REG_FIELD(dev->user1, usr_dummy_cyclelen, dummy_n - 1); + if (dummy_n > 0) { + HAL_FORCE_MODIFY_U32_REG_FIELD(dev->user1, usr_dummy_cyclelen, dummy_n - 1); + } } /** @@ -388,14 +390,24 @@ static inline void gpspi_flash_ll_set_dummy_out(spi_dev_t *dev, uint32_t out_en, */ static inline void gpspi_flash_ll_set_hold(spi_dev_t *dev, uint32_t hold_n) { - dev->user1.cs_hold_time = hold_n - 1; - dev->user.cs_hold = (hold_n > 0? 1: 0); + dev->user.cs_hold = (hold_n > 0 ? 1 : 0); + if (hold_n > 0) { + dev->user1.cs_hold_time = hold_n - 1; + } } +/** + * Set the delay of SPI clocks before the first SPI clock after the CS active edge. + * + * @param dev Beginning address of the peripheral registers. + * @param cs_setup_time Delay of SPI clocks after the CS active edge, 0 to disable the setup phase. + */ static inline void gpspi_flash_ll_set_cs_setup(spi_dev_t *dev, uint32_t cs_setup_time) { dev->user.cs_setup = (cs_setup_time > 0 ? 1 : 0); - dev->user1.cs_setup_time = cs_setup_time - 1; + if (cs_setup_time > 0) { + dev->user1.cs_setup_time = cs_setup_time - 1; + } } /** @@ -412,7 +424,7 @@ static inline uint32_t gpspi_flash_ll_calculate_clock_reg(uint8_t clkdiv) if (clkdiv == 1) { div_parameter = (1 << 31); } else { - div_parameter = ((clkdiv - 1) | (((clkdiv/2 - 1) & 0xff) << 6 ) | (((clkdiv - 1) & 0xff) << 12)); + div_parameter = ((clkdiv - 1) | (((clkdiv / 2 - 1) & 0xff) << 6) | (((clkdiv - 1) & 0xff) << 12)); } return div_parameter; } diff --git a/components/hal/esp32c6/include/hal/spi_ll.h b/components/hal/esp32c6/include/hal/spi_ll.h index 9ef3d32280..7e3bdc0bd8 100644 --- a/components/hal/esp32c6/include/hal/spi_ll.h +++ b/components/hal/esp32c6/include/hal/spi_ll.h @@ -75,7 +75,7 @@ typedef enum { // SPI base command typedef enum { - /* Slave HD Only */ + /* Slave HD Only */ SPI_LL_BASE_CMD_HD_WRBUF = 0x01, SPI_LL_BASE_CMD_HD_RDBUF = 0x02, SPI_LL_BASE_CMD_HD_WRDMA = 0x03, @@ -97,9 +97,9 @@ typedef enum { * @param host_id Peripheral index number, see `spi_host_device_t` * @param enable Enable/Disable */ -static inline void spi_ll_enable_bus_clock(spi_host_device_t host_id, bool enable) { - switch (host_id) - { +static inline void spi_ll_enable_bus_clock(spi_host_device_t host_id, bool enable) +{ + switch (host_id) { case SPI1_HOST: PCR.mspi_conf.mspi_clk_en = enable; break; @@ -115,9 +115,9 @@ static inline void spi_ll_enable_bus_clock(spi_host_device_t host_id, bool enabl * * @param host_id Peripheral index number, see `spi_host_device_t` */ -static inline void spi_ll_reset_register(spi_host_device_t host_id) { - switch (host_id) - { +static inline void spi_ll_reset_register(spi_host_device_t host_id) +{ + switch (host_id) { case SPI1_HOST: PCR.mspi_conf.mspi_rst_en = 1; PCR.mspi_conf.mspi_rst_en = 0; @@ -151,17 +151,16 @@ static inline void spi_ll_enable_clock(spi_host_device_t host_id, bool enable) __attribute__((always_inline)) static inline void spi_ll_set_clk_source(spi_dev_t *hw, spi_clock_source_t clk_source) { - switch (clk_source) - { - case SPI_CLK_SRC_RC_FAST: - PCR.spi2_clkm_conf.spi2_clkm_sel = 2; - break; - case SPI_CLK_SRC_XTAL: - PCR.spi2_clkm_conf.spi2_clkm_sel = 0; - break; - default: - PCR.spi2_clkm_conf.spi2_clkm_sel = 1; - break; + switch (clk_source) { + case SPI_CLK_SRC_RC_FAST: + PCR.spi2_clkm_conf.spi2_clkm_sel = 2; + break; + case SPI_CLK_SRC_XTAL: + PCR.spi2_clkm_conf.spi2_clkm_sel = 0; + break; + default: + PCR.spi2_clkm_conf.spi2_clkm_sel = 1; + break; } } @@ -1012,7 +1011,9 @@ static inline void spi_ll_set_command(spi_dev_t *hw, uint16_t cmd, int cmdlen, b static inline void spi_ll_set_dummy(spi_dev_t *hw, int dummy_n) { hw->user.usr_dummy = dummy_n ? 1 : 0; - HAL_FORCE_MODIFY_U32_REG_FIELD(hw->user1, usr_dummy_cyclelen, dummy_n - 1); + if (dummy_n > 0) { + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->user1, usr_dummy_cyclelen, dummy_n - 1); + } } /** @@ -1250,28 +1251,25 @@ static inline void spi_ll_format_line_mode_conf_buff(spi_dev_t *hw, spi_line_mod conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET] &= ~SPI_LL_ONE_LINE_CTRL_MASK; conf_buffer[SPI_LL_USER_REG_POS + SPI_LL_CONF_BUFFER_OFFSET] &= ~SPI_LL_ONE_LINE_USER_MASK; - switch (line_mode.cmd_lines) - { + switch (line_mode.cmd_lines) { case 2: SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FCMD_DUAL_M); break; case 4: SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FCMD_QUAD_M); break; default: break; } - switch (line_mode.addr_lines) - { + switch (line_mode.addr_lines) { case 2: SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FADDR_DUAL_M); break; case 4: SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FADDR_QUAD_M); break; default: break; } - switch (line_mode.data_lines) - { - case 2: SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FREAD_DUAL_M ); - SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_USER_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FWRITE_DUAL_M); - break; - case 4: SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FREAD_QUAD_M ); - SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_USER_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FWRITE_QUAD_M); - break; + switch (line_mode.data_lines) { + case 2: SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FREAD_DUAL_M); + SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_USER_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FWRITE_DUAL_M); + break; + case 4: SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FREAD_QUAD_M); + SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_USER_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FWRITE_QUAD_M); + break; default: break; } } @@ -1286,7 +1284,7 @@ static inline void spi_ll_format_line_mode_conf_buff(spi_dev_t *hw, spi_line_mod static inline void spi_ll_format_prep_phase_conf_buffer(spi_dev_t *hw, uint8_t setup, uint32_t conf_buffer[SOC_SPI_SCT_BUFFER_NUM_MAX]) { //user reg: cs_setup - if(setup) { + if (setup) { SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_USER_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_CS_SETUP_M); } else { SPI_LL_CONF_BUF_CLR_BIT(conf_buffer[SPI_LL_USER_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_CS_SETUP_M); @@ -1432,7 +1430,7 @@ static inline void spi_ll_format_din_phase_conf_buffer(spi_dev_t *hw, int bitlen static inline void spi_ll_format_done_phase_conf_buffer(spi_dev_t *hw, int hold, uint32_t conf_buffer[SOC_SPI_SCT_BUFFER_NUM_MAX]) { //user reg: cs_hold - if(hold) { + if (hold) { SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_USER_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_CS_HOLD_M); } else { SPI_LL_CONF_BUF_CLR_BIT(conf_buffer[SPI_LL_USER_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_CS_HOLD_M); @@ -1504,8 +1502,7 @@ static inline void spi_ll_set_magic_number(spi_dev_t *hw, uint8_t magic_value) static inline uint8_t spi_ll_get_slave_hd_base_command(spi_command_t cmd_t) { uint8_t cmd_base = 0x00; - switch (cmd_t) - { + switch (cmd_t) { case SPI_CMD_HD_WRBUF: cmd_base = SPI_LL_BASE_CMD_HD_WRBUF; break; diff --git a/components/hal/esp32c6/include/hal/spimem_flash_ll.h b/components/hal/esp32c6/include/hal/spimem_flash_ll.h index ba68cc3bc7..4c0dbfbde4 100644 --- a/components/hal/esp32c6/include/hal/spimem_flash_ll.h +++ b/components/hal/esp32c6/include/hal/spimem_flash_ll.h @@ -413,7 +413,7 @@ static inline bool spimem_flash_ll_host_idle(const spi_mem_dev_t *dev) */ static inline void spimem_flash_ll_read_phase(spi_mem_dev_t *dev) { - typeof (dev->user) user = { + typeof(dev->user) user = { .usr_mosi = 0, .usr_miso = 1, .usr_addr = 1, @@ -444,7 +444,7 @@ static inline void spimem_flash_ll_set_cs_pin(spi_mem_dev_t *dev, int pin) */ static inline void spimem_flash_ll_set_read_mode(spi_mem_dev_t *dev, esp_flash_io_mode_t read_mode) { - typeof (dev->ctrl) ctrl; + typeof(dev->ctrl) ctrl; ctrl.val = dev->ctrl.val; ctrl.val &= ~(SPI_MEM_FREAD_QIO_M | SPI_MEM_FREAD_QUAD_M | SPI_MEM_FREAD_DIO_M | SPI_MEM_FREAD_DUAL_M); @@ -597,7 +597,9 @@ static inline void spimem_flash_ll_set_usr_address(spi_mem_dev_t *dev, uint32_t static inline void spimem_flash_ll_set_dummy(spi_mem_dev_t *dev, uint32_t dummy_n) { dev->user.usr_dummy = dummy_n ? 1 : 0; - dev->user1.usr_dummy_cyclelen = dummy_n - 1; + if (dummy_n > 0) { + dev->user1.usr_dummy_cyclelen = dummy_n - 1; + } } /** @@ -609,7 +611,7 @@ static inline void spimem_flash_ll_set_dummy(spi_mem_dev_t *dev, uint32_t dummy_ static inline void spimem_flash_ll_set_hold(spi_mem_dev_t *dev, uint32_t hold_n) { dev->ctrl2.cs_hold_time = hold_n - 1; - dev->user.cs_hold = (hold_n > 0? 1: 0); + dev->user.cs_hold = (hold_n > 0 ? 1 : 0); } static inline void spimem_flash_ll_set_cs_setup(spi_mem_dev_t *dev, uint32_t cs_setup_time) @@ -681,7 +683,7 @@ static inline uint32_t spimem_flash_ll_calculate_clock_reg(uint8_t clkdiv) if (clkdiv == 1) { div_parameter = (1 << 31); } else { - div_parameter = ((clkdiv - 1) | (((clkdiv - 1) / 2 & 0xff) << 8 ) | (((clkdiv - 1) & 0xff) << 16)); + div_parameter = ((clkdiv - 1) | (((clkdiv - 1) / 2 & 0xff) << 8) | (((clkdiv - 1) & 0xff) << 16)); } return div_parameter; } diff --git a/components/hal/esp32c61/include/hal/gpspi_flash_ll.h b/components/hal/esp32c61/include/hal/gpspi_flash_ll.h index f305388201..654d8e5f20 100644 --- a/components/hal/esp32c61/include/hal/gpspi_flash_ll.h +++ b/components/hal/esp32c61/include/hal/gpspi_flash_ll.h @@ -180,7 +180,7 @@ static inline bool gpspi_flash_ll_host_idle(const spi_dev_t *dev) */ static inline void gpspi_flash_ll_read_phase(spi_dev_t *dev) { - typeof (dev->user) user = { + typeof(dev->user) user = { .usr_mosi = 0, .usr_miso = 1, .usr_addr = 1, @@ -211,9 +211,9 @@ static inline void gpspi_flash_ll_set_cs_pin(spi_dev_t *dev, int pin) */ static inline void gpspi_flash_ll_set_read_mode(spi_dev_t *dev, esp_flash_io_mode_t read_mode) { - typeof (dev->ctrl) ctrl; + typeof(dev->ctrl) ctrl; ctrl.val = dev->ctrl.val; - typeof (dev->user) user; + typeof(dev->user) user; user.val = dev->user.val; ctrl.val &= ~(SPI_FCMD_QUAD_M | SPI_FADDR_QUAD_M | SPI_FREAD_QUAD_M | SPI_FCMD_DUAL_M | SPI_FADDR_DUAL_M | SPI_FREAD_DUAL_M); @@ -221,7 +221,7 @@ static inline void gpspi_flash_ll_set_read_mode(spi_dev_t *dev, esp_flash_io_mod switch (read_mode) { case SPI_FLASH_FASTRD: - //the default option + //the default option case SPI_FLASH_SLOWRD: break; case SPI_FLASH_QIO: @@ -339,7 +339,7 @@ static inline void gpspi_flash_ll_set_addr_bitlen(spi_dev_t *dev, uint32_t bitle static inline void gpspi_flash_ll_set_usr_address(spi_dev_t *dev, uint32_t addr, uint32_t bitlen) { // The blank region should be all ones - uint32_t padding_ones = (bitlen == 32? 0 : UINT32_MAX >> bitlen); + uint32_t padding_ones = (bitlen == 32 ? 0 : UINT32_MAX >> bitlen); dev->addr.val = (addr << (32 - bitlen)) | padding_ones; } @@ -363,7 +363,9 @@ static inline void gpspi_flash_ll_set_address(spi_dev_t *dev, uint32_t addr) static inline void gpspi_flash_ll_set_dummy(spi_dev_t *dev, uint32_t dummy_n) { dev->user.usr_dummy = dummy_n ? 1 : 0; - HAL_FORCE_MODIFY_U32_REG_FIELD(dev->user1, usr_dummy_cyclelen, dummy_n - 1); + if (dummy_n > 0) { + HAL_FORCE_MODIFY_U32_REG_FIELD(dev->user1, usr_dummy_cyclelen, dummy_n - 1); + } } /** @@ -388,14 +390,24 @@ static inline void gpspi_flash_ll_set_dummy_out(spi_dev_t *dev, uint32_t out_en, */ static inline void gpspi_flash_ll_set_hold(spi_dev_t *dev, uint32_t hold_n) { - dev->user1.cs_hold_time = hold_n - 1; - dev->user.cs_hold = (hold_n > 0? 1: 0); + dev->user.cs_hold = (hold_n > 0 ? 1 : 0); + if (hold_n > 0) { + dev->user1.cs_hold_time = hold_n - 1; + } } +/** + * Set the delay of SPI clocks before the first SPI clock after the CS active edge. + * + * @param dev Beginning address of the peripheral registers. + * @param cs_setup_time Delay of SPI clocks after the CS active edge, 0 to disable the setup phase. + */ static inline void gpspi_flash_ll_set_cs_setup(spi_dev_t *dev, uint32_t cs_setup_time) { dev->user.cs_setup = (cs_setup_time > 0 ? 1 : 0); - dev->user1.cs_setup_time = cs_setup_time - 1; + if (cs_setup_time > 0) { + dev->user1.cs_setup_time = cs_setup_time - 1; + } } /** @@ -412,7 +424,7 @@ static inline uint32_t gpspi_flash_ll_calculate_clock_reg(uint8_t clkdiv) if (clkdiv == 1) { div_parameter = (1 << 31); } else { - div_parameter = ((clkdiv - 1) | (((clkdiv/2 - 1) & 0xff) << 6 ) | (((clkdiv - 1) & 0xff) << 12)); + div_parameter = ((clkdiv - 1) | (((clkdiv / 2 - 1) & 0xff) << 6) | (((clkdiv - 1) & 0xff) << 12)); } return div_parameter; } diff --git a/components/hal/esp32c61/include/hal/spi_ll.h b/components/hal/esp32c61/include/hal/spi_ll.h index 164b88ba39..c71bbb2125 100644 --- a/components/hal/esp32c61/include/hal/spi_ll.h +++ b/components/hal/esp32c61/include/hal/spi_ll.h @@ -77,7 +77,7 @@ typedef enum { // SPI base command typedef enum { - /* Slave HD Only */ + /* Slave HD Only */ SPI_LL_BASE_CMD_HD_WRBUF = 0x01, SPI_LL_BASE_CMD_HD_RDBUF = 0x02, SPI_LL_BASE_CMD_HD_WRDMA = 0x03, @@ -99,9 +99,9 @@ typedef enum { * @param host_id Peripheral index number, see `spi_host_device_t` * @param enable Enable/Disable */ -static inline void spi_ll_enable_bus_clock(spi_host_device_t host_id, bool enable) { - switch (host_id) - { +static inline void spi_ll_enable_bus_clock(spi_host_device_t host_id, bool enable) +{ + switch (host_id) { case SPI1_HOST: PCR.mspi_conf.mspi_clk_en = enable; break; @@ -117,9 +117,9 @@ static inline void spi_ll_enable_bus_clock(spi_host_device_t host_id, bool enabl * * @param host_id Peripheral index number, see `spi_host_device_t` */ -static inline void spi_ll_reset_register(spi_host_device_t host_id) { - switch (host_id) - { +static inline void spi_ll_reset_register(spi_host_device_t host_id) +{ + switch (host_id) { case SPI1_HOST: PCR.mspi_conf.mspi_rst_en = 1; PCR.mspi_conf.mspi_rst_en = 0; @@ -153,17 +153,16 @@ static inline void spi_ll_enable_clock(spi_host_device_t host_id, bool enable) __attribute__((always_inline)) static inline void spi_ll_set_clk_source(spi_dev_t *hw, spi_clock_source_t clk_source) { - switch (clk_source) - { - case SPI_CLK_SRC_RC_FAST: - PCR.spi2_clkm_conf.spi2_clkm_sel = 2; - break; - case SPI_CLK_SRC_XTAL: - PCR.spi2_clkm_conf.spi2_clkm_sel = 0; - break; - default: - PCR.spi2_clkm_conf.spi2_clkm_sel = 1; - break; + switch (clk_source) { + case SPI_CLK_SRC_RC_FAST: + PCR.spi2_clkm_conf.spi2_clkm_sel = 2; + break; + case SPI_CLK_SRC_XTAL: + PCR.spi2_clkm_conf.spi2_clkm_sel = 0; + break; + default: + PCR.spi2_clkm_conf.spi2_clkm_sel = 1; + break; } } @@ -1032,7 +1031,9 @@ static inline void spi_ll_set_command(spi_dev_t *hw, uint16_t cmd, int cmdlen, b static inline void spi_ll_set_dummy(spi_dev_t *hw, int dummy_n) { hw->user.usr_dummy = dummy_n ? 1 : 0; - HAL_FORCE_MODIFY_U32_REG_FIELD(hw->user1, usr_dummy_cyclelen, dummy_n - 1); + if (dummy_n > 0) { + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->user1, usr_dummy_cyclelen, dummy_n - 1); + } } /** @@ -1198,8 +1199,7 @@ static inline uint32_t spi_ll_slave_hd_get_last_addr(spi_dev_t *hw) static inline uint8_t spi_ll_get_slave_hd_base_command(spi_command_t cmd_t) { uint8_t cmd_base = 0x00; - switch (cmd_t) - { + switch (cmd_t) { case SPI_CMD_HD_WRBUF: cmd_base = SPI_LL_BASE_CMD_HD_WRBUF; break; diff --git a/components/hal/esp32c61/include/hal/spimem_flash_ll.h b/components/hal/esp32c61/include/hal/spimem_flash_ll.h index 4a2507d03f..b9f4ef3a1d 100644 --- a/components/hal/esp32c61/include/hal/spimem_flash_ll.h +++ b/components/hal/esp32c61/include/hal/spimem_flash_ll.h @@ -415,7 +415,7 @@ static inline bool spimem_flash_ll_host_idle(const spi_mem_dev_t *dev) */ static inline void spimem_flash_ll_read_phase(spi_mem_dev_t *dev) { - typeof (dev->user) user = { + typeof(dev->user) user = { .usr_mosi = 0, .usr_miso = 1, .usr_addr = 1, @@ -446,7 +446,7 @@ static inline void spimem_flash_ll_set_cs_pin(spi_mem_dev_t *dev, int pin) */ static inline void spimem_flash_ll_set_read_mode(spi_mem_dev_t *dev, esp_flash_io_mode_t read_mode) { - typeof (dev->ctrl) ctrl; + typeof(dev->ctrl) ctrl; ctrl.val = dev->ctrl.val; ctrl.val &= ~(SPI_MEM_FREAD_QIO_M | SPI_MEM_FREAD_QUAD_M | SPI_MEM_FREAD_DIO_M | SPI_MEM_FREAD_DUAL_M); @@ -599,7 +599,9 @@ static inline void spimem_flash_ll_set_usr_address(spi_mem_dev_t *dev, uint32_t static inline void spimem_flash_ll_set_dummy(spi_mem_dev_t *dev, uint32_t dummy_n) { dev->user.usr_dummy = dummy_n ? 1 : 0; - dev->user1.usr_dummy_cyclelen = dummy_n - 1; + if (dummy_n > 0) { + dev->user1.usr_dummy_cyclelen = dummy_n - 1; + } } /** @@ -630,13 +632,12 @@ static inline uint8_t spimem_flash_ll_get_source_freq_mhz(void) { int source_clk_mhz = 0; - switch (PCR.mspi_clk_conf.mspi_func_clk_sel) - { + switch (PCR.mspi_clk_conf.mspi_func_clk_sel) { case 0: source_clk_mhz = clk_ll_xtal_get_freq_mhz(); break; case 1: - source_clk_mhz = (SOC_CLK_RC_FAST_FREQ_APPROX/(1 * 1000 * 1000)); + source_clk_mhz = (SOC_CLK_RC_FAST_FREQ_APPROX / (1 * 1000 * 1000)); break; case 2: source_clk_mhz = clk_ll_bbpll_get_freq_mhz(); @@ -663,7 +664,7 @@ static inline uint32_t spimem_flash_ll_calculate_clock_reg(uint8_t clkdiv) if (clkdiv == 1) { div_parameter = (1 << 31); } else { - div_parameter = ((clkdiv - 1) | (((clkdiv - 1) / 2 & 0xff) << 8 ) | (((clkdiv - 1) & 0xff) << 16)); + div_parameter = ((clkdiv - 1) | (((clkdiv - 1) / 2 & 0xff) << 8) | (((clkdiv - 1) & 0xff) << 16)); } return div_parameter; } diff --git a/components/hal/esp32h2/include/hal/gpspi_flash_ll.h b/components/hal/esp32h2/include/hal/gpspi_flash_ll.h index 124863b7d6..682a0cacb3 100644 --- a/components/hal/esp32h2/include/hal/gpspi_flash_ll.h +++ b/components/hal/esp32h2/include/hal/gpspi_flash_ll.h @@ -180,7 +180,7 @@ static inline bool gpspi_flash_ll_host_idle(const spi_dev_t *dev) */ static inline void gpspi_flash_ll_read_phase(spi_dev_t *dev) { - typeof (dev->user) user = { + typeof(dev->user) user = { .usr_mosi = 0, .usr_miso = 1, .usr_addr = 1, @@ -211,9 +211,9 @@ static inline void gpspi_flash_ll_set_cs_pin(spi_dev_t *dev, int pin) */ static inline void gpspi_flash_ll_set_read_mode(spi_dev_t *dev, esp_flash_io_mode_t read_mode) { - typeof (dev->ctrl) ctrl; + typeof(dev->ctrl) ctrl; ctrl.val = dev->ctrl.val; - typeof (dev->user) user; + typeof(dev->user) user; user.val = dev->user.val; ctrl.val &= ~(SPI_FCMD_QUAD_M | SPI_FADDR_QUAD_M | SPI_FREAD_QUAD_M | SPI_FCMD_DUAL_M | SPI_FADDR_DUAL_M | SPI_FREAD_DUAL_M); @@ -221,7 +221,7 @@ static inline void gpspi_flash_ll_set_read_mode(spi_dev_t *dev, esp_flash_io_mod switch (read_mode) { case SPI_FLASH_FASTRD: - //the default option + //the default option case SPI_FLASH_SLOWRD: break; case SPI_FLASH_QIO: @@ -339,7 +339,7 @@ static inline void gpspi_flash_ll_set_addr_bitlen(spi_dev_t *dev, uint32_t bitle static inline void gpspi_flash_ll_set_usr_address(spi_dev_t *dev, uint32_t addr, uint32_t bitlen) { // The blank region should be all ones - uint32_t padding_ones = (bitlen == 32? 0 : UINT32_MAX >> bitlen); + uint32_t padding_ones = (bitlen == 32 ? 0 : UINT32_MAX >> bitlen); dev->addr.val = (addr << (32 - bitlen)) | padding_ones; } @@ -363,7 +363,9 @@ static inline void gpspi_flash_ll_set_address(spi_dev_t *dev, uint32_t addr) static inline void gpspi_flash_ll_set_dummy(spi_dev_t *dev, uint32_t dummy_n) { dev->user.usr_dummy = dummy_n ? 1 : 0; - HAL_FORCE_MODIFY_U32_REG_FIELD(dev->user1, usr_dummy_cyclelen, dummy_n - 1); + if (dummy_n > 0) { + HAL_FORCE_MODIFY_U32_REG_FIELD(dev->user1, usr_dummy_cyclelen, dummy_n - 1); + } } /** @@ -388,14 +390,24 @@ static inline void gpspi_flash_ll_set_dummy_out(spi_dev_t *dev, uint32_t out_en, */ static inline void gpspi_flash_ll_set_hold(spi_dev_t *dev, uint32_t hold_n) { - dev->user1.cs_hold_time = hold_n - 1; - dev->user.cs_hold = (hold_n > 0? 1: 0); + dev->user.cs_hold = (hold_n > 0 ? 1 : 0); + if (hold_n > 0) { + dev->user1.cs_hold_time = hold_n - 1; + } } +/** + * Set the delay of SPI clocks before the first SPI clock after the CS active edge. + * + * @param dev Beginning address of the peripheral registers. + * @param cs_setup_time Delay of SPI clocks after the CS active edge, 0 to disable the setup phase. + */ static inline void gpspi_flash_ll_set_cs_setup(spi_dev_t *dev, uint32_t cs_setup_time) { dev->user.cs_setup = (cs_setup_time > 0 ? 1 : 0); - dev->user1.cs_setup_time = cs_setup_time - 1; + if (cs_setup_time > 0) { + dev->user1.cs_setup_time = cs_setup_time - 1; + } } /** @@ -412,7 +424,7 @@ static inline uint32_t gpspi_flash_ll_calculate_clock_reg(uint8_t clkdiv) if (clkdiv == 1) { div_parameter = (1 << 31); } else { - div_parameter = ((clkdiv - 1) | (((clkdiv/2 - 1) & 0xff) << 6 ) | (((clkdiv - 1) & 0xff) << 12)); + div_parameter = ((clkdiv - 1) | (((clkdiv / 2 - 1) & 0xff) << 6) | (((clkdiv - 1) & 0xff) << 12)); } return div_parameter; } diff --git a/components/hal/esp32h2/include/hal/spi_ll.h b/components/hal/esp32h2/include/hal/spi_ll.h index 7fbb59aa2c..ed4dec39e7 100644 --- a/components/hal/esp32h2/include/hal/spi_ll.h +++ b/components/hal/esp32h2/include/hal/spi_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -75,7 +75,7 @@ typedef enum { // SPI base command typedef enum { - /* Slave HD Only */ + /* Slave HD Only */ SPI_LL_BASE_CMD_HD_WRBUF = 0x01, SPI_LL_BASE_CMD_HD_RDBUF = 0x02, SPI_LL_BASE_CMD_HD_WRDMA = 0x03, @@ -96,9 +96,9 @@ typedef enum { * @param host_id Peripheral index number, see `spi_host_device_t` * @param enable Enable/Disable */ -static inline void spi_ll_enable_bus_clock(spi_host_device_t host_id, bool enable) { - switch (host_id) - { +static inline void spi_ll_enable_bus_clock(spi_host_device_t host_id, bool enable) +{ + switch (host_id) { case SPI1_HOST: PCR.mspi_conf.mspi_clk_en = enable; break; @@ -114,9 +114,9 @@ static inline void spi_ll_enable_bus_clock(spi_host_device_t host_id, bool enabl * * @param host_id Peripheral index number, see `spi_host_device_t` */ -static inline void spi_ll_reset_register(spi_host_device_t host_id) { - switch (host_id) - { +static inline void spi_ll_reset_register(spi_host_device_t host_id) +{ + switch (host_id) { case SPI1_HOST: PCR.mspi_conf.mspi_rst_en = 1; PCR.mspi_conf.mspi_rst_en = 0; @@ -150,17 +150,16 @@ static inline void spi_ll_enable_clock(spi_host_device_t host_id, bool enable) __attribute__((always_inline)) static inline void spi_ll_set_clk_source(spi_dev_t *hw, spi_clock_source_t clk_source) { - switch (clk_source) - { - case SPI_CLK_SRC_RC_FAST: - PCR.spi2_clkm_conf.spi2_clkm_sel = 2; - break; - case SPI_CLK_SRC_XTAL: - PCR.spi2_clkm_conf.spi2_clkm_sel = 0; - break; - default: - PCR.spi2_clkm_conf.spi2_clkm_sel = 1; - break; + switch (clk_source) { + case SPI_CLK_SRC_RC_FAST: + PCR.spi2_clkm_conf.spi2_clkm_sel = 2; + break; + case SPI_CLK_SRC_XTAL: + PCR.spi2_clkm_conf.spi2_clkm_sel = 0; + break; + default: + PCR.spi2_clkm_conf.spi2_clkm_sel = 1; + break; } } @@ -1011,7 +1010,9 @@ static inline void spi_ll_set_command(spi_dev_t *hw, uint16_t cmd, int cmdlen, b static inline void spi_ll_set_dummy(spi_dev_t *hw, int dummy_n) { hw->user.usr_dummy = dummy_n ? 1 : 0; - HAL_FORCE_MODIFY_U32_REG_FIELD(hw->user1, usr_dummy_cyclelen, dummy_n - 1); + if (dummy_n > 0) { + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->user1, usr_dummy_cyclelen, dummy_n - 1); + } } /** @@ -1249,33 +1250,30 @@ static inline void spi_ll_format_line_mode_conf_buff(spi_dev_t *hw, spi_line_mod conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET] &= ~SPI_LL_ONE_LINE_CTRL_MASK; conf_buffer[SPI_LL_USER_REG_POS + SPI_LL_CONF_BUFFER_OFFSET] &= ~SPI_LL_ONE_LINE_USER_MASK; - switch (line_mode.cmd_lines) - { + switch (line_mode.cmd_lines) { case 2: SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FCMD_DUAL_M); break; case 4: SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FCMD_QUAD_M); break; - case 8: SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FCMD_OCT_M ); break; + case 8: SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FCMD_OCT_M); break; default: break; } - switch (line_mode.addr_lines) - { + switch (line_mode.addr_lines) { case 2: SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FADDR_DUAL_M); break; case 4: SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FADDR_QUAD_M); break; - case 8: SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FADDR_OCT_M ); break; + case 8: SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FADDR_OCT_M); break; default: break; } - switch (line_mode.data_lines) - { - case 2: SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FREAD_DUAL_M ); - SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_USER_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FWRITE_DUAL_M); - break; - case 4: SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FREAD_QUAD_M ); - SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_USER_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FWRITE_QUAD_M); - break; - case 8: SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FREAD_OCT_M ); - SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_USER_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FWRITE_OCT_M); - break; + switch (line_mode.data_lines) { + case 2: SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FREAD_DUAL_M); + SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_USER_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FWRITE_DUAL_M); + break; + case 4: SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FREAD_QUAD_M); + SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_USER_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FWRITE_QUAD_M); + break; + case 8: SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FREAD_OCT_M); + SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_USER_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FWRITE_OCT_M); + break; default: break; } } @@ -1290,7 +1288,7 @@ static inline void spi_ll_format_line_mode_conf_buff(spi_dev_t *hw, spi_line_mod static inline void spi_ll_format_prep_phase_conf_buffer(spi_dev_t *hw, uint8_t setup, uint32_t conf_buffer[SOC_SPI_SCT_BUFFER_NUM_MAX]) { //user reg: cs_setup - if(setup) { + if (setup) { SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_USER_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_CS_SETUP_M); } else { SPI_LL_CONF_BUF_CLR_BIT(conf_buffer[SPI_LL_USER_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_CS_SETUP_M); @@ -1436,7 +1434,7 @@ static inline void spi_ll_format_din_phase_conf_buffer(spi_dev_t *hw, int bitlen static inline void spi_ll_format_done_phase_conf_buffer(spi_dev_t *hw, int hold, uint32_t conf_buffer[SOC_SPI_SCT_BUFFER_NUM_MAX]) { //user reg: cs_hold - if(hold) { + if (hold) { SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_USER_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_CS_HOLD_M); } else { SPI_LL_CONF_BUF_CLR_BIT(conf_buffer[SPI_LL_USER_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_CS_HOLD_M); @@ -1509,8 +1507,7 @@ static inline void spi_ll_set_magic_number(spi_dev_t *hw, uint8_t magic_value) static inline uint8_t spi_ll_get_slave_hd_base_command(spi_command_t cmd_t) { uint8_t cmd_base = 0x00; - switch (cmd_t) - { + switch (cmd_t) { case SPI_CMD_HD_WRBUF: cmd_base = SPI_LL_BASE_CMD_HD_WRBUF; break; diff --git a/components/hal/esp32h2/include/hal/spimem_flash_ll.h b/components/hal/esp32h2/include/hal/spimem_flash_ll.h index caf551023f..feaf317f74 100644 --- a/components/hal/esp32h2/include/hal/spimem_flash_ll.h +++ b/components/hal/esp32h2/include/hal/spimem_flash_ll.h @@ -414,7 +414,7 @@ static inline bool spimem_flash_ll_host_idle(const spi_mem_dev_t *dev) */ static inline void spimem_flash_ll_read_phase(spi_mem_dev_t *dev) { - typeof (dev->user) user = { + typeof(dev->user) user = { .usr_mosi = 0, .usr_miso = 1, .usr_addr = 1, @@ -445,7 +445,7 @@ static inline void spimem_flash_ll_set_cs_pin(spi_mem_dev_t *dev, int pin) */ static inline void spimem_flash_ll_set_read_mode(spi_mem_dev_t *dev, esp_flash_io_mode_t read_mode) { - typeof (dev->ctrl) ctrl; + typeof(dev->ctrl) ctrl; ctrl.val = dev->ctrl.val; ctrl.val &= ~(SPI_MEM_FREAD_QIO_M | SPI_MEM_FREAD_QUAD_M | SPI_MEM_FREAD_DIO_M | SPI_MEM_FREAD_DUAL_M); ctrl.val |= SPI_MEM_FASTRD_MODE_M; @@ -618,7 +618,9 @@ static inline void spimem_flash_ll_set_usr_address(spi_mem_dev_t *dev, uint32_t static inline void spimem_flash_ll_set_dummy(spi_mem_dev_t *dev, uint32_t dummy_n) { dev->user.usr_dummy = dummy_n ? 1 : 0; - dev->user1.usr_dummy_cyclelen = dummy_n - 1; + if (dummy_n > 0) { + dev->user1.usr_dummy_cyclelen = dummy_n - 1; + } } /** @@ -630,7 +632,7 @@ static inline void spimem_flash_ll_set_dummy(spi_mem_dev_t *dev, uint32_t dummy_ static inline void spimem_flash_ll_set_hold(spi_mem_dev_t *dev, uint32_t hold_n) { dev->ctrl2.cs_hold_time = hold_n - 1; - dev->user.cs_hold = (hold_n > 0? 1: 0); + dev->user.cs_hold = (hold_n > 0 ? 1 : 0); } static inline void spimem_flash_ll_set_cs_setup(spi_mem_dev_t *dev, uint32_t cs_setup_time) @@ -683,7 +685,7 @@ static inline uint32_t spimem_flash_ll_calculate_clock_reg(uint8_t clkdiv) if (clkdiv == 1) { div_parameter = (1 << 31); } else { - div_parameter = ((clkdiv - 1) | (((clkdiv - 1) / 2 & 0xff) << 8 ) | (((clkdiv - 1) & 0xff) << 16)); + div_parameter = ((clkdiv - 1) | (((clkdiv - 1) / 2 & 0xff) << 8) | (((clkdiv - 1) & 0xff) << 16)); } return div_parameter; } diff --git a/components/hal/esp32p4/include/hal/gpspi_flash_ll.h b/components/hal/esp32p4/include/hal/gpspi_flash_ll.h index 73d64db653..3622702db2 100644 --- a/components/hal/esp32p4/include/hal/gpspi_flash_ll.h +++ b/components/hal/esp32p4/include/hal/gpspi_flash_ll.h @@ -180,7 +180,7 @@ static inline bool gpspi_flash_ll_host_idle(const spi_dev_t *dev) */ static inline void gpspi_flash_ll_read_phase(spi_dev_t *dev) { - typeof (dev->user) user = { + typeof(dev->user) user = { .usr_mosi = 0, .usr_miso = 1, .usr_addr = 1, @@ -211,9 +211,9 @@ static inline void gpspi_flash_ll_set_cs_pin(spi_dev_t *dev, int pin) */ static inline void gpspi_flash_ll_set_read_mode(spi_dev_t *dev, esp_flash_io_mode_t read_mode) { - typeof (dev->ctrl) ctrl; + typeof(dev->ctrl) ctrl; ctrl.val = dev->ctrl.val; - typeof (dev->user) user; + typeof(dev->user) user; user.val = dev->user.val; ctrl.val &= ~(SPI_FCMD_QUAD_M | SPI_FADDR_QUAD_M | SPI_FREAD_QUAD_M | SPI_FCMD_DUAL_M | SPI_FADDR_DUAL_M | SPI_FREAD_DUAL_M); @@ -221,7 +221,7 @@ static inline void gpspi_flash_ll_set_read_mode(spi_dev_t *dev, esp_flash_io_mod switch (read_mode) { case SPI_FLASH_FASTRD: - //the default option + //the default option case SPI_FLASH_SLOWRD: break; case SPI_FLASH_QIO: @@ -339,7 +339,7 @@ static inline void gpspi_flash_ll_set_addr_bitlen(spi_dev_t *dev, uint32_t bitle static inline void gpspi_flash_ll_set_usr_address(spi_dev_t *dev, uint32_t addr, uint32_t bitlen) { // The blank region should be all ones - uint32_t padding_ones = (bitlen == 32? 0 : UINT32_MAX >> bitlen); + uint32_t padding_ones = (bitlen == 32 ? 0 : UINT32_MAX >> bitlen); dev->addr.val = (addr << (32 - bitlen)) | padding_ones; } @@ -363,7 +363,9 @@ static inline void gpspi_flash_ll_set_address(spi_dev_t *dev, uint32_t addr) static inline void gpspi_flash_ll_set_dummy(spi_dev_t *dev, uint32_t dummy_n) { dev->user.usr_dummy = dummy_n ? 1 : 0; - HAL_FORCE_MODIFY_U32_REG_FIELD(dev->user1, usr_dummy_cyclelen, dummy_n - 1); + if (dummy_n > 0) { + HAL_FORCE_MODIFY_U32_REG_FIELD(dev->user1, usr_dummy_cyclelen, dummy_n - 1); + } } /** @@ -388,14 +390,24 @@ static inline void gpspi_flash_ll_set_dummy_out(spi_dev_t *dev, uint32_t out_en, */ static inline void gpspi_flash_ll_set_hold(spi_dev_t *dev, uint32_t hold_n) { - dev->user1.cs_hold_time = hold_n - 1; - dev->user.cs_hold = (hold_n > 0? 1: 0); + dev->user.cs_hold = (hold_n > 0 ? 1 : 0); + if (hold_n > 0) { + dev->user1.cs_hold_time = hold_n - 1; + } } +/** + * Set the delay of SPI clocks before the first SPI clock after the CS active edge. + * + * @param dev Beginning address of the peripheral registers. + * @param cs_setup_time Delay of SPI clocks after the CS active edge, 0 to disable the setup phase. + */ static inline void gpspi_flash_ll_set_cs_setup(spi_dev_t *dev, uint32_t cs_setup_time) { dev->user.cs_setup = (cs_setup_time > 0 ? 1 : 0); - dev->user1.cs_setup_time = cs_setup_time - 1; + if (cs_setup_time > 0) { + dev->user1.cs_setup_time = cs_setup_time - 1; + } } /** @@ -412,7 +424,7 @@ static inline uint32_t gpspi_flash_ll_calculate_clock_reg(uint8_t clkdiv) if (clkdiv == 1) { div_parameter = (1 << 31); } else { - div_parameter = ((clkdiv - 1) | (((clkdiv/2 - 1) & 0xff) << 6 ) | (((clkdiv - 1) & 0xff) << 12)); + div_parameter = ((clkdiv - 1) | (((clkdiv / 2 - 1) & 0xff) << 6) | (((clkdiv - 1) & 0xff) << 12)); } return div_parameter; } diff --git a/components/hal/esp32p4/include/hal/lcd_ll.h b/components/hal/esp32p4/include/hal/lcd_ll.h index 99e41cfc68..b698b91e84 100644 --- a/components/hal/esp32p4/include/hal/lcd_ll.h +++ b/components/hal/esp32p4/include/hal/lcd_ll.h @@ -363,8 +363,12 @@ static inline void lcd_ll_set_phase_cycles(lcd_cam_dev_t *dev, uint32_t cmd_cycl dev->lcd_user.lcd_dummy = (dummy_cycles > 0); dev->lcd_user.lcd_dout = (data_cycles > 0); dev->lcd_user.lcd_cmd_2_cycle_en = cmd_cycles > 1; - dev->lcd_user.lcd_dummy_cyclelen = dummy_cycles - 1; - dev->lcd_user.lcd_dout_cyclelen = data_cycles - 1; + if (dummy_cycles > 0) { + dev->lcd_user.lcd_dummy_cyclelen = dummy_cycles - 1; + } + if (data_cycles > 0) { + dev->lcd_user.lcd_dout_cyclelen = data_cycles - 1; + } } /** @@ -377,8 +381,12 @@ static inline void lcd_ll_set_phase_cycles(lcd_cam_dev_t *dev, uint32_t cmd_cycl static inline void lcd_ll_set_blank_cycles(lcd_cam_dev_t *dev, uint32_t fk_cycles, uint32_t bk_cycles) { dev->lcd_misc.lcd_bk_en = (fk_cycles || bk_cycles); - dev->lcd_misc.lcd_vfk_cyclelen = fk_cycles - 1; - dev->lcd_misc.lcd_vbk_cyclelen = bk_cycles - 1; + if (fk_cycles > 0) { + dev->lcd_misc.lcd_vfk_cyclelen = fk_cycles - 1; + } + if (bk_cycles > 0) { + dev->lcd_misc.lcd_vbk_cyclelen = bk_cycles - 1; + } } /** diff --git a/components/hal/esp32p4/include/hal/spi_ll.h b/components/hal/esp32p4/include/hal/spi_ll.h index 7f3bc1ed98..955c7f63a6 100644 --- a/components/hal/esp32p4/include/hal/spi_ll.h +++ b/components/hal/esp32p4/include/hal/spi_ll.h @@ -76,7 +76,7 @@ typedef enum { // SPI base command typedef enum { - /* Slave HD Only */ + /* Slave HD Only */ SPI_LL_BASE_CMD_HD_WRBUF = 0x01, SPI_LL_BASE_CMD_HD_RDBUF = 0x02, SPI_LL_BASE_CMD_HD_WRDMA = 0x03, @@ -98,9 +98,9 @@ typedef enum { * @param host_id Peripheral index number, see `spi_host_device_t` * @param enable Enable/Disable */ -static inline void _spi_ll_enable_bus_clock(spi_host_device_t host_id, bool enable) { - switch (host_id) - { +static inline void _spi_ll_enable_bus_clock(spi_host_device_t host_id, bool enable) +{ + switch (host_id) { case SPI2_HOST: HP_SYS_CLKRST.soc_clk_ctrl1.reg_gpspi2_sys_clk_en = enable; HP_SYS_CLKRST.soc_clk_ctrl2.reg_gpspi2_apb_clk_en = enable; @@ -122,9 +122,9 @@ static inline void _spi_ll_enable_bus_clock(spi_host_device_t host_id, bool enab * * @param host_id Peripheral index number, see `spi_host_device_t` */ -static inline void spi_ll_reset_register(spi_host_device_t host_id) { - switch (host_id) - { +static inline void spi_ll_reset_register(spi_host_device_t host_id) +{ + switch (host_id) { case SPI2_HOST: HP_SYS_CLKRST.hp_rst_en2.reg_rst_en_spi2 = 1; HP_SYS_CLKRST.hp_rst_en2.reg_rst_en_spi2 = 0; @@ -149,8 +149,7 @@ static inline void spi_ll_reset_register(spi_host_device_t host_id) { */ static inline void _spi_ll_enable_clock(spi_host_device_t host_id, bool enable) { - switch (host_id) - { + switch (host_id) { case SPI2_HOST: HP_SYS_CLKRST.peri_clk_ctrl116.reg_gpspi2_hs_clk_en = enable; HP_SYS_CLKRST.peri_clk_ctrl116.reg_gpspi2_mst_clk_en = enable; @@ -1078,7 +1077,9 @@ static inline void spi_ll_set_command(spi_dev_t *hw, uint16_t cmd, int cmdlen, b static inline void spi_ll_set_dummy(spi_dev_t *hw, int dummy_n) { hw->user.usr_dummy = dummy_n ? 1 : 0; - HAL_FORCE_MODIFY_U32_REG_FIELD(hw->user1, usr_dummy_cyclelen, dummy_n - 1); + if (dummy_n > 0) { + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->user1, usr_dummy_cyclelen, dummy_n - 1); + } } /** @@ -1244,8 +1245,7 @@ static inline uint32_t spi_ll_slave_hd_get_last_addr(spi_dev_t *hw) static inline uint8_t spi_ll_get_slave_hd_base_command(spi_command_t cmd_t) { uint8_t cmd_base = 0x00; - switch (cmd_t) - { + switch (cmd_t) { case SPI_CMD_HD_WRBUF: cmd_base = SPI_LL_BASE_CMD_HD_WRBUF; break; diff --git a/components/hal/esp32p4/include/hal/spimem_flash_ll.h b/components/hal/esp32p4/include/hal/spimem_flash_ll.h index 95d11df008..c2c84cd29c 100644 --- a/components/hal/esp32p4/include/hal/spimem_flash_ll.h +++ b/components/hal/esp32p4/include/hal/spimem_flash_ll.h @@ -424,7 +424,7 @@ static inline bool spimem_flash_ll_host_idle(const spi_mem_dev_t *dev) */ static inline void spimem_flash_ll_read_phase(spi_mem_dev_t *dev) { - typeof (dev->user) user = { + typeof(dev->user) user = { .usr_mosi = 0, .usr_miso = 1, .usr_addr = 1, @@ -455,7 +455,7 @@ static inline void spimem_flash_ll_set_cs_pin(spi_mem_dev_t *dev, int pin) */ static inline void spimem_flash_ll_set_read_mode(spi_mem_dev_t *dev, esp_flash_io_mode_t read_mode) { - typeof (dev->ctrl) ctrl; + typeof(dev->ctrl) ctrl; ctrl.val = dev->ctrl.val; ctrl.val &= ~(SPI1_MEM_C_FREAD_QIO_M | SPI1_MEM_C_FREAD_QUAD_M | SPI1_MEM_C_FREAD_DIO_M | SPI1_MEM_C_FREAD_DUAL_M); ctrl.val |= SPI1_MEM_C_FASTRD_MODE_M; @@ -611,7 +611,9 @@ static inline void spimem_flash_ll_set_usr_address(spi_mem_dev_t *dev, uint32_t static inline void spimem_flash_ll_set_dummy(spi_mem_dev_t *dev, uint32_t dummy_n) { dev->user.usr_dummy = dummy_n ? 1 : 0; - dev->user1.usr_dummy_cyclelen = dummy_n - 1; + if (dummy_n > 0) { + dev->user1.usr_dummy_cyclelen = dummy_n - 1; + } } /** @@ -654,8 +656,7 @@ static inline uint8_t spimem_flash_ll_get_source_freq_mhz(void) // return 80; int source_clk_mhz = 0; - switch (HP_SYS_CLKRST.peri_clk_ctrl00.reg_flash_clk_src_sel) - { + switch (HP_SYS_CLKRST.peri_clk_ctrl00.reg_flash_clk_src_sel) { case 0: source_clk_mhz = clk_ll_xtal_load_freq_mhz(); break; @@ -687,7 +688,7 @@ static inline uint32_t spimem_flash_ll_calculate_clock_reg(uint8_t clkdiv) if (clkdiv == 1) { div_parameter = (1 << 31); } else { - div_parameter = ((clkdiv - 1) | (((clkdiv - 1) / 2 & 0xff) << 8 ) | (((clkdiv - 1) & 0xff) << 16)); + div_parameter = ((clkdiv - 1) | (((clkdiv - 1) / 2 & 0xff) << 8) | (((clkdiv - 1) & 0xff) << 16)); } return div_parameter; } diff --git a/components/hal/esp32s2/include/hal/gpspi_flash_ll.h b/components/hal/esp32s2/include/hal/gpspi_flash_ll.h index 7ff525a694..b016334ee0 100644 --- a/components/hal/esp32s2/include/hal/gpspi_flash_ll.h +++ b/components/hal/esp32s2/include/hal/gpspi_flash_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -174,7 +174,7 @@ static inline bool gpspi_flash_ll_host_idle(const spi_dev_t *dev) */ static inline void gpspi_flash_ll_read_phase(spi_dev_t *dev) { - typeof (dev->user) user = { + typeof(dev->user) user = { .usr_mosi = 0, .usr_miso = 1, .usr_addr = 1, @@ -209,9 +209,9 @@ static inline void gpspi_flash_ll_set_cs_pin(spi_dev_t *dev, int pin) */ static inline void gpspi_flash_ll_set_read_mode(spi_dev_t *dev, esp_flash_io_mode_t read_mode) { - typeof (dev->ctrl) ctrl; + typeof(dev->ctrl) ctrl; ctrl.val = dev->ctrl.val; - typeof (dev->user) user; + typeof(dev->user) user; user.val = dev->user.val; ctrl.val &= ~(SPI_FCMD_QUAD_M | SPI_FADDR_QUAD_M | SPI_FREAD_QUAD_M | SPI_FCMD_DUAL_M | SPI_FADDR_DUAL_M | SPI_FREAD_DUAL_M); @@ -219,7 +219,7 @@ static inline void gpspi_flash_ll_set_read_mode(spi_dev_t *dev, esp_flash_io_mod switch (read_mode) { case SPI_FLASH_FASTRD: - //the default option + //the default option case SPI_FLASH_SLOWRD: break; case SPI_FLASH_QIO: @@ -333,7 +333,7 @@ static inline void gpspi_flash_ll_set_addr_bitlen(spi_dev_t *dev, uint32_t bitle static inline void gpspi_flash_ll_set_usr_address(spi_dev_t *dev, uint32_t addr, uint32_t bitlen) { // The blank region should be all ones - uint32_t padding_ones = (bitlen == 32? 0 : UINT32_MAX >> bitlen); + uint32_t padding_ones = (bitlen == 32 ? 0 : UINT32_MAX >> bitlen); dev->addr = (addr << (32 - bitlen)) | padding_ones; } @@ -357,7 +357,9 @@ static inline void gpspi_flash_ll_set_address(spi_dev_t *dev, uint32_t addr) static inline void gpspi_flash_ll_set_dummy(spi_dev_t *dev, uint32_t dummy_n) { dev->user.usr_dummy = dummy_n ? 1 : 0; - HAL_FORCE_MODIFY_U32_REG_FIELD(dev->user1, usr_dummy_cyclelen, dummy_n - 1); + if (dummy_n > 0) { + HAL_FORCE_MODIFY_U32_REG_FIELD(dev->user1, usr_dummy_cyclelen, dummy_n - 1); + } } /** @@ -374,16 +376,32 @@ static inline void gpspi_flash_ll_set_dummy_out(spi_dev_t *dev, uint32_t out_en, dev->ctrl.d_pol = out_lev; } +/** + * Set extra hold time of CS after the clocks. + * + * @param dev Beginning address of the peripheral registers. + * @param hold_n Cycles of clocks before CS is inactive + */ static inline void gpspi_flash_ll_set_hold(spi_dev_t *dev, uint32_t hold_n) { - dev->ctrl2.cs_hold_time = hold_n - 1; - dev->user.cs_hold = (hold_n > 0? 1: 0); + dev->user.cs_hold = (hold_n > 0 ? 1 : 0); + if (hold_n > 0) { + dev->ctrl2.cs_hold_time = hold_n - 1; + } } +/** + * Set the delay of SPI clocks before the first SPI clock after the CS active edge. + * + * @param dev Beginning address of the peripheral registers. + * @param cs_setup_time Delay of SPI clocks after the CS active edge, 0 to disable the setup phase. + */ static inline void gpspi_flash_ll_set_cs_setup(spi_dev_t *dev, uint32_t cs_setup_time) { dev->user.cs_setup = (cs_setup_time > 0 ? 1 : 0); - dev->ctrl2.cs_setup_time = cs_setup_time - 1; + if (cs_setup_time > 0) { + dev->ctrl2.cs_setup_time = cs_setup_time - 1; + } } /** @@ -400,7 +418,7 @@ static inline uint32_t gpspi_flash_ll_calculate_clock_reg(uint8_t clkdiv) if (clkdiv == 1) { div_parameter = (1 << 31); } else { - div_parameter = ((clkdiv - 1) | (((clkdiv/2 - 1) & 0xff) << 6 ) | (((clkdiv - 1) & 0xff) << 12)); + div_parameter = ((clkdiv - 1) | (((clkdiv / 2 - 1) & 0xff) << 6) | (((clkdiv - 1) & 0xff) << 12)); } return div_parameter; } diff --git a/components/hal/esp32s2/include/hal/spi_ll.h b/components/hal/esp32s2/include/hal/spi_ll.h index 19d62c57e2..3c64961d20 100644 --- a/components/hal/esp32s2/include/hal/spi_ll.h +++ b/components/hal/esp32s2/include/hal/spi_ll.h @@ -90,7 +90,7 @@ typedef enum { // SPI base command in esp32s2 typedef enum { - /* Slave HD Only */ + /* Slave HD Only */ SPI_LL_BASE_CMD_HD_WRBUF = 0x01, SPI_LL_BASE_CMD_HD_RDBUF = 0x02, SPI_LL_BASE_CMD_HD_WRDMA = 0x03, @@ -112,10 +112,10 @@ typedef enum { * @param host_id Peripheral index number, see `spi_host_device_t` * @param enable Enable/Disable */ -static inline void spi_ll_enable_bus_clock(spi_host_device_t host_id, bool enable) { +static inline void spi_ll_enable_bus_clock(spi_host_device_t host_id, bool enable) +{ if (enable) { - switch (host_id) - { + switch (host_id) { case SPI1_HOST: DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_SPI01_CLK_EN); break; @@ -128,8 +128,7 @@ static inline void spi_ll_enable_bus_clock(spi_host_device_t host_id, bool enabl default: HAL_ASSERT(false); } } else { - switch (host_id) - { + switch (host_id) { case SPI1_HOST: DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_SPI01_CLK_EN); break; @@ -153,9 +152,9 @@ static inline void spi_ll_enable_bus_clock(spi_host_device_t host_id, bool enabl * * @param host_id Peripheral index number, see `spi_host_device_t` */ -static inline void spi_ll_reset_register(spi_host_device_t host_id) { - switch (host_id) - { +static inline void spi_ll_reset_register(spi_host_device_t host_id) +{ + switch (host_id) { case SPI1_HOST: DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_SPI01_RST); DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_SPI01_RST); @@ -853,7 +852,9 @@ static inline void spi_ll_set_miso_delay(spi_dev_t *hw, int delay_mode, int dela static inline void spi_ll_set_dummy(spi_dev_t *hw, int dummy_n) { hw->user.usr_dummy = dummy_n ? 1 : 0; - HAL_FORCE_MODIFY_U32_REG_FIELD(hw->user1, usr_dummy_cyclelen, dummy_n - 1); + if (dummy_n > 0) { + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->user1, usr_dummy_cyclelen, dummy_n - 1); + } } /** @@ -1207,10 +1208,10 @@ static inline uint32_t spi_ll_slave_hd_get_last_addr(spi_dev_t *hw) * @param host_id Peripheral index number, see `spi_host_device_t` * @param enable Enable/Disable */ -static inline void spi_dma_ll_enable_bus_clock(spi_host_device_t host_id, bool enable) { +static inline void spi_dma_ll_enable_bus_clock(spi_host_device_t host_id, bool enable) +{ if (enable) { - switch (host_id) - { + switch (host_id) { case SPI2_HOST: DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_SPI2_DMA_CLK_EN); break; @@ -1221,8 +1222,7 @@ static inline void spi_dma_ll_enable_bus_clock(spi_host_device_t host_id, bool e HAL_ASSERT(false); } } else { - switch (host_id) - { + switch (host_id) { case SPI2_HOST: DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_SPI2_DMA_CLK_EN); break; @@ -1244,9 +1244,9 @@ static inline void spi_dma_ll_enable_bus_clock(spi_host_device_t host_id, bool e * * @param host_id Peripheral index number, see `spi_host_device_t` */ -static inline void spi_dma_ll_reset_register(spi_host_device_t host_id) { - switch (host_id) - { +static inline void spi_dma_ll_reset_register(spi_host_device_t host_id) +{ + switch (host_id) { case SPI2_HOST: DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_SPI2_DMA_RST); DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_SPI2_DMA_RST); @@ -1531,7 +1531,7 @@ static inline bool spi_ll_tx_get_empty_err(spi_dev_t *hw) static inline void spi_ll_set_conf_base_bitslen(spi_dev_t *hw, uint8_t conf_base) { // 7 bits wide - if(conf_base < 128) { + if (conf_base < 128) { hw->slv_wrbuf_dlen.conf_base_bitlen = conf_base; } } @@ -1592,33 +1592,30 @@ static inline void spi_ll_format_line_mode_conf_buff(spi_dev_t *hw, spi_line_mod conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET] &= ~SPI_LL_ONE_LINE_CTRL_MASK; conf_buffer[SPI_LL_USER_REG_POS + SPI_LL_CONF_BUFFER_OFFSET] &= ~SPI_LL_ONE_LINE_USER_MASK; - switch (line_mode.cmd_lines) - { + switch (line_mode.cmd_lines) { case 2: SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FCMD_DUAL_M); break; case 4: SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FCMD_QUAD_M); break; - case 8: SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FCMD_OCT_M ); break; + case 8: SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FCMD_OCT_M); break; default: break; } - switch (line_mode.addr_lines) - { + switch (line_mode.addr_lines) { case 2: SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FADDR_DUAL_M); break; case 4: SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FADDR_QUAD_M); break; - case 8: SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FADDR_OCT_M ); break; + case 8: SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FADDR_OCT_M); break; default: break; } - switch (line_mode.data_lines) - { - case 2: SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FREAD_DUAL_M ); - SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_USER_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FWRITE_DUAL_M); - break; - case 4: SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FREAD_QUAD_M ); - SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_USER_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FWRITE_QUAD_M); - break; - case 8: SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FREAD_OCT_M ); - SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_USER_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FWRITE_OCT_M); - break; + switch (line_mode.data_lines) { + case 2: SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FREAD_DUAL_M); + SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_USER_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FWRITE_DUAL_M); + break; + case 4: SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FREAD_QUAD_M); + SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_USER_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FWRITE_QUAD_M); + break; + case 8: SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FREAD_OCT_M); + SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_USER_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FWRITE_OCT_M); + break; default: break; } } @@ -1633,7 +1630,7 @@ static inline void spi_ll_format_line_mode_conf_buff(spi_dev_t *hw, spi_line_mod static inline void spi_ll_format_prep_phase_conf_buffer(spi_dev_t *hw, uint8_t setup, uint32_t conf_buffer[SOC_SPI_SCT_BUFFER_NUM_MAX]) { //user reg: cs_setup - if(setup) { + if (setup) { SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_USER_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_CS_SETUP_M); } else { SPI_LL_CONF_BUF_CLR_BIT(conf_buffer[SPI_LL_USER_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_CS_SETUP_M); @@ -1771,7 +1768,7 @@ static inline void spi_ll_format_din_phase_conf_buffer(spi_dev_t *hw, int bitlen static inline void spi_ll_format_done_phase_conf_buffer(spi_dev_t *hw, int hold, uint32_t conf_buffer[SOC_SPI_SCT_BUFFER_NUM_MAX]) { //user reg: cs_hold - if(hold) { + if (hold) { SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_USER_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_CS_HOLD_M); } else { SPI_LL_CONF_BUF_CLR_BIT(conf_buffer[SPI_LL_USER_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_CS_HOLD_M); @@ -1856,8 +1853,7 @@ static inline void spi_ll_set_magic_number(spi_dev_t *hw, uint8_t magic_value) static inline uint8_t spi_ll_get_slave_hd_base_command(spi_command_t cmd_t) { uint8_t cmd_base = 0x00; - switch (cmd_t) - { + switch (cmd_t) { case SPI_CMD_HD_WRBUF: cmd_base = SPI_LL_BASE_CMD_HD_WRBUF; break; diff --git a/components/hal/esp32s2/include/hal/spimem_flash_ll.h b/components/hal/esp32s2/include/hal/spimem_flash_ll.h index 42a0fba45b..e03745f7e1 100644 --- a/components/hal/esp32s2/include/hal/spimem_flash_ll.h +++ b/components/hal/esp32s2/include/hal/spimem_flash_ll.h @@ -353,7 +353,7 @@ static inline bool spimem_flash_ll_host_idle(const spi_mem_dev_t *dev) */ static inline void spimem_flash_ll_read_phase(spi_mem_dev_t *dev) { - typeof (dev->user) user = { + typeof(dev->user) user = { .usr_mosi = 0, .usr_miso = 1, .usr_addr = 1, @@ -384,7 +384,7 @@ static inline void spimem_flash_ll_set_cs_pin(spi_mem_dev_t *dev, int pin) */ static inline void spimem_flash_ll_set_read_mode(spi_mem_dev_t *dev, esp_flash_io_mode_t read_mode) { - typeof (dev->ctrl) ctrl; + typeof(dev->ctrl) ctrl; ctrl.val = dev->ctrl.val; ctrl.val &= ~(SPI_MEM_FREAD_QIO_M | SPI_MEM_FREAD_QUAD_M | SPI_MEM_FREAD_DIO_M | SPI_MEM_FREAD_DUAL_M); ctrl.val |= SPI_MEM_FASTRD_MODE_M; @@ -524,7 +524,9 @@ static inline void spimem_flash_ll_set_usr_address(spi_mem_dev_t *dev, uint32_t static inline void spimem_flash_ll_set_dummy(spi_mem_dev_t *dev, uint32_t dummy_n) { dev->user.usr_dummy = dummy_n ? 1 : 0; - HAL_FORCE_MODIFY_U32_REG_FIELD(dev->user1, usr_dummy_cyclelen, dummy_n - 1); + if (dummy_n > 0) { + HAL_FORCE_MODIFY_U32_REG_FIELD(dev->user1, usr_dummy_cyclelen, dummy_n - 1); + } } /** @@ -544,7 +546,7 @@ static inline void spimem_flash_ll_set_dummy_out(spi_mem_dev_t *dev, uint32_t ou static inline void spimem_flash_ll_set_hold(spi_mem_dev_t *dev, uint32_t hold_n) { dev->ctrl2.cs_hold_time = hold_n - 1; - dev->user.cs_hold = (hold_n > 0? 1: 0); + dev->user.cs_hold = (hold_n > 0 ? 1 : 0); } static inline void spimem_flash_ll_set_cs_setup(spi_mem_dev_t *dev, uint32_t cs_setup_time) @@ -567,17 +569,17 @@ static inline uint8_t spimem_flash_ll_get_source_freq_mhz(void) // In the future, we can get the CPU clock source by calling interface. uint8_t clock_val = 0; switch (SPIMEM0.spi_core_clk_sel.spi01_clk_sel) { - case 0: - clock_val = 80; - break; - case 1: - clock_val = 120; - break; - case 2: - clock_val = 160; - break; - default: - abort(); + case 0: + clock_val = 80; + break; + case 1: + clock_val = 120; + break; + case 2: + clock_val = 160; + break; + default: + abort(); } return clock_val; } @@ -596,7 +598,7 @@ static inline uint32_t spimem_flash_ll_calculate_clock_reg(uint8_t clkdiv) if (clkdiv == 1) { div_parameter = (1 << 31); } else { - div_parameter = ((clkdiv - 1) | (((clkdiv - 1) / 2 & 0xff) << 8 ) | (((clkdiv - 1) & 0xff) << 16)); + div_parameter = ((clkdiv - 1) | (((clkdiv - 1) / 2 & 0xff) << 8) | (((clkdiv - 1) & 0xff) << 16)); } return div_parameter; } diff --git a/components/hal/esp32s3/include/hal/gpspi_flash_ll.h b/components/hal/esp32s3/include/hal/gpspi_flash_ll.h index f0068e4f90..d80622f0b0 100644 --- a/components/hal/esp32s3/include/hal/gpspi_flash_ll.h +++ b/components/hal/esp32s3/include/hal/gpspi_flash_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -185,7 +185,7 @@ static inline bool gpspi_flash_ll_host_idle(const spi_dev_t *dev) */ static inline void gpspi_flash_ll_read_phase(spi_dev_t *dev) { - typeof (dev->user) user = { + typeof(dev->user) user = { .usr_mosi = 0, .usr_miso = 1, .usr_addr = 1, @@ -216,9 +216,9 @@ static inline void gpspi_flash_ll_set_cs_pin(spi_dev_t *dev, int pin) */ static inline void gpspi_flash_ll_set_read_mode(spi_dev_t *dev, esp_flash_io_mode_t read_mode) { - typeof (dev->ctrl) ctrl; + typeof(dev->ctrl) ctrl; ctrl.val = dev->ctrl.val; - typeof (dev->user) user; + typeof(dev->user) user; user.val = dev->user.val; ctrl.val &= ~(SPI_FCMD_QUAD_M | SPI_FADDR_QUAD_M | SPI_FREAD_QUAD_M | SPI_FCMD_DUAL_M | SPI_FADDR_DUAL_M | SPI_FREAD_DUAL_M); @@ -226,7 +226,7 @@ static inline void gpspi_flash_ll_set_read_mode(spi_dev_t *dev, esp_flash_io_mod switch (read_mode) { case SPI_FLASH_FASTRD: - //the default option + //the default option case SPI_FLASH_SLOWRD: break; case SPI_FLASH_QIO: @@ -344,7 +344,7 @@ static inline void gpspi_flash_ll_set_addr_bitlen(spi_dev_t *dev, uint32_t bitle static inline void gpspi_flash_ll_set_usr_address(spi_dev_t *dev, uint32_t addr, uint32_t bitlen) { // The blank region should be all ones - uint32_t padding_ones = (bitlen == 32? 0 : UINT32_MAX >> bitlen); + uint32_t padding_ones = (bitlen == 32 ? 0 : UINT32_MAX >> bitlen); dev->addr = (addr << (32 - bitlen)) | padding_ones; } @@ -369,7 +369,9 @@ static inline void gpspi_flash_ll_set_address(spi_dev_t *dev, uint32_t addr) static inline void gpspi_flash_ll_set_dummy(spi_dev_t *dev, uint32_t dummy_n) { dev->user.usr_dummy = dummy_n ? 1 : 0; - HAL_FORCE_MODIFY_U32_REG_FIELD(dev->user1, usr_dummy_cyclelen, dummy_n - 1) + if (dummy_n > 0) { + HAL_FORCE_MODIFY_U32_REG_FIELD(dev->user1, usr_dummy_cyclelen, dummy_n - 1) + } } /** @@ -394,14 +396,24 @@ static inline void gpspi_flash_ll_set_dummy_out(spi_dev_t *dev, uint32_t out_en, */ static inline void gpspi_flash_ll_set_hold(spi_dev_t *dev, uint32_t hold_n) { - dev->user1.cs_hold_time = hold_n - 1; - dev->user.cs_hold = (hold_n > 0? 1: 0); + dev->user.cs_hold = (hold_n > 0 ? 1 : 0); + if (hold_n > 0) { + dev->user1.cs_hold_time = hold_n - 1; + } } +/** + * Set the delay of SPI clocks before the first SPI clock after the CS active edge. + * + * @param dev Beginning address of the peripheral registers. + * @param cs_setup_time Delay of SPI clocks after the CS active edge, 0 to disable the setup phase. + */ static inline void gpspi_flash_ll_set_cs_setup(spi_dev_t *dev, uint32_t cs_setup_time) { dev->user.cs_setup = (cs_setup_time > 0 ? 1 : 0); - dev->user1.cs_setup_time = cs_setup_time - 1; + if (cs_setup_time > 0) { + dev->user1.cs_setup_time = cs_setup_time - 1; + } } /** @@ -418,7 +430,7 @@ static inline uint32_t gpspi_flash_ll_calculate_clock_reg(uint8_t clkdiv) if (clkdiv == 1) { div_parameter = (1 << 31); } else { - div_parameter = ((clkdiv - 1) | (((clkdiv/2 - 1) & 0xff) << 6 ) | (((clkdiv - 1) & 0xff) << 12)); + div_parameter = ((clkdiv - 1) | (((clkdiv / 2 - 1) & 0xff) << 6) | (((clkdiv - 1) & 0xff) << 12)); } return div_parameter; } diff --git a/components/hal/esp32s3/include/hal/lcd_ll.h b/components/hal/esp32s3/include/hal/lcd_ll.h index 7e46542a37..ce864003c6 100644 --- a/components/hal/esp32s3/include/hal/lcd_ll.h +++ b/components/hal/esp32s3/include/hal/lcd_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -347,8 +347,12 @@ static inline void lcd_ll_set_phase_cycles(lcd_cam_dev_t *dev, uint32_t cmd_cycl dev->lcd_user.lcd_dummy = (dummy_cycles > 0); dev->lcd_user.lcd_dout = (data_cycles > 0); dev->lcd_user.lcd_cmd_2_cycle_en = cmd_cycles > 1; - dev->lcd_user.lcd_dummy_cyclelen = dummy_cycles - 1; - dev->lcd_user.lcd_dout_cyclelen = data_cycles - 1; + if (dummy_cycles > 0) { + dev->lcd_user.lcd_dummy_cyclelen = dummy_cycles - 1; + } + if (data_cycles > 0) { + dev->lcd_user.lcd_dout_cyclelen = data_cycles - 1; + } } /** @@ -361,8 +365,12 @@ static inline void lcd_ll_set_phase_cycles(lcd_cam_dev_t *dev, uint32_t cmd_cycl static inline void lcd_ll_set_blank_cycles(lcd_cam_dev_t *dev, uint32_t fk_cycles, uint32_t bk_cycles) { dev->lcd_misc.lcd_bk_en = (fk_cycles || bk_cycles); - dev->lcd_misc.lcd_vfk_cyclelen = fk_cycles - 1; - dev->lcd_misc.lcd_vbk_cyclelen = bk_cycles - 1; + if (fk_cycles > 0) { + dev->lcd_misc.lcd_vfk_cyclelen = fk_cycles - 1; + } + if (bk_cycles > 0) { + dev->lcd_misc.lcd_vbk_cyclelen = bk_cycles - 1; + } } /** @@ -571,7 +579,7 @@ static inline void lcd_ll_set_command(lcd_cam_dev_t *dev, uint32_t data_width, u } /** - * @brief Wether to enable RGB interface + * @brief Whether to enable RGB interface * * @param dev LCD register base address * @param en True to enable RGB interface, False to disable RGB interface @@ -594,7 +602,7 @@ static inline void lcd_ll_enable_auto_next_frame(lcd_cam_dev_t *dev, bool en) } /** - * @brief Wether to output HSYNC signal in porch resion + * @brief Whether to output HSYNC signal in porch region * * @param dev LCD register base address * @param en True to enable, False to disable @@ -726,7 +734,7 @@ static inline uint32_t lcd_ll_get_interrupt_status(lcd_cam_dev_t *dev) * @brief Clear interrupt status by mask * * @param dev LCD register base address - * @param mask Interupt status mask + * @param mask Interrupt status mask */ __attribute__((always_inline)) static inline void lcd_ll_clear_interrupt_status(lcd_cam_dev_t *dev, uint32_t mask) diff --git a/components/hal/esp32s3/include/hal/spi_ll.h b/components/hal/esp32s3/include/hal/spi_ll.h index bdbeb9267d..29f69048d2 100644 --- a/components/hal/esp32s3/include/hal/spi_ll.h +++ b/components/hal/esp32s3/include/hal/spi_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -77,7 +77,7 @@ typedef enum { // SPI base command in esp32s3 typedef enum { - /* Slave HD Only */ + /* Slave HD Only */ SPI_LL_BASE_CMD_HD_WRBUF = 0x01, SPI_LL_BASE_CMD_HD_RDBUF = 0x02, SPI_LL_BASE_CMD_HD_WRDMA = 0x03, @@ -99,9 +99,9 @@ typedef enum { * @param host_id Peripheral index number, see `spi_host_device_t` * @param enable Enable/Disable */ -static inline void spi_ll_enable_bus_clock(spi_host_device_t host_id, bool enable) { - switch (host_id) - { +static inline void spi_ll_enable_bus_clock(spi_host_device_t host_id, bool enable) +{ + switch (host_id) { case SPI1_HOST: SYSTEM.perip_clk_en0.spi01_clk_en = enable; break; @@ -124,9 +124,9 @@ static inline void spi_ll_enable_bus_clock(spi_host_device_t host_id, bool enabl * * @param host_id Peripheral index number, see `spi_host_device_t` */ -static inline void spi_ll_reset_register(spi_host_device_t host_id) { - switch (host_id) - { +static inline void spi_ll_reset_register(spi_host_device_t host_id) +{ + switch (host_id) { case SPI1_HOST: SYSTEM.perip_rst_en0.spi01_rst = 1; SYSTEM.perip_rst_en0.spi01_rst = 0; @@ -167,15 +167,15 @@ static inline void spi_ll_enable_clock(spi_host_device_t host_id, bool enable) * @param clk_source clock source to select, see valid sources in type `spi_clock_source_t` */ __attribute__((always_inline)) -static inline void spi_ll_set_clk_source(spi_dev_t *hw, spi_clock_source_t clk_source){ - switch (clk_source) - { - case SPI_CLK_SRC_XTAL: - hw->clk_gate.mst_clk_sel = 0; - break; - default: - hw->clk_gate.mst_clk_sel = 1; - break; +static inline void spi_ll_set_clk_source(spi_dev_t *hw, spi_clock_source_t clk_source) +{ + switch (clk_source) { + case SPI_CLK_SRC_XTAL: + hw->clk_gate.mst_clk_sel = 0; + break; + default: + hw->clk_gate.mst_clk_sel = 1; + break; } } @@ -1040,7 +1040,9 @@ static inline void spi_ll_set_command(spi_dev_t *hw, uint16_t cmd, int cmdlen, b static inline void spi_ll_set_dummy(spi_dev_t *hw, int dummy_n) { hw->user.usr_dummy = dummy_n ? 1 : 0; - HAL_FORCE_MODIFY_U32_REG_FIELD(hw->user1, usr_dummy_cyclelen, dummy_n - 1); + if (dummy_n > 0) { + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->user1, usr_dummy_cyclelen, dummy_n - 1); + } } /** @@ -1279,33 +1281,30 @@ static inline void spi_ll_format_line_mode_conf_buff(spi_dev_t *hw, spi_line_mod conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET] &= ~SPI_LL_ONE_LINE_CTRL_MASK; conf_buffer[SPI_LL_USER_REG_POS + SPI_LL_CONF_BUFFER_OFFSET] &= ~SPI_LL_ONE_LINE_USER_MASK; - switch (line_mode.cmd_lines) - { + switch (line_mode.cmd_lines) { case 2: SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FCMD_DUAL_M); break; case 4: SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FCMD_QUAD_M); break; - case 8: SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FCMD_OCT_M ); break; + case 8: SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FCMD_OCT_M); break; default: break; } - switch (line_mode.addr_lines) - { + switch (line_mode.addr_lines) { case 2: SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FADDR_DUAL_M); break; case 4: SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FADDR_QUAD_M); break; - case 8: SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FADDR_OCT_M ); break; + case 8: SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FADDR_OCT_M); break; default: break; } - switch (line_mode.data_lines) - { - case 2: SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FREAD_DUAL_M ); - SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_USER_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FWRITE_DUAL_M); - break; - case 4: SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FREAD_QUAD_M ); - SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_USER_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FWRITE_QUAD_M); - break; - case 8: SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FREAD_OCT_M ); - SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_USER_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FWRITE_OCT_M); - break; + switch (line_mode.data_lines) { + case 2: SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FREAD_DUAL_M); + SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_USER_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FWRITE_DUAL_M); + break; + case 4: SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FREAD_QUAD_M); + SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_USER_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FWRITE_QUAD_M); + break; + case 8: SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FREAD_OCT_M); + SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_USER_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FWRITE_OCT_M); + break; default: break; } } @@ -1320,7 +1319,7 @@ static inline void spi_ll_format_line_mode_conf_buff(spi_dev_t *hw, spi_line_mod static inline void spi_ll_format_prep_phase_conf_buffer(spi_dev_t *hw, uint8_t setup, uint32_t conf_buffer[SOC_SPI_SCT_BUFFER_NUM_MAX]) { //user reg: cs_setup - if(setup) { + if (setup) { SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_USER_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_CS_SETUP_M); } else { SPI_LL_CONF_BUF_CLR_BIT(conf_buffer[SPI_LL_USER_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_CS_SETUP_M); @@ -1466,7 +1465,7 @@ static inline void spi_ll_format_din_phase_conf_buffer(spi_dev_t *hw, int bitlen static inline void spi_ll_format_done_phase_conf_buffer(spi_dev_t *hw, int hold, uint32_t conf_buffer[SOC_SPI_SCT_BUFFER_NUM_MAX]) { //user reg: cs_hold - if(hold) { + if (hold) { SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_USER_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_CS_HOLD_M); } else { SPI_LL_CONF_BUF_CLR_BIT(conf_buffer[SPI_LL_USER_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_CS_HOLD_M); @@ -1538,8 +1537,7 @@ static inline void spi_ll_set_magic_number(spi_dev_t *hw, uint8_t magic_value) static inline uint8_t spi_ll_get_slave_hd_base_command(spi_command_t cmd_t) { uint8_t cmd_base = 0x00; - switch (cmd_t) - { + switch (cmd_t) { case SPI_CMD_HD_WRBUF: cmd_base = SPI_LL_BASE_CMD_HD_WRBUF; break; diff --git a/components/hal/esp32s3/include/hal/spimem_flash_ll.h b/components/hal/esp32s3/include/hal/spimem_flash_ll.h index 41c1e8b388..e034092606 100644 --- a/components/hal/esp32s3/include/hal/spimem_flash_ll.h +++ b/components/hal/esp32s3/include/hal/spimem_flash_ll.h @@ -416,7 +416,7 @@ static inline bool spimem_flash_ll_host_idle(const spi_mem_dev_t *dev) */ static inline void spimem_flash_ll_read_phase(spi_mem_dev_t *dev) { - typeof (dev->user) user = { + typeof(dev->user) user = { .usr_mosi = 0, .usr_miso = 1, .usr_addr = 1, @@ -447,7 +447,7 @@ static inline void spimem_flash_ll_set_cs_pin(spi_mem_dev_t *dev, int pin) */ static inline void spimem_flash_ll_set_read_mode(spi_mem_dev_t *dev, esp_flash_io_mode_t read_mode) { - typeof (dev->ctrl) ctrl; + typeof(dev->ctrl) ctrl; ctrl.val = dev->ctrl.val; ctrl.val &= ~(SPI_MEM_FREAD_QIO_M | SPI_MEM_FREAD_QUAD_M | SPI_MEM_FREAD_DIO_M | SPI_MEM_FREAD_DUAL_M | SPI_MEM_FCMD_OCT | SPI_MEM_FADDR_OCT | SPI_MEM_FDIN_OCT | SPI_MEM_FDOUT_OCT); @@ -604,7 +604,9 @@ static inline void spimem_flash_ll_set_usr_address(spi_mem_dev_t *dev, uint32_t static inline void spimem_flash_ll_set_dummy(spi_mem_dev_t *dev, uint32_t dummy_n) { dev->user.usr_dummy = dummy_n ? 1 : 0; - dev->user1.usr_dummy_cyclelen = dummy_n - 1; + if (dummy_n > 0) { + dev->user1.usr_dummy_cyclelen = dummy_n - 1; + } } /** @@ -624,7 +626,7 @@ static inline void spimem_flash_ll_set_dummy_out(spi_mem_dev_t *dev, uint32_t ou static inline void spimem_flash_ll_set_hold(spi_mem_dev_t *dev, uint32_t hold_n) { dev->ctrl2.cs_hold_time = hold_n - 1; - dev->user.cs_hold = (hold_n > 0? 1: 0); + dev->user.cs_hold = (hold_n > 0 ? 1 : 0); } static inline void spimem_flash_ll_set_cs_setup(spi_mem_dev_t *dev, uint32_t cs_setup_time) @@ -652,20 +654,20 @@ static inline uint8_t spimem_flash_ll_get_source_freq_mhz(void) // In the future, we can get the CPU clock source by calling interface. uint8_t clock_val = 0; switch (SPIMEM0.core_clk_sel.core_clk_sel) { - case 0: - clock_val = 80; - break; - case 1: - clock_val = 120; - break; - case 2: - clock_val = 160; - break; - case 3: - clock_val = 240; - break; - default: - abort(); + case 0: + clock_val = 80; + break; + case 1: + clock_val = 120; + break; + case 2: + clock_val = 160; + break; + case 3: + clock_val = 240; + break; + default: + abort(); } return clock_val; } @@ -684,7 +686,7 @@ static inline uint32_t spimem_flash_ll_calculate_clock_reg(uint8_t clkdiv) if (clkdiv == 1) { div_parameter = (1 << 31); } else { - div_parameter = ((clkdiv - 1) | (((clkdiv - 1) / 2 & 0xff) << 8 ) | (((clkdiv - 1) & 0xff) << 16)); + div_parameter = ((clkdiv - 1) | (((clkdiv - 1) / 2 & 0xff) << 8) | (((clkdiv - 1) & 0xff) << 16)); } return div_parameter; } From 13d0e83cd6abf339863f14ffc270c1d6015a6a6b Mon Sep 17 00:00:00 2001 From: morris Date: Tue, 26 Nov 2024 12:50:04 +0800 Subject: [PATCH 2/2] fix(driver): issues reported by coverity --- .../dvp/src/esp_cam_ctlr_dvp_gdma.c | 4 +- .../esp_driver_jpeg/jpeg_parse_marker.c | 4 +- components/esp_driver_parlio/src/parlio_rx.c | 4 +- components/esp_driver_uart/src/uart_vfs.c | 2 +- .../esp_hw_support/debug_probe/debug_probe.c | 43 ++++++++----------- 5 files changed, 28 insertions(+), 29 deletions(-) diff --git a/components/esp_driver_cam/dvp/src/esp_cam_ctlr_dvp_gdma.c b/components/esp_driver_cam/dvp/src/esp_cam_ctlr_dvp_gdma.c index 4e428b2505..e3c76f20bf 100644 --- a/components/esp_driver_cam/dvp/src/esp_cam_ctlr_dvp_gdma.c +++ b/components/esp_driver_cam/dvp/src/esp_cam_ctlr_dvp_gdma.c @@ -44,7 +44,9 @@ static void IRAM_ATTR esp_cam_ctlr_dvp_config_dma_desc(esp_cam_ctlr_dvp_dma_desc n++; } - desc[n - 1].next = NULL; + if (n > 0) { + desc[n - 1].next = NULL; + } } /** diff --git a/components/esp_driver_jpeg/jpeg_parse_marker.c b/components/esp_driver_jpeg/jpeg_parse_marker.c index 13fcc831d0..0e238a1971 100644 --- a/components/esp_driver_jpeg/jpeg_parse_marker.c +++ b/components/esp_driver_jpeg/jpeg_parse_marker.c @@ -130,10 +130,10 @@ esp_err_t jpeg_parse_sof_marker(jpeg_dec_header_info_t *header_info) // The vertical and horizontal in process must be divided by mcu block. if (header_info->origin_v % header_info->mcuy != 0) { - header_info->process_v = (uint32_t)(ceil(header_info->origin_v / header_info->mcuy) + 1) * header_info->mcuy; + header_info->process_v = ((header_info->origin_v / header_info->mcuy) + 1) * header_info->mcuy; } if (header_info->origin_h % header_info->mcux != 0) { - header_info->process_h = (uint32_t)(ceil(header_info->origin_h / header_info->mcux) + 1) * header_info->mcux; + header_info->process_h = ((header_info->origin_h / header_info->mcux) + 1) * header_info->mcux; } return ESP_OK; diff --git a/components/esp_driver_parlio/src/parlio_rx.c b/components/esp_driver_parlio/src/parlio_rx.c index 97acef1973..abf0d30159 100644 --- a/components/esp_driver_parlio/src/parlio_rx.c +++ b/components/esp_driver_parlio/src/parlio_rx.c @@ -138,7 +138,9 @@ static IRAM_ATTR size_t s_parlio_mount_transaction_buffer(parlio_rx_unit_handle_ /* Update the current transaction to the next one, and declare the delimiter is under using of the rx unit */ memcpy(&rx_unit->curr_trans, trans, sizeof(parlio_rx_transaction_t)); portENTER_CRITICAL_SAFE(&s_rx_spinlock); - trans->delimiter->under_using = true; + if (trans->delimiter) { + trans->delimiter->under_using = true; + } portEXIT_CRITICAL_SAFE(&s_rx_spinlock); uint32_t desc_num = trans->size / PARLIO_MAX_ALIGNED_DMA_BUF_SIZE; diff --git a/components/esp_driver_uart/src/uart_vfs.c b/components/esp_driver_uart/src/uart_vfs.c index a56630168d..a4ea3ca347 100644 --- a/components/esp_driver_uart/src/uart_vfs.c +++ b/components/esp_driver_uart/src/uart_vfs.c @@ -215,7 +215,7 @@ static int uart_rx_char(int fd) static int uart_rx_char_via_driver(int fd) { uint8_t c; - int timeout = s_ctx[fd]->non_blocking ? 0 : portMAX_DELAY; + TickType_t timeout = s_ctx[fd]->non_blocking ? 0 : portMAX_DELAY; int n = uart_read_bytes(fd, &c, 1, timeout); if (n <= 0) { return NONE; diff --git a/components/esp_hw_support/debug_probe/debug_probe.c b/components/esp_hw_support/debug_probe/debug_probe.c index 94574427b8..19ea956eb2 100644 --- a/components/esp_hw_support/debug_probe/debug_probe.c +++ b/components/esp_hw_support/debug_probe/debug_probe.c @@ -15,10 +15,12 @@ #include "esp_heap_caps.h" #include "soc/soc_caps.h" #include "soc/debug_probe_periph.h" +#include "soc/io_mux_reg.h" #include "hal/debug_probe_ll.h" #include "esp_private/debug_probe.h" +#include "esp_private/gpio.h" +#include "esp_private/esp_gpio_reserve.h" #include "esp_rom_gpio.h" -#include "driver/gpio.h" static const char *TAG = "dbg_probe"; @@ -28,6 +30,7 @@ typedef struct debug_probe_channel_t debug_probe_channel_t; struct debug_probe_unit_t { int unit_id; // unit id debug_probe_channel_t *channels[DEBUG_PROBE_LL_CHANNELS_PER_UNIT]; // channels installed in this unit + uint64_t pin_bit_mask; // bit-mask of the GPIOs used by this unit }; struct debug_probe_channel_t { @@ -53,6 +56,7 @@ static esp_err_t debug_probe_unit_destroy(debug_probe_unit_t *unit) // disable the probe output debug_probe_ll_enable_unit(unit_id, false); + esp_gpio_revoke(unit->pin_bit_mask); // free the memory free(unit); return ESP_OK; @@ -60,7 +64,6 @@ static esp_err_t debug_probe_unit_destroy(debug_probe_unit_t *unit) esp_err_t debug_probe_new_unit(const debug_probe_unit_config_t *config, debug_probe_unit_handle_t *out_handle) { - esp_err_t ret = ESP_OK; debug_probe_unit_t *unit = NULL; int unit_id = -1; ESP_RETURN_ON_FALSE(config && out_handle, ESP_ERR_INVALID_ARG, TAG, "invalid args"); @@ -80,43 +83,35 @@ esp_err_t debug_probe_new_unit(const debug_probe_unit_config_t *config, debug_pr ESP_RETURN_ON_FALSE(unit, ESP_ERR_NO_MEM, TAG, "no mem for unit"); unit->unit_id = unit_id; - // configure the GPIOs - gpio_config_t monitor_io_conf = { - .mode = GPIO_MODE_OUTPUT, - .pin_bit_mask = 0, - }; + uint64_t pin_bit_mask = 0; for (int i = 0; i < SOC_DEBUG_PROBE_MAX_OUTPUT_WIDTH; i++) { - // skip unused IOs - if (config->probe_out_gpio_nums[i] < 0) { - continue; + if (config->probe_out_gpio_nums[i] >= 0) { + pin_bit_mask |= BIT64(config->probe_out_gpio_nums[i]); } - monitor_io_conf.pin_bit_mask |= (1ULL << config->probe_out_gpio_nums[i]); } - if (monitor_io_conf.pin_bit_mask) { - ESP_GOTO_ON_ERROR(gpio_config(&monitor_io_conf), err, TAG, "gpio_config failed"); + // reserve the GPIO output path, because we don't expect another peripheral to signal to the same GPIO + uint64_t old_gpio_rsv_mask = esp_gpio_reserve(pin_bit_mask); + // check if the GPIO is already used by others, RMT TX channel only uses the output path of the GPIO + if (old_gpio_rsv_mask & pin_bit_mask) { + ESP_LOGW(TAG, "GPIO conflict with others"); } // connect the probe output signals to the GPIOs for (int i = 0; i < SOC_DEBUG_PROBE_MAX_OUTPUT_WIDTH; i++) { - if (config->probe_out_gpio_nums[i] < 0) { - continue; + if (config->probe_out_gpio_nums[i] >= 0) { + gpio_func_sel(config->probe_out_gpio_nums[i], PIN_FUNC_GPIO); + esp_rom_gpio_connect_out_signal(config->probe_out_gpio_nums[i], + debug_probe_periph_signals.units[unit_id].out_sig[i], + false, false); } - esp_rom_gpio_connect_out_signal(config->probe_out_gpio_nums[i], - debug_probe_periph_signals.units[unit_id].out_sig[i], - false, false); } + unit->pin_bit_mask = pin_bit_mask; // enable the probe unit debug_probe_ll_enable_unit(unit_id, true); *out_handle = unit; return ESP_OK; - -err: - if (unit) { - debug_probe_unit_destroy(unit); - } - return ret; } esp_err_t debug_probe_del_unit(debug_probe_unit_handle_t unit)