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fix(hal/sha): Add RCC enable and reset API definitions for ESP32-C5 SHA

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harshal.patil
2024-03-27 18:09:33 +05:30
parent 5274bf88e4
commit e454fa4026
1 changed files with 25 additions and 0 deletions
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25
components/hal/esp32c5/include/hal/sha_ll.h
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@@ -7,6 +7,7 @@
#include <stdbool.h> #include <stdbool.h>
#include "soc/hwcrypto_reg.h" #include "soc/hwcrypto_reg.h"
#include "soc/pcr_struct.h"
#include "hal/sha_types.h" #include "hal/sha_types.h"
#ifdef __cplusplus #ifdef __cplusplus
@@ -14,6 +15,30 @@ extern "C" {
#endif #endif
/**
* @brief Enable the bus clock for SHA peripheral module
*
* @param enable true to enable the module, false to disable the module
*/
static inline void sha_ll_enable_bus_clock(bool enable)
{
PCR.sha_conf.sha_clk_en = enable;
}
/**
* @brief Reset the SHA peripheral module
*/
static inline void sha_ll_reset_register(void)
{
PCR.sha_conf.sha_rst_en = 1;
PCR.sha_conf.sha_rst_en = 0;
// Clear reset on digital signature, hmac and ecdsa also, otherwise SHA is held in reset
PCR.ds_conf.ds_rst_en = 0;
PCR.hmac_conf.hmac_rst_en = 0;
PCR.ecdsa_conf.ecdsa_rst_en = 0;
}
/** /**
* @brief Start a new SHA block conversions (no initial hash in HW) * @brief Start a new SHA block conversions (no initial hash in HW)
* *