Merge branch 'bugfix/clear_ulp_wake_intr_in_wake_source_enable_v5.1' into 'release/v5.1'

fix(esp_hw_support): clear all type ULP wakeup intr status at ulp wakeup source enable (backport v5.1)

See merge request espressif/esp-idf!27188

components/esp_hw_support/include/esp_private/esp_pmu.h

@@ -41,31 +41,64 @@ extern "C" {
 #else
 #define RTC_EXT0_TRIG_EN            0
 #endif
+
 #if SOC_PM_SUPPORT_EXT1_WAKEUP
 #define RTC_EXT1_TRIG_EN            PMU_EXT1_WAKEUP_EN      //!< EXT1 wakeup
+#else
+#define RTC_EXT1_TRIG_EN            0
 #endif
+
 #define RTC_GPIO_TRIG_EN            PMU_GPIO_WAKEUP_EN      //!< GPIO wakeup
+
+#if SOC_LP_TIMER_SUPPORTED
 #define RTC_TIMER_TRIG_EN           PMU_LP_TIMER_WAKEUP_EN  //!< Timer wakeup
+#else
+#define RTC_TIMER_TRIG_EN           0
+#endif
+
+#if SOC_WIFI_SUPPORTED
 #define RTC_WIFI_TRIG_EN            PMU_WIFI_SOC_WAKEUP_EN  //!< WIFI wakeup (light sleep only)
+#else
+#define RTC_WIFI_TRIG_EN            0
+#endif
+
+#if SOC_UART_SUPPORT_WAKEUP_INT
 #define RTC_UART0_TRIG_EN           PMU_UART0_WAKEUP_EN     //!< UART0 wakeup (light sleep only)
 #define RTC_UART1_TRIG_EN           PMU_UART1_WAKEUP_EN     //!< UART1 wakeup (light sleep only)
+#else
+#define RTC_UART0_TRIG_EN           0
+#define RTC_UART1_TRIG_EN           0
+#endif
+
+#if SOC_BT_SUPPORTED
 #define RTC_BT_TRIG_EN              PMU_BLE_SOC_WAKEUP_EN   //!< BT wakeup (light sleep only)
+#else
+#define RTC_BT_TRIG_EN              0
+#endif
+
 #define RTC_USB_TRIG_EN             PMU_USB_WAKEUP_EN
+
 #if SOC_LP_CORE_SUPPORTED
 #define RTC_LP_CORE_TRIG_EN         PMU_LP_CORE_WAKEUP_EN   //!< LP core wakeup
+#else
+#define RTC_LP_CORE_TRIG_EN         0
 #endif //SOC_LP_CORE_SUPPORTED
+
 #define RTC_XTAL32K_DEAD_TRIG_EN    0 // TODO
 #define RTC_BROWNOUT_DET_TRIG_EN    0 // TODO
 
 /**
  * RTC_SLEEP_REJECT_MASK records sleep reject sources supported by chip
  */
-#define RTC_SLEEP_REJECT_MASK (RTC_GPIO_TRIG_EN         | \
+#define RTC_SLEEP_REJECT_MASK (RTC_EXT0_TRIG_EN         | \
+                               RTC_EXT1_TRIG_EN         | \
+                               RTC_GPIO_TRIG_EN         | \
                                RTC_TIMER_TRIG_EN        | \
                                RTC_WIFI_TRIG_EN         | \
                                RTC_UART0_TRIG_EN        | \
                                RTC_UART1_TRIG_EN        | \
                                RTC_BT_TRIG_EN           | \
+                               RTC_LP_CORE_TRIG_EN      | \
                                RTC_XTAL32K_DEAD_TRIG_EN | \
                                RTC_USB_TRIG_EN          | \
                                RTC_BROWNOUT_DET_TRIG_EN)

components/esp_hw_support/port/esp32c6/pmu_sleep.c

@@ -264,7 +264,6 @@ uint32_t pmu_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt, uint32_t lslp
     pmu_ll_hp_clear_wakeup_intr_status(PMU_instance()->hal->dev);
     pmu_ll_hp_clear_reject_intr_status(PMU_instance()->hal->dev);
     pmu_ll_hp_clear_reject_cause(PMU_instance()->hal->dev);
-    pmu_ll_hp_clear_sw_intr_status(PMU_instance()->hal->dev);
 
     /* Start entry into sleep mode */
     pmu_ll_hp_set_sleep_enable(PMU_instance()->hal->dev);

components/esp_hw_support/sleep_modes.c

@@ -628,16 +628,25 @@ static esp_err_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags, esp_sleep_mode_t m
     }
 #endif
 
-#if CONFIG_ULP_COPROC_TYPE_FSM
+#if CONFIG_ULP_COPROC_ENABLED
     // Enable ULP wakeup
+#if CONFIG_ULP_COPROC_TYPE_FSM
     if (s_config.wakeup_triggers & RTC_ULP_TRIG_EN) {
+#elif CONFIG_ULP_COPROC_TYPE_RISCV
+    if (s_config.wakeup_triggers & (RTC_COCPU_TRIG_EN | RTC_COCPU_TRAP_TRIG_EN)) {
+#elif CONFIG_ULP_COPROC_TYPE_LP_CORE
+    if (s_config.wakeup_triggers & RTC_LP_CORE_TRIG_EN) {
+#endif
 #ifdef CONFIG_IDF_TARGET_ESP32
         rtc_hal_ulp_wakeup_enable();
+#elif CONFIG_ULP_COPROC_TYPE_LP_CORE
+        pmu_ll_hp_clear_sw_intr_status(&PMU);
 #else
         rtc_hal_ulp_int_clear();
 #endif
     }
-#endif
+#endif // CONFIG_ULP_COPROC_ENABLED
+
     misc_modules_sleep_prepare(deep_sleep);
 
 #if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3

components/hal/esp32c6/include/hal/pmu_ll.h

@@ -666,7 +666,7 @@ FORCE_INLINE_ATTR uint32_t pmu_ll_hp_get_digital_power_up_wait_cycle(pmu_dev_t *
     return hw->power.wait_timer0.powerup_timer;
 }
 
-static inline uint32_t pmu_ll_get_sysclk_sleep_select_state(pmu_dev_t *hw)
+FORCE_INLINE_ATTR uint32_t pmu_ll_get_sysclk_sleep_select_state(pmu_dev_t *hw)
 {
     return hw->clk_state0.sysclk_slp_sel;
 }

components/ulp/test_apps/ulp_riscv/main/test_ulp_riscv.c

@@ -217,7 +217,7 @@ TEST_CASE("ULP-RISC-V can be reloaded with a good fimware after a crash", "[ulp]
 
     /* Verify that main CPU wakes up by a COCPU trap signal trigger */
     esp_sleep_wakeup_cause_t cause = esp_sleep_get_wakeup_cause();
-    TEST_ASSERT(cause != ESP_SLEEP_WAKEUP_COCPU);
+    TEST_ASSERT(cause == ESP_SLEEP_WAKEUP_COCPU_TRAP_TRIG);
 
     printf("Resetting the ULP\n");
     ulp_riscv_reset();

components/ulp/test_apps/ulp_riscv/main/ulp/test_main_cocpu_crash.c

@@ -6,9 +6,12 @@
 
 #include <stdio.h>
 #include <stdint.h>
+#include "ulp_riscv_utils.h"
 
 int main (void)
 {
+    // Wait for the main core in the test case to enter lightsleep
+    ulp_riscv_delay_cycles(100 * ULP_RISCV_CYCLES_PER_MS);
     /* Make sure ULP core crashes by doing a NULL pointer access */
     uint32_t *null_ptr = NULL;
     *null_ptr = 1;