From e74dcb1fab6d0dce2fae3e5a56417378530cb75c Mon Sep 17 00:00:00 2001 From: "nilesh.kale" Date: Thu, 27 Jun 2024 12:14:05 +0530 Subject: [PATCH] feat: remove support for aes and rsa peripherals in esp32c61 --- components/esp_system/port/soc/esp32c61/clk.c | 3 ++ .../test_apps/main/test_aes_sha_parallel.c | 15 +++++----- .../mbedtls/test_apps/main/test_mbedtls_mpi.c | 14 +++++++--- .../mbedtls/test_apps/main/test_mbedtls_sha.c | 4 +-- .../esp32c2/include/soc/Kconfig.soc_caps.in | 4 --- components/soc/esp32c2/include/soc/soc_caps.h | 3 -- .../esp32c61/include/soc/Kconfig.soc_caps.in | 28 ------------------- .../soc/esp32c61/include/soc/soc_caps.h | 19 ------------- 8 files changed, 22 insertions(+), 68 deletions(-) diff --git a/components/esp_system/port/soc/esp32c61/clk.c b/components/esp_system/port/soc/esp32c61/clk.c index 035cc1c87f..77fa2a75fd 100644 --- a/components/esp_system/port/soc/esp32c61/clk.c +++ b/components/esp_system/port/soc/esp32c61/clk.c @@ -106,6 +106,9 @@ __attribute__((weak)) void esp_clk_init(void) // Re calculate the ccount to make time calculation correct. esp_cpu_set_cycle_count((uint64_t)esp_cpu_get_cycle_count() * new_freq_mhz / old_freq_mhz); + + // Set crypto clock (`clk_sec`) to use 480M SPLL clock + REG_SET_FIELD(PCR_SEC_CONF_REG, PCR_SEC_CLK_SEL, 0x2); } static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src) diff --git a/components/mbedtls/test_apps/main/test_aes_sha_parallel.c b/components/mbedtls/test_apps/main/test_aes_sha_parallel.c index a018eca9ab..453e5ca26d 100644 --- a/components/mbedtls/test_apps/main/test_aes_sha_parallel.c +++ b/components/mbedtls/test_apps/main/test_aes_sha_parallel.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -16,7 +16,6 @@ #include "freertos/task.h" #include "freertos/semphr.h" - static SemaphoreHandle_t done_sem; static const unsigned char *one_hundred_bs = (unsigned char *) @@ -77,11 +76,11 @@ static void tskRunAES256Test(void *pvParameters) memcpy(nonce, iv, 16); // allocate internal memory - uint8_t *chipertext = heap_caps_malloc(SZ, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL); + uint8_t *ciphertext = heap_caps_malloc(SZ, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL); uint8_t *plaintext = heap_caps_malloc(SZ, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL); uint8_t *decryptedtext = heap_caps_malloc(SZ, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL); - TEST_ASSERT_NOT_NULL(chipertext); + TEST_ASSERT_NOT_NULL(ciphertext); TEST_ASSERT_NOT_NULL(plaintext); TEST_ASSERT_NOT_NULL(decryptedtext); @@ -92,19 +91,19 @@ static void tskRunAES256Test(void *pvParameters) memset(decryptedtext, 0x0, SZ); // Encrypt - mbedtls_aes_crypt_cbc(&ctx, MBEDTLS_AES_ENCRYPT, SZ, nonce, plaintext, chipertext); - TEST_ASSERT_EQUAL_HEX8_ARRAY(expected_cipher_end, chipertext + SZ - 32, 32); + mbedtls_aes_crypt_cbc(&ctx, MBEDTLS_AES_ENCRYPT, SZ, nonce, plaintext, ciphertext); + TEST_ASSERT_EQUAL_HEX8_ARRAY(expected_cipher_end, ciphertext + SZ - 32, 32); // Decrypt memcpy(nonce, iv, 16); mbedtls_aes_setkey_dec(&ctx, key_256, 256); - mbedtls_aes_crypt_cbc(&ctx, MBEDTLS_AES_DECRYPT, SZ, nonce, chipertext, decryptedtext); + mbedtls_aes_crypt_cbc(&ctx, MBEDTLS_AES_DECRYPT, SZ, nonce, ciphertext, decryptedtext); TEST_ASSERT_EQUAL_HEX8_ARRAY(plaintext, decryptedtext, SZ); mbedtls_aes_free(&ctx); free(plaintext); - free(chipertext); + free(ciphertext); free(decryptedtext); } xSemaphoreGive(done_sem); diff --git a/components/mbedtls/test_apps/main/test_mbedtls_mpi.c b/components/mbedtls/test_apps/main/test_mbedtls_mpi.c index 14bdc84974..6b1ca3b8dd 100644 --- a/components/mbedtls/test_apps/main/test_mbedtls_mpi.c +++ b/components/mbedtls/test_apps/main/test_mbedtls_mpi.c @@ -1,6 +1,6 @@ /* mbedTLS bignum (MPI) self-tests as unit tests * - * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -17,6 +17,12 @@ #include "sdkconfig.h" #include "test_utils.h" +#ifdef SOC_MPI_SUPPORTED +#define RSA_MAX_BIT_LEN SOC_RSA_MAX_BIT_LEN +#else +#define RSA_MAX_BIT_LEN 3072 +#endif + #define MBEDTLS_OK 0 /* Debugging function to print an MPI number to stdout. Happens to @@ -54,7 +60,7 @@ static void test_bignum_mult_variant(const char *a_str, const char *b_str, const TEST_ASSERT_FALSE(mbedtls_mpi_read_string(&A, 16, a_str)); TEST_ASSERT_FALSE(mbedtls_mpi_read_string(&B, 16, b_str)); - /* calulate X = A * B variant */ + /* calculate X = A * B variant */ TEST_ASSERT_FALSE(mbedtls_mpi_read_string(&E, 16, e_str)); if (res_operands_overlap == 0) { TEST_ASSERT_FALSE(mbedtls_mpi_mul_mpi(&X, &A, &B)); @@ -72,7 +78,7 @@ static void test_bignum_mult_variant(const char *a_str, const char *b_str, const #ifdef CONFIG_MBEDTLS_HARDWARE_MPI mbedtls_mpi M; /* if mod_bits arg is set, also do a esp_mpi_mul_mod() call */ - if (mod_bits > 0 && mod_bits <= SOC_RSA_MAX_BIT_LEN) { + if (mod_bits > 0 && mod_bits <= RSA_MAX_BIT_LEN) { mbedtls_mpi_init(&M); for(int i = 0; i < mod_bits; i++) { mbedtls_mpi_set_bit(&M, i, 1); @@ -106,7 +112,7 @@ TEST_CASE("test MPI multiplication", "[bignum]") /* Run some trivial numbers tests w/ various high modulo bit counts, should make no difference to the result */ - for(int i = 512; i <= SOC_RSA_MAX_BIT_LEN; i+= 512) { + for(int i = 512; i <= RSA_MAX_BIT_LEN; i+= 512) { test_bignum_mult("10", "100", "1000", i); } diff --git a/components/mbedtls/test_apps/main/test_mbedtls_sha.c b/components/mbedtls/test_apps/main/test_mbedtls_sha.c index 6eebf9c4c6..003b35db8b 100644 --- a/components/mbedtls/test_apps/main/test_mbedtls_sha.c +++ b/components/mbedtls/test_apps/main/test_mbedtls_sha.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -249,7 +249,7 @@ TEST_CASE("mbedtls SHA384 clone", "[mbedtls]") TEST_ASSERT_EQUAL(0, mbedtls_sha512_update(&ctx, one_hundred_bs, 100)); TEST_ASSERT_EQUAL(0, mbedtls_sha512_update(&clone, one_hundred_bs, 100)); } -/* intended warning supression: is384 == true */ +/* intended warning suppression: is384 == true */ #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wstringop-overflow" TEST_ASSERT_EQUAL(0, mbedtls_sha512_finish(&ctx, sha384)); diff --git a/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in index 2e71155117..42517302e3 100644 --- a/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in @@ -435,10 +435,6 @@ config SOC_RTCIO_PIN_COUNT int default 0 -config SOC_RSA_MAX_BIT_LEN - int - default 3072 - config SOC_SHA_SUPPORT_RESUME bool default y diff --git a/components/soc/esp32c2/include/soc/soc_caps.h b/components/soc/esp32c2/include/soc/soc_caps.h index 9ee2f14fed..f2fec0cc93 100644 --- a/components/soc/esp32c2/include/soc/soc_caps.h +++ b/components/soc/esp32c2/include/soc/soc_caps.h @@ -196,9 +196,6 @@ * for hold, wake & 32kHz crystal functions - via rtc_cntl_reg */ #define SOC_RTCIO_PIN_COUNT (0U) -/*--------------------------- RSA CAPS ---------------------------------------*/ -#define SOC_RSA_MAX_BIT_LEN (3072) - /*--------------------------- SHA CAPS ---------------------------------------*/ /* Due to very limited availability of the DMA channels, DMA support for the SHA peripheral is disabled */ diff --git a/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in index a8afa1dca2..0f6e56673b 100644 --- a/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in @@ -71,22 +71,6 @@ config SOC_XTAL_SUPPORT_40M bool default y -config SOC_AES_SUPPORT_DMA - bool - default y - -config SOC_AES_GDMA - bool - default y - -config SOC_AES_SUPPORT_AES_128 - bool - default y - -config SOC_AES_SUPPORT_AES_256 - bool - default y - config SOC_ADC_PERIPH_NUM int default 1 @@ -283,18 +267,6 @@ config SOC_MPU_REGION_WO_SUPPORTED bool default n -config SOC_MPI_MEM_BLOCKS_NUM - int - default 4 - -config SOC_MPI_OPERATIONS_NUM - int - default 3 - -config SOC_RSA_MAX_BIT_LEN - int - default 3072 - config SOC_ECDSA_SUPPORT_EXPORT_PUBKEY bool default y diff --git a/components/soc/esp32c61/include/soc/soc_caps.h b/components/soc/esp32c61/include/soc/soc_caps.h index 1513a65cf7..f33548cfc3 100644 --- a/components/soc/esp32c61/include/soc/soc_caps.h +++ b/components/soc/esp32c61/include/soc/soc_caps.h @@ -41,7 +41,6 @@ // \#define SOC_I2C_SUPPORTED 1 //TODO: [ESP32C61] IDF-9296, IDF-9297 #define SOC_SYSTIMER_SUPPORTED 1 //TODO: [ESP32C61] IDF-9307, IDF-9308 // \#define SOC_SUPPORT_COEXISTENCE 1 -// \#define SOC_MPI_SUPPORTED 1 // \#define SOC_SHA_SUPPORTED 1 //TODO: [ESP32C61] IDF-9234 #define SOC_ECC_SUPPORTED 1 #define SOC_ECC_EXTENDED_MODES_SUPPORTED 1 @@ -64,7 +63,6 @@ // \#define SOC_TWAI_SUPPORTED 0 //TODO: [ESP32C61] IDF-9336 // \#define SOC_ETM_SUPPORTED 0 // \#define SOC_LP_CORE_SUPPORTED 0 //TODO: [ESP32C61] IDF-9331 -// \#define SOC_AES_SUPPORTED 0 //TODO: [ESP32C61] IDF-9328 // \#define SOC_SDIO_SLAVE_SUPPORTED 0 // \#define SOC_PAU_SUPPORTED 0 // \#define SOC_LP_I2C_SUPPORTED 0 //TODO: [ESP32C61] IDF-9330, IDF-9337 @@ -73,15 +71,6 @@ /*-------------------------- XTAL CAPS ---------------------------------------*/ #define SOC_XTAL_SUPPORT_40M 1 -/*-------------------------- AES CAPS -----------------------------------------*/ -#define SOC_AES_SUPPORT_DMA (1) - -/* Has a centralized DMA, which is shared with all peripherals */ -#define SOC_AES_GDMA (1) - -#define SOC_AES_SUPPORT_AES_128 (1) -#define SOC_AES_SUPPORT_AES_256 (1) - //TODO: [ESP32C61] IDF-9302, IDF-9303, IDF-9304 /*-------------------------- ADC CAPS -------------------------------*/ /*!< SAR ADC Module*/ @@ -279,14 +268,6 @@ /*------------------------ USB SERIAL JTAG CAPS ------------------------------*/ // \#define SOC_USB_SERIAL_JTAG_SUPPORT_LIGHT_SLEEP (1) /*!< Support to maintain minimum usb communication during light sleep */ // TODO: IDF-6395 -/*--------------------------- MPI CAPS ---------------------------------------*/ -#define SOC_MPI_MEM_BLOCKS_NUM (4) -#define SOC_MPI_OPERATIONS_NUM (3) - -/*--------------------------- RSA CAPS ---------------------------------------*/ -//TODO: [ESP32C61] IDF-9326 -#define SOC_RSA_MAX_BIT_LEN (3072) - // TODO: IDF-5353 (Copy from esp32c3, need check) /*--------------------------- SHA CAPS ---------------------------------------*/