diff --git a/components/esp_driver_gpio/test_apps/gpio/main/test_rtcio.c b/components/esp_driver_gpio/test_apps/gpio/main/test_rtcio.c index 44d93165a9..fa6af22462 100644 --- a/components/esp_driver_gpio/test_apps/gpio/main/test_rtcio.c +++ b/components/esp_driver_gpio/test_apps/gpio/main/test_rtcio.c @@ -238,7 +238,7 @@ TEST_CASE("RTCIO_output_hold_test", "[rtcio]") #if SOC_DEEP_SLEEP_SUPPORTED // It is not necessary to test every rtcio pin, it will take too much ci testing time for deep sleep // Only tests on s_test_map[TEST_RTCIO_DEEP_SLEEP_PIN_INDEX] pin -// (ESP32: IO25, ESP32S2, S3: IO6, C6: IO5, H2: IO12) these pads' default configuration is low level +// (ESP32: IO25, ESP32S2, S3: IO6, C6: IO5, H2: IO12, P4: IO5, C5: IO5) these pads' default configuration is low level #define TEST_RTCIO_DEEP_SLEEP_PIN_INDEX 5 static void rtcio_deep_sleep_hold_test_first_stage(void) diff --git a/components/esp_driver_gpio/test_apps/gpio/main/test_rtcio.h b/components/esp_driver_gpio/test_apps/gpio/main/test_rtcio.h index e2eb1f00d3..a33d64f0fb 100644 --- a/components/esp_driver_gpio/test_apps/gpio/main/test_rtcio.h +++ b/components/esp_driver_gpio/test_apps/gpio/main/test_rtcio.h @@ -93,7 +93,7 @@ const int s_test_map[TEST_GPIO_PIN_COUNT] = { GPIO_NUM_20, //GPIO20 GPIO_NUM_21, //GPIO21 }; -#elif CONFIG_IDF_TARGET_ESP32C6 +#elif CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32C5 // Has no input-only rtcio pins, all pins support pull-up/down #define RTCIO_SUPPORT_PU_PD(num) 1 #define TEST_GPIO_PIN_COUNT 8 diff --git a/components/esp_driver_uart/src/uart.c b/components/esp_driver_uart/src/uart.c index 9999398994..1cfcb6d343 100644 --- a/components/esp_driver_uart/src/uart.c +++ b/components/esp_driver_uart/src/uart.c @@ -23,14 +23,17 @@ #include "soc/uart_periph.h" #include "driver/uart.h" #include "driver/gpio.h" -#include "driver/rtc_io.h" #include "driver/uart_select.h" -#include "driver/lp_io.h" #include "esp_private/gpio.h" #include "esp_private/uart_share_hw_ctrl.h" #include "esp_clk_tree.h" #include "sdkconfig.h" #include "esp_rom_gpio.h" +#if (SOC_UART_LP_NUM >= 1) +#include "driver/rtc_io.h" +#include "hal/rtc_io_ll.h" +#include "driver/lp_io.h" +#endif #include "clk_ctrl_os.h" #include "esp_pm.h" #include "esp_private/sleep_retention.h" @@ -744,7 +747,7 @@ esp_err_t uart_set_pin(uart_port_t uart_num, int tx_io_num, int rx_io_num, int r else { rtc_gpio_set_direction(tx_io_num, RTC_GPIO_MODE_OUTPUT_ONLY); rtc_gpio_init(tx_io_num); - rtc_gpio_iomux_func_sel(tx_io_num, 1); + rtc_gpio_iomux_func_sel(tx_io_num, RTCIO_LL_PIN_FUNC); lp_gpio_connect_out_signal(tx_io_num, UART_PERIPH_SIGNAL(uart_num, SOC_UART_TX_PIN_IDX), 0, 0); } diff --git a/components/esp_hw_support/port/esp32c5/io_mux.c b/components/esp_hw_support/port/esp32c5/io_mux.c index 6e9cd84303..e8fb906555 100644 --- a/components/esp_hw_support/port/esp32c5/io_mux.c +++ b/components/esp_hw_support/port/esp32c5/io_mux.c @@ -6,11 +6,23 @@ #include "freertos/FreeRTOS.h" #include "esp_private/io_mux.h" +#include "esp_private/periph_ctrl.h" #include "hal/gpio_ll.h" +#include "hal/rtc_io_ll.h" + +#define RTCIO_RCC_ATOMIC() PERIPH_RCC_ATOMIC() static portMUX_TYPE s_io_mux_spinlock = portMUX_INITIALIZER_UNLOCKED; static soc_module_clk_t s_io_mux_clk_src = 0; // by default, the clock source is not set explicitly by any consumer (e.g. SDM, Filter) +#if CONFIG_ULP_COPROC_ENABLED +RTC_DATA_ATTR +#endif +static rtc_io_status_t s_rtc_io_status = { + .rtc_io_enabled_cnt = { 0 }, + .rtc_io_using_mask = 0 +}; + esp_err_t io_mux_set_clock_source(soc_module_clk_t clk_src) { bool clk_conflict = false; @@ -31,3 +43,27 @@ esp_err_t io_mux_set_clock_source(soc_module_clk_t clk_src) return ESP_OK; } + +void io_mux_enable_lp_io_clock(gpio_num_t gpio_num, bool enable) +{ + portENTER_CRITICAL(&s_io_mux_spinlock); + if (enable) { + if (s_rtc_io_status.rtc_io_enabled_cnt[gpio_num] == 0) { + s_rtc_io_status.rtc_io_using_mask |= (1ULL << gpio_num); + } + s_rtc_io_status.rtc_io_enabled_cnt[gpio_num]++; + } else if (!enable && (s_rtc_io_status.rtc_io_enabled_cnt[gpio_num] > 0)) { + s_rtc_io_status.rtc_io_enabled_cnt[gpio_num]--; + if (s_rtc_io_status.rtc_io_enabled_cnt[gpio_num] == 0) { + s_rtc_io_status.rtc_io_using_mask &= ~(1ULL << gpio_num); + } + } + RTCIO_RCC_ATOMIC() { + if (s_rtc_io_status.rtc_io_using_mask == 0) { + rtcio_ll_enable_io_clock(false); + } else { + rtcio_ll_enable_io_clock(true); + } + } + portEXIT_CRITICAL(&s_io_mux_spinlock); +} diff --git a/components/hal/esp32c5/include/hal/rtc_io_ll.h b/components/hal/esp32c5/include/hal/rtc_io_ll.h index ef2eb7bcf6..7b3d10819c 100644 --- a/components/hal/esp32c5/include/hal/rtc_io_ll.h +++ b/components/hal/esp32c5/include/hal/rtc_io_ll.h @@ -16,8 +16,10 @@ #include #include "soc/soc_caps.h" #include "soc/pcr_struct.h" -// #include "soc/lp_io_struct.h" -// #include "soc/lp_aon_struct.h" +#include "soc/lp_iomux_struct.h" +#include "soc/lp_aon_struct.h" +#include "soc/lp_gpio_struct.h" +#include "soc/lpperi_struct.h" #include "soc/pmu_struct.h" #include "hal/misc.h" #include "hal/assert.h" @@ -26,7 +28,7 @@ extern "C" { #endif -#define RTCIO_LL_PIN_FUNC 0 +#define RTCIO_LL_PIN_FUNC 1 typedef enum { RTCIO_LL_FUNC_RTC = 0x0, /*!< The pin controlled by RTC module. */ @@ -39,11 +41,6 @@ typedef enum { RTCIO_LL_WAKEUP_HIGH_LEVEL = 0x5, /*!< GPIO interrupt type : input high level trigger */ } rtcio_ll_wake_type_t; -typedef enum { - RTCIO_LL_OUTPUT_NORMAL = 0, /*!< RTCIO output mode is normal. */ - RTCIO_LL_OUTPUT_OD = 0x1, /*!< RTCIO output mode is open-drain. */ -} rtcio_ll_out_mode_t; - typedef enum { RTCIO_INTR_DISABLE = 0, /*!< Disable GPIO interrupt */ RTCIO_INTR_POSEDGE = 1, /*!< GPIO interrupt type : rising edge */ @@ -53,6 +50,11 @@ typedef enum { RTCIO_INTR_HIGH_LEVEL = 5, /*!< GPIO interrupt type : input high level trigger */ } rtcio_ll_intr_type_t; +typedef enum { + RTCIO_LL_OUTPUT_NORMAL = 0, /*!< RTCIO output mode is normal. */ + RTCIO_LL_OUTPUT_OD = 0x1, /*!< RTCIO output mode is open-drain. */ +} rtcio_ll_out_mode_t; + /** * @brief Select a RTC IOMUX function for the RTC IO * @@ -61,11 +63,24 @@ typedef enum { */ static inline void rtcio_ll_iomux_func_sel(int rtcio_num, int func) { - // TODO: [ESP32C5] IDF-8719 - // LP_IO.gpio[rtcio_num].mcu_sel = func; - abort(); + LP_IO_MUX.gpion[rtcio_num].gpion_mcu_sel = func; } +/** + * @brief Enable/Disable LP_GPIO peripheral clock. + * + * @param enable true to enable the clock / false to disable the clock + */ +static inline void _rtcio_ll_enable_io_clock(bool enable) +{ + LPPERI.clk_en.lp_io_ck_en = enable; + while (LPPERI.clk_en.lp_io_ck_en != enable) { + ; + } +} + +#define rtcio_ll_enable_io_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; _rtcio_ll_enable_io_clock(__VA_ARGS__) + /** * @brief Select the rtcio function. * @@ -78,21 +93,19 @@ static inline void rtcio_ll_iomux_func_sel(int rtcio_num, int func) */ static inline void rtcio_ll_function_select(int rtcio_num, rtcio_ll_func_t func) { - // TODO: [ESP32C5] IDF-8719 - // if (func == RTCIO_LL_FUNC_RTC) { - // // 0: GPIO connected to digital GPIO module. 1: GPIO connected to analog RTC module. - // uint32_t sel_mask = HAL_FORCE_READ_U32_REG_FIELD(LP_AON.gpio_mux, gpio_mux_sel); - // sel_mask |= BIT(rtcio_num); - // HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.gpio_mux, gpio_mux_sel, sel_mask); - // //0:RTC FUNCTION 1,2,3:Reserved - // rtcio_ll_iomux_func_sel(rtcio_num, RTCIO_LL_PIN_FUNC); - // } else if (func == RTCIO_LL_FUNC_DIGITAL) { - // // Clear the bit to use digital GPIO module - // uint32_t sel_mask = HAL_FORCE_READ_U32_REG_FIELD(LP_AON.gpio_mux, gpio_mux_sel); - // sel_mask &= ~BIT(rtcio_num); - // HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.gpio_mux, gpio_mux_sel, sel_mask); - // } - abort(); + if (func == RTCIO_LL_FUNC_RTC) { + // 0: GPIO connected to digital GPIO module. 1: GPIO connected to analog RTC module. + uint32_t sel_mask = HAL_FORCE_READ_U32_REG_FIELD(LP_AON.gpio_mux, gpio_mux_sel); + sel_mask |= BIT(rtcio_num); + HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.gpio_mux, gpio_mux_sel, sel_mask); + // LP_GPIO is FUNC 1 + rtcio_ll_iomux_func_sel(rtcio_num, RTCIO_LL_PIN_FUNC); + } else if (func == RTCIO_LL_FUNC_DIGITAL) { + // Clear the bit to use digital GPIO module + uint32_t sel_mask = HAL_FORCE_READ_U32_REG_FIELD(LP_AON.gpio_mux, gpio_mux_sel); + sel_mask &= ~BIT(rtcio_num); + HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.gpio_mux, gpio_mux_sel, sel_mask); + } } /** @@ -102,9 +115,7 @@ static inline void rtcio_ll_function_select(int rtcio_num, rtcio_ll_func_t func) */ static inline void rtcio_ll_output_enable(int rtcio_num) { - // TODO: [ESP32C5] IDF-8719 - // HAL_FORCE_MODIFY_U32_REG_FIELD(LP_IO.out_enable_w1ts, enable_w1ts, BIT(rtcio_num)); - abort(); + HAL_FORCE_MODIFY_U32_REG_FIELD(LP_GPIO.enable_w1ts, enable_w1ts, BIT(rtcio_num)); } /** @@ -114,9 +125,7 @@ static inline void rtcio_ll_output_enable(int rtcio_num) */ static inline void rtcio_ll_output_disable(int rtcio_num) { - // TODO: [ESP32C5] IDF-8719 - // HAL_FORCE_MODIFY_U32_REG_FIELD(LP_IO.out_enable_w1tc, enable_w1tc, BIT(rtcio_num)); - abort(); + HAL_FORCE_MODIFY_U32_REG_FIELD(LP_GPIO.enable_w1tc, enable_w1tc, BIT(rtcio_num)); } /** @@ -127,13 +136,11 @@ static inline void rtcio_ll_output_disable(int rtcio_num) */ static inline void rtcio_ll_set_level(int rtcio_num, uint32_t level) { - // TODO: [ESP32C5] IDF-8719 - // if (level) { - // HAL_FORCE_MODIFY_U32_REG_FIELD(LP_IO.out_data_w1ts, out_data_w1ts, BIT(rtcio_num)); - // } else { - // HAL_FORCE_MODIFY_U32_REG_FIELD(LP_IO.out_data_w1tc, out_data_w1tc, BIT(rtcio_num)); - // } - abort(); + if (level) { + HAL_FORCE_MODIFY_U32_REG_FIELD(LP_GPIO.out_w1ts, out_w1ts, BIT(rtcio_num)); + } else { + HAL_FORCE_MODIFY_U32_REG_FIELD(LP_GPIO.out_w1tc, out_w1tc, BIT(rtcio_num)); + } } /** @@ -143,9 +150,7 @@ static inline void rtcio_ll_set_level(int rtcio_num, uint32_t level) */ static inline void rtcio_ll_input_enable(int rtcio_num) { - // TODO: [ESP32C5] IDF-8719 - // LP_IO.gpio[rtcio_num].fun_ie = 1; - abort(); + LP_IO_MUX.gpion[rtcio_num].gpion_fun_ie = 1; } /** @@ -155,9 +160,7 @@ static inline void rtcio_ll_input_enable(int rtcio_num) */ static inline void rtcio_ll_input_disable(int rtcio_num) { - // TODO: [ESP32C5] IDF-8719 - // LP_IO.gpio[rtcio_num].fun_ie = 0; - abort(); + LP_IO_MUX.gpion[rtcio_num].gpion_fun_ie = 0; } /** @@ -168,10 +171,7 @@ static inline void rtcio_ll_input_disable(int rtcio_num) */ static inline uint32_t rtcio_ll_get_level(int rtcio_num) { - // TODO: [ESP32C5] IDF-8719 - // return (uint32_t)(HAL_FORCE_READ_U32_REG_FIELD(LP_IO.in, in_data_next) >> rtcio_num) & 0x1; - abort(); - return (uint32_t)0; + return (uint32_t)(HAL_FORCE_READ_U32_REG_FIELD(LP_GPIO.in, in_data_next) >> rtcio_num) & 0x1; } /** @@ -182,9 +182,7 @@ static inline uint32_t rtcio_ll_get_level(int rtcio_num) */ static inline void rtcio_ll_set_drive_capability(int rtcio_num, uint32_t strength) { - // TODO: [ESP32C5] IDF-8719 - // LP_IO.gpio[rtcio_num].fun_drv = strength; - abort(); + LP_IO_MUX.gpion[rtcio_num].gpion_fun_drv = strength; } /** @@ -195,10 +193,7 @@ static inline void rtcio_ll_set_drive_capability(int rtcio_num, uint32_t strengt */ static inline uint32_t rtcio_ll_get_drive_capability(int rtcio_num) { - // TODO: [ESP32C5] IDF-8719 - // return LP_IO.gpio[rtcio_num].fun_drv; - abort(); - return (uint32_t)0; + return LP_IO_MUX.gpion[rtcio_num].gpion_fun_drv; } /** @@ -209,9 +204,7 @@ static inline uint32_t rtcio_ll_get_drive_capability(int rtcio_num) */ static inline void rtcio_ll_output_mode_set(int rtcio_num, rtcio_ll_out_mode_t mode) { - // TODO: [ESP32C5] IDF-8719 - // LP_IO.pin[rtcio_num].pad_driver = mode; - abort(); + LP_GPIO.pinn[rtcio_num].pinn_pad_driver = mode; } /** @@ -221,10 +214,8 @@ static inline void rtcio_ll_output_mode_set(int rtcio_num, rtcio_ll_out_mode_t m */ static inline void rtcio_ll_pullup_enable(int rtcio_num) { - // TODO: [ESP32C5] IDF-8719 - // /* Enable internal weak pull-up */ - // LP_IO.gpio[rtcio_num].fun_wpu = 1; - abort(); + /* Enable internal weak pull-up */ + LP_IO_MUX.gpion[rtcio_num].gpion_fun_wpu = 1; } /** @@ -234,10 +225,8 @@ static inline void rtcio_ll_pullup_enable(int rtcio_num) */ static inline void rtcio_ll_pullup_disable(int rtcio_num) { - // TODO: [ESP32C5] IDF-8719 - // /* Disable internal weak pull-up */ - // LP_IO.gpio[rtcio_num].fun_wpu = 0; - abort(); + /* Disable internal weak pull-up */ + LP_IO_MUX.gpion[rtcio_num].gpion_fun_wpu = 0; } /** @@ -247,10 +236,8 @@ static inline void rtcio_ll_pullup_disable(int rtcio_num) */ static inline void rtcio_ll_pulldown_enable(int rtcio_num) { - // TODO: [ESP32C5] IDF-8719 - // /* Enable internal weak pull-down */ - // LP_IO.gpio[rtcio_num].fun_wpd = 1; - abort(); + /* Enable internal weak pull-down */ + LP_IO_MUX.gpion[rtcio_num].gpion_fun_wpd = 1; } /** @@ -260,10 +247,8 @@ static inline void rtcio_ll_pulldown_enable(int rtcio_num) */ static inline void rtcio_ll_pulldown_disable(int rtcio_num) { - // TODO: [ESP32C5] IDF-8719 - // /* Enable internal weak pull-down */ - // LP_IO.gpio[rtcio_num].fun_wpd = 0; - abort(); + /* Enable internal weak pull-down */ + LP_IO_MUX.gpion[rtcio_num].gpion_fun_wpd = 0; } /** @@ -278,9 +263,7 @@ static inline void rtcio_ll_pulldown_disable(int rtcio_num) */ static inline void rtcio_ll_force_hold_enable(int rtcio_num) { - // TODO: [ESP32C5] IDF-8719 - // LP_AON.gpio_hold0.gpio_hold0 |= BIT(rtcio_num); - abort(); + LP_AON.gpio_hold0.gpio_hold0 |= BIT(rtcio_num); } /** @@ -291,9 +274,7 @@ static inline void rtcio_ll_force_hold_enable(int rtcio_num) */ static inline void rtcio_ll_force_hold_disable(int rtcio_num) { - // TODO: [ESP32C5] IDF-8719 - // LP_AON.gpio_hold0.gpio_hold0 &= ~BIT(rtcio_num); - abort(); + LP_AON.gpio_hold0.gpio_hold0 &= ~BIT(rtcio_num); } /** @@ -306,9 +287,7 @@ static inline void rtcio_ll_force_hold_disable(int rtcio_num) */ static inline void rtcio_ll_force_hold_all(void) { - // TODO: [ESP32C5] IDF-8719 - // PMU.imm.pad_hold_all.tie_high_lp_pad_hold_all = 1; - abort(); + PMU.imm.pad_hold_all.tie_high_lp_pad_hold_all = 1; } /** @@ -318,9 +297,7 @@ static inline void rtcio_ll_force_hold_all(void) */ static inline void rtcio_ll_force_unhold_all(void) { - // TODO: [ESP32C5] IDF-8719 - // PMU.imm.pad_hold_all.tie_low_lp_pad_hold_all = 1; - abort(); + PMU.imm.pad_hold_all.tie_low_lp_pad_hold_all = 1; } /** @@ -331,10 +308,8 @@ static inline void rtcio_ll_force_unhold_all(void) */ static inline void rtcio_ll_wakeup_enable(int rtcio_num, rtcio_ll_wake_type_t type) { - // TODO: [ESP32C5] IDF-8719 - // LP_IO.pin[rtcio_num].wakeup_enable = 1; - // LP_IO.pin[rtcio_num].int_type = type; - abort(); + LP_GPIO.pinn[rtcio_num].pinn_wakeup_enable = 1; + LP_GPIO.pinn[rtcio_num].pinn_int_type = type; } /** @@ -344,10 +319,26 @@ static inline void rtcio_ll_wakeup_enable(int rtcio_num, rtcio_ll_wake_type_t ty */ static inline void rtcio_ll_wakeup_disable(int rtcio_num) { - // TODO: [ESP32C5] IDF-8719 - // LP_IO.pin[rtcio_num].wakeup_enable = 0; - // LP_IO.pin[rtcio_num].int_type = RTCIO_LL_WAKEUP_DISABLE; - abort(); + LP_GPIO.pinn[rtcio_num].pinn_wakeup_enable = 0; + LP_GPIO.pinn[rtcio_num].pinn_int_type = RTCIO_LL_WAKEUP_DISABLE; +} + +/** + * Enable interrupt function and set interrupt type + * + * @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio). + * @param type Interrupt type on high level or low level. + */ + +static inline void rtcio_ll_intr_enable(int rtcio_num, rtcio_ll_intr_type_t type) +{ + LP_GPIO.pinn[rtcio_num].pinn_int_type = type; + + /* Work around for HW issue, + need to also enable this clk, so that LP_GPIO.status.status_interrupt can get updated, + and trigger the interrupt on the LP Core + */ + LP_GPIO.clock_gate.clk_en = 1; } /** @@ -357,9 +348,7 @@ static inline void rtcio_ll_wakeup_disable(int rtcio_num) */ static inline void rtcio_ll_enable_output_in_sleep(int rtcio_num) { - // TODO: [ESP32C5] IDF-8719 - // LP_IO.gpio[rtcio_num].mcu_oe = 1; - abort(); + LP_IO_MUX.gpion[rtcio_num].gpion_mcu_oe = 1; } /** @@ -369,9 +358,7 @@ static inline void rtcio_ll_enable_output_in_sleep(int rtcio_num) */ static inline void rtcio_ll_disable_output_in_sleep(int rtcio_num) { - // TODO: [ESP32C5] IDF-8719 - // LP_IO.gpio[rtcio_num].mcu_oe = 0; - abort(); + LP_IO_MUX.gpion[rtcio_num].gpion_mcu_oe = 0; } /** @@ -381,9 +368,7 @@ static inline void rtcio_ll_disable_output_in_sleep(int rtcio_num) */ static inline void rtcio_ll_enable_input_in_sleep(int rtcio_num) { - // TODO: [ESP32C5] IDF-8719 - // LP_IO.gpio[rtcio_num].mcu_ie = 1; - abort(); + LP_IO_MUX.gpion[rtcio_num].gpion_mcu_ie = 1; } /** @@ -393,9 +378,7 @@ static inline void rtcio_ll_enable_input_in_sleep(int rtcio_num) */ static inline void rtcio_ll_disable_input_in_sleep(int rtcio_num) { - // TODO: [ESP32C5] IDF-8719 - // LP_IO.gpio[rtcio_num].mcu_ie = 0; - abort(); + LP_IO_MUX.gpion[rtcio_num].gpion_mcu_ie = 0; } /** @@ -405,9 +388,7 @@ static inline void rtcio_ll_disable_input_in_sleep(int rtcio_num) */ static inline void rtcio_ll_enable_sleep_setting(int rtcio_num) { - // TODO: [ESP32C5] IDF-8719 - // LP_IO.gpio[rtcio_num].slp_sel = 1; - abort(); + LP_IO_MUX.gpion[rtcio_num].gpion_slp_sel = 1; } /** @@ -417,9 +398,7 @@ static inline void rtcio_ll_enable_sleep_setting(int rtcio_num) */ static inline void rtcio_ll_disable_sleep_setting(int rtcio_num) { - // TODO: [ESP32C5] IDF-8719 - // LP_IO.gpio[rtcio_num].slp_sel = 0; - abort(); + LP_IO_MUX.gpion[rtcio_num].gpion_slp_sel = 0; } /** @@ -430,11 +409,8 @@ static inline void rtcio_ll_disable_sleep_setting(int rtcio_num) */ static inline bool rtcio_ll_wakeup_is_enabled(int rtcio_num) { - // TODO: [ESP32C5] IDF-8719 - // HAL_ASSERT(rtcio_num >= 0 && rtcio_num < SOC_RTCIO_PIN_COUNT && "io does not support deep sleep wake-up function"); - // return LP_IO.pin[rtcio_num].wakeup_enable; - abort(); - return (bool)0; + HAL_ASSERT(rtcio_num >= 0 && rtcio_num < SOC_RTCIO_PIN_COUNT && "io does not support deep sleep wake-up function"); + return LP_GPIO.pinn[rtcio_num].pinn_wakeup_enable; } /** @@ -444,10 +420,7 @@ static inline bool rtcio_ll_wakeup_is_enabled(int rtcio_num) */ static inline uint32_t rtcio_ll_get_interrupt_status(void) { - // TODO: [ESP32C5] IDF-8719 - // return (uint32_t)HAL_FORCE_READ_U32_REG_FIELD(LP_IO.status, status_interrupt); - abort(); - return (uint32_t)0; + return (uint32_t)HAL_FORCE_READ_U32_REG_FIELD(LP_GPIO.status, status_interrupt); } /** @@ -455,21 +428,7 @@ static inline uint32_t rtcio_ll_get_interrupt_status(void) */ static inline void rtcio_ll_clear_interrupt_status(void) { - // TODO: [ESP32C5] IDF-8719 - // HAL_FORCE_MODIFY_U32_REG_FIELD(LP_IO.status_w1tc, status_w1tc, 0xff); - abort(); -} - -/** - * Enable interrupt function and set interrupt type - * - * @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio). - * @param type Interrupt type on high level or low level. - */ -static inline void rtcio_ll_intr_enable(int rtcio_num, rtcio_ll_intr_type_t type) -{ - // TODO: [ESP32C5] IDF-8719 - //LP_GPIO.pin[rtcio_num].int_type = type; + HAL_FORCE_MODIFY_U32_REG_FIELD(LP_GPIO.status_w1tc, status_w1tc, 0xff); } #ifdef __cplusplus diff --git a/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in index cd6b6ff498..bb9456119d 100644 --- a/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in @@ -295,6 +295,14 @@ config SOC_GPIO_SUPPORT_RTC_INDEPENDENT bool default y +config SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP + bool + default y + +config SOC_LP_IO_CLOCK_IS_INDEPENDENT + bool + default y + config SOC_GPIO_IN_RANGE_MAX int default 28 @@ -325,7 +333,19 @@ config SOC_GPIO_CLOCKOUT_CHANNEL_NUM config SOC_RTCIO_PIN_COUNT int - default 0 + default 8 + +config SOC_RTCIO_INPUT_OUTPUT_SUPPORTED + bool + default y + +config SOC_RTCIO_HOLD_SUPPORTED + bool + default y + +config SOC_RTCIO_WAKE_SUPPORTED + bool + default y config SOC_I2C_NUM int diff --git a/components/soc/esp32c5/include/soc/rtc_io_channel.h b/components/soc/esp32c5/include/soc/rtc_io_channel.h new file mode 100644 index 0000000000..df2120f045 --- /dev/null +++ b/components/soc/esp32c5/include/soc/rtc_io_channel.h @@ -0,0 +1,31 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define RTCIO_GPIO0_CHANNEL 0 //RTCIO_CHANNEL_0 +#define RTCIO_CHANNEL_0_GPIO_NUM 0 + +#define RTCIO_GPIO1_CHANNEL 1 //RTCIO_CHANNEL_1 +#define RTCIO_CHANNEL_1_GPIO_NUM 1 + +#define RTCIO_GPIO2_CHANNEL 2 //RTCIO_CHANNEL_2 +#define RTCIO_CHANNEL_2_GPIO_NUM 2 + +#define RTCIO_GPIO3_CHANNEL 3 //RTCIO_CHANNEL_3 +#define RTCIO_CHANNEL_3_GPIO_NUM 3 + +#define RTCIO_GPIO4_CHANNEL 4 //RTCIO_CHANNEL_4 +#define RTCIO_CHANNEL_4_GPIO_NUM 4 + +#define RTCIO_GPIO5_CHANNEL 5 //RTCIO_CHANNEL_5 +#define RTCIO_CHANNEL_5_GPIO_NUM 5 + +#define RTCIO_GPIO6_CHANNEL 6 //RTCIO_CHANNEL_6 +#define RTCIO_CHANNEL_6_GPIO_NUM 6 + +#define RTCIO_GPIO7_CHANNEL 7 //RTCIO_CHANNEL_7 +#define RTCIO_CHANNEL_7_GPIO_NUM 7 diff --git a/components/soc/esp32c5/include/soc/soc_caps.h b/components/soc/esp32c5/include/soc/soc_caps.h index cdfddd9f91..9eb54ce783 100644 --- a/components/soc/esp32c5/include/soc/soc_caps.h +++ b/components/soc/esp32c5/include/soc/soc_caps.h @@ -196,7 +196,9 @@ // On ESP32-C5, Digital IOs have their own registers to control pullup/down capability, independent of LP registers. #define SOC_GPIO_SUPPORT_RTC_INDEPENDENT (1) // GPIO0~7 on ESP32C5 can support chip deep sleep wakeup -// #define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP (1) // TODO: [ESP32C5] IDF-8719 +#define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP (1) +// LP IO peripherals have independent clock gating to manage +#define SOC_LP_IO_CLOCK_IS_INDEPENDENT (1) #define SOC_GPIO_VALID_GPIO_MASK ((1U<