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feat(cache): added cache init configurations on p4

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This commit is contained in:
Armando
2023-07-21 12:37:06 +08:00
committed by Armando (Dou Yiwen)
parent 756c36504a
commit e8bbb490ec
2 changed files with 33 additions and 1 deletions
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5
components/esp_system/port/cpu_start.c
View File

@@ -483,6 +483,11 @@ void IRAM_ATTR call_start_cpu0(void)
Cache_Resume_DCache(0); Cache_Resume_DCache(0);
#endif // CONFIG_IDF_TARGET_ESP32S3 #endif // CONFIG_IDF_TARGET_ESP32S3
#if CONFIG_IDF_TARGET_ESP32P4
//TODO: IDF-7516, add cache init API
extern void esp_config_llc_mode(void);
esp_config_llc_mode();
#endif
if (esp_efuse_check_errors() != ESP_OK) { if (esp_efuse_check_errors() != ESP_OK) {
esp_restart(); esp_restart();
} }

29
components/spi_flash/cache_utils.c
View File

@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -39,6 +39,8 @@
#include "esp32h2/rom/cache.h" #include "esp32h2/rom/cache.h"
#include "soc/extmem_reg.h" #include "soc/extmem_reg.h"
#include "soc/ext_mem_defs.h" #include "soc/ext_mem_defs.h"
#elif CONFIG_IDF_TARGET_ESP32P4
#include "esp32p4/rom/cache.h"
#endif #endif
#include "esp_rom_spiflash.h" #include "esp_rom_spiflash.h"
#include "hal/cache_hal.h" #include "hal/cache_hal.h"
@@ -914,3 +916,28 @@ esp_err_t esp_enable_cache_wrap(bool icache_wrap_enable)
return ESP_OK; return ESP_OK;
} }
#endif // CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 #endif // CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2
#if CONFIG_IDF_TARGET_ESP32P4
//TODO: IDF-5670
TCM_IRAM_ATTR void esp_config_llc_mode(void)
{
cache_size_t cache_size;
cache_line_size_t cache_line_size;
#if CONFIG_ESP32P4_L2_CACHE_128KB
cache_size = CACHE_SIZE_128K;
#elif CONFIG_ESP32P4_L2_CACHE_256KB
cache_size = CACHE_SIZE_256K;
#else
cache_size = CACHE_SIZE_512K;
#endif
#if CONFIG_ESP32P4_L2_CACHE_LINE_64B
cache_line_size = CACHE_LINE_SIZE_64B;
#else
cache_line_size = CACHE_LINE_SIZE_128B;
#endif
Cache_Set_L2_Cache_Mode(cache_size, 8, cache_line_size);
Cache_Invalidate_All(CACHE_MAP_L2_CACHE);
}
#endif