From e921d03a0d4b5ce47d7d23432aa3d928f92e67e2 Mon Sep 17 00:00:00 2001 From: Armando Date: Fri, 30 Jun 2023 10:49:44 +0800 Subject: [PATCH] feat(soc): update gpio_ext_reg.h and its base addr --- .../soc/esp32p4/include/soc/gpio_ext_reg.h | 80 +++++++++---------- components/soc/esp32p4/include/soc/reg_base.h | 6 +- 2 files changed, 41 insertions(+), 45 deletions(-) diff --git a/components/soc/esp32p4/include/soc/gpio_ext_reg.h b/components/soc/esp32p4/include/soc/gpio_ext_reg.h index f994cd233e..157a4c9e0a 100644 --- a/components/soc/esp32p4/include/soc/gpio_ext_reg.h +++ b/components/soc/esp32p4/include/soc/gpio_ext_reg.h @@ -23,7 +23,7 @@ extern "C" { /** GPIOSD_SIGMADELTA0_REG register * Duty Cycle Configure Register of SDM0 */ -#define GPIOSD_SIGMADELTA0_REG (DR_REG_GPIOSD_BASE + 0x0) +#define GPIOSD_SIGMADELTA0_REG (DR_REG_GPIO_EXT_BASE + 0x0) /** GPIOSD_SD0_IN : R/W; bitpos: [7:0]; default: 0; * This field is used to configure the duty cycle of sigma delta modulation output. */ @@ -42,7 +42,7 @@ extern "C" { /** GPIOSD_SIGMADELTA1_REG register * Duty Cycle Configure Register of SDM1 */ -#define GPIOSD_SIGMADELTA1_REG (DR_REG_GPIOSD_BASE + 0x4) +#define GPIOSD_SIGMADELTA1_REG (DR_REG_GPIO_EXT_BASE + 0x4) /** GPIOSD_SD0_IN : R/W; bitpos: [7:0]; default: 0; * This field is used to configure the duty cycle of sigma delta modulation output. */ @@ -61,7 +61,7 @@ extern "C" { /** GPIOSD_SIGMADELTA2_REG register * Duty Cycle Configure Register of SDM2 */ -#define GPIOSD_SIGMADELTA2_REG (DR_REG_GPIOSD_BASE + 0x8) +#define GPIOSD_SIGMADELTA2_REG (DR_REG_GPIO_EXT_BASE + 0x8) /** GPIOSD_SD0_IN : R/W; bitpos: [7:0]; default: 0; * This field is used to configure the duty cycle of sigma delta modulation output. */ @@ -80,7 +80,7 @@ extern "C" { /** GPIOSD_SIGMADELTA3_REG register * Duty Cycle Configure Register of SDM3 */ -#define GPIOSD_SIGMADELTA3_REG (DR_REG_GPIOSD_BASE + 0xc) +#define GPIOSD_SIGMADELTA3_REG (DR_REG_GPIO_EXT_BASE + 0xc) /** GPIOSD_SD0_IN : R/W; bitpos: [7:0]; default: 0; * This field is used to configure the duty cycle of sigma delta modulation output. */ @@ -99,7 +99,7 @@ extern "C" { /** GPIOSD_SIGMADELTA4_REG register * Duty Cycle Configure Register of SDM4 */ -#define GPIOSD_SIGMADELTA4_REG (DR_REG_GPIOSD_BASE + 0x10) +#define GPIOSD_SIGMADELTA4_REG (DR_REG_GPIO_EXT_BASE + 0x10) /** GPIOSD_SD0_IN : R/W; bitpos: [7:0]; default: 0; * This field is used to configure the duty cycle of sigma delta modulation output. */ @@ -118,7 +118,7 @@ extern "C" { /** GPIOSD_SIGMADELTA5_REG register * Duty Cycle Configure Register of SDM5 */ -#define GPIOSD_SIGMADELTA5_REG (DR_REG_GPIOSD_BASE + 0x14) +#define GPIOSD_SIGMADELTA5_REG (DR_REG_GPIO_EXT_BASE + 0x14) /** GPIOSD_SD0_IN : R/W; bitpos: [7:0]; default: 0; * This field is used to configure the duty cycle of sigma delta modulation output. */ @@ -137,7 +137,7 @@ extern "C" { /** GPIOSD_SIGMADELTA6_REG register * Duty Cycle Configure Register of SDM6 */ -#define GPIOSD_SIGMADELTA6_REG (DR_REG_GPIOSD_BASE + 0x18) +#define GPIOSD_SIGMADELTA6_REG (DR_REG_GPIO_EXT_BASE + 0x18) /** GPIOSD_SD0_IN : R/W; bitpos: [7:0]; default: 0; * This field is used to configure the duty cycle of sigma delta modulation output. */ @@ -156,7 +156,7 @@ extern "C" { /** GPIOSD_SIGMADELTA7_REG register * Duty Cycle Configure Register of SDM7 */ -#define GPIOSD_SIGMADELTA7_REG (DR_REG_GPIOSD_BASE + 0x1c) +#define GPIOSD_SIGMADELTA7_REG (DR_REG_GPIO_EXT_BASE + 0x1c) /** GPIOSD_SD0_IN : R/W; bitpos: [7:0]; default: 0; * This field is used to configure the duty cycle of sigma delta modulation output. */ @@ -175,7 +175,7 @@ extern "C" { /** GPIOSD_SIGMADELTA_MISC_REG register * MISC Register */ -#define GPIOSD_SIGMADELTA_MISC_REG (DR_REG_GPIOSD_BASE + 0x24) +#define GPIOSD_SIGMADELTA_MISC_REG (DR_REG_GPIO_EXT_BASE + 0x24) /** GPIOSD_FUNCTION_CLK_EN : R/W; bitpos: [30]; default: 0; * Clock enable bit of sigma delta modulation. */ @@ -194,7 +194,7 @@ extern "C" { /** GPIOSD_GLITCH_FILTER_CH0_REG register * Glitch Filter Configure Register of Channel0 */ -#define GPIOSD_GLITCH_FILTER_CH0_REG (DR_REG_GPIOSD_BASE + 0x30) +#define GPIOSD_GLITCH_FILTER_CH0_REG (DR_REG_GPIO_EXT_BASE + 0x30) /** GPIOSD_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0; * Glitch Filter channel enable bit. */ @@ -227,7 +227,7 @@ extern "C" { /** GPIOSD_GLITCH_FILTER_CH1_REG register * Glitch Filter Configure Register of Channel1 */ -#define GPIOSD_GLITCH_FILTER_CH1_REG (DR_REG_GPIOSD_BASE + 0x34) +#define GPIOSD_GLITCH_FILTER_CH1_REG (DR_REG_GPIO_EXT_BASE + 0x34) /** GPIOSD_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0; * Glitch Filter channel enable bit. */ @@ -260,7 +260,7 @@ extern "C" { /** GPIOSD_GLITCH_FILTER_CH2_REG register * Glitch Filter Configure Register of Channel2 */ -#define GPIOSD_GLITCH_FILTER_CH2_REG (DR_REG_GPIOSD_BASE + 0x38) +#define GPIOSD_GLITCH_FILTER_CH2_REG (DR_REG_GPIO_EXT_BASE + 0x38) /** GPIOSD_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0; * Glitch Filter channel enable bit. */ @@ -293,7 +293,7 @@ extern "C" { /** GPIOSD_GLITCH_FILTER_CH3_REG register * Glitch Filter Configure Register of Channel3 */ -#define GPIOSD_GLITCH_FILTER_CH3_REG (DR_REG_GPIOSD_BASE + 0x3c) +#define GPIOSD_GLITCH_FILTER_CH3_REG (DR_REG_GPIO_EXT_BASE + 0x3c) /** GPIOSD_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0; * Glitch Filter channel enable bit. */ @@ -326,7 +326,7 @@ extern "C" { /** GPIOSD_GLITCH_FILTER_CH4_REG register * Glitch Filter Configure Register of Channel4 */ -#define GPIOSD_GLITCH_FILTER_CH4_REG (DR_REG_GPIOSD_BASE + 0x40) +#define GPIOSD_GLITCH_FILTER_CH4_REG (DR_REG_GPIO_EXT_BASE + 0x40) /** GPIOSD_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0; * Glitch Filter channel enable bit. */ @@ -359,7 +359,7 @@ extern "C" { /** GPIOSD_GLITCH_FILTER_CH5_REG register * Glitch Filter Configure Register of Channel5 */ -#define GPIOSD_GLITCH_FILTER_CH5_REG (DR_REG_GPIOSD_BASE + 0x44) +#define GPIOSD_GLITCH_FILTER_CH5_REG (DR_REG_GPIO_EXT_BASE + 0x44) /** GPIOSD_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0; * Glitch Filter channel enable bit. */ @@ -392,7 +392,7 @@ extern "C" { /** GPIOSD_GLITCH_FILTER_CH6_REG register * Glitch Filter Configure Register of Channel6 */ -#define GPIOSD_GLITCH_FILTER_CH6_REG (DR_REG_GPIOSD_BASE + 0x48) +#define GPIOSD_GLITCH_FILTER_CH6_REG (DR_REG_GPIO_EXT_BASE + 0x48) /** GPIOSD_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0; * Glitch Filter channel enable bit. */ @@ -425,7 +425,7 @@ extern "C" { /** GPIOSD_GLITCH_FILTER_CH7_REG register * Glitch Filter Configure Register of Channel7 */ -#define GPIOSD_GLITCH_FILTER_CH7_REG (DR_REG_GPIOSD_BASE + 0x4c) +#define GPIOSD_GLITCH_FILTER_CH7_REG (DR_REG_GPIO_EXT_BASE + 0x4c) /** GPIOSD_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0; * Glitch Filter channel enable bit. */ @@ -458,7 +458,7 @@ extern "C" { /** GPIOSD_ETM_EVENT_CH0_CFG_REG register * Etm Config register of Channel0 */ -#define GPIOSD_ETM_EVENT_CH0_CFG_REG (DR_REG_GPIOSD_BASE + 0x60) +#define GPIOSD_ETM_EVENT_CH0_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x60) /** GPIOSD_ETM_CH0_EVENT_SEL : R/W; bitpos: [5:0]; default: 0; * Etm event channel select gpio. */ @@ -477,7 +477,7 @@ extern "C" { /** GPIOSD_ETM_EVENT_CH1_CFG_REG register * Etm Config register of Channel1 */ -#define GPIOSD_ETM_EVENT_CH1_CFG_REG (DR_REG_GPIOSD_BASE + 0x64) +#define GPIOSD_ETM_EVENT_CH1_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x64) /** GPIOSD_ETM_CH0_EVENT_SEL : R/W; bitpos: [5:0]; default: 0; * Etm event channel select gpio. */ @@ -496,7 +496,7 @@ extern "C" { /** GPIOSD_ETM_EVENT_CH2_CFG_REG register * Etm Config register of Channel2 */ -#define GPIOSD_ETM_EVENT_CH2_CFG_REG (DR_REG_GPIOSD_BASE + 0x68) +#define GPIOSD_ETM_EVENT_CH2_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x68) /** GPIOSD_ETM_CH0_EVENT_SEL : R/W; bitpos: [5:0]; default: 0; * Etm event channel select gpio. */ @@ -515,7 +515,7 @@ extern "C" { /** GPIOSD_ETM_EVENT_CH3_CFG_REG register * Etm Config register of Channel3 */ -#define GPIOSD_ETM_EVENT_CH3_CFG_REG (DR_REG_GPIOSD_BASE + 0x6c) +#define GPIOSD_ETM_EVENT_CH3_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x6c) /** GPIOSD_ETM_CH0_EVENT_SEL : R/W; bitpos: [5:0]; default: 0; * Etm event channel select gpio. */ @@ -534,7 +534,7 @@ extern "C" { /** GPIOSD_ETM_EVENT_CH4_CFG_REG register * Etm Config register of Channel4 */ -#define GPIOSD_ETM_EVENT_CH4_CFG_REG (DR_REG_GPIOSD_BASE + 0x70) +#define GPIOSD_ETM_EVENT_CH4_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x70) /** GPIOSD_ETM_CH0_EVENT_SEL : R/W; bitpos: [5:0]; default: 0; * Etm event channel select gpio. */ @@ -553,7 +553,7 @@ extern "C" { /** GPIOSD_ETM_EVENT_CH5_CFG_REG register * Etm Config register of Channel5 */ -#define GPIOSD_ETM_EVENT_CH5_CFG_REG (DR_REG_GPIOSD_BASE + 0x74) +#define GPIOSD_ETM_EVENT_CH5_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x74) /** GPIOSD_ETM_CH0_EVENT_SEL : R/W; bitpos: [5:0]; default: 0; * Etm event channel select gpio. */ @@ -572,7 +572,7 @@ extern "C" { /** GPIOSD_ETM_EVENT_CH6_CFG_REG register * Etm Config register of Channel6 */ -#define GPIOSD_ETM_EVENT_CH6_CFG_REG (DR_REG_GPIOSD_BASE + 0x78) +#define GPIOSD_ETM_EVENT_CH6_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x78) /** GPIOSD_ETM_CH0_EVENT_SEL : R/W; bitpos: [5:0]; default: 0; * Etm event channel select gpio. */ @@ -591,7 +591,7 @@ extern "C" { /** GPIOSD_ETM_EVENT_CH7_CFG_REG register * Etm Config register of Channel7 */ -#define GPIOSD_ETM_EVENT_CH7_CFG_REG (DR_REG_GPIOSD_BASE + 0x7c) +#define GPIOSD_ETM_EVENT_CH7_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x7c) /** GPIOSD_ETM_CH0_EVENT_SEL : R/W; bitpos: [5:0]; default: 0; * Etm event channel select gpio. */ @@ -610,7 +610,7 @@ extern "C" { /** GPIOSD_ETM_TASK_P0_CFG_REG register * Etm Configure Register to decide which GPIO been chosen */ -#define GPIOSD_ETM_TASK_P0_CFG_REG (DR_REG_GPIOSD_BASE + 0xa0) +#define GPIOSD_ETM_TASK_P0_CFG_REG (DR_REG_GPIO_EXT_BASE + 0xa0) /** GPIOSD_ETM_TASK_GPIO0_EN : R/W; bitpos: [0]; default: 0; * Enable bit of GPIO response etm task. */ @@ -671,7 +671,7 @@ extern "C" { /** GPIOSD_ETM_TASK_P1_CFG_REG register * Etm Configure Register to decide which GPIO been chosen */ -#define GPIOSD_ETM_TASK_P1_CFG_REG (DR_REG_GPIOSD_BASE + 0xa4) +#define GPIOSD_ETM_TASK_P1_CFG_REG (DR_REG_GPIO_EXT_BASE + 0xa4) /** GPIOSD_ETM_TASK_GPIO4_EN : R/W; bitpos: [0]; default: 0; * Enable bit of GPIO response etm task. */ @@ -732,7 +732,7 @@ extern "C" { /** GPIOSD_ETM_TASK_P2_CFG_REG register * Etm Configure Register to decide which GPIO been chosen */ -#define GPIOSD_ETM_TASK_P2_CFG_REG (DR_REG_GPIOSD_BASE + 0xa8) +#define GPIOSD_ETM_TASK_P2_CFG_REG (DR_REG_GPIO_EXT_BASE + 0xa8) /** GPIOSD_ETM_TASK_GPIO8_EN : R/W; bitpos: [0]; default: 0; * Enable bit of GPIO response etm task. */ @@ -793,7 +793,7 @@ extern "C" { /** GPIOSD_ETM_TASK_P3_CFG_REG register * Etm Configure Register to decide which GPIO been chosen */ -#define GPIOSD_ETM_TASK_P3_CFG_REG (DR_REG_GPIOSD_BASE + 0xac) +#define GPIOSD_ETM_TASK_P3_CFG_REG (DR_REG_GPIO_EXT_BASE + 0xac) /** GPIOSD_ETM_TASK_GPIO12_EN : R/W; bitpos: [0]; default: 0; * Enable bit of GPIO response etm task. */ @@ -854,7 +854,7 @@ extern "C" { /** GPIOSD_ETM_TASK_P4_CFG_REG register * Etm Configure Register to decide which GPIO been chosen */ -#define GPIOSD_ETM_TASK_P4_CFG_REG (DR_REG_GPIOSD_BASE + 0xb0) +#define GPIOSD_ETM_TASK_P4_CFG_REG (DR_REG_GPIO_EXT_BASE + 0xb0) /** GPIOSD_ETM_TASK_GPIO16_EN : R/W; bitpos: [0]; default: 0; * Enable bit of GPIO response etm task. */ @@ -915,7 +915,7 @@ extern "C" { /** GPIOSD_ETM_TASK_P5_CFG_REG register * Etm Configure Register to decide which GPIO been chosen */ -#define GPIOSD_ETM_TASK_P5_CFG_REG (DR_REG_GPIOSD_BASE + 0xb4) +#define GPIOSD_ETM_TASK_P5_CFG_REG (DR_REG_GPIO_EXT_BASE + 0xb4) /** GPIOSD_ETM_TASK_GPIO20_EN : R/W; bitpos: [0]; default: 0; * Enable bit of GPIO response etm task. */ @@ -976,7 +976,7 @@ extern "C" { /** GPIOSD_ETM_TASK_P6_CFG_REG register * Etm Configure Register to decide which GPIO been chosen */ -#define GPIOSD_ETM_TASK_P6_CFG_REG (DR_REG_GPIOSD_BASE + 0xb8) +#define GPIOSD_ETM_TASK_P6_CFG_REG (DR_REG_GPIO_EXT_BASE + 0xb8) /** GPIOSD_ETM_TASK_GPIO24_EN : R/W; bitpos: [0]; default: 0; * Enable bit of GPIO response etm task. */ @@ -1037,7 +1037,7 @@ extern "C" { /** GPIOSD_ETM_TASK_P7_CFG_REG register * Etm Configure Register to decide which GPIO been chosen */ -#define GPIOSD_ETM_TASK_P7_CFG_REG (DR_REG_GPIOSD_BASE + 0xbc) +#define GPIOSD_ETM_TASK_P7_CFG_REG (DR_REG_GPIO_EXT_BASE + 0xbc) /** GPIOSD_ETM_TASK_GPIO28_EN : R/W; bitpos: [0]; default: 0; * Enable bit of GPIO response etm task. */ @@ -1098,7 +1098,7 @@ extern "C" { /** GPIOSD_ETM_TASK_P8_CFG_REG register * Etm Configure Register to decide which GPIO been chosen */ -#define GPIOSD_ETM_TASK_P8_CFG_REG (DR_REG_GPIOSD_BASE + 0xc0) +#define GPIOSD_ETM_TASK_P8_CFG_REG (DR_REG_GPIO_EXT_BASE + 0xc0) /** GPIOSD_ETM_TASK_GPIO32_EN : R/W; bitpos: [0]; default: 0; * Enable bit of GPIO response etm task. */ @@ -1159,7 +1159,7 @@ extern "C" { /** GPIOSD_ETM_TASK_P9_CFG_REG register * Etm Configure Register to decide which GPIO been chosen */ -#define GPIOSD_ETM_TASK_P9_CFG_REG (DR_REG_GPIOSD_BASE + 0xc4) +#define GPIOSD_ETM_TASK_P9_CFG_REG (DR_REG_GPIO_EXT_BASE + 0xc4) /** GPIOSD_ETM_TASK_GPIO36_EN : R/W; bitpos: [0]; default: 0; * Enable bit of GPIO response etm task. */ @@ -1220,7 +1220,7 @@ extern "C" { /** GPIOSD_ETM_TASK_P10_CFG_REG register * Etm Configure Register to decide which GPIO been chosen */ -#define GPIOSD_ETM_TASK_P10_CFG_REG (DR_REG_GPIOSD_BASE + 0xc8) +#define GPIOSD_ETM_TASK_P10_CFG_REG (DR_REG_GPIO_EXT_BASE + 0xc8) /** GPIOSD_ETM_TASK_GPIO40_EN : R/W; bitpos: [0]; default: 0; * Enable bit of GPIO response etm task. */ @@ -1281,7 +1281,7 @@ extern "C" { /** GPIOSD_ETM_TASK_P11_CFG_REG register * Etm Configure Register to decide which GPIO been chosen */ -#define GPIOSD_ETM_TASK_P11_CFG_REG (DR_REG_GPIOSD_BASE + 0xcc) +#define GPIOSD_ETM_TASK_P11_CFG_REG (DR_REG_GPIO_EXT_BASE + 0xcc) /** GPIOSD_ETM_TASK_GPIO44_EN : R/W; bitpos: [0]; default: 0; * Enable bit of GPIO response etm task. */ @@ -1342,7 +1342,7 @@ extern "C" { /** GPIOSD_ETM_TASK_P12_CFG_REG register * Etm Configure Register to decide which GPIO been chosen */ -#define GPIOSD_ETM_TASK_P12_CFG_REG (DR_REG_GPIOSD_BASE + 0xd0) +#define GPIOSD_ETM_TASK_P12_CFG_REG (DR_REG_GPIO_EXT_BASE + 0xd0) /** GPIOSD_ETM_TASK_GPIO48_EN : R/W; bitpos: [0]; default: 0; * Enable bit of GPIO response etm task. */ @@ -1403,7 +1403,7 @@ extern "C" { /** GPIOSD_ETM_TASK_P13_CFG_REG register * Etm Configure Register to decide which GPIO been chosen */ -#define GPIOSD_ETM_TASK_P13_CFG_REG (DR_REG_GPIOSD_BASE + 0xd4) +#define GPIOSD_ETM_TASK_P13_CFG_REG (DR_REG_GPIO_EXT_BASE + 0xd4) /** GPIOSD_ETM_TASK_GPIO52_EN : R/W; bitpos: [0]; default: 0; * Enable bit of GPIO response etm task. */ @@ -1450,7 +1450,7 @@ extern "C" { /** GPIOSD_VERSION_REG register * Version Control Register */ -#define GPIOSD_VERSION_REG (DR_REG_GPIOSD_BASE + 0xfc) +#define GPIOSD_VERSION_REG (DR_REG_GPIO_EXT_BASE + 0xfc) /** GPIOSD_GPIO_SD_DATE : R/W; bitpos: [27:0]; default: 35663952; * Version control register. */ diff --git a/components/soc/esp32p4/include/soc/reg_base.h b/components/soc/esp32p4/include/soc/reg_base.h index c6397f4729..5fb009f8cb 100644 --- a/components/soc/esp32p4/include/soc/reg_base.h +++ b/components/soc/esp32p4/include/soc/reg_base.h @@ -106,7 +106,7 @@ #define DR_REG_ADC_BASE (DR_REG_HPPERIPH1_BASE + 0x1E000) #define DR_REG_UHCI_BASE (DR_REG_HPPERIPH1_BASE + 0x1F000) #define DR_REG_GPIO_BASE (DR_REG_HPPERIPH1_BASE + 0x20000) -#define DR_REG_GPIO_SD_BASE (DR_REG_HPPERIPH1_BASE + 0x20F00) +#define DR_REG_GPIO_EXT_BASE (DR_REG_HPPERIPH1_BASE + 0x20F00) #define DR_REG_IO_MUX_BASE (DR_REG_HPPERIPH1_BASE + 0x21000) #define DR_REG_SYSTIMER_BASE (DR_REG_HPPERIPH1_BASE + 0x22000) #define DR_REG_MEM_MON_BASE (DR_REG_HPPERIPH1_BASE + 0x23000) @@ -186,10 +186,6 @@ #define DR_REG_LPPERI_BASE DR_REG_LP_PERI_CLKRST_BASE #define DR_REG_CPU_BUS_MONITOR_BASE DR_REG_CPU_BUS_MON_BASE - -//TODO: IDF-7481, TODO: IDF-7479, TODO: IDF-7551 -// #define DR_REG_GPIO_EXT_BASE 0x60091f00 - //TODO: IDF-7542 // #define DR_REG_TEE_BASE 0x60098000 // #define DR_REG_HP_APM_BASE 0x60099000