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fix(cache): no longer use freeze in esp_cache_msync

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Writeback and invalidation don't need cache to be frozen first
This commit is contained in:
Armando
2023-07-13 15:09:12 +08:00
parent 83683d8b12
commit eb1831f8d7
1 changed files with 7 additions and 38 deletions
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45
components/esp_mm/esp_cache.c
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@@ -9,40 +9,16 @@
#include "sdkconfig.h" #include "sdkconfig.h"
#include "esp_check.h" #include "esp_check.h"
#include "esp_log.h" #include "esp_log.h"
#include "esp_rom_caps.h"
#include "soc/soc_caps.h" #include "soc/soc_caps.h"
#include "hal/mmu_hal.h" #include "hal/mmu_hal.h"
#include "hal/cache_hal.h" #include "hal/cache_hal.h"
#include "esp_cache.h" #include "esp_cache.h"
#include "esp_private/critical_section.h" #include "esp_private/critical_section.h"
static const char *TAG = "cache"; static const char *TAG = "cache";
DEFINE_CRIT_SECTION_LOCK_STATIC(s_spinlock); DEFINE_CRIT_SECTION_LOCK_STATIC(s_spinlock);
void s_cache_freeze(void)
{
#if SOC_CACHE_FREEZE_SUPPORTED
cache_hal_freeze(CACHE_TYPE_DATA | CACHE_TYPE_INSTRUCTION);
#endif
/**
* For writeback supported, but the freeze not supported chip (Now only S2),
* as it's single core, the critical section is enough to prevent preemption from an non-IRAM ISR
*/
}
void s_cache_unfreeze(void)
{
#if SOC_CACHE_FREEZE_SUPPORTED
cache_hal_unfreeze(CACHE_TYPE_DATA | CACHE_TYPE_INSTRUCTION);
#endif
/**
* Similarly, for writeback supported, but the freeze not supported chip (Now only S2),
* we don't need to do more
*/
}
esp_err_t esp_cache_msync(void *addr, size_t size, int flags) esp_err_t esp_cache_msync(void *addr, size_t size, int flags)
{ {
@@ -57,21 +33,15 @@ esp_err_t esp_cache_msync(void *addr, size_t size, int flags)
ESP_EARLY_LOGD(TAG, "M2C DIR"); ESP_EARLY_LOGD(TAG, "M2C DIR");
esp_os_enter_critical_safe(&s_spinlock); esp_os_enter_critical_safe(&s_spinlock);
s_cache_freeze();
//Add preload feature / flag here, IDF-7800 //Add preload feature / flag here, IDF-7800
cache_hal_invalidate_addr(vaddr, size); cache_hal_invalidate_addr(vaddr, size);
s_cache_unfreeze();
esp_os_exit_critical_safe(&s_spinlock); esp_os_exit_critical_safe(&s_spinlock);
} else { } else {
ESP_EARLY_LOGD(TAG, "C2M DIR"); ESP_EARLY_LOGD(TAG, "C2M DIR");
#if SOC_CACHE_WRITEBACK_SUPPORTED #if SOC_CACHE_WRITEBACK_SUPPORTED
esp_os_enter_critical_safe(&s_spinlock);
uint32_t data_cache_line_size = cache_hal_get_cache_line_size(CACHE_TYPE_DATA); uint32_t data_cache_line_size = cache_hal_get_cache_line_size(CACHE_TYPE_DATA);
esp_os_exit_critical_safe(&s_spinlock);
if ((flags & ESP_CACHE_MSYNC_FLAG_UNALIGNED) == 0) { if ((flags & ESP_CACHE_MSYNC_FLAG_UNALIGNED) == 0) {
bool aligned_addr = (((uint32_t)addr % data_cache_line_size) == 0) && ((size % data_cache_line_size) == 0); bool aligned_addr = (((uint32_t)addr % data_cache_line_size) == 0) && ((size % data_cache_line_size) == 0);
@@ -79,15 +49,14 @@ esp_err_t esp_cache_msync(void *addr, size_t size, int flags)
} }
esp_os_enter_critical_safe(&s_spinlock); esp_os_enter_critical_safe(&s_spinlock);
s_cache_freeze();
cache_hal_writeback_addr(vaddr, size); cache_hal_writeback_addr(vaddr, size);
if (flags & ESP_CACHE_MSYNC_FLAG_INVALIDATE) {
cache_hal_invalidate_addr(vaddr, size);
}
s_cache_unfreeze();
esp_os_exit_critical_safe(&s_spinlock); esp_os_exit_critical_safe(&s_spinlock);
if (flags & ESP_CACHE_MSYNC_FLAG_INVALIDATE) {
esp_os_enter_critical_safe(&s_spinlock);
cache_hal_invalidate_addr(vaddr, size);
esp_os_exit_critical_safe(&s_spinlock);
}
#endif #endif
} }