From eb74a5f9ddb325ec4f01b0e9cca830b6b07bcc8b Mon Sep 17 00:00:00 2001 From: Laukik Hase Date: Tue, 16 Sep 2025 18:33:24 +0530 Subject: [PATCH] feat(esp_tee): Enable MSPI tuning for Flash and PSRAM --- components/esp_hw_support/CMakeLists.txt | 13 +++++++ .../mspi_timing_tuning/mspi_timing_tuning.c | 14 ++++++++ .../port/esp32c5/mspi_timing_tuning_configs.h | 8 ++--- .../scripts/esp32c5/sec_srv_tbl_default.yml | 24 +++++++++++++ .../esp_tee/src/esp_secure_service_wrapper.c | 34 +++++++++++++++++++ .../main/core/esp_secure_services_iram.c | 33 ++++++++++++++++++ 6 files changed, 120 insertions(+), 6 deletions(-) diff --git a/components/esp_hw_support/CMakeLists.txt b/components/esp_hw_support/CMakeLists.txt index 9005a47f248..710ffb28f83 100644 --- a/components/esp_hw_support/CMakeLists.txt +++ b/components/esp_hw_support/CMakeLists.txt @@ -175,7 +175,20 @@ if(NOT non_os_build) else() if(ESP_TEE_BUILD) list(APPEND srcs "esp_clk.c" "hw_random.c") + if(CONFIG_SECURE_TEE_EXT_FLASH_MEMPROT_SPI1) + list(APPEND srcs "mspi_timing_tuning/mspi_timing_tuning.c") + if(CONFIG_SOC_MEMSPI_TIMING_TUNING_BY_MSPI_DELAY) + list(APPEND srcs "mspi_timing_tuning/tuning_scheme_impl/mspi_timing_by_mspi_delay.c") + endif() + if(CONFIG_SOC_MEMSPI_TIMING_TUNING_BY_DQS) + list(APPEND srcs "mspi_timing_tuning/tuning_scheme_impl/mspi_timing_by_dqs.c") + endif() + if(CONFIG_SOC_MEMSPI_TIMING_TUNING_BY_FLASH_DELAY) + list(APPEND srcs "mspi_timing_tuning/tuning_scheme_impl/mspi_timing_by_flash_delay.c") + endif() + endif() endif() + # Requires "_esp_error_check_failed()" function list(APPEND priv_requires "esp_system") endif() diff --git a/components/esp_hw_support/mspi_timing_tuning/mspi_timing_tuning.c b/components/esp_hw_support/mspi_timing_tuning/mspi_timing_tuning.c index 62e9d301ae5..97517c565ec 100644 --- a/components/esp_hw_support/mspi_timing_tuning/mspi_timing_tuning.c +++ b/components/esp_hw_support/mspi_timing_tuning/mspi_timing_tuning.c @@ -15,7 +15,12 @@ #include "soc/soc.h" #include "hal/spi_flash_hal.h" #include "hal/mspi_ll.h" +#if !ESP_TEE_BUILD #include "esp_private/esp_cache_private.h" +#else +#include "hal/cache_ll.h" +#include "hal/cache_hal.h" +#endif #include "esp_private/mspi_timing_tuning.h" #include "esp_private/mspi_timing_config.h" #include "esp_private/mspi_timing_by_mspi_delay.h" @@ -553,7 +558,12 @@ void mspi_timing_change_speed_mode_cache_safe(bool switch_down) * for preventing concurrent from MSPI to external memory */ #if SOC_CACHE_FREEZE_SUPPORTED +#if !ESP_TEE_BUILD esp_cache_freeze_ext_mem_cache(); +#else + /* NOTE: [ESP-TEE] Check implementation when SoCs with 2-level cache are supported */ + cache_hal_freeze(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL); +#endif #endif //#if SOC_CACHE_FREEZE_SUPPORTED if (switch_down) { @@ -565,7 +575,11 @@ void mspi_timing_change_speed_mode_cache_safe(bool switch_down) } #if SOC_CACHE_FREEZE_SUPPORTED +#if !ESP_TEE_BUILD esp_cache_unfreeze_ext_mem_cache(); +#else + cache_hal_unfreeze(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL); +#endif #endif //#if SOC_CACHE_FREEZE_SUPPORTED #if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE && !CONFIG_FREERTOS_UNICORE diff --git a/components/esp_hw_support/mspi_timing_tuning/port/esp32c5/mspi_timing_tuning_configs.h b/components/esp_hw_support/mspi_timing_tuning/port/esp32c5/mspi_timing_tuning_configs.h index 82558dbb9eb..a4a623e5989 100644 --- a/components/esp_hw_support/mspi_timing_tuning/port/esp32c5/mspi_timing_tuning_configs.h +++ b/components/esp_hw_support/mspi_timing_tuning/port/esp32c5/mspi_timing_tuning_configs.h @@ -28,10 +28,7 @@ #define MSPI_TIMING_FLASH_MODULE_CLOCK 120 #endif //------------------------------------FLASH Needs Tuning or not-------------------------------------// -/* TODO: [ESP-TEE | IDF-10425] The SPI1 controller is protected by APM when ESP-TEE is enabled. - * MSPI tuning requires access to this controller, so it is currently disabled. - */ -#if MSPI_TIMING_FLASH_STR_MODE && !CONFIG_SECURE_ENABLE_TEE +#if MSPI_TIMING_FLASH_STR_MODE #define MSPI_TIMING_FLASH_NEEDS_TUNING (MSPI_TIMING_FLASH_MODULE_CLOCK > 40) #endif @@ -48,8 +45,7 @@ #define MSPI_TIMING_PSRAM_MODULE_CLOCK 10 //Define this to 10MHz #endif //------------------------------------PSRAM Needs Tuning or not-------------------------------------// -/* TODO: [ESP-TEE | IDF-10425] */ -#if MSPI_TIMING_PSRAM_STR_MODE && !CONFIG_SECURE_ENABLE_TEE +#if MSPI_TIMING_PSRAM_STR_MODE #define MSPI_TIMING_PSRAM_NEEDS_TUNING (MSPI_TIMING_PSRAM_MODULE_CLOCK > 40) #endif diff --git a/components/esp_tee/scripts/esp32c5/sec_srv_tbl_default.yml b/components/esp_tee/scripts/esp32c5/sec_srv_tbl_default.yml index 038e8388762..eca52728504 100644 --- a/components/esp_tee/scripts/esp32c5/sec_srv_tbl_default.yml +++ b/components/esp_tee/scripts/esp32c5/sec_srv_tbl_default.yml @@ -96,6 +96,30 @@ secure_services: type: IDF function: spi_flash_chip_generic_config_host_io_mode args: 2 + - id: 23 + type: IDF + function: mspi_timing_flash_tuning + args: 0 + - id: 24 + type: IDF + function: mspi_timing_psram_tuning + args: 0 + - id: 25 + type: IDF + function: mspi_timing_enter_low_speed_mode + args: 1 + - id: 26 + type: IDF + function: mspi_timing_enter_high_speed_mode + args: 1 + - id: 27 + type: IDF + function: mspi_timing_change_speed_mode_cache_safe + args: 1 + - id: 28 + type: IDF + function: spi_timing_get_flash_timing_param + args: 1 # ID: 30-53 (24) - Interrupt Handling - family: interrupt_handling entries: diff --git a/components/esp_tee/src/esp_secure_service_wrapper.c b/components/esp_tee/src/esp_secure_service_wrapper.c index a34ec4df56f..a6c8e39ea3a 100644 --- a/components/esp_tee/src/esp_secure_service_wrapper.c +++ b/components/esp_tee/src/esp_secure_service_wrapper.c @@ -13,7 +13,9 @@ #include "rom/digital_signature.h" #include "hal/mmu_types.h" #include "hal/wdt_hal.h" +#include "hal/spi_flash_hal.h" #include "hal/spi_flash_types.h" +#include "esp_private/mspi_timing_tuning.h" #include "esp_hmac.h" #include "esp_ds.h" #include "esp_crypto_lock.h" @@ -490,4 +492,36 @@ esp_err_t IRAM_ATTR __wrap_spi_flash_chip_generic_config_host_io_mode(esp_flash_ { return esp_tee_service_call(3, SS_SPI_FLASH_CHIP_GENERIC_CONFIG_HOST_IO_MODE, chip, flags); } + +#if CONFIG_IDF_TARGET_ESP32C5 +void IRAM_ATTR __wrap_mspi_timing_flash_tuning(void) +{ + esp_tee_service_call(1, SS_MSPI_TIMING_FLASH_TUNING); +} + +void IRAM_ATTR __wrap_mspi_timing_psram_tuning(void) +{ + esp_tee_service_call(1, SS_MSPI_TIMING_PSRAM_TUNING); +} + +void IRAM_ATTR __wrap_mspi_timing_enter_low_speed_mode(bool control_spi1) +{ + esp_tee_service_call(2, SS_MSPI_TIMING_ENTER_LOW_SPEED_MODE, control_spi1); +} + +void IRAM_ATTR __wrap_mspi_timing_enter_high_speed_mode(bool control_spi1) +{ + esp_tee_service_call(2, SS_MSPI_TIMING_ENTER_HIGH_SPEED_MODE, control_spi1); +} + +void IRAM_ATTR __wrap_mspi_timing_change_speed_mode_cache_safe(bool switch_down) +{ + esp_tee_service_call(2, SS_MSPI_TIMING_CHANGE_SPEED_MODE_CACHE_SAFE, switch_down); +} + +void IRAM_ATTR __wrap_spi_timing_get_flash_timing_param(spi_flash_hal_timing_config_t *out_timing_config) +{ + esp_tee_service_call(2, SS_SPI_TIMING_GET_FLASH_TIMING_PARAM, out_timing_config); +} +#endif #endif diff --git a/components/esp_tee/subproject/main/core/esp_secure_services_iram.c b/components/esp_tee/subproject/main/core/esp_secure_services_iram.c index 169448f406a..0413e147b7c 100644 --- a/components/esp_tee/subproject/main/core/esp_secure_services_iram.c +++ b/components/esp_tee/subproject/main/core/esp_secure_services_iram.c @@ -18,6 +18,7 @@ #include "hal/spi_flash_types.h" #include "spi_flash_chip_generic.h" #include "memspi_host_driver.h" +#include "esp_private/mspi_timing_tuning.h" #include "esp_flash.h" #include "riscv/rv_utils.h" @@ -417,4 +418,36 @@ esp_err_t _ss_spi_flash_chip_generic_config_host_io_mode(esp_flash_t *chip, uint { return spi_flash_chip_generic_config_host_io_mode(chip, flags); } + +#if CONFIG_IDF_TARGET_ESP32C5 +void _ss_mspi_timing_psram_tuning(void) +{ + mspi_timing_psram_tuning(); +} + +void _ss_mspi_timing_flash_tuning(void) +{ + mspi_timing_flash_tuning(); +} + +void _ss_mspi_timing_enter_low_speed_mode(bool control_spi1) +{ + mspi_timing_enter_low_speed_mode(control_spi1); +} + +void _ss_mspi_timing_enter_high_speed_mode(bool control_spi1) +{ + mspi_timing_enter_high_speed_mode(control_spi1); +} + +void _ss_mspi_timing_change_speed_mode_cache_safe(bool switch_down) +{ + mspi_timing_change_speed_mode_cache_safe(switch_down); +} + +void _ss_spi_timing_get_flash_timing_param(spi_flash_hal_timing_config_t *out_timing_config) +{ + spi_timing_get_flash_timing_param(out_timing_config); +} +#endif #endif