From 6afbc0666601883646306c48556a75409aa3f4dd Mon Sep 17 00:00:00 2001 From: Song Ruo Jing Date: Fri, 20 Sep 2024 12:09:06 +0800 Subject: [PATCH] feat(gdma): add retention support for esp32p4, esp32c5, esp32c61 --- components/esp_hw_support/CMakeLists.txt | 2 +- components/esp_hw_support/dma/gdma.c | 9 +- .../esp_hw_support/dma/gdma_sleep_retention.c | 11 +- .../dma/include/esp_private/gdma.h | 13 +- .../test_apps/dma/main/CMakeLists.txt | 20 +- .../test_apps/dma/main/gdma_test_utils.c | 36 +++ .../test_apps/dma/main/gdma_test_utils.h | 28 +++ .../test_apps/dma/main/test_gdma.c | 22 +- .../test_apps/dma/sdkconfig.ci.release | 3 + components/esp_system/port/soc/esp32c6/clk.c | 2 +- components/esp_system/port/soc/esp32h2/clk.c | 2 +- components/hal/esp32c2/include/hal/gdma_ll.h | 8 +- components/hal/esp32c3/include/hal/gdma_ll.h | 8 +- .../hal/esp32c5/include/hal/ahb_dma_ll.h | 3 - components/hal/esp32c5/include/hal/gdma_ll.h | 8 +- components/hal/esp32c6/include/hal/gdma_ll.h | 11 +- .../hal/esp32c61/include/hal/ahb_dma_ll.h | 3 - components/hal/esp32c61/include/hal/gdma_ll.h | 8 +- components/hal/esp32h2/include/hal/gdma_ll.h | 11 +- components/hal/esp32p4/include/hal/gdma_ll.h | 6 +- components/hal/esp32s3/include/hal/gdma_ll.h | 8 +- components/soc/esp32c5/gdma_periph.c | 88 ++++--- .../esp32c5/include/soc/Kconfig.soc_caps.in | 4 + components/soc/esp32c5/include/soc/soc_caps.h | 2 +- components/soc/esp32c6/gdma_periph.c | 26 +- components/soc/esp32c61/gdma_periph.c | 83 ++++++ .../esp32c61/include/soc/Kconfig.soc_caps.in | 4 + .../soc/esp32c61/include/soc/reg_base.h | 2 +- .../include/soc/retention_periph_defs.h | 3 - .../soc/esp32c61/include/soc/soc_caps.h | 5 +- components/soc/esp32h2/gdma_periph.c | 26 +- components/soc/esp32p4/gdma_periph.c | 236 +++++++++++++++++- .../esp32p4/include/soc/Kconfig.soc_caps.in | 8 + .../include/soc/retention_periph_defs.h | 22 ++ components/soc/esp32p4/include/soc/soc_caps.h | 3 +- components/soc/include/soc/gdma_periph.h | 18 +- 36 files changed, 624 insertions(+), 128 deletions(-) create mode 100644 components/esp_hw_support/test_apps/dma/main/gdma_test_utils.c create mode 100644 components/esp_hw_support/test_apps/dma/main/gdma_test_utils.h diff --git a/components/esp_hw_support/CMakeLists.txt b/components/esp_hw_support/CMakeLists.txt index cadb4762a7..e1b6efc00d 100644 --- a/components/esp_hw_support/CMakeLists.txt +++ b/components/esp_hw_support/CMakeLists.txt @@ -73,7 +73,7 @@ if(NOT BOOTLOADER_BUILD) if(CONFIG_SOC_GDMA_SUPPORTED) list(APPEND srcs "dma/gdma.c" "deprecated/gdma_legacy.c") - if(CONFIG_SOC_GDMA_SUPPORT_SLEEP_RETENTION) + if(CONFIG_SOC_GDMA_SUPPORT_SLEEP_RETENTION AND CONFIG_SOC_PAU_SUPPORTED) list(APPEND srcs "dma/gdma_sleep_retention.c") endif() if(CONFIG_SOC_GDMA_SUPPORT_ETM) diff --git a/components/esp_hw_support/dma/gdma.c b/components/esp_hw_support/dma/gdma.c index 9e179e7e65..9d847dd9e4 100644 --- a/components/esp_hw_support/dma/gdma.c +++ b/components/esp_hw_support/dma/gdma.c @@ -255,13 +255,18 @@ esp_err_t gdma_del_channel(gdma_channel_handle_t dma_chan) return dma_chan->del(dma_chan); } -esp_err_t gdma_get_channel_id(gdma_channel_handle_t dma_chan, int *channel_id) +esp_err_t gdma_get_group_channel_id(gdma_channel_handle_t dma_chan, int *group_id, int *channel_id) { esp_err_t ret = ESP_OK; gdma_pair_t *pair = NULL; ESP_GOTO_ON_FALSE(dma_chan, ESP_ERR_INVALID_ARG, err, TAG, "invalid argument"); pair = dma_chan->pair; - *channel_id = pair->pair_id; + if (group_id != NULL) { + *group_id = pair->group->group_id; + } + if (channel_id != NULL) { + *channel_id = pair->pair_id; + } err: return ret; } diff --git a/components/esp_hw_support/dma/gdma_sleep_retention.c b/components/esp_hw_support/dma/gdma_sleep_retention.c index 00f3a75445..31b6ba09a5 100644 --- a/components/esp_hw_support/dma/gdma_sleep_retention.c +++ b/components/esp_hw_support/dma/gdma_sleep_retention.c @@ -21,8 +21,6 @@ #include "esp_private/sleep_retention.h" #include "esp_private/esp_regdma.h" -#include "hal/gdma_ll.h" - static const char *TAG = "gdma"; typedef struct { @@ -36,7 +34,7 @@ static esp_err_t sleep_gdma_channel_retention_init(void *arg) int group_id = parg->group_id; int pair_id = parg->pair_id; - sleep_retention_module_bitmap_t module = GDMA_CH_RETENTION_GET_MODULE_ID(group_id, pair_id); + sleep_retention_module_t module = gdma_chx_regs_retention[group_id][pair_id].module_id; esp_err_t err = sleep_retention_entries_create(gdma_chx_regs_retention[group_id][pair_id].link_list, gdma_chx_regs_retention[group_id][pair_id].link_num, REGDMA_LINK_PRI_GDMA, module); if (err == ESP_OK) { ESP_LOGD(TAG, "GDMA pair (%d, %d) retention initialization", group_id, pair_id); @@ -53,7 +51,7 @@ esp_err_t gdma_sleep_retention_init(int group_id, int pair_id) .cbs = { .create = { .handle = sleep_gdma_channel_retention_init, .arg = &arg } }, .depends = BIT(SLEEP_RETENTION_MODULE_CLOCK_SYSTEM) }; - sleep_retention_module_bitmap_t module = GDMA_CH_RETENTION_GET_MODULE_ID(group_id, pair_id); + sleep_retention_module_t module = gdma_chx_regs_retention[group_id][pair_id].module_id; esp_err_t err = sleep_retention_module_init(module, &init_param); if (err == ESP_OK) { err = sleep_retention_module_allocate(module); @@ -66,11 +64,12 @@ esp_err_t gdma_sleep_retention_init(int group_id, int pair_id) esp_err_t gdma_sleep_retention_deinit(int group_id, int pair_id) { - esp_err_t err = sleep_retention_module_free(GDMA_CH_RETENTION_GET_MODULE_ID(group_id, pair_id)); + sleep_retention_module_t module = gdma_chx_regs_retention[group_id][pair_id].module_id; + esp_err_t err = sleep_retention_module_free(module); if (err != ESP_OK) { ESP_LOGW(TAG, "GDMA pair (%d, %d) retention destroy failed", group_id, pair_id); } - err = sleep_retention_module_deinit(GDMA_CH_RETENTION_GET_MODULE_ID(group_id, pair_id)); + err = sleep_retention_module_deinit(module); if (err != ESP_OK) { ESP_LOGW(TAG, "GDMA pair (%d, %d) retention deinit failed", group_id, pair_id); } diff --git a/components/esp_hw_support/dma/include/esp_private/gdma.h b/components/esp_hw_support/dma/include/esp_private/gdma.h index 778f87a2bb..22868fa3bd 100644 --- a/components/esp_hw_support/dma/include/esp_private/gdma.h +++ b/components/esp_hw_support/dma/include/esp_private/gdma.h @@ -249,19 +249,22 @@ esp_err_t gdma_set_priority(gdma_channel_handle_t dma_chan, uint32_t priority); esp_err_t gdma_del_channel(gdma_channel_handle_t dma_chan); /** - * @brief Get the channel ID + * @brief Get the group ID and the channel ID * * @note This API breaks the encapsulation of GDMA Channel Object. - * With the returned channel ID, you can even bypass all other GDMA driver API and access Low Level API directly. + * With the returned group/channel ID, you can even bypass all other GDMA driver API and access Low Level API directly. * * @param[in] dma_chan GDMA channel handle, allocated by `gdma_new_channel` + * @param[out] group_id Returned group ID * @param[out] channel_id Returned channel ID * @return - * - ESP_OK: Get GDMA channel ID successfully - * - ESP_ERR_INVALID_ARG: Get GDMA channel ID failed because of invalid argument + * - ESP_OK: Get GDMA channel/group ID successfully + * - ESP_ERR_INVALID_ARG: Get GDMA channel/group ID failed because of invalid argument * - ESP_FAIL: Get GDMA channel ID failed because of other error */ -esp_err_t gdma_get_channel_id(gdma_channel_handle_t dma_chan, int *channel_id); +esp_err_t gdma_get_group_channel_id(gdma_channel_handle_t dma_chan, int *group_id, int *channel_id); + +#define gdma_get_channel_id(dma_chan, channel_id) gdma_get_group_channel_id(dma_chan, NULL, channel_id) /** * @brief Set GDMA event callbacks for TX channel diff --git a/components/esp_hw_support/test_apps/dma/main/CMakeLists.txt b/components/esp_hw_support/test_apps/dma/main/CMakeLists.txt index 643898bfb5..1037b2c348 100644 --- a/components/esp_hw_support/test_apps/dma/main/CMakeLists.txt +++ b/components/esp_hw_support/test_apps/dma/main/CMakeLists.txt @@ -5,23 +5,27 @@ if(CONFIG_SOC_ASYNC_MEMCPY_SUPPORTED) endif() if(CONFIG_SOC_GDMA_SUPPORTED) - list(APPEND srcs "test_gdma.c") -endif() + list(APPEND srcs "test_gdma.c" "gdma_test_utils.c") -if(CONFIG_SOC_ETM_SUPPORTED AND CONFIG_SOC_GDMA_SUPPORT_ETM) - list(APPEND srcs "test_gdma_etm.c") + if(CONFIG_SOC_ETM_SUPPORTED AND CONFIG_SOC_GDMA_SUPPORT_ETM) + list(APPEND srcs "test_gdma_etm.c") + endif() + + if(CONFIG_SOC_GDMA_SUPPORT_CRC) + list(APPEND srcs "test_gdma_crc.c") + endif() endif() if(CONFIG_SOC_DW_GDMA_SUPPORTED) list(APPEND srcs "test_dw_gdma.c") endif() -if(CONFIG_SOC_GDMA_SUPPORT_CRC) - list(APPEND srcs "test_gdma_crc.c") -endif() - # In order for the cases defined by `TEST_CASE` to be linked into the final elf, # the component can be registered as WHOLE_ARCHIVE idf_component_register(SRCS ${srcs} PRIV_REQUIRES unity esp_mm esp_driver_gpio WHOLE_ARCHIVE) + +idf_component_get_property(lib_name soc COMPONENT_LIB) +# Test GDMA retention correctness with software retention feature +target_compile_definitions(${lib_name} PRIVATE "CI_TEST_SW_RETENTION=1") diff --git a/components/esp_hw_support/test_apps/dma/main/gdma_test_utils.c b/components/esp_hw_support/test_apps/dma/main/gdma_test_utils.c new file mode 100644 index 0000000000..ab39688f22 --- /dev/null +++ b/components/esp_hw_support/test_apps/dma/main/gdma_test_utils.c @@ -0,0 +1,36 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "freertos/FreeRTOS.h" +#include "freertos/task.h" +#include "soc/soc_caps.h" +#include "gdma_test_utils.h" +#include "esp_private/sleep_retention.h" +#include "hal/gdma_ll.h" + +void test_gdma_trigger_retention_backup(gdma_channel_handle_t chan, ...) +{ +#if SOC_PAU_SUPPORTED && SOC_GDMA_SUPPORT_SLEEP_RETENTION + // trigger a software retention to test GDMA retention correctnesss + // 1. backup gdma register context + sleep_retention_do_extra_retention(true); + + // 2. reset gdma registers to default value + gdma_channel_handle_t chan_itor = chan; + va_list args; + int group_id = -1; + va_start(args, chan); + while (chan_itor) { + gdma_get_group_channel_id(chan_itor, &group_id, NULL); + _gdma_ll_reset_register(group_id); + chan_itor = va_arg(args, gdma_channel_handle_t); + } + va_end(args); + + // 3. restore gdma register context + sleep_retention_do_extra_retention(false); +#endif + vTaskDelay(pdMS_TO_TICKS(10)); +} diff --git a/components/esp_hw_support/test_apps/dma/main/gdma_test_utils.h b/components/esp_hw_support/test_apps/dma/main/gdma_test_utils.h new file mode 100644 index 0000000000..b8ddac4d80 --- /dev/null +++ b/components/esp_hw_support/test_apps/dma/main/gdma_test_utils.h @@ -0,0 +1,28 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include "esp_private/gdma.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Trigger a "fake" sleep retention process. + * + * @note Call this help function after the gdma set up is completed. Then check the gdma functionality is still working. + * + * @param chan GDMA channel handle to be reset + * @param ... Other GDMA channel handle if any + */ +void test_gdma_trigger_retention_backup(gdma_channel_handle_t chan, ...); + +#ifdef __cplusplus +} +#endif diff --git a/components/esp_hw_support/test_apps/dma/main/test_gdma.c b/components/esp_hw_support/test_apps/dma/main/test_gdma.c index abaf59a7ed..14ae6f12fb 100644 --- a/components/esp_hw_support/test_apps/dma/main/test_gdma.c +++ b/components/esp_hw_support/test_apps/dma/main/test_gdma.c @@ -22,6 +22,7 @@ #include "hal/cache_hal.h" #include "esp_cache.h" #include "esp_memory_utils.h" +#include "gdma_test_utils.h" #define ALIGN_UP(num, align) (((num) + ((align) - 1)) & ~((align) - 1)) #define ALIGN_DOWN(num, align) ((num) & ~((align) - 1)) @@ -202,7 +203,7 @@ static bool test_gdma_m2m_rx_eof_callback(gdma_channel_handle_t dma_chan, gdma_e return task_woken == pdTRUE; } -static void test_gdma_m2m_mode(gdma_channel_handle_t tx_chan, gdma_channel_handle_t rx_chan, bool dma_link_in_ext_mem) +static void test_gdma_m2m_transaction(gdma_channel_handle_t tx_chan, gdma_channel_handle_t rx_chan, bool dma_link_in_ext_mem, bool trig_retention_backup) { size_t sram_alignment = cache_hal_get_cache_line_size(CACHE_LL_LEVEL_INT_MEM, CACHE_TYPE_DATA); gdma_rx_event_callbacks_t rx_cbs = { @@ -280,6 +281,10 @@ static void test_gdma_m2m_mode(gdma_channel_handle_t tx_chan, gdma_channel_handl }; TEST_ESP_OK(gdma_link_mount_buffers(rx_link_list, 0, &rx_buf_mount_config, 1, NULL)); + if (trig_retention_backup) { + test_gdma_trigger_retention_backup(tx_chan, rx_chan); + } + TEST_ESP_OK(gdma_start(rx_chan, gdma_link_get_head_addr(rx_link_list))); TEST_ESP_OK(gdma_start(tx_chan, gdma_link_get_head_addr(tx_link_list))); @@ -313,7 +318,7 @@ static void test_gdma_m2m_mode(gdma_channel_handle_t tx_chan, gdma_channel_handl vSemaphoreDelete(done_sem); } -TEST_CASE("GDMA M2M Mode", "[GDMA][M2M]") +static void test_gdma_m2m_mode(bool trig_retention_backup) { gdma_channel_handle_t tx_chan = NULL; gdma_channel_handle_t rx_chan = NULL; @@ -332,7 +337,7 @@ TEST_CASE("GDMA M2M Mode", "[GDMA][M2M]") }; TEST_ESP_OK(gdma_new_ahb_channel(&rx_chan_alloc_config, &rx_chan)); - test_gdma_m2m_mode(tx_chan, rx_chan, false); + test_gdma_m2m_transaction(tx_chan, rx_chan, false, trig_retention_backup); TEST_ESP_OK(gdma_del_channel(tx_chan)); TEST_ESP_OK(gdma_del_channel(rx_chan)); @@ -351,13 +356,22 @@ TEST_CASE("GDMA M2M Mode", "[GDMA][M2M]") TEST_ESP_OK(gdma_new_axi_channel(&rx_chan_alloc_config, &rx_chan)); // the AXI GDMA allows to put the DMA link list in the external memory - test_gdma_m2m_mode(tx_chan, rx_chan, true); + test_gdma_m2m_transaction(tx_chan, rx_chan, true, trig_retention_backup); TEST_ESP_OK(gdma_del_channel(tx_chan)); TEST_ESP_OK(gdma_del_channel(rx_chan)); #endif // SOC_AXI_GDMA_SUPPORTED } +TEST_CASE("GDMA M2M Mode", "[GDMA][M2M]") +{ + test_gdma_m2m_mode(false); +#if SOC_GDMA_SUPPORT_SLEEP_RETENTION + // test again with retention + test_gdma_m2m_mode(true); +#endif +} + typedef struct { SemaphoreHandle_t done_sem; dma_buffer_split_array_t *align_array; diff --git a/components/esp_hw_support/test_apps/dma/sdkconfig.ci.release b/components/esp_hw_support/test_apps/dma/sdkconfig.ci.release index 8b0a31a9bc..521e7decae 100644 --- a/components/esp_hw_support/test_apps/dma/sdkconfig.ci.release +++ b/components/esp_hw_support/test_apps/dma/sdkconfig.ci.release @@ -4,3 +4,6 @@ CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE=y # we can silent the assertion to save the binary footprint CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_SILENT=y + +# enable the option to test retention correctness +CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP=y diff --git a/components/esp_system/port/soc/esp32c6/clk.c b/components/esp_system/port/soc/esp32c6/clk.c index 6ac2ff9553..23a8ddab32 100644 --- a/components/esp_system/port/soc/esp32c6/clk.c +++ b/components/esp_system/port/soc/esp32c6/clk.c @@ -264,7 +264,7 @@ __attribute__((weak)) void esp_perip_clk_init(void) parlio_ll_tx_enable_clock(&PARL_IO, false); parlio_ll_enable_bus_clock(0, false); gdma_ll_force_enable_reg_clock(&GDMA, false); - gdma_ll_enable_bus_clock(0, false); + _gdma_ll_enable_bus_clock(0, false); #if CONFIG_APP_BUILD_TYPE_PURE_RAM_APP spi_ll_enable_bus_clock(SPI1_HOST, false); #endif diff --git a/components/esp_system/port/soc/esp32h2/clk.c b/components/esp_system/port/soc/esp32h2/clk.c index d012e3e00a..02aa13411a 100644 --- a/components/esp_system/port/soc/esp32h2/clk.c +++ b/components/esp_system/port/soc/esp32h2/clk.c @@ -252,7 +252,7 @@ __attribute__((weak)) void esp_perip_clk_init(void) parlio_ll_tx_enable_clock(&PARL_IO, false); parlio_ll_enable_bus_clock(0, false); gdma_ll_force_enable_reg_clock(&GDMA, false); - gdma_ll_enable_bus_clock(0, false); + _gdma_ll_enable_bus_clock(0, false); #if CONFIG_APP_BUILD_TYPE_PURE_RAM_APP spi_ll_enable_bus_clock(SPI1_HOST, false); #endif diff --git a/components/hal/esp32c2/include/hal/gdma_ll.h b/components/hal/esp32c2/include/hal/gdma_ll.h index 37d7179c68..ee877d5b3e 100644 --- a/components/hal/esp32c2/include/hal/gdma_ll.h +++ b/components/hal/esp32c2/include/hal/gdma_ll.h @@ -55,7 +55,7 @@ extern "C" { /** * @brief Enable the bus clock for the DMA module */ -static inline void gdma_ll_enable_bus_clock(int group_id, bool enable) +static inline void _gdma_ll_enable_bus_clock(int group_id, bool enable) { (void)group_id; SYSTEM.perip_clk_en1.dma_clk_en = enable; @@ -63,12 +63,12 @@ static inline void gdma_ll_enable_bus_clock(int group_id, bool enable) /// use a macro to wrap the function, force the caller to use it in a critical section /// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance -#define gdma_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; gdma_ll_enable_bus_clock(__VA_ARGS__) +#define gdma_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; _gdma_ll_enable_bus_clock(__VA_ARGS__) /** * @brief Reset the DMA module */ -static inline void gdma_ll_reset_register(int group_id) +static inline void _gdma_ll_reset_register(int group_id) { (void)group_id; SYSTEM.perip_rst_en1.dma_rst = 1; @@ -77,7 +77,7 @@ static inline void gdma_ll_reset_register(int group_id) /// use a macro to wrap the function, force the caller to use it in a critical section /// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance -#define gdma_ll_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; gdma_ll_reset_register(__VA_ARGS__) +#define gdma_ll_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; _gdma_ll_reset_register(__VA_ARGS__) /** * @brief Force enable register clock diff --git a/components/hal/esp32c3/include/hal/gdma_ll.h b/components/hal/esp32c3/include/hal/gdma_ll.h index e11d1fbc49..f7b3147e4d 100644 --- a/components/hal/esp32c3/include/hal/gdma_ll.h +++ b/components/hal/esp32c3/include/hal/gdma_ll.h @@ -55,7 +55,7 @@ extern "C" { /** * @brief Enable the bus clock for the DMA module */ -static inline void gdma_ll_enable_bus_clock(int group_id, bool enable) +static inline void _gdma_ll_enable_bus_clock(int group_id, bool enable) { (void)group_id; SYSTEM.perip_clk_en1.reg_dma_clk_en = enable; @@ -63,12 +63,12 @@ static inline void gdma_ll_enable_bus_clock(int group_id, bool enable) /// use a macro to wrap the function, force the caller to use it in a critical section /// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance -#define gdma_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; gdma_ll_enable_bus_clock(__VA_ARGS__) +#define gdma_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; _gdma_ll_enable_bus_clock(__VA_ARGS__) /** * @brief Reset the DMA module */ -static inline void gdma_ll_reset_register(int group_id) +static inline void _gdma_ll_reset_register(int group_id) { (void)group_id; SYSTEM.perip_rst_en1.reg_dma_rst = 1; @@ -77,7 +77,7 @@ static inline void gdma_ll_reset_register(int group_id) /// use a macro to wrap the function, force the caller to use it in a critical section /// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance -#define gdma_ll_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; gdma_ll_reset_register(__VA_ARGS__) +#define gdma_ll_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; _gdma_ll_reset_register(__VA_ARGS__) /** * @brief Force enable register clock diff --git a/components/hal/esp32c5/include/hal/ahb_dma_ll.h b/components/hal/esp32c5/include/hal/ahb_dma_ll.h index fc67d245bc..b9a0c74bad 100644 --- a/components/hal/esp32c5/include/hal/ahb_dma_ll.h +++ b/components/hal/esp32c5/include/hal/ahb_dma_ll.h @@ -14,14 +14,11 @@ #include "soc/ahb_dma_struct.h" #include "soc/ahb_dma_reg.h" #include "soc/soc_etm_source.h" -#include "soc/retention_periph_defs.h" #ifdef __cplusplus extern "C" { #endif -#define GDMA_CH_RETENTION_GET_MODULE_ID(group_id, pair_id) (SLEEP_RETENTION_MODULE_GDMA_CH0 << (SOC_GDMA_PAIRS_PER_GROUP_MAX * group_id) << pair_id) - #define AHB_DMA_LL_GET_HW(id) (((id) == 0) ? (&AHB_DMA) : NULL) #define GDMA_LL_CHANNEL_MAX_PRIORITY 5 // supported priority levels: [0,5] diff --git a/components/hal/esp32c5/include/hal/gdma_ll.h b/components/hal/esp32c5/include/hal/gdma_ll.h index 4a43d3374a..f167217769 100644 --- a/components/hal/esp32c5/include/hal/gdma_ll.h +++ b/components/hal/esp32c5/include/hal/gdma_ll.h @@ -16,22 +16,26 @@ extern "C" { /** * @brief Enable the bus clock for the DMA module */ -static inline void gdma_ll_enable_bus_clock(int group_id, bool enable) +static inline void _gdma_ll_enable_bus_clock(int group_id, bool enable) { (void)group_id; PCR.gdma_conf.gdma_clk_en = enable; } +#define gdma_ll_enable_bus_clock(...) _gdma_ll_enable_bus_clock(__VA_ARGS__) + /** * @brief Reset the DMA module */ -static inline void gdma_ll_reset_register(int group_id) +static inline void _gdma_ll_reset_register(int group_id) { (void)group_id; PCR.gdma_conf.gdma_rst_en = 1; PCR.gdma_conf.gdma_rst_en = 0; } +#define gdma_ll_reset_register(...) _gdma_ll_reset_register(__VA_ARGS__) + #ifdef __cplusplus } #endif diff --git a/components/hal/esp32c6/include/hal/gdma_ll.h b/components/hal/esp32c6/include/hal/gdma_ll.h index 2a168bb692..5a1d8d2417 100644 --- a/components/hal/esp32c6/include/hal/gdma_ll.h +++ b/components/hal/esp32c6/include/hal/gdma_ll.h @@ -13,14 +13,11 @@ #include "soc/gdma_reg.h" #include "soc/soc_etm_source.h" #include "soc/pcr_struct.h" -#include "soc/retention_periph_defs.h" #ifdef __cplusplus extern "C" { #endif -#define GDMA_CH_RETENTION_GET_MODULE_ID(group_id, pair_id) (SLEEP_RETENTION_MODULE_GDMA_CH0 + (SOC_GDMA_PAIRS_PER_GROUP_MAX * group_id) + pair_id) - #define GDMA_LL_GET_HW(id) (((id) == 0) ? (&GDMA) : NULL) #define GDMA_LL_CHANNEL_MAX_PRIORITY 5 // supported priority levels: [0,5] @@ -102,22 +99,26 @@ extern "C" { /** * @brief Enable the bus clock for the DMA module */ -static inline void gdma_ll_enable_bus_clock(int group_id, bool enable) +static inline void _gdma_ll_enable_bus_clock(int group_id, bool enable) { (void)group_id; PCR.gdma_conf.gdma_clk_en = enable; } +#define gdma_ll_enable_bus_clock(...) _gdma_ll_enable_bus_clock(__VA_ARGS__) + /** * @brief Reset the DMA module */ -static inline void gdma_ll_reset_register(int group_id) +static inline void _gdma_ll_reset_register(int group_id) { (void)group_id; PCR.gdma_conf.gdma_rst_en = 1; PCR.gdma_conf.gdma_rst_en = 0; } +#define gdma_ll_reset_register(...) _gdma_ll_reset_register(__VA_ARGS__) + /** * @brief Force enable register clock */ diff --git a/components/hal/esp32c61/include/hal/ahb_dma_ll.h b/components/hal/esp32c61/include/hal/ahb_dma_ll.h index bd7a1c46a4..943f18d36f 100644 --- a/components/hal/esp32c61/include/hal/ahb_dma_ll.h +++ b/components/hal/esp32c61/include/hal/ahb_dma_ll.h @@ -14,14 +14,11 @@ #include "soc/ahb_dma_struct.h" #include "soc/ahb_dma_reg.h" #include "soc/soc_etm_source.h" -#include "soc/retention_periph_defs.h" #ifdef __cplusplus extern "C" { #endif -#define GDMA_CH_RETENTION_GET_MODULE_ID(group_id, pair_id) (SLEEP_RETENTION_MODULE_GDMA_CH0 << (SOC_GDMA_PAIRS_PER_GROUP_MAX * group_id) << pair_id) - #define AHB_DMA_LL_GET_HW(id) (((id) == 0) ? (&AHB_DMA) : NULL) #define GDMA_LL_CHANNEL_MAX_PRIORITY 5 // supported priority levels: [0,5] diff --git a/components/hal/esp32c61/include/hal/gdma_ll.h b/components/hal/esp32c61/include/hal/gdma_ll.h index 6f61062936..5dfa8e31af 100644 --- a/components/hal/esp32c61/include/hal/gdma_ll.h +++ b/components/hal/esp32c61/include/hal/gdma_ll.h @@ -17,22 +17,26 @@ extern "C" { /** * @brief Enable the bus clock for the DMA module */ -static inline void gdma_ll_enable_bus_clock(int group_id, bool enable) +static inline void _gdma_ll_enable_bus_clock(int group_id, bool enable) { (void)group_id; PCR.gdma_conf.gdma_clk_en = enable; } +#define gdma_ll_enable_bus_clock(...) _gdma_ll_enable_bus_clock(__VA_ARGS__) + /** * @brief Reset the DMA module */ -static inline void gdma_ll_reset_register(int group_id) +static inline void _gdma_ll_reset_register(int group_id) { (void)group_id; PCR.gdma_conf.gdma_rst_en = 1; PCR.gdma_conf.gdma_rst_en = 0; } +#define gdma_ll_reset_register(...) _gdma_ll_reset_register(__VA_ARGS__) + #ifdef __cplusplus } #endif diff --git a/components/hal/esp32h2/include/hal/gdma_ll.h b/components/hal/esp32h2/include/hal/gdma_ll.h index 2a168bb692..5a1d8d2417 100644 --- a/components/hal/esp32h2/include/hal/gdma_ll.h +++ b/components/hal/esp32h2/include/hal/gdma_ll.h @@ -13,14 +13,11 @@ #include "soc/gdma_reg.h" #include "soc/soc_etm_source.h" #include "soc/pcr_struct.h" -#include "soc/retention_periph_defs.h" #ifdef __cplusplus extern "C" { #endif -#define GDMA_CH_RETENTION_GET_MODULE_ID(group_id, pair_id) (SLEEP_RETENTION_MODULE_GDMA_CH0 + (SOC_GDMA_PAIRS_PER_GROUP_MAX * group_id) + pair_id) - #define GDMA_LL_GET_HW(id) (((id) == 0) ? (&GDMA) : NULL) #define GDMA_LL_CHANNEL_MAX_PRIORITY 5 // supported priority levels: [0,5] @@ -102,22 +99,26 @@ extern "C" { /** * @brief Enable the bus clock for the DMA module */ -static inline void gdma_ll_enable_bus_clock(int group_id, bool enable) +static inline void _gdma_ll_enable_bus_clock(int group_id, bool enable) { (void)group_id; PCR.gdma_conf.gdma_clk_en = enable; } +#define gdma_ll_enable_bus_clock(...) _gdma_ll_enable_bus_clock(__VA_ARGS__) + /** * @brief Reset the DMA module */ -static inline void gdma_ll_reset_register(int group_id) +static inline void _gdma_ll_reset_register(int group_id) { (void)group_id; PCR.gdma_conf.gdma_rst_en = 1; PCR.gdma_conf.gdma_rst_en = 0; } +#define gdma_ll_reset_register(...) _gdma_ll_reset_register(__VA_ARGS__) + /** * @brief Force enable register clock */ diff --git a/components/hal/esp32p4/include/hal/gdma_ll.h b/components/hal/esp32p4/include/hal/gdma_ll.h index 055b643664..a3e9e38fed 100644 --- a/components/hal/esp32p4/include/hal/gdma_ll.h +++ b/components/hal/esp32p4/include/hal/gdma_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -111,7 +111,7 @@ static inline void _gdma_ll_enable_bus_clock(int group_id, bool enable) /** * @brief Reset the DMA module */ -static inline void gdma_ll_reset_register(int group_id) +static inline void _gdma_ll_reset_register(int group_id) { if (group_id == 0) { HP_SYS_CLKRST.hp_rst_en1.reg_rst_en_ahb_pdma = 1; @@ -124,7 +124,7 @@ static inline void gdma_ll_reset_register(int group_id) /// use a macro to wrap the function, force the caller to use it in a critical section /// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance -#define gdma_ll_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; gdma_ll_reset_register(__VA_ARGS__) +#define gdma_ll_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; _gdma_ll_reset_register(__VA_ARGS__) #ifdef __cplusplus } diff --git a/components/hal/esp32s3/include/hal/gdma_ll.h b/components/hal/esp32s3/include/hal/gdma_ll.h index 33c5c934eb..c232966ca5 100644 --- a/components/hal/esp32s3/include/hal/gdma_ll.h +++ b/components/hal/esp32s3/include/hal/gdma_ll.h @@ -70,7 +70,7 @@ extern "C" { /** * @brief Enable the bus clock for the DMA module */ -static inline void gdma_ll_enable_bus_clock(int group_id, bool enable) +static inline void _gdma_ll_enable_bus_clock(int group_id, bool enable) { (void)group_id; SYSTEM.perip_clk_en1.dma_clk_en = enable; @@ -78,12 +78,12 @@ static inline void gdma_ll_enable_bus_clock(int group_id, bool enable) /// use a macro to wrap the function, force the caller to use it in a critical section /// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance -#define gdma_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; gdma_ll_enable_bus_clock(__VA_ARGS__) +#define gdma_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; _gdma_ll_enable_bus_clock(__VA_ARGS__) /** * @brief Reset the DMA module */ -static inline void gdma_ll_reset_register(int group_id) +static inline void _gdma_ll_reset_register(int group_id) { (void)group_id; SYSTEM.perip_rst_en1.dma_rst = 1; @@ -92,7 +92,7 @@ static inline void gdma_ll_reset_register(int group_id) /// use a macro to wrap the function, force the caller to use it in a critical section /// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance -#define gdma_ll_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; gdma_ll_reset_register(__VA_ARGS__) +#define gdma_ll_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; _gdma_ll_reset_register(__VA_ARGS__) /** * @brief Force enable register clock diff --git a/components/soc/esp32c5/gdma_periph.c b/components/soc/esp32c5/gdma_periph.c index 9385a76ed5..ee82803157 100644 --- a/components/soc/esp32c5/gdma_periph.c +++ b/components/soc/esp32c5/gdma_periph.c @@ -29,12 +29,11 @@ const gdma_signal_conn_t gdma_periph_signals = { } }; -#if SOC_GDMA_SUPPORT_SLEEP_RETENTION -/* GDMA Channel (Group0, Pair0) Registers Context - Include: GDMA_MISC_CONF_REG - GDMA_IN_INT_ENA_CH0_REG / GDMA_OUT_INT_ENA_CH0_REG / GDMA_IN_PERI_SEL_CH0_REG / GDMA_OUT_PERI_SEL_CH0_REG - GDMA_IN_CONF0_CH0_REG / GDMA_IN_CONF1_CH0_REG / GDMA_IN_LINK_CH0_REG / GDMA_IN_PRI_CH0_REG - GDMA_OUT_CONF0_CH0_REG / GDMA_OUT_CONF1_CH0_REG / GDMA_OUT_LINK_CH0_REG /GDMA_OUT_PRI_CH0_REG +/* AHB_DMA Channel (Group0, Pair0) Registers Context + Include: AHB_DMA_MISC_CONF_REG + AHB_DMA_IN_INT_ENA_CH0_REG / AHB_DMA_OUT_INT_ENA_CH0_REG / AHB_DMA_IN_PERI_SEL_CH0_REG / AHB_DMA_OUT_PERI_SEL_CH0_REG + AHB_DMA_IN_CONF0_CH0_REG / AHB_DMA_IN_CONF1_CH0_REG / AHB_DMA_IN_LINK_CH0_REG / AHB_DMA_IN_PRI_CH0_REG + AHB_DMA_OUT_CONF0_CH0_REG / AHB_DMA_OUT_CONF1_CH0_REG / AHB_DMA_OUT_LINK_CH0_REG / AHB_DMA_OUT_PRI_CH0_REG AHB_DMA_TX_CH_ARB_WEIGH_CH0_REG / AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH0_REG AHB_DMA_RX_CH_ARB_WEIGH_CH0_REG / AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH0_REG @@ -44,31 +43,31 @@ const gdma_signal_conn_t gdma_periph_signals = { AHB_DMA_WEIGHT_EN_TX_REG / AHB_DMA_WEIGHT_EN_RX_REG */ #define G0P0_RETENTION_REGS_CNT_0 13 -#define G0P0_RETENTION_MAP_BASE_0 (REG_AHB_DMA_BASE + 0x8) +#define G0P0_RETENTION_MAP_BASE_0 (DR_REG_AHB_DMA_BASE + 0x8) #define G0P0_RETENTION_REGS_CNT_1 12 -#define G0P0_RETENTION_MAP_BASE_1 (REG_AHB_DMA_BASE + 0x2dc) +#define G0P0_RETENTION_MAP_BASE_1 (DR_REG_AHB_DMA_BASE + 0x2dc) static const uint32_t g0p0_regs_map0[4] = {0x4c801001, 0x604c0060, 0x0, 0x0}; static const uint32_t g0p0_regs_map1[4] = {0xc0000003, 0xfc900000, 0x0, 0x0}; static const regdma_entries_config_t gdma_g0p0_regs_retention[] = { - [0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \ + [0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \ G0P0_RETENTION_MAP_BASE_0, G0P0_RETENTION_MAP_BASE_0, \ G0P0_RETENTION_REGS_CNT_0, 0, 0, \ g0p0_regs_map0[0], g0p0_regs_map0[1], \ g0p0_regs_map0[2], g0p0_regs_map0[3]), \ - .owner = ENTRY(0) | ENTRY(2) }, \ - [1] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x01), \ + .owner = GDMA_RETENTION_ENTRY }, \ + [1] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \ G0P0_RETENTION_MAP_BASE_1, G0P0_RETENTION_MAP_BASE_1, \ G0P0_RETENTION_REGS_CNT_1, 0, 0, \ g0p0_regs_map1[0], g0p0_regs_map1[1], \ g0p0_regs_map1[2], g0p0_regs_map1[3]), \ - .owner = ENTRY(0) | ENTRY(2) }, + .owner = GDMA_RETENTION_ENTRY }, }; -/* GDMA Channel (Group0, Pair1) Registers Context - Include: GDMA_MISC_CONF_REG - GDMA_IN_INT_ENA_CH1_REG / GDMA_OUT_INT_ENA_CH1_REG / GDMA_IN_PERI_SEL_CH1_REG / GDMA_OUT_PERI_SEL_CH1_REG - GDMA_IN_CONF0_CH1_REG / GDMA_IN_CONF1_CH1_REG / GDMA_IN_LINK_CH1_REG / GDMA_IN_PRI_CH1_REG - GDMA_OUT_CONF0_CH1_REG / GDMA_OUT_CONF1_CH1_REG / GDMA_OUT_LINK_CH1_REG /GDMA_OUT_PRI_CH1_REG +/* AHB_DMA Channel (Group0, Pair1) Registers Context + Include: AHB_DMA_MISC_CONF_REG + AHB_DMA_IN_INT_ENA_CH1_REG / AHB_DMA_OUT_INT_ENA_CH1_REG / AHB_DMA_IN_PERI_SEL_CH1_REG / AHB_DMA_OUT_PERI_SEL_CH1_REG + AHB_DMA_IN_CONF0_CH1_REG / AHB_DMA_IN_CONF1_CH1_REG / AHB_DMA_IN_LINK_CH1_REG / AHB_DMA_IN_PRI_CH1_REG + AHB_DMA_OUT_CONF0_CH1_REG / AHB_DMA_OUT_CONF1_CH1_REG / AHB_DMA_OUT_LINK_CH1_REG / AHB_DMA_OUT_PRI_CH1_REG AHB_DMA_TX_CH_ARB_WEIGH_CH1_REG / AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH1_REG AHB_DMA_RX_CH_ARB_WEIGH_CH1_REG / AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH1_REG @@ -78,33 +77,33 @@ static const regdma_entries_config_t gdma_g0p0_regs_retention[] = { AHB_DMA_WEIGHT_EN_TX_REG / AHB_DMA_WEIGHT_EN_RX_REG */ #define G0P1_RETENTION_REGS_CNT_0 13 -#define G0P1_RETENTION_MAP_BASE_0 (REG_AHB_DMA_BASE + 0x18) +#define G0P1_RETENTION_MAP_BASE_0 (DR_REG_AHB_DMA_BASE + 0x18) #define G0P1_RETENTION_REGS_CNT_1 12 -#define G0P1_RETENTION_MAP_BASE_1 (REG_AHB_DMA_BASE + 0x304) +#define G0P1_RETENTION_MAP_BASE_1 (DR_REG_AHB_DMA_BASE + 0x304) static const uint32_t g0p1_regs_map0[4] = {0x81001, 0x0, 0xc00604c0, 0x604}; static const uint32_t g0p1_regs_map1[4] = {0xc0000003, 0x3f4800, 0x0, 0x0}; static const regdma_entries_config_t gdma_g0p1_regs_retention[] = { - [0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \ + [0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \ G0P1_RETENTION_MAP_BASE_0, G0P1_RETENTION_MAP_BASE_0, \ G0P1_RETENTION_REGS_CNT_0, 0, 0, \ g0p1_regs_map0[0], g0p1_regs_map0[1], \ g0p1_regs_map0[2], g0p1_regs_map0[3]), \ - .owner = ENTRY(0) | ENTRY(2) }, - [1] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x01), \ + .owner = GDMA_RETENTION_ENTRY }, + [1] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \ G0P1_RETENTION_MAP_BASE_1, G0P1_RETENTION_MAP_BASE_1, \ G0P1_RETENTION_REGS_CNT_1, 0, 0, \ g0p1_regs_map1[0], g0p1_regs_map1[1], \ g0p1_regs_map1[2], g0p1_regs_map1[3]), \ - .owner = ENTRY(0) | ENTRY(2) }, + .owner = GDMA_RETENTION_ENTRY }, }; -/* GDMA Channel (Group0, Pair2) Registers Context - Include: GDMA_MISC_CONF_REG - GDMA_IN_INT_ENA_CH2_REG / GDMA_OUT_INT_ENA_CH2_REG +/* AHB_DMA Channel (Group0, Pair2) Registers Context + Include: AHB_DMA_MISC_CONF_REG + AHB_DMA_IN_INT_ENA_CH2_REG / AHB_DMA_OUT_INT_ENA_CH2_REG - GDMA_IN_PERI_SEL_CH2_REG / GDMA_OUT_PERI_SEL_CH2_REG - GDMA_IN_CONF0_CH2_REG / GDMA_IN_CONF1_CH2_REG / GDMA_IN_LINK_CH2_REG / GDMA_IN_PRI_CH2_REG - GDMA_OUT_CONF0_CH2_REG / GDMA_OUT_CONF1_CH2_REG / GDMA_OUT_LINK_CH2_REG /GDMA_OUT_PRI_CH2_REG + AHB_DMA_IN_PERI_SEL_CH2_REG / AHB_DMA_OUT_PERI_SEL_CH2_REG + AHB_DMA_IN_CONF0_CH2_REG / AHB_DMA_IN_CONF1_CH2_REG / AHB_DMA_IN_LINK_CH2_REG / AHB_DMA_IN_PRI_CH2_REG + AHB_DMA_OUT_CONF0_CH2_REG / AHB_DMA_OUT_CONF1_CH2_REG / AHB_DMA_OUT_LINK_CH2_REG / AHB_DMA_OUT_PRI_CH2_REG AHB_DMA_TX_CH_ARB_WEIGH_CH2_REG / AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH2_REG AHB_DMA_RX_CH_ARB_WEIGH_CH2_REG / AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH2_REG AHB_DMA_IN_LINK_ADDR_CH2_REG / AHB_DMA_OUT_LINK_ADDR_CH2_REG @@ -113,31 +112,42 @@ static const regdma_entries_config_t gdma_g0p1_regs_retention[] = { AHB_DMA_WEIGHT_EN_TX_REG / AHB_DMA_WEIGHT_EN_RX_REG */ #define G0P2_RETENTION_REGS_CNT_0 3 -#define G0P2_RETENTION_MAP_BASE_0 (REG_AHB_DMA_BASE + 0x28) +#define G0P2_RETENTION_MAP_BASE_0 (DR_REG_AHB_DMA_BASE + 0x28) #define G0P2_RETENTION_REGS_CNT_1 22 -#define G0P2_RETENTION_MAP_BASE_1 (REG_AHB_DMA_BASE + 0x1f0) +#define G0P2_RETENTION_MAP_BASE_1 (DR_REG_AHB_DMA_BASE + 0x1f0) static const uint32_t g0p2_regs_map0[4] = {0x9001, 0x0, 0x0, 0x0}; static const uint32_t g0p2_regs_map1[4] = {0x13001813, 0x18, 0x18000, 0x7f26000}; static const regdma_entries_config_t gdma_g0p2_regs_retention[] = { - [0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \ + [0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \ G0P2_RETENTION_MAP_BASE_0, G0P2_RETENTION_MAP_BASE_0, \ G0P2_RETENTION_REGS_CNT_0, 0, 0, \ g0p2_regs_map0[0], g0p2_regs_map0[1], \ g0p2_regs_map0[2], g0p2_regs_map0[3]), \ - .owner = ENTRY(0) | ENTRY(2) }, - [1] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x01), \ + .owner = GDMA_RETENTION_ENTRY }, + [1] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \ G0P2_RETENTION_MAP_BASE_1, G0P2_RETENTION_MAP_BASE_1, \ G0P2_RETENTION_REGS_CNT_1, 0, 0, \ g0p2_regs_map1[0], g0p2_regs_map1[1], \ g0p2_regs_map1[2], g0p2_regs_map1[3]), \ - .owner = ENTRY(0) | ENTRY(2) }, + .owner = GDMA_RETENTION_ENTRY }, }; const gdma_chx_reg_ctx_link_t gdma_chx_regs_retention[SOC_GDMA_NUM_GROUPS_MAX][SOC_GDMA_PAIRS_PER_GROUP_MAX] = { [0] = { - [0] = {gdma_g0p0_regs_retention, ARRAY_SIZE(gdma_g0p0_regs_retention)}, - [1] = {gdma_g0p1_regs_retention, ARRAY_SIZE(gdma_g0p1_regs_retention)}, - [2] = {gdma_g0p2_regs_retention, ARRAY_SIZE(gdma_g0p2_regs_retention)} + [0] = { + gdma_g0p0_regs_retention, + ARRAY_SIZE(gdma_g0p0_regs_retention), + SLEEP_RETENTION_MODULE_GDMA_CH0, + }, + [1] = { + gdma_g0p1_regs_retention, + ARRAY_SIZE(gdma_g0p1_regs_retention), + SLEEP_RETENTION_MODULE_GDMA_CH1, + }, + [2] = { + gdma_g0p2_regs_retention, + ARRAY_SIZE(gdma_g0p2_regs_retention), + SLEEP_RETENTION_MODULE_GDMA_CH2, + } } }; -#endif diff --git a/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in index 33987950ad..976c38e7eb 100644 --- a/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in @@ -451,6 +451,10 @@ config SOC_GDMA_SUPPORT_ETM bool default y +config SOC_GDMA_SUPPORT_SLEEP_RETENTION + bool + default y + config SOC_ETM_GROUPS int default 1 diff --git a/components/soc/esp32c5/include/soc/soc_caps.h b/components/soc/esp32c5/include/soc/soc_caps.h index f096be0f22..434e3b58e4 100644 --- a/components/soc/esp32c5/include/soc/soc_caps.h +++ b/components/soc/esp32c5/include/soc/soc_caps.h @@ -186,7 +186,7 @@ #define SOC_GDMA_NUM_GROUPS_MAX 1U #define SOC_GDMA_PAIRS_PER_GROUP_MAX 3 #define SOC_GDMA_SUPPORT_ETM 1 -// #define SOC_GDMA_SUPPORT_SLEEP_RETENTION 1 // TODO: IDF-9225 +#define SOC_GDMA_SUPPORT_SLEEP_RETENTION 1 /*-------------------------- ETM CAPS --------------------------------------*/ #define SOC_ETM_GROUPS 1U // Number of ETM groups diff --git a/components/soc/esp32c6/gdma_periph.c b/components/soc/esp32c6/gdma_periph.c index fd24fad766..4e2790c1af 100644 --- a/components/soc/esp32c6/gdma_periph.c +++ b/components/soc/esp32c6/gdma_periph.c @@ -44,7 +44,7 @@ static const regdma_entries_config_t gdma_g0p0_regs_retention[] = { G0P0_RETENTION_REGS_CNT, 0, 0, \ g0p0_regs_map[0], g0p0_regs_map[1], \ g0p0_regs_map[2], g0p0_regs_map[3]), \ - .owner = ENTRY(0) | ENTRY(2) }, + .owner = GDMA_RETENTION_ENTRY }, }; /* GDMA Channel (Group0, Pair1) Registers Context @@ -62,7 +62,7 @@ static const regdma_entries_config_t gdma_g0p1_regs_retention[] = { G0P1_RETENTION_REGS_CNT, 0, 0, \ g0p1_regs_map[0], g0p1_regs_map[1], \ g0p1_regs_map[2], g0p1_regs_map[3]), \ - .owner = ENTRY(0) | ENTRY(2) }, + .owner = GDMA_RETENTION_ENTRY }, }; /* GDMA Channel (Group0, Pair2) Registers Context @@ -83,19 +83,31 @@ static const regdma_entries_config_t gdma_g0p2_regs_retention[] = { G0P2_RETENTION_REGS_CNT_0, 0, 0, \ g0p2_regs_map0[0], g0p2_regs_map0[1], \ g0p2_regs_map0[2], g0p2_regs_map0[3]), \ - .owner = ENTRY(0) | ENTRY(2) }, + .owner = GDMA_RETENTION_ENTRY }, [1] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \ G0P2_RETENTION_MAP_BASE_1, G0P2_RETENTION_MAP_BASE_1, \ G0P2_RETENTION_REGS_CNT_1, 0, 0, \ g0p2_regs_map1[0], g0p2_regs_map1[1], \ g0p2_regs_map1[2], g0p2_regs_map1[3]), \ - .owner = ENTRY(0) | ENTRY(2) }, + .owner = GDMA_RETENTION_ENTRY }, }; const gdma_chx_reg_ctx_link_t gdma_chx_regs_retention[SOC_GDMA_NUM_GROUPS_MAX][SOC_GDMA_PAIRS_PER_GROUP_MAX] = { [0] = { - [0] = {gdma_g0p0_regs_retention, ARRAY_SIZE(gdma_g0p0_regs_retention)}, - [1] = {gdma_g0p1_regs_retention, ARRAY_SIZE(gdma_g0p1_regs_retention)}, - [2] = {gdma_g0p2_regs_retention, ARRAY_SIZE(gdma_g0p2_regs_retention)} + [0] = { + gdma_g0p0_regs_retention, + ARRAY_SIZE(gdma_g0p0_regs_retention), + SLEEP_RETENTION_MODULE_GDMA_CH0, + }, + [1] = { + gdma_g0p1_regs_retention, + ARRAY_SIZE(gdma_g0p1_regs_retention), + SLEEP_RETENTION_MODULE_GDMA_CH1, + }, + [2] = { + gdma_g0p2_regs_retention, + ARRAY_SIZE(gdma_g0p2_regs_retention), + SLEEP_RETENTION_MODULE_GDMA_CH2, + }, } }; diff --git a/components/soc/esp32c61/gdma_periph.c b/components/soc/esp32c61/gdma_periph.c index 929f058a92..d4ff02eeca 100644 --- a/components/soc/esp32c61/gdma_periph.c +++ b/components/soc/esp32c61/gdma_periph.c @@ -24,3 +24,86 @@ const gdma_signal_conn_t gdma_periph_signals = { } } }; + +/* AHB_DMA Channel (Group0, Pair0) Registers Context + Include: AHB_DMA_MISC_CONF_REG + AHB_DMA_IN_INT_ENA_CH0_REG / AHB_DMA_OUT_INT_ENA_CH0_REG / AHB_DMA_IN_PERI_SEL_CH0_REG / AHB_DMA_OUT_PERI_SEL_CH0_REG + AHB_DMA_IN_CONF0_CH0_REG / AHB_DMA_IN_CONF1_CH0_REG / AHB_DMA_IN_LINK_CH0_REG / AHB_DMA_IN_PRI_CH0_REG + AHB_DMA_OUT_CONF0_CH0_REG / AHB_DMA_OUT_CONF1_CH0_REG / AHB_DMA_OUT_LINK_CH0_REG / AHB_DMA_OUT_PRI_CH0_REG + + AHB_DMA_TX_CH_ARB_WEIGH_CH0_REG / AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH0_REG + AHB_DMA_RX_CH_ARB_WEIGH_CH0_REG / AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH0_REG + AHB_DMA_IN_LINK_ADDR_CH0_REG / AHB_DMA_OUT_LINK_ADDR_CH0_REG + AHB_DMA_INTR_MEM_START_ADDR_REG / AHB_DMA_INTR_MEM_END_ADDR_REG + AHB_DMA_ARB_TIMEOUT_TX_REG / AHB_DMA_ARB_TIMEOUT_RX_REG + AHB_DMA_WEIGHT_EN_TX_REG / AHB_DMA_WEIGHT_EN_RX_REG +*/ +#define G0P0_RETENTION_REGS_CNT_0 13 +#define G0P0_RETENTION_MAP_BASE_0 AHB_DMA_IN_INT_ENA_CH0_REG +#define G0P0_RETENTION_REGS_CNT_1 12 +#define G0P0_RETENTION_MAP_BASE_1 AHB_DMA_TX_CH_ARB_WEIGH_CH0_REG +static const uint32_t g0p0_regs_map0[4] = {0x4c801001, 0x604c0060, 0x0, 0x0}; +static const uint32_t g0p0_regs_map1[4] = {0xc0000003, 0xfc900000, 0x0, 0x0}; +static const regdma_entries_config_t gdma_g0p0_regs_retention[] = { + [0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \ + G0P0_RETENTION_MAP_BASE_0, G0P0_RETENTION_MAP_BASE_0, \ + G0P0_RETENTION_REGS_CNT_0, 0, 0, \ + g0p0_regs_map0[0], g0p0_regs_map0[1], \ + g0p0_regs_map0[2], g0p0_regs_map0[3]), \ + .owner = GDMA_RETENTION_ENTRY }, \ + [1] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \ + G0P0_RETENTION_MAP_BASE_1, G0P0_RETENTION_MAP_BASE_1, \ + G0P0_RETENTION_REGS_CNT_1, 0, 0, \ + g0p0_regs_map1[0], g0p0_regs_map1[1], \ + g0p0_regs_map1[2], g0p0_regs_map1[3]), \ + .owner = GDMA_RETENTION_ENTRY }, +}; + +/* AHB_DMA Channel (Group0, Pair1) Registers Context + Include: AHB_DMA_MISC_CONF_REG + AHB_DMA_IN_INT_ENA_CH1_REG / AHB_DMA_OUT_INT_ENA_CH1_REG / AHB_DMA_IN_PERI_SEL_CH1_REG / AHB_DMA_OUT_PERI_SEL_CH1_REG + AHB_DMA_IN_CONF0_CH1_REG / AHB_DMA_IN_CONF1_CH1_REG / AHB_DMA_IN_LINK_CH1_REG / AHB_DMA_IN_PRI_CH1_REG + AHB_DMA_OUT_CONF0_CH1_REG / AHB_DMA_OUT_CONF1_CH1_REG / AHB_DMA_OUT_LINK_CH1_REG / AHB_DMA_OUT_PRI_CH1_REG + + AHB_DMA_TX_CH_ARB_WEIGH_CH1_REG / AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH1_REG + AHB_DMA_RX_CH_ARB_WEIGH_CH1_REG / AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH1_REG + AHB_DMA_IN_LINK_ADDR_CH1_REG / AHB_DMA_OUT_LINK_ADDR_CH1_REG + AHB_DMA_INTR_MEM_START_ADDR_REG / AHB_DMA_INTR_MEM_END_ADDR_REG + AHB_DMA_ARB_TIMEOUT_TX_REG / AHB_DMA_ARB_TIMEOUT_RX_REG + AHB_DMA_WEIGHT_EN_TX_REG / AHB_DMA_WEIGHT_EN_RX_REG +*/ +#define G0P1_RETENTION_REGS_CNT_0 13 +#define G0P1_RETENTION_MAP_BASE_0 AHB_DMA_IN_INT_ENA_CH1_REG +#define G0P1_RETENTION_REGS_CNT_1 12 +#define G0P1_RETENTION_MAP_BASE_1 AHB_DMA_TX_CH_ARB_WEIGH_CH1_REG +static const uint32_t g0p1_regs_map0[4] = {0x81001, 0x0, 0xc00604c0, 0x604}; +static const uint32_t g0p1_regs_map1[4] = {0xc0000003, 0x3f4800, 0x0, 0x0}; +static const regdma_entries_config_t gdma_g0p1_regs_retention[] = { + [0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \ + G0P1_RETENTION_MAP_BASE_0, G0P1_RETENTION_MAP_BASE_0, \ + G0P1_RETENTION_REGS_CNT_0, 0, 0, \ + g0p1_regs_map0[0], g0p1_regs_map0[1], \ + g0p1_regs_map0[2], g0p1_regs_map0[3]), \ + .owner = GDMA_RETENTION_ENTRY }, + [1] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \ + G0P1_RETENTION_MAP_BASE_1, G0P1_RETENTION_MAP_BASE_1, \ + G0P1_RETENTION_REGS_CNT_1, 0, 0, \ + g0p1_regs_map1[0], g0p1_regs_map1[1], \ + g0p1_regs_map1[2], g0p1_regs_map1[3]), \ + .owner = GDMA_RETENTION_ENTRY }, +}; + +const gdma_chx_reg_ctx_link_t gdma_chx_regs_retention[SOC_GDMA_NUM_GROUPS_MAX][SOC_GDMA_PAIRS_PER_GROUP_MAX] = { + [0] = { + [0] = { + gdma_g0p0_regs_retention, + ARRAY_SIZE(gdma_g0p0_regs_retention), + SLEEP_RETENTION_MODULE_GDMA_CH0, + }, + [1] = { + gdma_g0p1_regs_retention, + ARRAY_SIZE(gdma_g0p1_regs_retention), + SLEEP_RETENTION_MODULE_GDMA_CH1, + }, + } +}; diff --git a/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in index 65c3b8491b..00f960bd87 100644 --- a/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in @@ -267,6 +267,10 @@ config SOC_GDMA_PAIRS_PER_GROUP_MAX int default 2 +config SOC_GDMA_SUPPORT_SLEEP_RETENTION + bool + default y + config SOC_ETM_GROUPS int default 1 diff --git a/components/soc/esp32c61/include/soc/reg_base.h b/components/soc/esp32c61/include/soc/reg_base.h index 5fe48114a2..e092f8726b 100644 --- a/components/soc/esp32c61/include/soc/reg_base.h +++ b/components/soc/esp32c61/include/soc/reg_base.h @@ -23,7 +23,7 @@ #define DR_REG_SOC_ETM_BASE 0x60013000 #define DR_REG_PVT_MONITOR_BASE 0x60019000 #define DR_REG_PSRAM_MEM_MONITOR_BASE 0x6001A000 -#define DR_REG_AHB_GDMA_BASE 0x60080000 +#define DR_REG_AHB_DMA_BASE 0x60080000 #define DR_REG_GPSPI_BASE 0x60081000 #define DR_REG_SHA_BASE 0x60089000 #define DR_REG_ECC_MULT_BASE 0x6008B000 diff --git a/components/soc/esp32c61/include/soc/retention_periph_defs.h b/components/soc/esp32c61/include/soc/retention_periph_defs.h index 0904c5a2a2..5bc404860b 100644 --- a/components/soc/esp32c61/include/soc/retention_periph_defs.h +++ b/components/soc/esp32c61/include/soc/retention_periph_defs.h @@ -29,7 +29,6 @@ typedef enum periph_retention_module { /* GDMA by channel */ SLEEP_RETENTION_MODULE_GDMA_CH0 = 8, SLEEP_RETENTION_MODULE_GDMA_CH1 = 9, - SLEEP_RETENTION_MODULE_GDMA_CH2 = 10, /* MISC Peripherals */ SLEEP_RETENTION_MODULE_I2C0 = 12, SLEEP_RETENTION_MODULE_UART0 = 14, @@ -59,7 +58,6 @@ typedef enum periph_retention_module_bitmap { /* GDMA by channel */ SLEEP_RETENTION_MODULE_BM_GDMA_CH0 = BIT(SLEEP_RETENTION_MODULE_GDMA_CH0), SLEEP_RETENTION_MODULE_BM_GDMA_CH1 = BIT(SLEEP_RETENTION_MODULE_GDMA_CH1), - SLEEP_RETENTION_MODULE_BM_GDMA_CH2 = BIT(SLEEP_RETENTION_MODULE_GDMA_CH2), /* MISC Peripherals */ SLEEP_RETENTION_MODULE_BM_I2C0 = BIT(SLEEP_RETENTION_MODULE_I2C0), SLEEP_RETENTION_MODULE_BM_UART0 = BIT(SLEEP_RETENTION_MODULE_UART0), @@ -80,7 +78,6 @@ typedef enum periph_retention_module_bitmap { | SLEEP_RETENTION_MODULE_BM_TG1_TIMER \ | SLEEP_RETENTION_MODULE_BM_GDMA_CH0 \ | SLEEP_RETENTION_MODULE_BM_GDMA_CH1 \ - | SLEEP_RETENTION_MODULE_BM_GDMA_CH2 \ | SLEEP_RETENTION_MODULE_BM_I2C0 \ | SLEEP_RETENTION_MODULE_BM_UART0 \ | SLEEP_RETENTION_MODULE_BM_UART1 \ diff --git a/components/soc/esp32c61/include/soc/soc_caps.h b/components/soc/esp32c61/include/soc/soc_caps.h index c37570c33f..db614fd75b 100644 --- a/components/soc/esp32c61/include/soc/soc_caps.h +++ b/components/soc/esp32c61/include/soc/soc_caps.h @@ -49,8 +49,7 @@ #define SOC_PMU_SUPPORTED 1 #define SOC_LP_TIMER_SUPPORTED 1 #define SOC_LP_AON_SUPPORTED 1 -// \#define SOC_LP_PERIPHERALS_SUPPORTED 1 - #define SOC_CLK_TREE_SUPPORTED 1 +#define SOC_CLK_TREE_SUPPORTED 1 // \#define SOC_ASSIST_DEBUG_SUPPORTED 1 //TODO: [ESP32C61] IDF-9269 #define SOC_WDT_SUPPORTED 1 #define SOC_SPI_FLASH_SUPPORTED 1 //TODO: [ESP32C61] IDF-9314 @@ -150,7 +149,7 @@ #define SOC_GDMA_NUM_GROUPS_MAX 1U #define SOC_GDMA_PAIRS_PER_GROUP_MAX 2 // \#define SOC_GDMA_SUPPORT_ETM 1 // Support ETM submodule TODO: IDF-9964 -// \#define SOC_GDMA_SUPPORT_SLEEP_RETENTION 1 // TODO: IDF-10380 +#define SOC_GDMA_SUPPORT_SLEEP_RETENTION 1 /*-------------------------- ETM CAPS --------------------------------------*/ #define SOC_ETM_GROUPS 1U // Number of ETM groups diff --git a/components/soc/esp32h2/gdma_periph.c b/components/soc/esp32h2/gdma_periph.c index fd24fad766..5e55ca93e8 100644 --- a/components/soc/esp32h2/gdma_periph.c +++ b/components/soc/esp32h2/gdma_periph.c @@ -44,7 +44,7 @@ static const regdma_entries_config_t gdma_g0p0_regs_retention[] = { G0P0_RETENTION_REGS_CNT, 0, 0, \ g0p0_regs_map[0], g0p0_regs_map[1], \ g0p0_regs_map[2], g0p0_regs_map[3]), \ - .owner = ENTRY(0) | ENTRY(2) }, + .owner = GDMA_RETENTION_ENTRY }, }; /* GDMA Channel (Group0, Pair1) Registers Context @@ -62,7 +62,7 @@ static const regdma_entries_config_t gdma_g0p1_regs_retention[] = { G0P1_RETENTION_REGS_CNT, 0, 0, \ g0p1_regs_map[0], g0p1_regs_map[1], \ g0p1_regs_map[2], g0p1_regs_map[3]), \ - .owner = ENTRY(0) | ENTRY(2) }, + .owner = GDMA_RETENTION_ENTRY }, }; /* GDMA Channel (Group0, Pair2) Registers Context @@ -83,19 +83,31 @@ static const regdma_entries_config_t gdma_g0p2_regs_retention[] = { G0P2_RETENTION_REGS_CNT_0, 0, 0, \ g0p2_regs_map0[0], g0p2_regs_map0[1], \ g0p2_regs_map0[2], g0p2_regs_map0[3]), \ - .owner = ENTRY(0) | ENTRY(2) }, + .owner = GDMA_RETENTION_ENTRY }, [1] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \ G0P2_RETENTION_MAP_BASE_1, G0P2_RETENTION_MAP_BASE_1, \ G0P2_RETENTION_REGS_CNT_1, 0, 0, \ g0p2_regs_map1[0], g0p2_regs_map1[1], \ g0p2_regs_map1[2], g0p2_regs_map1[3]), \ - .owner = ENTRY(0) | ENTRY(2) }, + .owner = GDMA_RETENTION_ENTRY }, }; const gdma_chx_reg_ctx_link_t gdma_chx_regs_retention[SOC_GDMA_NUM_GROUPS_MAX][SOC_GDMA_PAIRS_PER_GROUP_MAX] = { [0] = { - [0] = {gdma_g0p0_regs_retention, ARRAY_SIZE(gdma_g0p0_regs_retention)}, - [1] = {gdma_g0p1_regs_retention, ARRAY_SIZE(gdma_g0p1_regs_retention)}, - [2] = {gdma_g0p2_regs_retention, ARRAY_SIZE(gdma_g0p2_regs_retention)} + [0] = { + gdma_g0p0_regs_retention, + ARRAY_SIZE(gdma_g0p0_regs_retention), + SLEEP_RETENTION_MODULE_GDMA_CH0, + }, + [1] = { + gdma_g0p1_regs_retention, + ARRAY_SIZE(gdma_g0p1_regs_retention), + SLEEP_RETENTION_MODULE_GDMA_CH1, + }, + [2] = { + gdma_g0p2_regs_retention, + ARRAY_SIZE(gdma_g0p2_regs_retention), + SLEEP_RETENTION_MODULE_GDMA_CH2, + } } }; diff --git a/components/soc/esp32p4/gdma_periph.c b/components/soc/esp32p4/gdma_periph.c index 49c0611848..61d00e6f86 100644 --- a/components/soc/esp32p4/gdma_periph.c +++ b/components/soc/esp32p4/gdma_periph.c @@ -1,10 +1,12 @@ /* - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ #include "soc/gdma_periph.h" +#include "soc/ahb_dma_reg.h" +#include "soc/axi_dma_reg.h" const gdma_signal_conn_t gdma_periph_signals = { .groups = { @@ -44,3 +46,235 @@ const gdma_signal_conn_t gdma_periph_signals = { } } }; + +/* AHB_DMA Channel (Group0, Pair0) Registers Context + Include: AHB_DMA_INTR_MEM_START_ADDR_REG / AHB_DMA_INTR_MEM_END_ADDR_REG + AHB_DMA_ARB_TIMEOUT_TX_REG / AHB_DMA_ARB_TIMEOUT_RX_REG / AHB_DMA_WEIGHT_EN_TX_REG / AHB_DMA_WEIGHT_EN_RX_REG + AHB_DMA_MISC_CONF_REG / + AHB_DMA_IN_INT_ENA_CH0_REG / AHB_DMA_OUT_INT_ENA_CH0_REG / AHB_DMA_IN_PERI_SEL_CH0_REG / AHB_DMA_OUT_PERI_SEL_CH0_REG + AHB_DMA_IN_CONF0_CH0_REG / AHB_DMA_IN_CONF1_CH0_REG / AHB_DMA_IN_LINK_CH0_REG / AHB_DMA_IN_LINK_ADDR_CH0_REG / AHB_DMA_IN_PRI_CH0_REG + AHB_DMA_OUT_CONF0_CH0_REG / AHB_DMA_OUT_CONF1_CH0_REG / AHB_DMA_OUT_LINK_CH0_REG / AHB_DMA_OUT_LINK_ADDR_CH0_REG / AHB_DMA_OUT_PRI_CH0_REG + AHB_DMA_TX_CH_ARB_WEIGH_CH0_REG / AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH0_REG + AHB_DMA_RX_CH_ARB_WEIGH_CH0_REG / AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH0_REG + + Note: CRC functionality is hard to do hardware retention, will consider to use software to do the backup and restore. +*/ +#define AHB_DMA_G0P0_RETENTION_REGS_CNT_0 13 +#define AHB_DMA_G0P0_RETENTION_MAP_BASE_0 AHB_DMA_IN_INT_ENA_CH0_REG +#define AHB_DMA_G0P0_RETENTION_REGS_CNT_1 12 +#define AHB_DMA_G0P0_RETENTION_MAP_BASE_1 AHB_DMA_TX_CH_ARB_WEIGH_CH0_REG +static const uint32_t ahb_dma_g0p0_regs_map0[4] = {0x4c801001, 0x604c0060, 0x0, 0x0}; +static const uint32_t ahb_dma_g0p0_regs_map1[4] = {0xc0000003, 0xfc900000, 0x0, 0x0}; +static const regdma_entries_config_t ahb_dma_g0p0_regs_retention[] = { + [0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \ + AHB_DMA_G0P0_RETENTION_MAP_BASE_0, AHB_DMA_G0P0_RETENTION_MAP_BASE_0, \ + AHB_DMA_G0P0_RETENTION_REGS_CNT_0, 0, 0, \ + ahb_dma_g0p0_regs_map0[0], ahb_dma_g0p0_regs_map0[1], \ + ahb_dma_g0p0_regs_map0[2], ahb_dma_g0p0_regs_map0[3]), \ + .owner = GDMA_RETENTION_ENTRY }, + [1] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \ + AHB_DMA_G0P0_RETENTION_MAP_BASE_1, AHB_DMA_G0P0_RETENTION_MAP_BASE_1, \ + AHB_DMA_G0P0_RETENTION_REGS_CNT_1, 0, 0, \ + ahb_dma_g0p0_regs_map1[0], ahb_dma_g0p0_regs_map1[1], \ + ahb_dma_g0p0_regs_map1[2], ahb_dma_g0p0_regs_map1[3]), \ + .owner = GDMA_RETENTION_ENTRY }, +}; + +/* AHB_DMA Channel (Group0, Pair1) Registers Context + Include: AHB_DMA_INTR_MEM_START_ADDR_REG / AHB_DMA_INTR_MEM_END_ADDR_REG + AHB_DMA_ARB_TIMEOUT_TX_REG / AHB_DMA_ARB_TIMEOUT_RX_REG / AHB_DMA_WEIGHT_EN_TX_REG / AHB_DMA_WEIGHT_EN_RX_REG + AHB_DMA_MISC_CONF_REG / + AHB_DMA_IN_INT_ENA_CH1_REG / AHB_DMA_OUT_INT_ENA_CH1_REG / AHB_DMA_IN_PERI_SEL_CH1_REG / AHB_DMA_OUT_PERI_SEL_CH1_REG + AHB_DMA_IN_CONF0_CH1_REG / AHB_DMA_IN_CONF1_CH1_REG / AHB_DMA_IN_LINK_CH1_REG / AHB_DMA_IN_LINK_ADDR_CH1_REG / AHB_DMA_IN_PRI_CH1_REG + AHB_DMA_OUT_CONF0_CH1_REG / AHB_DMA_OUT_CONF1_CH1_REG / AHB_DMA_OUT_LINK_CH1_REG / AHB_DMA_OUT_LINK_ADDR_CH1_REG / AHB_DMA_OUT_PRI_CH1_REG + AHB_DMA_TX_CH_ARB_WEIGH_CH1_REG / AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH1_REG + AHB_DMA_RX_CH_ARB_WEIGH_CH1_REG / AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH1_REG + + Note: CRC functionality is hard to do hardware retention, will consider to use software to do the backup and restore. +*/ +#define AHB_DMA_G0P1_RETENTION_REGS_CNT_0 13 +#define AHB_DMA_G0P1_RETENTION_MAP_BASE_0 AHB_DMA_IN_INT_ENA_CH1_REG +#define AHB_DMA_G0P1_RETENTION_REGS_CNT_1 12 +#define AHB_DMA_G0P1_RETENTION_MAP_BASE_1 AHB_DMA_TX_CH_ARB_WEIGH_CH1_REG +static const uint32_t ahb_dma_g0p1_regs_map0[4] = {0x81001, 0, 0xC00604C0, 0x604}; +static const uint32_t ahb_dma_g0p1_regs_map1[4] = {0xc0000003, 0x3f4800, 0x0, 0x0}; +static const regdma_entries_config_t ahb_dma_g0p1_regs_retention[] = { + [0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \ + AHB_DMA_G0P1_RETENTION_MAP_BASE_0, AHB_DMA_G0P1_RETENTION_MAP_BASE_0, \ + AHB_DMA_G0P1_RETENTION_REGS_CNT_0, 0, 0, \ + ahb_dma_g0p1_regs_map0[0], ahb_dma_g0p1_regs_map0[1], \ + ahb_dma_g0p1_regs_map0[2], ahb_dma_g0p1_regs_map0[3]), \ + .owner = GDMA_RETENTION_ENTRY }, + [1] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \ + AHB_DMA_G0P1_RETENTION_MAP_BASE_1, AHB_DMA_G0P1_RETENTION_MAP_BASE_1, \ + AHB_DMA_G0P1_RETENTION_REGS_CNT_1, 0, 0, \ + ahb_dma_g0p1_regs_map1[0], ahb_dma_g0p1_regs_map1[1], \ + ahb_dma_g0p1_regs_map1[2], ahb_dma_g0p1_regs_map1[3]), \ + .owner = GDMA_RETENTION_ENTRY }, +}; + +/* AHB_DMA Channel (Group0, Pair2) Registers Context + Include: AHB_DMA_INTR_MEM_START_ADDR_REG / AHB_DMA_INTR_MEM_END_ADDR_REG + AHB_DMA_ARB_TIMEOUT_TX_REG / AHB_DMA_ARB_TIMEOUT_RX_REG / AHB_DMA_WEIGHT_EN_TX_REG / AHB_DMA_WEIGHT_EN_RX_REG + AHB_DMA_MISC_CONF_REG / + AHB_DMA_IN_INT_ENA_CH2_REG / AHB_DMA_OUT_INT_ENA_CH2_REG / AHB_DMA_IN_PERI_SEL_CH2_REG / AHB_DMA_OUT_PERI_SEL_CH2_REG + AHB_DMA_IN_CONF0_CH2_REG / AHB_DMA_IN_CONF1_CH2_REG / AHB_DMA_IN_LINK_CH2_REG / AHB_DMA_IN_LINK_ADDR_CH2_REG / AHB_DMA_IN_PRI_CH2_REG + AHB_DMA_OUT_CONF0_CH2_REG / AHB_DMA_OUT_CONF1_CH2_REG / AHB_DMA_OUT_LINK_CH2_REG / AHB_DMA_OUT_LINK_ADDR_CH2_REG / AHB_DMA_OUT_PRI_CH2_REG + AHB_DMA_TX_CH_ARB_WEIGH_CH2_REG / AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH2_REG + AHB_DMA_RX_CH_ARB_WEIGH_CH2_REG / AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH2_REG + + Note: CRC functionality is hard to do hardware retention, will consider to use software to do the backup and restore. +*/ +#define AHB_DMA_G0P2_RETENTION_REGS_CNT_0 6 +#define AHB_DMA_G0P2_RETENTION_MAP_BASE_0 AHB_DMA_IN_INT_ENA_CH2_REG +#define AHB_DMA_G0P2_RETENTION_REGS_CNT_1 19 +#define AHB_DMA_G0P2_RETENTION_MAP_BASE_1 AHB_DMA_IN_PRI_CH2_REG +static const uint32_t ahb_dma_g0p2_regs_map0[4] = {0x9001, 0, 0, 0x4C0000}; +static const uint32_t ahb_dma_g0p2_regs_map1[4] = {0x3026003, 0x0, 0x30, 0xfe4c}; +static const regdma_entries_config_t ahb_dma_g0p2_regs_retention[] = { + [0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \ + AHB_DMA_G0P2_RETENTION_MAP_BASE_0, AHB_DMA_G0P2_RETENTION_MAP_BASE_0, \ + AHB_DMA_G0P2_RETENTION_REGS_CNT_0, 0, 0, \ + ahb_dma_g0p2_regs_map0[0], ahb_dma_g0p2_regs_map0[1], \ + ahb_dma_g0p2_regs_map0[2], ahb_dma_g0p2_regs_map0[3]), \ + .owner = GDMA_RETENTION_ENTRY }, + [1] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \ + AHB_DMA_G0P2_RETENTION_MAP_BASE_1, AHB_DMA_G0P2_RETENTION_MAP_BASE_1, \ + AHB_DMA_G0P2_RETENTION_REGS_CNT_1, 0, 0, \ + ahb_dma_g0p2_regs_map1[0], ahb_dma_g0p2_regs_map1[1], \ + ahb_dma_g0p2_regs_map1[2], ahb_dma_g0p2_regs_map1[3]), \ + .owner = GDMA_RETENTION_ENTRY }, +}; + +/* AXI_DMA Channel (Group1, Pair0) Registers Context + Include: AXI_DMA_IN_INT_ENA_CH0_REG / AXI_DMA_IN_CONF0_CH0_REG / AXI_DMA_IN_CONF1_CH0_REG / AXI_DMA_IN_LINK1_CH0_REG / AXI_DMA_IN_LINK2_CH0_REG + AXI_DMA_IN_PRI_CH0_REG / AXI_DMA_IN_PERI_SEL_CH0_REG + AXI_DMA_OUT_INT_ENA_CH0_REG / AXI_DMA_OUT_CONF0_CH0_REG / AXI_DMA_OUT_CONF1_CH0_REG / AXI_DMA_OUT_LINK1_CH0_REG / AXI_DMA_OUT_LINK2_CH0_REG + AXI_DMA_OUT_PRI_CH0_REG / AXI_DMA_OUT_PERI_SEL_CH0_REG + AXI_DMA_ARB_TIMEOUT_REG / AXI_DMA_WEIGHT_EN_REG / AXI_DMA_IN_MEM_CONF_REG + AXI_DMA_INTR_MEM_START_ADDR_REG / AXI_DMA_INTR_MEM_END_ADDR_REG / AXI_DMA_EXTR_MEM_START_ADDR_REG / AXI_DMA_EXTR_MEM_END_ADDR_REG + AXI_DMA_MISC_CONF_REG + + Note: CRC functionality is hard to do hardware retention, will consider to use software to do the backup and restore. +*/ +#define AXI_DMA_G1P0_RETENTION_REGS_CNT_0 14 +#define AXI_DMA_G1P0_RETENTION_MAP_BASE_0 AXI_DMA_IN_INT_ENA_CH0_REG +#define AXI_DMA_G1P0_RETENTION_REGS_CNT_1 8 +#define AXI_DMA_G1P0_RETENTION_MAP_BASE_1 AXI_DMA_ARB_TIMEOUT_REG +static const uint32_t axi_dma_g1p0_regs_map0[4] = {0xc0cd, 0x0, 0x30334000, 0x0}; +static const uint32_t axi_dma_g1p0_regs_map1[4] = {0x407f, 0x0, 0x0, 0x0}; +static const regdma_entries_config_t axi_dma_g1p0_regs_retention[] = { + [0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \ + AXI_DMA_G1P0_RETENTION_MAP_BASE_0, AXI_DMA_G1P0_RETENTION_MAP_BASE_0, \ + AXI_DMA_G1P0_RETENTION_REGS_CNT_0, 0, 0, \ + axi_dma_g1p0_regs_map0[0], axi_dma_g1p0_regs_map0[1], \ + axi_dma_g1p0_regs_map0[2], axi_dma_g1p0_regs_map0[3]), \ + .owner = GDMA_RETENTION_ENTRY }, + [1] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \ + AXI_DMA_G1P0_RETENTION_MAP_BASE_1, AXI_DMA_G1P0_RETENTION_MAP_BASE_1, \ + AXI_DMA_G1P0_RETENTION_REGS_CNT_1, 0, 0, \ + axi_dma_g1p0_regs_map1[0], axi_dma_g1p0_regs_map1[1], \ + axi_dma_g1p0_regs_map1[2], axi_dma_g1p0_regs_map1[3]), \ + .owner = GDMA_RETENTION_ENTRY}, +}; + +/* AXI_DMA Channel (Group1, Pair1) Registers Context + Include: AXI_DMA_IN_INT_ENA_CH1_REG / AXI_DMA_IN_CONF0_CH1_REG / AXI_DMA_IN_CONF1_CH1_REG / AXI_DMA_IN_LINK1_CH1_REG / AXI_DMA_IN_LINK2_CH1_REG + AXI_DMA_IN_PRI_CH1_REG / AXI_DMA_IN_PERI_SEL_CH1_REG + AXI_DMA_OUT_INT_ENA_CH1_REG / AXI_DMA_OUT_CONF0_CH1_REG / AXI_DMA_OUT_CONF1_CH1_REG / AXI_DMA_OUT_LINK1_CH1_REG / AXI_DMA_OUT_LINK2_CH1_REG + AXI_DMA_OUT_PRI_CH1_REG / AXI_DMA_OUT_PERI_SEL_CH1_REG + AXI_DMA_ARB_TIMEOUT_REG / AXI_DMA_WEIGHT_EN_REG / AXI_DMA_IN_MEM_CONF_REG + AXI_DMA_INTR_MEM_START_ADDR_REG / AXI_DMA_INTR_MEM_END_ADDR_REG / AXI_DMA_EXTR_MEM_START_ADDR_REG / AXI_DMA_EXTR_MEM_END_ADDR_REG + AXI_DMA_MISC_CONF_REG + + Note: CRC functionality is hard to do hardware retention, will consider to use software to do the backup and restore. +*/ +#define AXI_DMA_G1P1_RETENTION_REGS_CNT_0 14 +#define AXI_DMA_G1P1_RETENTION_MAP_BASE_0 AXI_DMA_IN_INT_ENA_CH1_REG +#define AXI_DMA_G1P1_RETENTION_REGS_CNT_1 8 +#define AXI_DMA_G1P1_RETENTION_MAP_BASE_1 AXI_DMA_ARB_TIMEOUT_REG +static const uint32_t axi_dma_g1p1_regs_map0[4] = {0xc0cd, 0x0, 0x30334000, 0x0}; +static const uint32_t axi_dma_g1p1_regs_map1[4] = {0x407f, 0x0, 0x0, 0x0}; +static const regdma_entries_config_t axi_dma_g1p1_regs_retention[] = { + [0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \ + AXI_DMA_G1P1_RETENTION_MAP_BASE_0, AXI_DMA_G1P1_RETENTION_MAP_BASE_0, \ + AXI_DMA_G1P1_RETENTION_REGS_CNT_0, 0, 0, \ + axi_dma_g1p1_regs_map0[0], axi_dma_g1p1_regs_map0[1], \ + axi_dma_g1p1_regs_map0[2], axi_dma_g1p1_regs_map0[3]), \ + .owner = GDMA_RETENTION_ENTRY }, + [1] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \ + AXI_DMA_G1P1_RETENTION_MAP_BASE_1, AXI_DMA_G1P1_RETENTION_MAP_BASE_1, \ + AXI_DMA_G1P1_RETENTION_REGS_CNT_1, 0, 0, \ + axi_dma_g1p1_regs_map1[0], axi_dma_g1p1_regs_map1[1], \ + axi_dma_g1p1_regs_map1[2], axi_dma_g1p1_regs_map1[3]), \ + .owner = GDMA_RETENTION_ENTRY }, +}; + +/* AXI_DMA Channel (Group1, Pair2) Registers Context + Include: AXI_DMA_IN_INT_ENA_CH2_REG / AXI_DMA_IN_CONF0_CH2_REG / AXI_DMA_IN_CONF1_CH2_REG / AXI_DMA_IN_LINK1_CH2_REG / AXI_DMA_IN_LINK2_CH2_REG + AXI_DMA_IN_PRI_CH2_REG / AXI_DMA_IN_PERI_SEL_CH2_REG + AXI_DMA_OUT_INT_ENA_CH2_REG / AXI_DMA_OUT_CONF0_CH2_REG / AXI_DMA_OUT_CONF1_CH2_REG / AXI_DMA_OUT_LINK1_CH2_REG / AXI_DMA_OUT_LINK2_CH2_REG + AXI_DMA_OUT_PRI_CH2_REG / AXI_DMA_OUT_PERI_SEL_CH2_REG + AXI_DMA_ARB_TIMEOUT_REG / AXI_DMA_WEIGHT_EN_REG / AXI_DMA_IN_MEM_CONF_REG + AXI_DMA_INTR_MEM_START_ADDR_REG / AXI_DMA_INTR_MEM_END_ADDR_REG / AXI_DMA_EXTR_MEM_START_ADDR_REG / AXI_DMA_EXTR_MEM_END_ADDR_REG + AXI_DMA_MISC_CONF_REG + + Note: CRC functionality is hard to do hardware retention, will consider to use software to do the backup and restore. +*/ +#define AXI_DMA_G1P2_RETENTION_REGS_CNT_0 14 +#define AXI_DMA_G1P2_RETENTION_MAP_BASE_0 AXI_DMA_IN_INT_ENA_CH2_REG +#define AXI_DMA_G1P2_RETENTION_REGS_CNT_1 8 +#define AXI_DMA_G1P2_RETENTION_MAP_BASE_1 AXI_DMA_ARB_TIMEOUT_REG +static const uint32_t axi_dma_g1p2_regs_map0[4] = {0xc0cd, 0x0, 0x30334000, 0x0}; +static const uint32_t axi_dma_g1p2_regs_map1[4] = {0x407f, 0x0, 0x0, 0x0}; +static const regdma_entries_config_t axi_dma_g1p2_regs_retention[] = { + [0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \ + AXI_DMA_G1P2_RETENTION_MAP_BASE_0, AXI_DMA_G1P2_RETENTION_MAP_BASE_0, \ + AXI_DMA_G1P2_RETENTION_REGS_CNT_0, 0, 0, \ + axi_dma_g1p2_regs_map0[0], axi_dma_g1p2_regs_map0[1], \ + axi_dma_g1p2_regs_map0[2], axi_dma_g1p2_regs_map0[3]), \ + .owner = GDMA_RETENTION_ENTRY }, + [1] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \ + AXI_DMA_G1P2_RETENTION_MAP_BASE_1, AXI_DMA_G1P2_RETENTION_MAP_BASE_1, \ + AXI_DMA_G1P2_RETENTION_REGS_CNT_1, 0, 0, \ + axi_dma_g1p2_regs_map1[0], axi_dma_g1p2_regs_map1[1], \ + axi_dma_g1p2_regs_map1[2], axi_dma_g1p2_regs_map1[3]), \ + .owner = GDMA_RETENTION_ENTRY }, +}; + +const gdma_chx_reg_ctx_link_t gdma_chx_regs_retention[SOC_GDMA_NUM_GROUPS_MAX][SOC_GDMA_PAIRS_PER_GROUP_MAX] = { + [0] = { + [0] = { + ahb_dma_g0p0_regs_retention, + ARRAY_SIZE(ahb_dma_g0p0_regs_retention), + SLEEP_RETENTION_MODULE_AHB_DMA_CH0, + }, + [1] = { + ahb_dma_g0p1_regs_retention, + ARRAY_SIZE(ahb_dma_g0p1_regs_retention), + SLEEP_RETENTION_MODULE_AHB_DMA_CH1, + }, + [2] = { + ahb_dma_g0p2_regs_retention, + ARRAY_SIZE(ahb_dma_g0p2_regs_retention), + SLEEP_RETENTION_MODULE_AHB_DMA_CH2, + }, + }, + [1] = { + [0] = { + axi_dma_g1p0_regs_retention, + ARRAY_SIZE(axi_dma_g1p0_regs_retention), + SLEEP_RETENTION_MODULE_AXI_DMA_CH0, + }, + [1] = { + axi_dma_g1p1_regs_retention, + ARRAY_SIZE(axi_dma_g1p1_regs_retention), + SLEEP_RETENTION_MODULE_AXI_DMA_CH1, + }, + [2] = { + axi_dma_g1p2_regs_retention, + ARRAY_SIZE(axi_dma_g1p2_regs_retention), + SLEEP_RETENTION_MODULE_AXI_DMA_CH2, + }, + } +}; diff --git a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in index ed2f427e54..32f555421e 100644 --- a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in @@ -567,6 +567,10 @@ config SOC_GDMA_SUPPORT_ETM bool default y +config SOC_GDMA_SUPPORT_SLEEP_RETENTION + bool + default y + config SOC_AXI_DMA_EXT_MEM_ENC_ALIGNMENT int default 16 @@ -1819,6 +1823,10 @@ config SOC_PM_PAU_LINK_NUM int default 4 +config SOC_PM_PAU_REGDMA_LINK_MULTI_ADDR + bool + default y + config SOC_PAU_IN_TOP_DOMAIN bool default y diff --git a/components/soc/esp32p4/include/soc/retention_periph_defs.h b/components/soc/esp32p4/include/soc/retention_periph_defs.h index 4d6c8eb19f..f70293e0f7 100644 --- a/components/soc/esp32p4/include/soc/retention_periph_defs.h +++ b/components/soc/esp32p4/include/soc/retention_periph_defs.h @@ -32,6 +32,14 @@ typedef enum periph_retention_module { SLEEP_RETENTION_MODULE_UART3 = 10, SLEEP_RETENTION_MODULE_UART4 = 11, SLEEP_RETENTION_MODULE_RMT0 = 12, + /* AHB_DMA by channel */ + SLEEP_RETENTION_MODULE_AHB_DMA_CH0 = 13, + SLEEP_RETENTION_MODULE_AHB_DMA_CH1 = 14, + SLEEP_RETENTION_MODULE_AHB_DMA_CH2 = 15, + /* AXI_DMA by channel */ + SLEEP_RETENTION_MODULE_AXI_DMA_CH0 = 16, + SLEEP_RETENTION_MODULE_AXI_DMA_CH1 = 17, + SLEEP_RETENTION_MODULE_AXI_DMA_CH2 = 18, SLEEP_RETENTION_MODULE_MAX = 31 } periph_retention_module_t; @@ -47,6 +55,14 @@ typedef enum periph_retention_module_bitmap { SLEEP_RETENTION_MODULE_BM_TG1_WDT = BIT(SLEEP_RETENTION_MODULE_TG1_WDT), SLEEP_RETENTION_MODULE_BM_TG0_TIMER = BIT(SLEEP_RETENTION_MODULE_TG0_TIMER), SLEEP_RETENTION_MODULE_BM_TG1_TIMER = BIT(SLEEP_RETENTION_MODULE_TG1_TIMER), + /* AHB_DMA by channel */ + SLEEP_RETENTION_MODULE_BM_AHB_DMA_CH0 = BIT(SLEEP_RETENTION_MODULE_AHB_DMA_CH0), + SLEEP_RETENTION_MODULE_BM_AHB_DMA_CH1 = BIT(SLEEP_RETENTION_MODULE_AHB_DMA_CH1), + SLEEP_RETENTION_MODULE_BM_AHB_DMA_CH2 = BIT(SLEEP_RETENTION_MODULE_AHB_DMA_CH2), + /* AXI_DMA by channel */ + SLEEP_RETENTION_MODULE_BM_AXI_DMA_CH0 = BIT(SLEEP_RETENTION_MODULE_AXI_DMA_CH0), + SLEEP_RETENTION_MODULE_BM_AXI_DMA_CH1 = BIT(SLEEP_RETENTION_MODULE_AXI_DMA_CH1), + SLEEP_RETENTION_MODULE_BM_AXI_DMA_CH2 = BIT(SLEEP_RETENTION_MODULE_AXI_DMA_CH2), /* MISC Peripherals */ SLEEP_RETENTION_MODULE_BM_UART0 = BIT(SLEEP_RETENTION_MODULE_UART0), SLEEP_RETENTION_MODULE_BM_UART1 = BIT(SLEEP_RETENTION_MODULE_UART1), @@ -63,6 +79,12 @@ typedef enum periph_retention_module_bitmap { | SLEEP_RETENTION_MODULE_BM_TG1_WDT \ | SLEEP_RETENTION_MODULE_BM_TG0_TIMER \ | SLEEP_RETENTION_MODULE_BM_TG1_TIMER \ + | SLEEP_RETENTION_MODULE_BM_AHB_DMA_CH0 \ + | SLEEP_RETENTION_MODULE_BM_AHB_DMA_CH1 \ + | SLEEP_RETENTION_MODULE_BM_AHB_DMA_CH2 \ + | SLEEP_RETENTION_MODULE_BM_AXI_DMA_CH0 \ + | SLEEP_RETENTION_MODULE_BM_AXI_DMA_CH1 \ + | SLEEP_RETENTION_MODULE_BM_AXI_DMA_CH2 \ | SLEEP_RETENTION_MODULE_BM_UART0 \ | SLEEP_RETENTION_MODULE_BM_UART1 \ | SLEEP_RETENTION_MODULE_BM_UART2 \ diff --git a/components/soc/esp32p4/include/soc/soc_caps.h b/components/soc/esp32p4/include/soc/soc_caps.h index f849e6f0e6..33cf1c070a 100644 --- a/components/soc/esp32p4/include/soc/soc_caps.h +++ b/components/soc/esp32p4/include/soc/soc_caps.h @@ -209,7 +209,7 @@ #define SOC_GDMA_PAIRS_PER_GROUP_MAX 3 #define SOC_AXI_GDMA_SUPPORT_PSRAM 1 #define SOC_GDMA_SUPPORT_ETM 1 -// #define SOC_GDMA_SUPPORT_SLEEP_RETENTION 1 +#define SOC_GDMA_SUPPORT_SLEEP_RETENTION 1 #define SOC_AXI_DMA_EXT_MEM_ENC_ALIGNMENT (16) /*-------------------------- 2D-DMA CAPS -------------------------------------*/ @@ -691,6 +691,7 @@ #define SOC_PM_CPU_RETENTION_BY_SW (1) #define SOC_PM_PAU_LINK_NUM (4) +#define SOC_PM_PAU_REGDMA_LINK_MULTI_ADDR (1) #define SOC_PAU_IN_TOP_DOMAIN (1) #define SOC_CPU_IN_TOP_DOMAIN (1) diff --git a/components/soc/include/soc/gdma_periph.h b/components/soc/include/soc/gdma_periph.h index 233c366ebb..4da8b042b2 100644 --- a/components/soc/include/soc/gdma_periph.h +++ b/components/soc/include/soc/gdma_periph.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -8,7 +8,10 @@ #include "soc/soc_caps.h" #include "soc/periph_defs.h" +#if SOC_PAU_SUPPORTED #include "soc/regdma.h" +#include "soc/retention_periph_defs.h" +#endif #ifdef __cplusplus extern "C" { @@ -27,10 +30,21 @@ typedef struct { extern const gdma_signal_conn_t gdma_periph_signals; -#if SOC_GDMA_SUPPORT_SLEEP_RETENTION +#if SOC_GDMA_SUPPORT_SLEEP_RETENTION && SOC_PAU_SUPPORTED +#if SOC_LIGHT_SLEEP_SUPPORTED && !CI_TEST_SW_RETENTION +#if SOC_PHY_SUPPORTED +#define GDMA_RETENTION_ENTRY (ENTRY(0) | ENTRY(2)) +#else +#define GDMA_RETENTION_ENTRY (ENTRY(0)) +#endif +#else // !SOC_LIGHT_SLEEP_SUPPORTED || CI_TEST_SW_RETENTION +#define GDMA_RETENTION_ENTRY REGDMA_SW_TRIGGER_ENTRY +#endif + typedef struct { const regdma_entries_config_t *link_list; uint32_t link_num; + periph_retention_module_t module_id; } gdma_chx_reg_ctx_link_t; extern const gdma_chx_reg_ctx_link_t gdma_chx_regs_retention[SOC_GDMA_NUM_GROUPS_MAX][SOC_GDMA_PAIRS_PER_GROUP_MAX];