From 8c52c983b48fdd719254773dfa66e932e92b59b6 Mon Sep 17 00:00:00 2001 From: Lou Tianhao Date: Mon, 17 Jun 2024 19:49:58 +0800 Subject: [PATCH 1/2] feat(esp_hw_support): support modem clock for esp32c5mp --- components/esp_hw_support/modem_clock.c | 1 + .../hal/esp32c5/include/hal/modem_lpcon_ll.h | 300 ++++++++ .../hal/esp32c5/include/hal/modem_syscon_ll.h | 664 ++++++++++++++++++ .../hal/esp32c6/include/hal/modem_syscon_ll.h | 8 +- .../hal/esp32h2/include/hal/modem_syscon_ll.h | 8 +- components/hal/include/hal/modem_clock_hal.h | 2 - .../include/modem/modem_lpcon_struct.h | 124 ++-- .../include/modem/modem_syscon_struct.h | 188 ++--- .../esp32c5/include/soc/Kconfig.soc_caps.in | 4 + components/soc/esp32c5/include/soc/soc_caps.h | 2 +- .../mp/include/modem/modem_lpcon_reg.h | 378 ---------- .../mp/include/modem/modem_lpcon_struct.h | 251 ------- .../mp/include/modem/modem_syscon_reg.h | 588 ---------------- .../mp/include/modem/modem_syscon_struct.h | 174 ----- .../soc/esp32c5/mp/include/modem/reg_base.h | 9 - 15 files changed, 1140 insertions(+), 1561 deletions(-) delete mode 100644 components/soc/esp32c5/mp/include/modem/modem_lpcon_reg.h delete mode 100644 components/soc/esp32c5/mp/include/modem/modem_lpcon_struct.h delete mode 100644 components/soc/esp32c5/mp/include/modem/modem_syscon_reg.h delete mode 100644 components/soc/esp32c5/mp/include/modem/modem_syscon_struct.h delete mode 100644 components/soc/esp32c5/mp/include/modem/reg_base.h diff --git a/components/esp_hw_support/modem_clock.c b/components/esp_hw_support/modem_clock.c index b46b5dbb46..bdbbf2690f 100644 --- a/components/esp_hw_support/modem_clock.c +++ b/components/esp_hw_support/modem_clock.c @@ -251,6 +251,7 @@ void IRAM_ATTR modem_clock_module_mac_reset(periph_module_t module) #if SOC_IEEE802154_SUPPORTED case PERIPH_IEEE802154_MODULE: modem_syscon_ll_reset_zbmac(ctx->hal->syscon_dev); + modem_syscon_ll_reset_zbmac_apb(ctx->hal->syscon_dev); break; #endif default: diff --git a/components/hal/esp32c5/include/hal/modem_lpcon_ll.h b/components/hal/esp32c5/include/hal/modem_lpcon_ll.h index 1d8b72af5a..91bd12b7c1 100644 --- a/components/hal/esp32c5/include/hal/modem_lpcon_ll.h +++ b/components/hal/esp32c5/include/hal/modem_lpcon_ll.h @@ -12,11 +12,311 @@ #include #include "soc/soc.h" #include "hal/assert.h" +#include "modem/modem_lpcon_struct.h" +#include "hal/modem_clock_types.h" #ifdef __cplusplus extern "C" { #endif +__attribute__((always_inline)) +static inline void modem_lpcon_ll_enable_test_clk(modem_lpcon_dev_t *hw, bool en) +{ + hw->test_conf.clk_en = en; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_enable_ble_rtc_timer_slow_osc(modem_lpcon_dev_t *hw, bool en) +{ + hw->lp_timer_conf.clk_lp_timer_sel_osc_slow = en; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_enable_ble_rtc_timer_fast_osc(modem_lpcon_dev_t *hw, bool en) +{ + hw->lp_timer_conf.clk_lp_timer_sel_osc_fast = en; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_enable_ble_rtc_timer_main_xtal(modem_lpcon_dev_t *hw, bool en) +{ + hw->lp_timer_conf.clk_lp_timer_sel_xtal = en; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_enable_ble_rtc_timer_32k_xtal(modem_lpcon_dev_t *hw, bool en) +{ + hw->lp_timer_conf.clk_lp_timer_sel_xtal32k = en; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_set_ble_rtc_timer_divisor_value(modem_lpcon_dev_t *hw, uint32_t value) +{ + hw->lp_timer_conf.clk_lp_timer_div_num = value; +} + +__attribute__((always_inline)) +static inline uint32_t modem_lpcon_ll_get_ble_rtc_timer_divisor_value(modem_lpcon_dev_t *hw) +{ + return hw->lp_timer_conf.clk_lp_timer_div_num; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_enable_coex_lpclk_slow_osc(modem_lpcon_dev_t *hw, bool en) +{ + hw->coex_lp_clk_conf.clk_coex_lp_sel_osc_slow = en; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_enable_coex_lpclk_fast_osc(modem_lpcon_dev_t *hw, bool en) +{ + hw->coex_lp_clk_conf.clk_coex_lp_sel_osc_fast = en; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_enable_coex_lpclk_main_xtal(modem_lpcon_dev_t *hw, bool en) +{ + hw->coex_lp_clk_conf.clk_coex_lp_sel_xtal = en; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_enable_coex_lpclk_32k_xtal(modem_lpcon_dev_t *hw, bool en) +{ + hw->coex_lp_clk_conf.clk_coex_lp_sel_xtal32k = en; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_set_coex_lpclk_divisor_value(modem_lpcon_dev_t *hw, uint32_t value) +{ + hw->coex_lp_clk_conf.clk_coex_lp_div_num = value; +} + +__attribute__((always_inline)) +static inline uint32_t modem_lpcon_ll_get_coex_lpclk_divisor_value(modem_lpcon_dev_t *hw) +{ + return hw->coex_lp_clk_conf.clk_coex_lp_div_num; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_enable_wifi_lpclk_slow_osc(modem_lpcon_dev_t *hw, bool en) +{ + hw->wifi_lp_clk_conf.clk_wifipwr_lp_sel_osc_slow = en; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_enable_wifi_lpclk_fast_osc(modem_lpcon_dev_t *hw, bool en) +{ + hw->wifi_lp_clk_conf.clk_wifipwr_lp_sel_osc_fast = en; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_enable_wifi_lpclk_main_xtal(modem_lpcon_dev_t *hw, bool en) +{ + hw->wifi_lp_clk_conf.clk_wifipwr_lp_sel_xtal = en; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_enable_wifi_lpclk_32k_xtal(modem_lpcon_dev_t *hw, bool en) +{ + hw->wifi_lp_clk_conf.clk_wifipwr_lp_sel_xtal32k = en; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_set_wifi_lpclk_divisor_value(modem_lpcon_dev_t *hw, uint32_t value) +{ + hw->wifi_lp_clk_conf.clk_wifipwr_lp_div_num = value; +} + +__attribute__((always_inline)) +static inline uint32_t modem_lpcon_ll_get_wifi_lpclk_divisor_value(modem_lpcon_dev_t *hw) +{ + return hw->wifi_lp_clk_conf.clk_wifipwr_lp_div_num; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_enable_i2c_master_160m_clock(modem_lpcon_dev_t *hw, bool en) +{ + // ESP32C5 Not Support +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_set_modem_pwr_clk_src_fo(modem_lpcon_dev_t *hw, bool value) +{ + hw->modem_src_clk_conf.modem_pwr_clk_src_fo = value; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_set_clk_modem_aon_force(modem_lpcon_dev_t *hw, uint32_t value) +{ + hw->modem_src_clk_conf.clk_modem_aon_force = value; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_select_modem_32k_clock_source(modem_lpcon_dev_t *hw, uint32_t src) +{ + hw->modem_32k_clk_conf.clk_modem_32k_sel = src; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_enable_wifipwr_clock(modem_lpcon_dev_t *hw, bool en) +{ + hw->clk_conf.clk_wifipwr_en = en; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_enable_coex_clock(modem_lpcon_dev_t *hw, bool en) +{ + hw->clk_conf.clk_coex_en = en; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_enable_i2c_master_clock(modem_lpcon_dev_t *hw, bool en) +{ + hw->clk_conf.clk_i2c_mst_en = en; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_enable_ble_rtc_timer_clock(modem_lpcon_dev_t *hw, bool en) +{ + hw->clk_conf.clk_lp_timer_en = en; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_enable_wifipwr_force_clock(modem_lpcon_dev_t *hw, bool en) +{ + hw->clk_conf_force_on.clk_wifipwr_fo = en; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_enable_coex_force_clock(modem_lpcon_dev_t *hw, bool en) +{ + hw->clk_conf_force_on.clk_coex_fo = en; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_enable_i2c_master_force_clock(modem_lpcon_dev_t *hw, bool en) +{ + hw->clk_conf_force_on.clk_i2c_mst_fo = en; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_enable_ble_rtc_timer_force_clock(modem_lpcon_dev_t *hw, bool en) +{ + hw->clk_conf_force_on.clk_lp_timer_fo = en; +} + +__attribute__((always_inline)) +static inline uint32_t modem_lpcon_ll_get_wifipwr_icg_bitmap(modem_lpcon_dev_t *hw) +{ + return hw->clk_conf_power_st.clk_wifipwr_st_map; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_set_wifipwr_icg_bitmap(modem_lpcon_dev_t *hw, uint32_t bitmap) +{ + hw->clk_conf_power_st.clk_wifipwr_st_map = bitmap; +} + +__attribute__((always_inline)) +static inline uint32_t modem_lpcon_ll_get_coex_icg_bitmap(modem_lpcon_dev_t *hw) +{ + return hw->clk_conf_power_st.clk_coex_st_map; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_set_coex_icg_bitmap(modem_lpcon_dev_t *hw, uint32_t bitmap) +{ + hw->clk_conf_power_st.clk_coex_st_map = bitmap; +} + +__attribute__((always_inline)) +static inline uint32_t modem_lpcon_ll_get_i2c_master_icg_bitmap(modem_lpcon_dev_t *hw) +{ + return hw->clk_conf_power_st.clk_i2c_mst_st_map; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_set_i2c_master_icg_bitmap(modem_lpcon_dev_t *hw, uint32_t bitmap) +{ + hw->clk_conf_power_st.clk_i2c_mst_st_map = bitmap; +} + +__attribute__((always_inline)) +static inline uint32_t modem_lpcon_ll_get_lp_apb_icg_bitmap(modem_lpcon_dev_t *hw) +{ + return hw->clk_conf_power_st.clk_lp_apb_st_map; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_set_lp_apb_icg_bitmap(modem_lpcon_dev_t *hw, uint32_t bitmap) +{ + hw->clk_conf_power_st.clk_lp_apb_st_map = bitmap; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_reset_wifipwr(modem_lpcon_dev_t *hw) +{ + hw->rst_conf.rst_wifipwr = 1; + hw->rst_conf.rst_wifipwr = 0; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_reset_coex(modem_lpcon_dev_t *hw) +{ + hw->rst_conf.rst_coex = 1; + hw->rst_conf.rst_coex = 0; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_reset_i2c_master(modem_lpcon_dev_t *hw) +{ + hw->rst_conf.rst_i2c_mst = 1; + hw->rst_conf.rst_i2c_mst = 0; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_reset_ble_rtc_timer(modem_lpcon_dev_t *hw) +{ + hw->rst_conf.rst_lp_timer = 1; + hw->rst_conf.rst_lp_timer = 0; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_reset_all(modem_lpcon_dev_t *hw) +{ + hw->rst_conf.val = 0xf; + hw->rst_conf.val = 0; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_set_pwr_tick_target(modem_lpcon_dev_t *hw, uint32_t val) +{ + hw->tick_conf.modem_pwr_tick_target = val; +} + +__attribute__((always_inline)) +static inline uint32_t modem_lpcon_ll_get_date(modem_lpcon_dev_t *hw) +{ + return hw->date.val; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_enable_chan_freq_mem(modem_lpcon_dev_t *hw, bool en) +{ + hw->apb_mem_sel.chan_freq_mem_en = en; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_enable_pbus_mem(modem_lpcon_dev_t *hw, bool en) +{ + hw->apb_mem_sel.pbus_mem_en = en; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_enable_agc_mem(modem_lpcon_dev_t *hw, bool en) +{ + hw->apb_mem_sel.agc_mem_en = en; +} #ifdef __cplusplus } diff --git a/components/hal/esp32c5/include/hal/modem_syscon_ll.h b/components/hal/esp32c5/include/hal/modem_syscon_ll.h index 6f237998ae..c1fdfafa71 100644 --- a/components/hal/esp32c5/include/hal/modem_syscon_ll.h +++ b/components/hal/esp32c5/include/hal/modem_syscon_ll.h @@ -12,11 +12,675 @@ #include #include "soc/soc.h" #include "hal/assert.h" +#include "modem/modem_syscon_struct.h" +#include "hal/modem_clock_types.h" #ifdef __cplusplus extern "C" { #endif +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_test_clk(modem_syscon_dev_t *hw, bool en) +{ + hw->test_conf.clk_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_pwdet_sar_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf.pwdet_sar_clock_ena = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_set_pwdet_clk_div_num(modem_syscon_dev_t *hw, uint32_t div) +{ + hw->clk_conf.pwdet_clk_div_num = div; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_clk_tx_dac_inv(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf.clk_tx_dac_inv_ena = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_clk_rx_dac_inv(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf.clk_rx_adc_inv_ena = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_clk_pwdet_adc_inv(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf.clk_pwdet_adc_inv_ena = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_clk_i2c_mst_sel_160m(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf.clk_i2c_mst_sel_160m = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_data_dump_mux_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf.clk_data_dump_mux = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_etm_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf.clk_etm_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_ieee802154_apb_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf.clk_zb_apb_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_ieee802154_mac_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf.clk_zbmac_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_modem_sec_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf.clk_modem_sec_en = en; + hw->clk_conf.clk_modem_sec_ecb_en = en; + hw->clk_conf.clk_modem_sec_ccm_en = en; + hw->clk_conf.clk_modem_sec_bah_en = en; + hw->clk_conf.clk_modem_sec_apb_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_ble_timer_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf.clk_ble_timer_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_data_dump_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf.clk_data_dump_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_etm_force_clock(modem_syscon_dev_t *hw) +{ + hw->clk_conf_force_on.clk_etm_fo = 1; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_ieee802154_apb_clock_force(modem_syscon_dev_t *hw) +{ + hw->clk_conf_force_on.clk_zbmac_apb_fo = 1; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_ieee802154_mac_clock_force(modem_syscon_dev_t *hw) +{ + hw->clk_conf_force_on.clk_zbmac_fo = 1; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_modem_sec_force_clock(modem_syscon_dev_t *hw) +{ + hw->clk_conf_force_on.clk_modem_sec_fo = 1; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_ble_timer_force_clock(modem_syscon_dev_t *hw) +{ + hw->clk_conf_force_on.clk_ble_timer_fo = 1; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_data_dump_force_clock(modem_syscon_dev_t *hw) +{ + hw->clk_conf_force_on.clk_data_dump_fo = 1; +} + +__attribute__((always_inline)) +static inline uint32_t modem_syscon_ll_get_ieee802154_icg_bitmap(modem_syscon_dev_t *hw) +{ + return hw->clk_conf_power_st.clk_zb_st_map; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_set_ieee802154_icg_bitmap(modem_syscon_dev_t *hw, uint32_t bitmap) +{ + hw->clk_conf_power_st.clk_zb_st_map = bitmap; +} + +__attribute__((always_inline)) +static inline uint32_t modem_syscon_ll_get_fe_icg_bitmap(modem_syscon_dev_t *hw) +{ + return hw->clk_conf_power_st.clk_fe_st_map; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_set_fe_icg_bitmap(modem_syscon_dev_t *hw, uint32_t bitmap) +{ + hw->clk_conf_power_st.clk_fe_st_map = bitmap; +} + +__attribute__((always_inline)) +static inline uint32_t modem_syscon_ll_get_bt_icg_bitmap(modem_syscon_dev_t *hw) +{ + return hw->clk_conf_power_st.clk_bt_st_map; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_set_bt_icg_bitmap(modem_syscon_dev_t *hw, uint32_t bitmap) +{ + hw->clk_conf_power_st.clk_bt_st_map = bitmap; +} + +__attribute__((always_inline)) +static inline uint32_t modem_syscon_ll_get_wifi_icg_bitmap(modem_syscon_dev_t *hw) +{ + return hw->clk_conf_power_st.clk_wifi_st_map; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_set_wifi_icg_bitmap(modem_syscon_dev_t *hw, uint32_t bitmap) +{ + hw->clk_conf_power_st.clk_wifi_st_map = bitmap; +} + +__attribute__((always_inline)) +static inline uint32_t modem_syscon_ll_get_modem_periph_icg_bitmap(modem_syscon_dev_t *hw) +{ + return hw->clk_conf_power_st.clk_modem_peri_st_map; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_set_modem_periph_icg_bitmap(modem_syscon_dev_t *hw, uint32_t bitmap) +{ + hw->clk_conf_power_st.clk_modem_peri_st_map = bitmap; +} + +__attribute__((always_inline)) +static inline uint32_t modem_syscon_ll_get_modem_apb_icg_bitmap(modem_syscon_dev_t *hw) +{ + return hw->clk_conf_power_st.clk_modem_apb_st_map; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_set_modem_apb_icg_bitmap(modem_syscon_dev_t *hw, uint32_t bitmap) +{ + hw->clk_conf_power_st.clk_modem_apb_st_map = bitmap; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_reset_wifibb(modem_syscon_dev_t *hw) +{ + hw->modem_rst_conf.rst_wifibb = 1; + hw->modem_rst_conf.rst_wifibb = 0; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_reset_wifimac(modem_syscon_dev_t *hw) +{ + hw->modem_rst_conf.rst_wifimac = 1; + hw->modem_rst_conf.rst_wifimac = 0; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_reset_fe(modem_syscon_dev_t *hw) +{ + hw->modem_rst_conf.rst_fe = 1; + hw->modem_rst_conf.rst_fe = 0; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_reset_btmac_apb(modem_syscon_dev_t *hw) +{ + hw->modem_rst_conf.rst_btmac_apb = 1; + hw->modem_rst_conf.rst_btmac_apb = 0; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_reset_btmac(modem_syscon_dev_t *hw) +{ + hw->modem_rst_conf.rst_btmac = 1; + hw->modem_rst_conf.rst_btmac = 0; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_reset_btbb_apb(modem_syscon_dev_t *hw) +{ + hw->modem_rst_conf.rst_btbb_apb = 1; + hw->modem_rst_conf.rst_btbb_apb = 0; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_reset_btbb(modem_syscon_dev_t *hw) +{ + hw->modem_rst_conf.rst_btbb = 1; + hw->modem_rst_conf.rst_btbb = 0; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_reset_etm(modem_syscon_dev_t *hw) +{ + hw->modem_rst_conf.rst_etm = 1; + hw->modem_rst_conf.rst_etm = 0; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_reset_zbmac_apb(modem_syscon_dev_t *hw) +{ + hw->modem_rst_conf.rst_zbmac_apb = 1; + hw->modem_rst_conf.rst_zbmac_apb = 0; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_reset_zbmac(modem_syscon_dev_t *hw) +{ + hw->modem_rst_conf.rst_zbmac = 1; + hw->modem_rst_conf.rst_zbmac = 0; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_reset_modem_sec(modem_syscon_dev_t *hw) +{ + hw->modem_rst_conf.rst_modem_ecb = 1; + hw->modem_rst_conf.rst_modem_ccm = 1; + hw->modem_rst_conf.rst_modem_bah = 1; + hw->modem_rst_conf.rst_modem_sec = 1; + hw->modem_rst_conf.rst_modem_ecb = 0; + hw->modem_rst_conf.rst_modem_ccm = 0; + hw->modem_rst_conf.rst_modem_bah = 0; + hw->modem_rst_conf.rst_modem_sec = 0; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_reset_ble_timer(modem_syscon_dev_t *hw) +{ + hw->modem_rst_conf.rst_ble_timer = 1; + hw->modem_rst_conf.rst_ble_timer = 0; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_reset_data_dump(modem_syscon_dev_t *hw) +{ + hw->modem_rst_conf.rst_data_dump = 1; + hw->modem_rst_conf.rst_data_dump = 0; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_reset_all(modem_syscon_dev_t *hw) +{ + hw->modem_rst_conf.val = 0xffffffff; + hw->modem_rst_conf.val = 0; +} + + +__attribute__((always_inline)) +static inline void modem_syscon_ll_clk_conf1_configure(modem_syscon_dev_t *hw, bool en, uint32_t mask) +{ + if(en){ + hw->clk_conf1.val = hw->clk_conf1.val | mask; + } else { + hw->clk_conf1.val = hw->clk_conf1.val & ~mask; + } +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_clk_wifibb_configure(modem_syscon_dev_t *hw, bool en) +{ + /* Configure + clk_wifibb_22m / clk_wifibb_40m / clk_wifibb_44m / clk_wifibb_80m + clk_wifibb_40x / clk_wifibb_80x / clk_wifibb_40x1 / clk_wifibb_80x1 + clk_wifibb_160x1 + */ + modem_syscon_ll_clk_conf1_configure(hw, en, 0x1ff); +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_wifibb_22m_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1.clk_wifibb_22m_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_wifibb_40m_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1.clk_wifibb_40m_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_wifibb_44m_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1.clk_wifibb_44m_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_wifibb_80m_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1.clk_wifibb_80m_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_wifibb_40x_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1.clk_wifibb_40x_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_wifibb_80x_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1.clk_wifibb_80x_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_wifibb_40x1_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1.clk_wifibb_40x1_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_wifibb_80x1_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1.clk_wifibb_80x1_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_wifibb_160x1_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1.clk_wifibb_160x1_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_wifibb_480m_clock(modem_syscon_dev_t *hw, bool en) +{ + HAL_ASSERT(0 && "not implemented yet"); + // hw->clk_conf1.clk_wifibb_480m_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_wifi_mac_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1.clk_wifimac_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_wifi_apb_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1.clk_wifi_apb_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_fe_20m_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1.clk_fe_20m_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_fe_40m_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1.clk_fe_40m_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_fe_80m_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1.clk_fe_80m_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_fe_160m_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1.clk_fe_160m_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_fe_apb_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1.clk_fe_apb_en = en; +} + +// The modem_syscon of esp32c5 adds the enablement of the adc clock on the analog front end compared to esp32h2 and esp32c6. +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_fe_adc_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1.clk_fe_adc_en = en; +} + +// The modem_syscon of esp32c5 adds the enablement of the dac clock on the analog front end compared to esp32h2 and esp32c6. +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_fe_dac_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1.clk_fe_dac_en = en; +} + +// The modem_syscon of esp32c5 adds the enablement of the analog power detect clock on the analog front end compared to esp32h2 and esp32c6. +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_fe_pwdet_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1.clk_fe_pwdet_adc_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_bt_apb_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1.clk_bt_apb_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_bt_mac_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1.clk_btmac_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_bt_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1.clk_btbb_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_fe_480m_clock(modem_syscon_dev_t *hw, bool en) +{ + HAL_ASSERT(0 && "not implemented yet"); + // hw->clk_conf1.clk_fe_480m_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_fe_anamode_40m_clock(modem_syscon_dev_t *hw, bool en) +{ + HAL_ASSERT(0 && "not implemented yet"); + // hw->clk_conf1.clk_fe_anamode_40m_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_fe_anamode_80m_clock(modem_syscon_dev_t *hw, bool en) +{ + HAL_ASSERT(0 && "not implemented yet"); + // hw->clk_conf1.clk_fe_anamode_80m_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_fe_anamode_160m_clock(modem_syscon_dev_t *hw, bool en) +{ + HAL_ASSERT(0 && "not implemented yet"); + // hw->clk_conf1.clk_fe_anamode_160m_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_wifibb_22m_force_clock(modem_syscon_dev_t *hw, bool en) +{ + HAL_ASSERT(0 && "not implemented yet"); + // hw->clk_conf1_force_on.clk_wifibb_22m_fo = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_wifibb_40m_force_clock(modem_syscon_dev_t *hw, bool en) +{ + HAL_ASSERT(0 && "not implemented yet"); + // hw->clk_conf1_force_on.clk_wifibb_40m_fo = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_wifibb_44m_force_clock(modem_syscon_dev_t *hw, bool en) +{ + HAL_ASSERT(0 && "not implemented yet"); + // hw->clk_conf1_force_on.clk_wifibb_44m_fo = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_wifibb_80m_force_clock(modem_syscon_dev_t *hw, bool en) +{ + HAL_ASSERT(0 && "not implemented yet"); + // hw->clk_conf1_force_on.clk_wifibb_80m_fo = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_wifibb_40x_force_clock(modem_syscon_dev_t *hw, bool en) +{ + HAL_ASSERT(0 && "not implemented yet"); + // hw->clk_conf1_force_on.clk_wifibb_40x_fo = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_wifibb_80x_force_clock(modem_syscon_dev_t *hw, bool en) +{ + HAL_ASSERT(0 && "not implemented yet"); + // hw->clk_conf1_force_on.clk_wifibb_80x_fo = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_wifibb_40x1_force_clock(modem_syscon_dev_t *hw, bool en) +{ + HAL_ASSERT(0 && "not implemented yet"); + // hw->clk_conf1_force_on.clk_wifibb_40x1_fo = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_wifibb_80x1_force_clock(modem_syscon_dev_t *hw, bool en) +{ + HAL_ASSERT(0 && "not implemented yet"); + // hw->clk_conf1_force_on.clk_wifibb_80x1_fo = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_wifibb_160x1_force_clock(modem_syscon_dev_t *hw, bool en) +{ + HAL_ASSERT(0 && "not implemented yet"); + // hw->clk_conf1_force_on.clk_wifibb_160x1_fo = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_wifibb_480m_force_clock(modem_syscon_dev_t *hw, bool en) +{ + HAL_ASSERT(0 && "not implemented yet"); +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_wifi_mac_force_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf_force_on.clk_wifimac_fo = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_wifi_apb_force_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf_force_on.clk_wifi_apb_fo = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_fe_20m_force_clock(modem_syscon_dev_t *hw, bool en) +{ + HAL_ASSERT(0 && "not implemented yet"); + // hw->clk_conf1_force_on.clk_fe_20m_fo = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_fe_40m_force_clock(modem_syscon_dev_t *hw, bool en) +{ + HAL_ASSERT(0 && "not implemented yet"); + // hw->clk_conf1_force_on.clk_fe_40m_fo = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_fe_80m_force_clock(modem_syscon_dev_t *hw, bool en) +{ + HAL_ASSERT(0 && "not implemented yet"); + // hw->clk_conf1_force_on.clk_fe_80m_fo = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_fe_160m_force_clock(modem_syscon_dev_t *hw, bool en) +{ + HAL_ASSERT(0 && "not implemented yet"); + // hw->clk_conf1_force_on.clk_fe_160m_fo = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_fe_cal_160m_force_clock(modem_syscon_dev_t *hw, bool en) +{ + HAL_ASSERT(0 && "not implemented yet"); + // hw->clk_conf1_force_on.clk_fe_cal_160m_fo = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_fe_apb_force_clock(modem_syscon_dev_t *hw, bool en) +{ + HAL_ASSERT(0 && "not implemented yet"); + // hw->clk_conf1_force_on.clk_fe_apb_fo = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_bt_apb_force_clock(modem_syscon_dev_t *hw, bool en) +{ + HAL_ASSERT(0 && "not implemented yet"); + // hw->clk_conf1_force_on.clk_bt_apb_fo = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_bt_force_clock(modem_syscon_dev_t *hw, bool en) +{ + HAL_ASSERT(0 && "not implemented yet"); + // hw->clk_conf1_force_on.clk_bt_fo = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_fe_480m_force_clock(modem_syscon_dev_t *hw, bool en) +{ + HAL_ASSERT(0 && "not implemented yet"); + // hw->clk_conf1_force_on.clk_fe_480m_fo = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_fe_anamode_40m_force_clock(modem_syscon_dev_t *hw, bool en) +{ + HAL_ASSERT(0 && "not implemented yet"); + // hw->clk_conf1_force_on.clk_fe_anamode_40m_fo = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_fe_anamode_80m_force_clock(modem_syscon_dev_t *hw, bool en) +{ + HAL_ASSERT(0 && "not implemented yet"); + // hw->clk_conf1_force_on.clk_fe_anamode_80m_fo = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_fe_anamode_160m_force_clock(modem_syscon_dev_t *hw, bool en) +{ + HAL_ASSERT(0 && "not implemented yet"); + // hw->clk_conf1_force_on.clk_fe_anamode_160m_fo = en; +} + +__attribute__((always_inline)) +static inline uint32_t modem_syscon_ll_get_date(modem_syscon_dev_t *hw) +{ + return hw->date.val; +} #ifdef __cplusplus } diff --git a/components/hal/esp32c6/include/hal/modem_syscon_ll.h b/components/hal/esp32c6/include/hal/modem_syscon_ll.h index 169f8b4022..27ad9187fe 100644 --- a/components/hal/esp32c6/include/hal/modem_syscon_ll.h +++ b/components/hal/esp32c6/include/hal/modem_syscon_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -242,6 +242,12 @@ static inline void modem_syscon_ll_reset_zbmac(modem_syscon_dev_t *hw) hw->modem_rst_conf.rst_zbmac = 0; } +__attribute__((always_inline)) +static inline void modem_syscon_ll_reset_zbmac_apb(modem_syscon_dev_t *hw) +{ + // ESP32C6 Not Support +} + __attribute__((always_inline)) static inline void modem_syscon_ll_reset_modem_sec(modem_syscon_dev_t *hw) { diff --git a/components/hal/esp32h2/include/hal/modem_syscon_ll.h b/components/hal/esp32h2/include/hal/modem_syscon_ll.h index 9f214db8ee..9d6f3e8bbe 100644 --- a/components/hal/esp32h2/include/hal/modem_syscon_ll.h +++ b/components/hal/esp32h2/include/hal/modem_syscon_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -151,6 +151,12 @@ static inline void modem_syscon_ll_reset_zbmac(modem_syscon_dev_t *hw) hw->modem_rst_conf.rst_zbmac = 0; } +__attribute__((always_inline)) +static inline void modem_syscon_ll_reset_zbmac_apb(modem_syscon_dev_t *hw) +{ + // ESP32H2 Not Support +} + __attribute__((always_inline)) static inline void modem_syscon_ll_reset_modem_sec(modem_syscon_dev_t *hw) { diff --git a/components/hal/include/hal/modem_clock_hal.h b/components/hal/include/hal/modem_clock_hal.h index 3bed2c72b3..dfc5009741 100644 --- a/components/hal/include/hal/modem_clock_hal.h +++ b/components/hal/include/hal/modem_clock_hal.h @@ -19,12 +19,10 @@ extern "C" { #endif -#if !CONFIG_IDF_TARGET_ESP32C5 typedef struct { modem_syscon_dev_t *syscon_dev; modem_lpcon_dev_t *lpcon_dev; } modem_clock_hal_context_t; -#endif #if !CONFIG_IDF_TARGET_ESP32H2 //TODO: PM-92 void modem_clock_hal_set_clock_domain_icg_bitmap(modem_clock_hal_context_t *hal, modem_clock_domain_t domain, uint32_t bitmap); diff --git a/components/soc/esp32c5/include/modem/modem_lpcon_struct.h b/components/soc/esp32c5/include/modem/modem_lpcon_struct.h index cb8e4ff8a5..8ce1a6ab15 100644 --- a/components/soc/esp32c5/include/modem/modem_lpcon_struct.h +++ b/components/soc/esp32c5/include/modem/modem_lpcon_struct.h @@ -13,7 +13,7 @@ extern "C" { typedef volatile struct { union { struct { - uint32_t reg_clk_en : 1; + uint32_t clk_en : 1; uint32_t reserved1 : 1; uint32_t reserved2 : 30; }; @@ -21,58 +21,58 @@ typedef volatile struct { } test_conf; union { struct { - uint32_t reg_clk_lp_timer_sel_osc_slow : 1; - uint32_t reg_clk_lp_timer_sel_osc_fast : 1; - uint32_t reg_clk_lp_timer_sel_xtal : 1; - uint32_t reg_clk_lp_timer_sel_xtal32k : 1; - uint32_t reg_clk_lp_timer_div_num : 12; + uint32_t clk_lp_timer_sel_osc_slow : 1; + uint32_t clk_lp_timer_sel_osc_fast : 1; + uint32_t clk_lp_timer_sel_xtal : 1; + uint32_t clk_lp_timer_sel_xtal32k : 1; + uint32_t clk_lp_timer_div_num : 12; uint32_t reserved16 : 16; }; uint32_t val; } lp_timer_conf; union { struct { - uint32_t reg_clk_coex_lp_sel_osc_slow : 1; - uint32_t reg_clk_coex_lp_sel_osc_fast : 1; - uint32_t reg_clk_coex_lp_sel_xtal : 1; - uint32_t reg_clk_coex_lp_sel_xtal32k : 1; - uint32_t reg_clk_coex_lp_div_num : 12; + uint32_t clk_coex_lp_sel_osc_slow : 1; + uint32_t clk_coex_lp_sel_osc_fast : 1; + uint32_t clk_coex_lp_sel_xtal : 1; + uint32_t clk_coex_lp_sel_xtal32k : 1; + uint32_t clk_coex_lp_div_num : 12; uint32_t reserved16 : 16; }; uint32_t val; } coex_lp_clk_conf; union { struct { - uint32_t reg_clk_wifipwr_lp_sel_osc_slow: 1; - uint32_t reg_clk_wifipwr_lp_sel_osc_fast: 1; - uint32_t reg_clk_wifipwr_lp_sel_xtal : 1; - uint32_t reg_clk_wifipwr_lp_sel_xtal32k: 1; - uint32_t reg_clk_wifipwr_lp_div_num : 12; + uint32_t clk_wifipwr_lp_sel_osc_slow: 1; + uint32_t clk_wifipwr_lp_sel_osc_fast: 1; + uint32_t clk_wifipwr_lp_sel_xtal : 1; + uint32_t clk_wifipwr_lp_sel_xtal32k: 1; + uint32_t clk_wifipwr_lp_div_num : 12; uint32_t reserved16 : 16; }; uint32_t val; } wifi_lp_clk_conf; union { struct { - uint32_t reg_clk_modem_aon_force : 2; - uint32_t reg_modem_pwr_clk_src_fo : 1; + uint32_t clk_modem_aon_force : 2; + uint32_t modem_pwr_clk_src_fo : 1; uint32_t reserved3 : 29; }; uint32_t val; } modem_src_clk_conf; union { struct { - uint32_t reg_clk_modem_32k_sel : 2; - uint32_t reserved2 : 30; + uint32_t clk_modem_32k_sel : 2; + uint32_t reserved2 : 30; }; uint32_t val; } modem_32k_clk_conf; union { struct { - uint32_t reg_clk_wifipwr_en : 1; - uint32_t reg_clk_coex_en : 1; - uint32_t reg_clk_i2c_mst_en : 1; - uint32_t reg_clk_lp_timer_en : 1; + uint32_t clk_wifipwr_en : 1; + uint32_t clk_coex_en : 1; + uint32_t clk_i2c_mst_en : 1; + uint32_t clk_lp_timer_en : 1; uint32_t reserved4 : 1; uint32_t reserved5 : 1; uint32_t reserved6 : 1; @@ -106,11 +106,11 @@ typedef volatile struct { } clk_conf; union { struct { - uint32_t reg_clk_wifipwr_fo : 1; - uint32_t reg_clk_coex_fo : 1; - uint32_t reg_clk_i2c_mst_fo : 1; - uint32_t reg_clk_lp_timer_fo : 1; - uint32_t reg_clk_fe_mem_fo : 1; + uint32_t clk_wifipwr_fo : 1; + uint32_t clk_coex_fo : 1; + uint32_t clk_i2c_mst_fo : 1; + uint32_t clk_lp_timer_fo : 1; + uint32_t clk_fe_mem_fo : 1; uint32_t reserved5 : 1; uint32_t reserved6 : 1; uint32_t reserved7 : 1; @@ -144,19 +144,19 @@ typedef volatile struct { union { struct { uint32_t reserved0 : 16; - uint32_t reg_clk_wifipwr_st_map : 4; - uint32_t reg_clk_coex_st_map : 4; - uint32_t reg_clk_i2c_mst_st_map : 4; - uint32_t reg_clk_lp_apb_st_map : 4; + uint32_t clk_wifipwr_st_map : 4; + uint32_t clk_coex_st_map : 4; + uint32_t clk_i2c_mst_st_map : 4; + uint32_t clk_lp_apb_st_map : 4; }; uint32_t val; } clk_conf_power_st; union { struct { - uint32_t reg_rst_wifipwr : 1; - uint32_t reg_rst_coex : 1; - uint32_t reg_rst_i2c_mst : 1; - uint32_t reg_rst_lp_timer : 1; + uint32_t rst_wifipwr : 1; + uint32_t rst_coex : 1; + uint32_t rst_i2c_mst : 1; + uint32_t rst_lp_timer : 1; uint32_t reserved4 : 1; uint32_t reserved5 : 1; uint32_t reserved6 : 1; @@ -190,33 +190,33 @@ typedef volatile struct { } rst_conf; union { struct { - uint32_t reg_modem_pwr_tick_target : 6; + uint32_t modem_pwr_tick_target : 6; uint32_t reserved6 : 26; }; uint32_t val; } tick_conf; union { struct { - uint32_t reg_dc_mem_mode : 3; - uint32_t reg_dc_mem_force : 1; - uint32_t reg_agc_mem_mode : 3; - uint32_t reg_agc_mem_force : 1; - uint32_t reg_pbus_mem_mode : 3; - uint32_t reg_pbus_mem_force : 1; - uint32_t reg_bc_mem_mode : 3; - uint32_t reg_bc_mem_force : 1; - uint32_t reg_i2c_mst_mem_mode : 3; - uint32_t reg_i2c_mst_mem_force : 1; - uint32_t reg_chan_freq_mem_mode : 3; - uint32_t reg_chan_freq_mem_force : 1; - uint32_t reserved24 : 1; - uint32_t reserved25 : 1; - uint32_t reserved26 : 1; - uint32_t reserved27 : 1; - uint32_t reserved28 : 1; - uint32_t reserved29 : 1; - uint32_t reserved30 : 1; - uint32_t reserved31 : 1; + uint32_t dc_mem_mode : 3; + uint32_t dc_mem_force : 1; + uint32_t agc_mem_mode : 3; + uint32_t agc_mem_force : 1; + uint32_t pbus_mem_mode : 3; + uint32_t pbus_mem_force : 1; + uint32_t bc_mem_mode : 3; + uint32_t bc_mem_force : 1; + uint32_t i2c_mst_mem_mode : 3; + uint32_t i2c_mst_mem_force : 1; + uint32_t chan_freq_mem_mode : 3; + uint32_t chan_freq_mem_force : 1; + uint32_t reserved24 : 1; + uint32_t reserved25 : 1; + uint32_t reserved26 : 1; + uint32_t reserved27 : 1; + uint32_t reserved28 : 1; + uint32_t reserved29 : 1; + uint32_t reserved30 : 1; + uint32_t reserved31 : 1; }; uint32_t val; } mem_conf; @@ -224,16 +224,16 @@ typedef volatile struct { uint32_t mem_rf2_aux_ctrl; union { struct { - uint32_t reg_chan_freq_mem_en : 1; - uint32_t reg_pbus_mem_en : 1; - uint32_t reg_agc_mem_en : 1; + uint32_t chan_freq_mem_en : 1; + uint32_t pbus_mem_en : 1; + uint32_t agc_mem_en : 1; uint32_t reserved3 : 29; }; uint32_t val; } apb_mem_sel; union { struct { - uint32_t reg_date : 28; + uint32_t date : 28; uint32_t reserved28 : 4; }; uint32_t val; diff --git a/components/soc/esp32c5/include/modem/modem_syscon_struct.h b/components/soc/esp32c5/include/modem/modem_syscon_struct.h index b7086ad37a..3e42205e60 100644 --- a/components/soc/esp32c5/include/modem/modem_syscon_struct.h +++ b/components/soc/esp32c5/include/modem/modem_syscon_struct.h @@ -13,76 +13,76 @@ extern "C" { typedef volatile struct { union { struct { - uint32_t reg_clk_en : 1; - uint32_t reg_modem_ant_force_sel_bt : 1; - uint32_t reg_modem_ant_force_sel_wifi : 1; - uint32_t reg_fpga_debug_clkswitch : 1; - uint32_t reg_fpga_debug_clk80 : 1; - uint32_t reg_fpga_debug_clk40 : 1; - uint32_t reg_fpga_debug_clk20 : 1; - uint32_t reg_fpga_debug_clk10 : 1; - uint32_t reg_modem_mem_mode_force : 1; - uint32_t reserved9 : 23; + uint32_t clk_en : 1; + uint32_t modem_ant_force_sel_bt : 1; + uint32_t modem_ant_force_sel_wifi : 1; + uint32_t fpga_debug_clkswitch : 1; + uint32_t fpga_debug_clk80 : 1; + uint32_t fpga_debug_clk40 : 1; + uint32_t fpga_debug_clk20 : 1; + uint32_t fpga_debug_clk10 : 1; + uint32_t modem_mem_mode_force : 1; + uint32_t reserved9 : 23; }; uint32_t val; } test_conf; union { struct { - uint32_t reg_pwdet_sar_clock_ena : 1; - uint32_t reg_pwdet_clk_div_num : 8; - uint32_t reg_clk_tx_dac_inv_ena : 1; - uint32_t reg_clk_rx_adc_inv_ena : 1; - uint32_t reg_clk_pwdet_adc_inv_ena : 1; - uint32_t reg_clk_i2c_mst_sel_160m : 1; - uint32_t reserved13 : 8; - uint32_t reg_clk_data_dump_mux : 1; - uint32_t reg_clk_etm_en : 1; - uint32_t reg_clk_zb_apb_en : 1; - uint32_t reg_clk_zbmac_en : 1; - uint32_t reg_clk_modem_sec_ecb_en : 1; - uint32_t reg_clk_modem_sec_ccm_en : 1; - uint32_t reg_clk_modem_sec_bah_en : 1; - uint32_t reg_clk_modem_sec_apb_en : 1; - uint32_t reg_clk_modem_sec_en : 1; - uint32_t reg_clk_ble_timer_en : 1; - uint32_t reg_clk_data_dump_en : 1; + uint32_t pwdet_sar_clock_ena : 1; + uint32_t pwdet_clk_div_num : 8; + uint32_t clk_tx_dac_inv_ena : 1; + uint32_t clk_rx_adc_inv_ena : 1; + uint32_t clk_pwdet_adc_inv_ena : 1; + uint32_t clk_i2c_mst_sel_160m : 1; + uint32_t reserved13 : 8; + uint32_t clk_data_dump_mux : 1; + uint32_t clk_etm_en : 1; + uint32_t clk_zb_apb_en : 1; + uint32_t clk_zbmac_en : 1; + uint32_t clk_modem_sec_ecb_en : 1; + uint32_t clk_modem_sec_ccm_en : 1; + uint32_t clk_modem_sec_bah_en : 1; + uint32_t clk_modem_sec_apb_en : 1; + uint32_t clk_modem_sec_en : 1; + uint32_t clk_ble_timer_en : 1; + uint32_t clk_data_dump_en : 1; }; uint32_t val; } clk_conf; union { struct { - uint32_t reg_clk_wifibb_fo : 1; - uint32_t reg_clk_wifimac_fo : 1; - uint32_t reg_clk_wifi_apb_fo : 1; - uint32_t reg_clk_fe_fo : 1; - uint32_t reg_clk_fe_apb_fo : 1; - uint32_t reg_clk_btbb_fo : 1; - uint32_t reg_clk_btmac_fo : 1; - uint32_t reg_clk_bt_apb_fo : 1; - uint32_t reg_clk_zbmac_fo : 1; - uint32_t reg_clk_zbmac_apb_fo : 1; + uint32_t clk_wifibb_fo : 1; + uint32_t clk_wifimac_fo : 1; + uint32_t clk_wifi_apb_fo : 1; + uint32_t clk_fe_fo : 1; + uint32_t clk_fe_apb_fo : 1; + uint32_t clk_btbb_fo : 1; + uint32_t clk_btmac_fo : 1; + uint32_t clk_bt_apb_fo : 1; + uint32_t clk_zbmac_fo : 1; + uint32_t clk_zbmac_apb_fo : 1; uint32_t reserved10 : 13; uint32_t reserved23 : 1; uint32_t reserved24 : 1; uint32_t reserved25 : 1; uint32_t reserved26 : 1; uint32_t reserved27 : 1; - uint32_t reg_clk_etm_fo : 1; - uint32_t reg_clk_modem_sec_fo : 1; - uint32_t reg_clk_ble_timer_fo : 1; - uint32_t reg_clk_data_dump_fo : 1; + uint32_t clk_etm_fo : 1; + uint32_t clk_modem_sec_fo : 1; + uint32_t clk_ble_timer_fo : 1; + uint32_t clk_data_dump_fo : 1; }; uint32_t val; } clk_conf_force_on; union { struct { uint32_t reserved0 : 8; - uint32_t reg_clk_zb_st_map : 4; - uint32_t reg_clk_fe_st_map : 4; - uint32_t reg_clk_bt_st_map : 4; - uint32_t reg_clk_wifi_st_map : 4; - uint32_t reg_clk_modem_peri_st_map : 4; - uint32_t reg_clk_modem_apb_st_map : 4; + uint32_t clk_zb_st_map : 4; + uint32_t clk_fe_st_map : 4; + uint32_t clk_bt_st_map : 4; + uint32_t clk_wifi_st_map : 4; + uint32_t clk_modem_peri_st_map : 4; + uint32_t clk_modem_apb_st_map : 4; }; uint32_t val; } clk_conf_power_st; @@ -96,58 +96,58 @@ typedef volatile struct { uint32_t reserved5 : 1; uint32_t reserved6 : 1; uint32_t reserved7 : 1; - uint32_t reg_rst_wifibb : 1; - uint32_t reg_rst_wifimac : 1; - uint32_t reg_rst_fe_pwdet_adc : 1; - uint32_t reg_rst_fe_dac : 1; - uint32_t reg_rst_fe_adc : 1; - uint32_t reg_rst_fe_ahb : 1; - uint32_t reg_rst_fe : 1; - uint32_t reg_rst_btmac_apb : 1; - uint32_t reg_rst_btmac : 1; - uint32_t reg_rst_btbb_apb : 1; - uint32_t reg_rst_btbb : 1; + uint32_t rst_wifibb : 1; + uint32_t rst_wifimac : 1; + uint32_t rst_fe_pwdet_adc : 1; + uint32_t rst_fe_dac : 1; + uint32_t rst_fe_adc : 1; + uint32_t rst_fe_ahb : 1; + uint32_t rst_fe : 1; + uint32_t rst_btmac_apb : 1; + uint32_t rst_btmac : 1; + uint32_t rst_btbb_apb : 1; + uint32_t rst_btbb : 1; uint32_t reserved19 : 3; - uint32_t reg_rst_etm : 1; - uint32_t reg_rst_zbmac_apb : 1; - uint32_t reg_rst_zbmac : 1; - uint32_t reg_rst_modem_ecb : 1; - uint32_t reg_rst_modem_ccm : 1; - uint32_t reg_rst_modem_bah : 1; + uint32_t rst_etm : 1; + uint32_t rst_zbmac_apb : 1; + uint32_t rst_zbmac : 1; + uint32_t rst_modem_ecb : 1; + uint32_t rst_modem_ccm : 1; + uint32_t rst_modem_bah : 1; uint32_t reserved28 : 1; - uint32_t reg_rst_modem_sec : 1; - uint32_t reg_rst_ble_timer : 1; - uint32_t reg_rst_data_dump : 1; + uint32_t rst_modem_sec : 1; + uint32_t rst_ble_timer : 1; + uint32_t rst_data_dump : 1; }; uint32_t val; } modem_rst_conf; union { struct { - uint32_t reg_clk_wifibb_22m_en : 1; - uint32_t reg_clk_wifibb_40m_en : 1; - uint32_t reg_clk_wifibb_44m_en : 1; - uint32_t reg_clk_wifibb_80m_en : 1; - uint32_t reg_clk_wifibb_40x_en : 1; - uint32_t reg_clk_wifibb_80x_en : 1; - uint32_t reg_clk_wifibb_40x1_en : 1; - uint32_t reg_clk_wifibb_80x1_en : 1; - uint32_t reg_clk_wifibb_160x1_en : 1; - uint32_t reg_clk_wifimac_en : 1; - uint32_t reg_clk_wifi_apb_en : 1; - uint32_t reg_clk_fe_20m_en : 1; - uint32_t reg_clk_fe_40m_en : 1; - uint32_t reg_clk_fe_80m_en : 1; - uint32_t reg_clk_fe_160m_en : 1; - uint32_t reg_clk_fe_apb_en : 1; - uint32_t reg_clk_bt_apb_en : 1; - uint32_t reg_clk_btbb_en : 1; - uint32_t reg_clk_btmac_en : 1; - uint32_t reg_clk_fe_pwdet_adc_en : 1; - uint32_t reg_clk_fe_adc_en : 1; - uint32_t reg_clk_fe_dac_en : 1; - uint32_t reserved22 : 1; - uint32_t reserved23 : 1; - uint32_t reserved24 : 8; + uint32_t clk_wifibb_22m_en : 1; + uint32_t clk_wifibb_40m_en : 1; + uint32_t clk_wifibb_44m_en : 1; + uint32_t clk_wifibb_80m_en : 1; + uint32_t clk_wifibb_40x_en : 1; + uint32_t clk_wifibb_80x_en : 1; + uint32_t clk_wifibb_40x1_en : 1; + uint32_t clk_wifibb_80x1_en : 1; + uint32_t clk_wifibb_160x1_en : 1; + uint32_t clk_wifimac_en : 1; + uint32_t clk_wifi_apb_en : 1; + uint32_t clk_fe_20m_en : 1; + uint32_t clk_fe_40m_en : 1; + uint32_t clk_fe_80m_en : 1; + uint32_t clk_fe_160m_en : 1; + uint32_t clk_fe_apb_en : 1; + uint32_t clk_bt_apb_en : 1; + uint32_t clk_btbb_en : 1; + uint32_t clk_btmac_en : 1; + uint32_t clk_fe_pwdet_adc_en : 1; + uint32_t clk_fe_adc_en : 1; + uint32_t clk_fe_dac_en : 1; + uint32_t reserved22 : 1; + uint32_t reserved23 : 1; + uint32_t reserved24 : 8; }; uint32_t val; } clk_conf1; @@ -156,7 +156,7 @@ typedef volatile struct { uint32_t mem_rf2_conf; union { struct { - uint32_t reg_date : 28; + uint32_t date : 28; uint32_t reserved28 : 4; }; uint32_t val; diff --git a/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in index e36ec0f749..1a6f17ef09 100644 --- a/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in @@ -119,6 +119,10 @@ config SOC_ECDSA_SUPPORTED bool default y +config SOC_MODEM_CLOCK_SUPPORTED + bool + default y + config SOC_XTAL_SUPPORT_40M bool default y diff --git a/components/soc/esp32c5/include/soc/soc_caps.h b/components/soc/esp32c5/include/soc/soc_caps.h index 9f2762b069..42ba9beffe 100644 --- a/components/soc/esp32c5/include/soc/soc_caps.h +++ b/components/soc/esp32c5/include/soc/soc_caps.h @@ -72,7 +72,7 @@ #define SOC_ECDSA_SUPPORTED 1 // #define SOC_KEY_MANAGER_SUPPORTED 1 // TODO: [ESP32C5] IDF-8621 // #define SOC_HUK_SUPPORTED 1 // TODO: [ESP32C5] IDF-8617 -// #define SOC_MODEM_CLOCK_SUPPORTED 1 // TODO: [ESP32C5] IDF-8845 +#define SOC_MODEM_CLOCK_SUPPORTED 1 // #define SOC_PM_SUPPORTED 1 // TODO: [ESP32C5] IDF-8643 /*-------------------------- XTAL CAPS ---------------------------------------*/ diff --git a/components/soc/esp32c5/mp/include/modem/modem_lpcon_reg.h b/components/soc/esp32c5/mp/include/modem/modem_lpcon_reg.h deleted file mode 100644 index 2e16b2e54c..0000000000 --- a/components/soc/esp32c5/mp/include/modem/modem_lpcon_reg.h +++ /dev/null @@ -1,378 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#include "modem/reg_base.h" -#ifdef __cplusplus -extern "C" { -#endif - -#define MODEM_LPCON_TEST_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x0) -/* MODEM_LPCON_CLK_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_EN (BIT(0)) -#define MODEM_LPCON_CLK_EN_M (BIT(0)) -#define MODEM_LPCON_CLK_EN_V 0x1 -#define MODEM_LPCON_CLK_EN_S 0 - -#define MODEM_LPCON_LP_TIMER_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x4) -/* MODEM_LPCON_CLK_LP_TIMER_DIV_NUM : R/W ;bitpos:[15:4] ;default: 12'h0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_LP_TIMER_DIV_NUM 0x00000FFF -#define MODEM_LPCON_CLK_LP_TIMER_DIV_NUM_M ((MODEM_LPCON_CLK_LP_TIMER_DIV_NUM_V)<<(MODEM_LPCON_CLK_LP_TIMER_DIV_NUM_S)) -#define MODEM_LPCON_CLK_LP_TIMER_DIV_NUM_V 0xFFF -#define MODEM_LPCON_CLK_LP_TIMER_DIV_NUM_S 4 -/* MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K (BIT(3)) -#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K_M (BIT(3)) -#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K_V 0x1 -#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K_S 3 -/* MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL (BIT(2)) -#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL_M (BIT(2)) -#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL_V 0x1 -#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL_S 2 -/* MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST (BIT(1)) -#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST_M (BIT(1)) -#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST_V 0x1 -#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST_S 1 -/* MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW (BIT(0)) -#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW_M (BIT(0)) -#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW_V 0x1 -#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW_S 0 - -#define MODEM_LPCON_COEX_LP_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x8) -/* MODEM_LPCON_CLK_COEX_LP_DIV_NUM : R/W ;bitpos:[15:4] ;default: 12'h0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_COEX_LP_DIV_NUM 0x00000FFF -#define MODEM_LPCON_CLK_COEX_LP_DIV_NUM_M ((MODEM_LPCON_CLK_COEX_LP_DIV_NUM_V)<<(MODEM_LPCON_CLK_COEX_LP_DIV_NUM_S)) -#define MODEM_LPCON_CLK_COEX_LP_DIV_NUM_V 0xFFF -#define MODEM_LPCON_CLK_COEX_LP_DIV_NUM_S 4 -/* MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K (BIT(3)) -#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K_M (BIT(3)) -#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K_V 0x1 -#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K_S 3 -/* MODEM_LPCON_CLK_COEX_LP_SEL_XTAL : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL (BIT(2)) -#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL_M (BIT(2)) -#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL_V 0x1 -#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL_S 2 -/* MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST (BIT(1)) -#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST_M (BIT(1)) -#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST_V 0x1 -#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST_S 1 -/* MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW (BIT(0)) -#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW_M (BIT(0)) -#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW_V 0x1 -#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW_S 0 - -#define MODEM_LPCON_WIFI_LP_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0xC) -/* MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM : R/W ;bitpos:[15:4] ;default: 12'h0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM 0x00000FFF -#define MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM_M ((MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM_V)<<(MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM_S)) -#define MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM_V 0xFFF -#define MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM_S 4 -/* MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K (BIT(3)) -#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K_M (BIT(3)) -#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K_V 0x1 -#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K_S 3 -/* MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL (BIT(2)) -#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL_M (BIT(2)) -#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL_V 0x1 -#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL_S 2 -/* MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST (BIT(1)) -#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST_M (BIT(1)) -#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST_V 0x1 -#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST_S 1 -/* MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW (BIT(0)) -#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW_M (BIT(0)) -#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW_V 0x1 -#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW_S 0 - -#define MODEM_LPCON_MODEM_SRC_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x10) -/* MODEM_LPCON_MODEM_PWR_CLK_SRC_FO : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_MODEM_PWR_CLK_SRC_FO (BIT(2)) -#define MODEM_LPCON_MODEM_PWR_CLK_SRC_FO_M (BIT(2)) -#define MODEM_LPCON_MODEM_PWR_CLK_SRC_FO_V 0x1 -#define MODEM_LPCON_MODEM_PWR_CLK_SRC_FO_S 2 -/* MODEM_LPCON_CLK_MODEM_AON_FORCE : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_MODEM_AON_FORCE 0x00000003 -#define MODEM_LPCON_CLK_MODEM_AON_FORCE_M ((MODEM_LPCON_CLK_MODEM_AON_FORCE_V)<<(MODEM_LPCON_CLK_MODEM_AON_FORCE_S)) -#define MODEM_LPCON_CLK_MODEM_AON_FORCE_V 0x3 -#define MODEM_LPCON_CLK_MODEM_AON_FORCE_S 0 - -#define MODEM_LPCON_MODEM_32K_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x14) -/* MODEM_LPCON_CLK_MODEM_32K_SEL : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_MODEM_32K_SEL 0x00000003 -#define MODEM_LPCON_CLK_MODEM_32K_SEL_M ((MODEM_LPCON_CLK_MODEM_32K_SEL_V)<<(MODEM_LPCON_CLK_MODEM_32K_SEL_S)) -#define MODEM_LPCON_CLK_MODEM_32K_SEL_V 0x3 -#define MODEM_LPCON_CLK_MODEM_32K_SEL_S 0 - -#define MODEM_LPCON_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x18) -/* MODEM_LPCON_CLK_LP_TIMER_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_LP_TIMER_EN (BIT(3)) -#define MODEM_LPCON_CLK_LP_TIMER_EN_M (BIT(3)) -#define MODEM_LPCON_CLK_LP_TIMER_EN_V 0x1 -#define MODEM_LPCON_CLK_LP_TIMER_EN_S 3 -/* MODEM_LPCON_CLK_I2C_MST_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_I2C_MST_EN (BIT(2)) -#define MODEM_LPCON_CLK_I2C_MST_EN_M (BIT(2)) -#define MODEM_LPCON_CLK_I2C_MST_EN_V 0x1 -#define MODEM_LPCON_CLK_I2C_MST_EN_S 2 -/* MODEM_LPCON_CLK_COEX_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_COEX_EN (BIT(1)) -#define MODEM_LPCON_CLK_COEX_EN_M (BIT(1)) -#define MODEM_LPCON_CLK_COEX_EN_V 0x1 -#define MODEM_LPCON_CLK_COEX_EN_S 1 -/* MODEM_LPCON_CLK_WIFIPWR_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_WIFIPWR_EN (BIT(0)) -#define MODEM_LPCON_CLK_WIFIPWR_EN_M (BIT(0)) -#define MODEM_LPCON_CLK_WIFIPWR_EN_V 0x1 -#define MODEM_LPCON_CLK_WIFIPWR_EN_S 0 - -#define MODEM_LPCON_CLK_CONF_FORCE_ON_REG (DR_REG_MODEM_LPCON_BASE + 0x1C) -/* MODEM_LPCON_CLK_FE_MEM_FO : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_FE_MEM_FO (BIT(4)) -#define MODEM_LPCON_CLK_FE_MEM_FO_M (BIT(4)) -#define MODEM_LPCON_CLK_FE_MEM_FO_V 0x1 -#define MODEM_LPCON_CLK_FE_MEM_FO_S 4 -/* MODEM_LPCON_CLK_LP_TIMER_FO : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_LP_TIMER_FO (BIT(3)) -#define MODEM_LPCON_CLK_LP_TIMER_FO_M (BIT(3)) -#define MODEM_LPCON_CLK_LP_TIMER_FO_V 0x1 -#define MODEM_LPCON_CLK_LP_TIMER_FO_S 3 -/* MODEM_LPCON_CLK_I2C_MST_FO : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_I2C_MST_FO (BIT(2)) -#define MODEM_LPCON_CLK_I2C_MST_FO_M (BIT(2)) -#define MODEM_LPCON_CLK_I2C_MST_FO_V 0x1 -#define MODEM_LPCON_CLK_I2C_MST_FO_S 2 -/* MODEM_LPCON_CLK_COEX_FO : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_COEX_FO (BIT(1)) -#define MODEM_LPCON_CLK_COEX_FO_M (BIT(1)) -#define MODEM_LPCON_CLK_COEX_FO_V 0x1 -#define MODEM_LPCON_CLK_COEX_FO_S 1 -/* MODEM_LPCON_CLK_WIFIPWR_FO : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_WIFIPWR_FO (BIT(0)) -#define MODEM_LPCON_CLK_WIFIPWR_FO_M (BIT(0)) -#define MODEM_LPCON_CLK_WIFIPWR_FO_V 0x1 -#define MODEM_LPCON_CLK_WIFIPWR_FO_S 0 - -#define MODEM_LPCON_CLK_CONF_POWER_ST_REG (DR_REG_MODEM_LPCON_BASE + 0x20) -/* MODEM_LPCON_CLK_LP_APB_ST_MAP : R/W ;bitpos:[31:28] ;default: 4'h0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_LP_APB_ST_MAP 0x0000000F -#define MODEM_LPCON_CLK_LP_APB_ST_MAP_M ((MODEM_LPCON_CLK_LP_APB_ST_MAP_V)<<(MODEM_LPCON_CLK_LP_APB_ST_MAP_S)) -#define MODEM_LPCON_CLK_LP_APB_ST_MAP_V 0xF -#define MODEM_LPCON_CLK_LP_APB_ST_MAP_S 28 -/* MODEM_LPCON_CLK_I2C_MST_ST_MAP : R/W ;bitpos:[27:24] ;default: 4'h0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_I2C_MST_ST_MAP 0x0000000F -#define MODEM_LPCON_CLK_I2C_MST_ST_MAP_M ((MODEM_LPCON_CLK_I2C_MST_ST_MAP_V)<<(MODEM_LPCON_CLK_I2C_MST_ST_MAP_S)) -#define MODEM_LPCON_CLK_I2C_MST_ST_MAP_V 0xF -#define MODEM_LPCON_CLK_I2C_MST_ST_MAP_S 24 -/* MODEM_LPCON_CLK_COEX_ST_MAP : R/W ;bitpos:[23:20] ;default: 4'h0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_COEX_ST_MAP 0x0000000F -#define MODEM_LPCON_CLK_COEX_ST_MAP_M ((MODEM_LPCON_CLK_COEX_ST_MAP_V)<<(MODEM_LPCON_CLK_COEX_ST_MAP_S)) -#define MODEM_LPCON_CLK_COEX_ST_MAP_V 0xF -#define MODEM_LPCON_CLK_COEX_ST_MAP_S 20 -/* MODEM_LPCON_CLK_WIFIPWR_ST_MAP : R/W ;bitpos:[19:16] ;default: 4'h0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_WIFIPWR_ST_MAP 0x0000000F -#define MODEM_LPCON_CLK_WIFIPWR_ST_MAP_M ((MODEM_LPCON_CLK_WIFIPWR_ST_MAP_V)<<(MODEM_LPCON_CLK_WIFIPWR_ST_MAP_S)) -#define MODEM_LPCON_CLK_WIFIPWR_ST_MAP_V 0xF -#define MODEM_LPCON_CLK_WIFIPWR_ST_MAP_S 16 - -#define MODEM_LPCON_RST_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x24) -/* MODEM_LPCON_RST_LP_TIMER : WO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_RST_LP_TIMER (BIT(3)) -#define MODEM_LPCON_RST_LP_TIMER_M (BIT(3)) -#define MODEM_LPCON_RST_LP_TIMER_V 0x1 -#define MODEM_LPCON_RST_LP_TIMER_S 3 -/* MODEM_LPCON_RST_I2C_MST : WO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_RST_I2C_MST (BIT(2)) -#define MODEM_LPCON_RST_I2C_MST_M (BIT(2)) -#define MODEM_LPCON_RST_I2C_MST_V 0x1 -#define MODEM_LPCON_RST_I2C_MST_S 2 -/* MODEM_LPCON_RST_COEX : WO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_RST_COEX (BIT(1)) -#define MODEM_LPCON_RST_COEX_M (BIT(1)) -#define MODEM_LPCON_RST_COEX_V 0x1 -#define MODEM_LPCON_RST_COEX_S 1 -/* MODEM_LPCON_RST_WIFIPWR : WO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_RST_WIFIPWR (BIT(0)) -#define MODEM_LPCON_RST_WIFIPWR_M (BIT(0)) -#define MODEM_LPCON_RST_WIFIPWR_V 0x1 -#define MODEM_LPCON_RST_WIFIPWR_S 0 - -#define MODEM_LPCON_TICK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x28) -/* MODEM_LPCON_MODEM_PWR_TICK_TARGET : R/W ;bitpos:[5:0] ;default: 6'd39 ; */ -/*description: .*/ -#define MODEM_LPCON_MODEM_PWR_TICK_TARGET 0x0000003F -#define MODEM_LPCON_MODEM_PWR_TICK_TARGET_M ((MODEM_LPCON_MODEM_PWR_TICK_TARGET_V)<<(MODEM_LPCON_MODEM_PWR_TICK_TARGET_S)) -#define MODEM_LPCON_MODEM_PWR_TICK_TARGET_V 0x3F -#define MODEM_LPCON_MODEM_PWR_TICK_TARGET_S 0 - -#define MODEM_LPCON_MEM_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x2C) -/* MODEM_LPCON_CHAN_FREQ_MEM_FORCE : R/W ;bitpos:[23] ;default: 1'b1 ; */ -/*description: .*/ -#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE (BIT(23)) -#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_M (BIT(23)) -#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_V 0x1 -#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_S 23 -/* MODEM_LPCON_CHAN_FREQ_MEM_MODE : R/W ;bitpos:[22:20] ;default: 3'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_CHAN_FREQ_MEM_MODE 0x00000007 -#define MODEM_LPCON_CHAN_FREQ_MEM_MODE_M ((MODEM_LPCON_CHAN_FREQ_MEM_MODE_V)<<(MODEM_LPCON_CHAN_FREQ_MEM_MODE_S)) -#define MODEM_LPCON_CHAN_FREQ_MEM_MODE_V 0x7 -#define MODEM_LPCON_CHAN_FREQ_MEM_MODE_S 20 -/* MODEM_LPCON_I2C_MST_MEM_FORCE : R/W ;bitpos:[19] ;default: 1'b1 ; */ -/*description: .*/ -#define MODEM_LPCON_I2C_MST_MEM_FORCE (BIT(19)) -#define MODEM_LPCON_I2C_MST_MEM_FORCE_M (BIT(19)) -#define MODEM_LPCON_I2C_MST_MEM_FORCE_V 0x1 -#define MODEM_LPCON_I2C_MST_MEM_FORCE_S 19 -/* MODEM_LPCON_I2C_MST_MEM_MODE : R/W ;bitpos:[18:16] ;default: 3'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_I2C_MST_MEM_MODE 0x00000007 -#define MODEM_LPCON_I2C_MST_MEM_MODE_M ((MODEM_LPCON_I2C_MST_MEM_MODE_V)<<(MODEM_LPCON_I2C_MST_MEM_MODE_S)) -#define MODEM_LPCON_I2C_MST_MEM_MODE_V 0x7 -#define MODEM_LPCON_I2C_MST_MEM_MODE_S 16 -/* MODEM_LPCON_BC_MEM_FORCE : R/W ;bitpos:[15] ;default: 1'b1 ; */ -/*description: .*/ -#define MODEM_LPCON_BC_MEM_FORCE (BIT(15)) -#define MODEM_LPCON_BC_MEM_FORCE_M (BIT(15)) -#define MODEM_LPCON_BC_MEM_FORCE_V 0x1 -#define MODEM_LPCON_BC_MEM_FORCE_S 15 -/* MODEM_LPCON_BC_MEM_MODE : R/W ;bitpos:[14:12] ;default: 3'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_BC_MEM_MODE 0x00000007 -#define MODEM_LPCON_BC_MEM_MODE_M ((MODEM_LPCON_BC_MEM_MODE_V)<<(MODEM_LPCON_BC_MEM_MODE_S)) -#define MODEM_LPCON_BC_MEM_MODE_V 0x7 -#define MODEM_LPCON_BC_MEM_MODE_S 12 -/* MODEM_LPCON_PBUS_MEM_FORCE : R/W ;bitpos:[11] ;default: 1'b1 ; */ -/*description: .*/ -#define MODEM_LPCON_PBUS_MEM_FORCE (BIT(11)) -#define MODEM_LPCON_PBUS_MEM_FORCE_M (BIT(11)) -#define MODEM_LPCON_PBUS_MEM_FORCE_V 0x1 -#define MODEM_LPCON_PBUS_MEM_FORCE_S 11 -/* MODEM_LPCON_PBUS_MEM_MODE : R/W ;bitpos:[10:8] ;default: 3'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_PBUS_MEM_MODE 0x00000007 -#define MODEM_LPCON_PBUS_MEM_MODE_M ((MODEM_LPCON_PBUS_MEM_MODE_V)<<(MODEM_LPCON_PBUS_MEM_MODE_S)) -#define MODEM_LPCON_PBUS_MEM_MODE_V 0x7 -#define MODEM_LPCON_PBUS_MEM_MODE_S 8 -/* MODEM_LPCON_AGC_MEM_FORCE : R/W ;bitpos:[7] ;default: 1'b1 ; */ -/*description: .*/ -#define MODEM_LPCON_AGC_MEM_FORCE (BIT(7)) -#define MODEM_LPCON_AGC_MEM_FORCE_M (BIT(7)) -#define MODEM_LPCON_AGC_MEM_FORCE_V 0x1 -#define MODEM_LPCON_AGC_MEM_FORCE_S 7 -/* MODEM_LPCON_AGC_MEM_MODE : R/W ;bitpos:[6:4] ;default: 3'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_AGC_MEM_MODE 0x00000007 -#define MODEM_LPCON_AGC_MEM_MODE_M ((MODEM_LPCON_AGC_MEM_MODE_V)<<(MODEM_LPCON_AGC_MEM_MODE_S)) -#define MODEM_LPCON_AGC_MEM_MODE_V 0x7 -#define MODEM_LPCON_AGC_MEM_MODE_S 4 -/* MODEM_LPCON_DC_MEM_FORCE : R/W ;bitpos:[3] ;default: 1'b1 ; */ -/*description: .*/ -#define MODEM_LPCON_DC_MEM_FORCE (BIT(3)) -#define MODEM_LPCON_DC_MEM_FORCE_M (BIT(3)) -#define MODEM_LPCON_DC_MEM_FORCE_V 0x1 -#define MODEM_LPCON_DC_MEM_FORCE_S 3 -/* MODEM_LPCON_DC_MEM_MODE : R/W ;bitpos:[2:0] ;default: 3'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_DC_MEM_MODE 0x00000007 -#define MODEM_LPCON_DC_MEM_MODE_M ((MODEM_LPCON_DC_MEM_MODE_V)<<(MODEM_LPCON_DC_MEM_MODE_S)) -#define MODEM_LPCON_DC_MEM_MODE_V 0x7 -#define MODEM_LPCON_DC_MEM_MODE_S 0 - -#define MODEM_LPCON_MEM_RF1_AUX_CTRL_REG (DR_REG_MODEM_LPCON_BASE + 0x30) -/* MODEM_LPCON_MODEM_PWR_RF1_AUX_CTRL : R/W ;bitpos:[31:0] ;default: 32'h00002070 ; */ -/*description: .*/ -#define MODEM_LPCON_MODEM_PWR_RF1_AUX_CTRL 0xFFFFFFFF -#define MODEM_LPCON_MODEM_PWR_RF1_AUX_CTRL_M ((MODEM_LPCON_MODEM_PWR_RF1_AUX_CTRL_V)<<(MODEM_LPCON_MODEM_PWR_RF1_AUX_CTRL_S)) -#define MODEM_LPCON_MODEM_PWR_RF1_AUX_CTRL_V 0xFFFFFFFF -#define MODEM_LPCON_MODEM_PWR_RF1_AUX_CTRL_S 0 - -#define MODEM_LPCON_MEM_RF2_AUX_CTRL_REG (DR_REG_MODEM_LPCON_BASE + 0x34) -/* MODEM_LPCON_MODEM_PWR_RF2_AUX_CTRL : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: .*/ -#define MODEM_LPCON_MODEM_PWR_RF2_AUX_CTRL 0xFFFFFFFF -#define MODEM_LPCON_MODEM_PWR_RF2_AUX_CTRL_M ((MODEM_LPCON_MODEM_PWR_RF2_AUX_CTRL_V)<<(MODEM_LPCON_MODEM_PWR_RF2_AUX_CTRL_S)) -#define MODEM_LPCON_MODEM_PWR_RF2_AUX_CTRL_V 0xFFFFFFFF -#define MODEM_LPCON_MODEM_PWR_RF2_AUX_CTRL_S 0 - -#define MODEM_LPCON_APB_MEM_SEL_REG (DR_REG_MODEM_LPCON_BASE + 0x38) -/* MODEM_LPCON_AGC_MEM_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_AGC_MEM_EN (BIT(2)) -#define MODEM_LPCON_AGC_MEM_EN_M (BIT(2)) -#define MODEM_LPCON_AGC_MEM_EN_V 0x1 -#define MODEM_LPCON_AGC_MEM_EN_S 2 -/* MODEM_LPCON_PBUS_MEM_EN : R/W ;bitpos:[1] ;default: 'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_PBUS_MEM_EN (BIT(1)) -#define MODEM_LPCON_PBUS_MEM_EN_M (BIT(1)) -#define MODEM_LPCON_PBUS_MEM_EN_V 0x1 -#define MODEM_LPCON_PBUS_MEM_EN_S 1 -/* MODEM_LPCON_CHAN_FREQ_MEM_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_CHAN_FREQ_MEM_EN (BIT(0)) -#define MODEM_LPCON_CHAN_FREQ_MEM_EN_M (BIT(0)) -#define MODEM_LPCON_CHAN_FREQ_MEM_EN_V 0x1 -#define MODEM_LPCON_CHAN_FREQ_MEM_EN_S 0 - -#define MODEM_LPCON_DATE_REG (DR_REG_MODEM_LPCON_BASE + 0x3C) -/* MODEM_LPCON_DATE : R/W ;bitpos:[27:0] ;default: 28'h2311220 ; */ -/*description: .*/ -#define MODEM_LPCON_DATE 0x0FFFFFFF -#define MODEM_LPCON_DATE_M ((MODEM_LPCON_DATE_V)<<(MODEM_LPCON_DATE_S)) -#define MODEM_LPCON_DATE_V 0xFFFFFFF -#define MODEM_LPCON_DATE_S 0 - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32c5/mp/include/modem/modem_lpcon_struct.h b/components/soc/esp32c5/mp/include/modem/modem_lpcon_struct.h deleted file mode 100644 index cb8e4ff8a5..0000000000 --- a/components/soc/esp32c5/mp/include/modem/modem_lpcon_struct.h +++ /dev/null @@ -1,251 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#ifdef __cplusplus -extern "C" { -#endif - -typedef volatile struct { - union { - struct { - uint32_t reg_clk_en : 1; - uint32_t reserved1 : 1; - uint32_t reserved2 : 30; - }; - uint32_t val; - } test_conf; - union { - struct { - uint32_t reg_clk_lp_timer_sel_osc_slow : 1; - uint32_t reg_clk_lp_timer_sel_osc_fast : 1; - uint32_t reg_clk_lp_timer_sel_xtal : 1; - uint32_t reg_clk_lp_timer_sel_xtal32k : 1; - uint32_t reg_clk_lp_timer_div_num : 12; - uint32_t reserved16 : 16; - }; - uint32_t val; - } lp_timer_conf; - union { - struct { - uint32_t reg_clk_coex_lp_sel_osc_slow : 1; - uint32_t reg_clk_coex_lp_sel_osc_fast : 1; - uint32_t reg_clk_coex_lp_sel_xtal : 1; - uint32_t reg_clk_coex_lp_sel_xtal32k : 1; - uint32_t reg_clk_coex_lp_div_num : 12; - uint32_t reserved16 : 16; - }; - uint32_t val; - } coex_lp_clk_conf; - union { - struct { - uint32_t reg_clk_wifipwr_lp_sel_osc_slow: 1; - uint32_t reg_clk_wifipwr_lp_sel_osc_fast: 1; - uint32_t reg_clk_wifipwr_lp_sel_xtal : 1; - uint32_t reg_clk_wifipwr_lp_sel_xtal32k: 1; - uint32_t reg_clk_wifipwr_lp_div_num : 12; - uint32_t reserved16 : 16; - }; - uint32_t val; - } wifi_lp_clk_conf; - union { - struct { - uint32_t reg_clk_modem_aon_force : 2; - uint32_t reg_modem_pwr_clk_src_fo : 1; - uint32_t reserved3 : 29; - }; - uint32_t val; - } modem_src_clk_conf; - union { - struct { - uint32_t reg_clk_modem_32k_sel : 2; - uint32_t reserved2 : 30; - }; - uint32_t val; - } modem_32k_clk_conf; - union { - struct { - uint32_t reg_clk_wifipwr_en : 1; - uint32_t reg_clk_coex_en : 1; - uint32_t reg_clk_i2c_mst_en : 1; - uint32_t reg_clk_lp_timer_en : 1; - uint32_t reserved4 : 1; - uint32_t reserved5 : 1; - uint32_t reserved6 : 1; - uint32_t reserved7 : 1; - uint32_t reserved8 : 1; - uint32_t reserved9 : 1; - uint32_t reserved10 : 1; - uint32_t reserved11 : 1; - uint32_t reserved12 : 1; - uint32_t reserved13 : 1; - uint32_t reserved14 : 1; - uint32_t reserved15 : 1; - uint32_t reserved16 : 1; - uint32_t reserved17 : 1; - uint32_t reserved18 : 1; - uint32_t reserved19 : 1; - uint32_t reserved20 : 1; - uint32_t reserved21 : 1; - uint32_t reserved22 : 1; - uint32_t reserved23 : 1; - uint32_t reserved24 : 1; - uint32_t reserved25 : 1; - uint32_t reserved26 : 1; - uint32_t reserved27 : 1; - uint32_t reserved28 : 1; - uint32_t reserved29 : 1; - uint32_t reserved30 : 1; - uint32_t reserved31 : 1; - }; - uint32_t val; - } clk_conf; - union { - struct { - uint32_t reg_clk_wifipwr_fo : 1; - uint32_t reg_clk_coex_fo : 1; - uint32_t reg_clk_i2c_mst_fo : 1; - uint32_t reg_clk_lp_timer_fo : 1; - uint32_t reg_clk_fe_mem_fo : 1; - uint32_t reserved5 : 1; - uint32_t reserved6 : 1; - uint32_t reserved7 : 1; - uint32_t reserved8 : 1; - uint32_t reserved9 : 1; - uint32_t reserved10 : 1; - uint32_t reserved11 : 1; - uint32_t reserved12 : 1; - uint32_t reserved13 : 1; - uint32_t reserved14 : 1; - uint32_t reserved15 : 1; - uint32_t reserved16 : 1; - uint32_t reserved17 : 1; - uint32_t reserved18 : 1; - uint32_t reserved19 : 1; - uint32_t reserved20 : 1; - uint32_t reserved21 : 1; - uint32_t reserved22 : 1; - uint32_t reserved23 : 1; - uint32_t reserved24 : 1; - uint32_t reserved25 : 1; - uint32_t reserved26 : 1; - uint32_t reserved27 : 1; - uint32_t reserved28 : 1; - uint32_t reserved29 : 1; - uint32_t reserved30 : 1; - uint32_t reserved31 : 1; - }; - uint32_t val; - } clk_conf_force_on; - union { - struct { - uint32_t reserved0 : 16; - uint32_t reg_clk_wifipwr_st_map : 4; - uint32_t reg_clk_coex_st_map : 4; - uint32_t reg_clk_i2c_mst_st_map : 4; - uint32_t reg_clk_lp_apb_st_map : 4; - }; - uint32_t val; - } clk_conf_power_st; - union { - struct { - uint32_t reg_rst_wifipwr : 1; - uint32_t reg_rst_coex : 1; - uint32_t reg_rst_i2c_mst : 1; - uint32_t reg_rst_lp_timer : 1; - uint32_t reserved4 : 1; - uint32_t reserved5 : 1; - uint32_t reserved6 : 1; - uint32_t reserved7 : 1; - uint32_t reserved8 : 1; - uint32_t reserved9 : 1; - uint32_t reserved10 : 1; - uint32_t reserved11 : 1; - uint32_t reserved12 : 1; - uint32_t reserved13 : 1; - uint32_t reserved14 : 1; - uint32_t reserved15 : 1; - uint32_t reserved16 : 1; - uint32_t reserved17 : 1; - uint32_t reserved18 : 1; - uint32_t reserved19 : 1; - uint32_t reserved20 : 1; - uint32_t reserved21 : 1; - uint32_t reserved22 : 1; - uint32_t reserved23 : 1; - uint32_t reserved24 : 1; - uint32_t reserved25 : 1; - uint32_t reserved26 : 1; - uint32_t reserved27 : 1; - uint32_t reserved28 : 1; - uint32_t reserved29 : 1; - uint32_t reserved30 : 1; - uint32_t reserved31 : 1; - }; - uint32_t val; - } rst_conf; - union { - struct { - uint32_t reg_modem_pwr_tick_target : 6; - uint32_t reserved6 : 26; - }; - uint32_t val; - } tick_conf; - union { - struct { - uint32_t reg_dc_mem_mode : 3; - uint32_t reg_dc_mem_force : 1; - uint32_t reg_agc_mem_mode : 3; - uint32_t reg_agc_mem_force : 1; - uint32_t reg_pbus_mem_mode : 3; - uint32_t reg_pbus_mem_force : 1; - uint32_t reg_bc_mem_mode : 3; - uint32_t reg_bc_mem_force : 1; - uint32_t reg_i2c_mst_mem_mode : 3; - uint32_t reg_i2c_mst_mem_force : 1; - uint32_t reg_chan_freq_mem_mode : 3; - uint32_t reg_chan_freq_mem_force : 1; - uint32_t reserved24 : 1; - uint32_t reserved25 : 1; - uint32_t reserved26 : 1; - uint32_t reserved27 : 1; - uint32_t reserved28 : 1; - uint32_t reserved29 : 1; - uint32_t reserved30 : 1; - uint32_t reserved31 : 1; - }; - uint32_t val; - } mem_conf; - uint32_t mem_rf1_aux_ctrl; - uint32_t mem_rf2_aux_ctrl; - union { - struct { - uint32_t reg_chan_freq_mem_en : 1; - uint32_t reg_pbus_mem_en : 1; - uint32_t reg_agc_mem_en : 1; - uint32_t reserved3 : 29; - }; - uint32_t val; - } apb_mem_sel; - union { - struct { - uint32_t reg_date : 28; - uint32_t reserved28 : 4; - }; - uint32_t val; - } date; -} modem_lpcon_dev_t; - -extern modem_lpcon_dev_t MODEM_LPCON; - -#ifndef __cplusplus -_Static_assert(sizeof(modem_lpcon_dev_t) == 0x40, "Invalid size of modem_lpcon_dev_t structure"); -#endif - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32c5/mp/include/modem/modem_syscon_reg.h b/components/soc/esp32c5/mp/include/modem/modem_syscon_reg.h deleted file mode 100644 index 765cb3a00c..0000000000 --- a/components/soc/esp32c5/mp/include/modem/modem_syscon_reg.h +++ /dev/null @@ -1,588 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#include "modem/reg_base.h" -#ifdef __cplusplus -extern "C" { -#endif - -#define MODEM_SYSCON_TEST_CONF_REG (DR_REG_MODEM_SYSCON_BASE + 0x0) -/* MODEM_SYSCON_MODEM_MEM_MODE_FORCE : R/W ;bitpos:[8] ;default: 1'b1 ; */ -/*description: .*/ -#define MODEM_SYSCON_MODEM_MEM_MODE_FORCE (BIT(8)) -#define MODEM_SYSCON_MODEM_MEM_MODE_FORCE_M (BIT(8)) -#define MODEM_SYSCON_MODEM_MEM_MODE_FORCE_V 0x1 -#define MODEM_SYSCON_MODEM_MEM_MODE_FORCE_S 8 -/* MODEM_SYSCON_FPGA_DEBUG_CLK10 : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_FPGA_DEBUG_CLK10 (BIT(7)) -#define MODEM_SYSCON_FPGA_DEBUG_CLK10_M (BIT(7)) -#define MODEM_SYSCON_FPGA_DEBUG_CLK10_V 0x1 -#define MODEM_SYSCON_FPGA_DEBUG_CLK10_S 7 -/* MODEM_SYSCON_FPGA_DEBUG_CLK20 : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_FPGA_DEBUG_CLK20 (BIT(6)) -#define MODEM_SYSCON_FPGA_DEBUG_CLK20_M (BIT(6)) -#define MODEM_SYSCON_FPGA_DEBUG_CLK20_V 0x1 -#define MODEM_SYSCON_FPGA_DEBUG_CLK20_S 6 -/* MODEM_SYSCON_FPGA_DEBUG_CLK40 : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_FPGA_DEBUG_CLK40 (BIT(5)) -#define MODEM_SYSCON_FPGA_DEBUG_CLK40_M (BIT(5)) -#define MODEM_SYSCON_FPGA_DEBUG_CLK40_V 0x1 -#define MODEM_SYSCON_FPGA_DEBUG_CLK40_S 5 -/* MODEM_SYSCON_FPGA_DEBUG_CLK80 : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_FPGA_DEBUG_CLK80 (BIT(4)) -#define MODEM_SYSCON_FPGA_DEBUG_CLK80_M (BIT(4)) -#define MODEM_SYSCON_FPGA_DEBUG_CLK80_V 0x1 -#define MODEM_SYSCON_FPGA_DEBUG_CLK80_S 4 -/* MODEM_SYSCON_FPGA_DEBUG_CLKSWITCH : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_FPGA_DEBUG_CLKSWITCH (BIT(3)) -#define MODEM_SYSCON_FPGA_DEBUG_CLKSWITCH_M (BIT(3)) -#define MODEM_SYSCON_FPGA_DEBUG_CLKSWITCH_V 0x1 -#define MODEM_SYSCON_FPGA_DEBUG_CLKSWITCH_S 3 -/* MODEM_SYSCON_MODEM_ANT_FORCE_SEL_WIFI : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_MODEM_ANT_FORCE_SEL_WIFI (BIT(2)) -#define MODEM_SYSCON_MODEM_ANT_FORCE_SEL_WIFI_M (BIT(2)) -#define MODEM_SYSCON_MODEM_ANT_FORCE_SEL_WIFI_V 0x1 -#define MODEM_SYSCON_MODEM_ANT_FORCE_SEL_WIFI_S 2 -/* MODEM_SYSCON_MODEM_ANT_FORCE_SEL_BT : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_MODEM_ANT_FORCE_SEL_BT (BIT(1)) -#define MODEM_SYSCON_MODEM_ANT_FORCE_SEL_BT_M (BIT(1)) -#define MODEM_SYSCON_MODEM_ANT_FORCE_SEL_BT_V 0x1 -#define MODEM_SYSCON_MODEM_ANT_FORCE_SEL_BT_S 1 -/* MODEM_SYSCON_CLK_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_EN (BIT(0)) -#define MODEM_SYSCON_CLK_EN_M (BIT(0)) -#define MODEM_SYSCON_CLK_EN_V 0x1 -#define MODEM_SYSCON_CLK_EN_S 0 - -#define MODEM_SYSCON_CLK_CONF_REG (DR_REG_MODEM_SYSCON_BASE + 0x4) -/* MODEM_SYSCON_CLK_DATA_DUMP_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_DATA_DUMP_EN (BIT(31)) -#define MODEM_SYSCON_CLK_DATA_DUMP_EN_M (BIT(31)) -#define MODEM_SYSCON_CLK_DATA_DUMP_EN_V 0x1 -#define MODEM_SYSCON_CLK_DATA_DUMP_EN_S 31 -/* MODEM_SYSCON_CLK_BLE_TIMER_EN : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_BLE_TIMER_EN (BIT(30)) -#define MODEM_SYSCON_CLK_BLE_TIMER_EN_M (BIT(30)) -#define MODEM_SYSCON_CLK_BLE_TIMER_EN_V 0x1 -#define MODEM_SYSCON_CLK_BLE_TIMER_EN_S 30 -/* MODEM_SYSCON_CLK_MODEM_SEC_EN : R/W ;bitpos:[29] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_MODEM_SEC_EN (BIT(29)) -#define MODEM_SYSCON_CLK_MODEM_SEC_EN_M (BIT(29)) -#define MODEM_SYSCON_CLK_MODEM_SEC_EN_V 0x1 -#define MODEM_SYSCON_CLK_MODEM_SEC_EN_S 29 -/* MODEM_SYSCON_CLK_MODEM_SEC_APB_EN : R/W ;bitpos:[28] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_MODEM_SEC_APB_EN (BIT(28)) -#define MODEM_SYSCON_CLK_MODEM_SEC_APB_EN_M (BIT(28)) -#define MODEM_SYSCON_CLK_MODEM_SEC_APB_EN_V 0x1 -#define MODEM_SYSCON_CLK_MODEM_SEC_APB_EN_S 28 -/* MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN : R/W ;bitpos:[27] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN (BIT(27)) -#define MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN_M (BIT(27)) -#define MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN_V 0x1 -#define MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN_S 27 -/* MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN : R/W ;bitpos:[26] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN (BIT(26)) -#define MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN_M (BIT(26)) -#define MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN_V 0x1 -#define MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN_S 26 -/* MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN : R/W ;bitpos:[25] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN (BIT(25)) -#define MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN_M (BIT(25)) -#define MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN_V 0x1 -#define MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN_S 25 -/* MODEM_SYSCON_CLK_ZBMAC_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_ZBMAC_EN (BIT(24)) -#define MODEM_SYSCON_CLK_ZBMAC_EN_M (BIT(24)) -#define MODEM_SYSCON_CLK_ZBMAC_EN_V 0x1 -#define MODEM_SYSCON_CLK_ZBMAC_EN_S 24 -/* MODEM_SYSCON_CLK_ZB_APB_EN : R/W ;bitpos:[23] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_ZB_APB_EN (BIT(23)) -#define MODEM_SYSCON_CLK_ZB_APB_EN_M (BIT(23)) -#define MODEM_SYSCON_CLK_ZB_APB_EN_V 0x1 -#define MODEM_SYSCON_CLK_ZB_APB_EN_S 23 -/* MODEM_SYSCON_CLK_ETM_EN : R/W ;bitpos:[22] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_ETM_EN (BIT(22)) -#define MODEM_SYSCON_CLK_ETM_EN_M (BIT(22)) -#define MODEM_SYSCON_CLK_ETM_EN_V 0x1 -#define MODEM_SYSCON_CLK_ETM_EN_S 22 -/* MODEM_SYSCON_CLK_DATA_DUMP_MUX : R/W ;bitpos:[21] ;default: 1'b1 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_DATA_DUMP_MUX (BIT(21)) -#define MODEM_SYSCON_CLK_DATA_DUMP_MUX_M (BIT(21)) -#define MODEM_SYSCON_CLK_DATA_DUMP_MUX_V 0x1 -#define MODEM_SYSCON_CLK_DATA_DUMP_MUX_S 21 -/* MODEM_SYSCON_CLK_I2C_MST_SEL_160M : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_I2C_MST_SEL_160M (BIT(12)) -#define MODEM_SYSCON_CLK_I2C_MST_SEL_160M_M (BIT(12)) -#define MODEM_SYSCON_CLK_I2C_MST_SEL_160M_V 0x1 -#define MODEM_SYSCON_CLK_I2C_MST_SEL_160M_S 12 -/* MODEM_SYSCON_CLK_PWDET_ADC_INV_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_PWDET_ADC_INV_ENA (BIT(11)) -#define MODEM_SYSCON_CLK_PWDET_ADC_INV_ENA_M (BIT(11)) -#define MODEM_SYSCON_CLK_PWDET_ADC_INV_ENA_V 0x1 -#define MODEM_SYSCON_CLK_PWDET_ADC_INV_ENA_S 11 -/* MODEM_SYSCON_CLK_RX_ADC_INV_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_RX_ADC_INV_ENA (BIT(10)) -#define MODEM_SYSCON_CLK_RX_ADC_INV_ENA_M (BIT(10)) -#define MODEM_SYSCON_CLK_RX_ADC_INV_ENA_V 0x1 -#define MODEM_SYSCON_CLK_RX_ADC_INV_ENA_S 10 -/* MODEM_SYSCON_CLK_TX_DAC_INV_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_TX_DAC_INV_ENA (BIT(9)) -#define MODEM_SYSCON_CLK_TX_DAC_INV_ENA_M (BIT(9)) -#define MODEM_SYSCON_CLK_TX_DAC_INV_ENA_V 0x1 -#define MODEM_SYSCON_CLK_TX_DAC_INV_ENA_S 9 -/* MODEM_SYSCON_PWDET_CLK_DIV_NUM : R/W ;bitpos:[8:1] ;default: 8'd1 ; */ -/*description: .*/ -#define MODEM_SYSCON_PWDET_CLK_DIV_NUM 0x000000FF -#define MODEM_SYSCON_PWDET_CLK_DIV_NUM_M ((MODEM_SYSCON_PWDET_CLK_DIV_NUM_V)<<(MODEM_SYSCON_PWDET_CLK_DIV_NUM_S)) -#define MODEM_SYSCON_PWDET_CLK_DIV_NUM_V 0xFF -#define MODEM_SYSCON_PWDET_CLK_DIV_NUM_S 1 -/* MODEM_SYSCON_PWDET_SAR_CLOCK_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_PWDET_SAR_CLOCK_ENA (BIT(0)) -#define MODEM_SYSCON_PWDET_SAR_CLOCK_ENA_M (BIT(0)) -#define MODEM_SYSCON_PWDET_SAR_CLOCK_ENA_V 0x1 -#define MODEM_SYSCON_PWDET_SAR_CLOCK_ENA_S 0 - -#define MODEM_SYSCON_CLK_CONF_FORCE_ON_REG (DR_REG_MODEM_SYSCON_BASE + 0x8) -/* MODEM_SYSCON_CLK_DATA_DUMP_FO : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_DATA_DUMP_FO (BIT(31)) -#define MODEM_SYSCON_CLK_DATA_DUMP_FO_M (BIT(31)) -#define MODEM_SYSCON_CLK_DATA_DUMP_FO_V 0x1 -#define MODEM_SYSCON_CLK_DATA_DUMP_FO_S 31 -/* MODEM_SYSCON_CLK_BLE_TIMER_FO : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_BLE_TIMER_FO (BIT(30)) -#define MODEM_SYSCON_CLK_BLE_TIMER_FO_M (BIT(30)) -#define MODEM_SYSCON_CLK_BLE_TIMER_FO_V 0x1 -#define MODEM_SYSCON_CLK_BLE_TIMER_FO_S 30 -/* MODEM_SYSCON_CLK_MODEM_SEC_FO : R/W ;bitpos:[29] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_MODEM_SEC_FO (BIT(29)) -#define MODEM_SYSCON_CLK_MODEM_SEC_FO_M (BIT(29)) -#define MODEM_SYSCON_CLK_MODEM_SEC_FO_V 0x1 -#define MODEM_SYSCON_CLK_MODEM_SEC_FO_S 29 -/* MODEM_SYSCON_CLK_ETM_FO : R/W ;bitpos:[28] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_ETM_FO (BIT(28)) -#define MODEM_SYSCON_CLK_ETM_FO_M (BIT(28)) -#define MODEM_SYSCON_CLK_ETM_FO_V 0x1 -#define MODEM_SYSCON_CLK_ETM_FO_S 28 -/* MODEM_SYSCON_CLK_ZBMAC_APB_FO : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_ZBMAC_APB_FO (BIT(9)) -#define MODEM_SYSCON_CLK_ZBMAC_APB_FO_M (BIT(9)) -#define MODEM_SYSCON_CLK_ZBMAC_APB_FO_V 0x1 -#define MODEM_SYSCON_CLK_ZBMAC_APB_FO_S 9 -/* MODEM_SYSCON_CLK_ZBMAC_FO : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_ZBMAC_FO (BIT(8)) -#define MODEM_SYSCON_CLK_ZBMAC_FO_M (BIT(8)) -#define MODEM_SYSCON_CLK_ZBMAC_FO_V 0x1 -#define MODEM_SYSCON_CLK_ZBMAC_FO_S 8 -/* MODEM_SYSCON_CLK_BT_APB_FO : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_BT_APB_FO (BIT(7)) -#define MODEM_SYSCON_CLK_BT_APB_FO_M (BIT(7)) -#define MODEM_SYSCON_CLK_BT_APB_FO_V 0x1 -#define MODEM_SYSCON_CLK_BT_APB_FO_S 7 -/* MODEM_SYSCON_CLK_BTMAC_FO : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_BTMAC_FO (BIT(6)) -#define MODEM_SYSCON_CLK_BTMAC_FO_M (BIT(6)) -#define MODEM_SYSCON_CLK_BTMAC_FO_V 0x1 -#define MODEM_SYSCON_CLK_BTMAC_FO_S 6 -/* MODEM_SYSCON_CLK_BTBB_FO : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_BTBB_FO (BIT(5)) -#define MODEM_SYSCON_CLK_BTBB_FO_M (BIT(5)) -#define MODEM_SYSCON_CLK_BTBB_FO_V 0x1 -#define MODEM_SYSCON_CLK_BTBB_FO_S 5 -/* MODEM_SYSCON_CLK_FE_APB_FO : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_FE_APB_FO (BIT(4)) -#define MODEM_SYSCON_CLK_FE_APB_FO_M (BIT(4)) -#define MODEM_SYSCON_CLK_FE_APB_FO_V 0x1 -#define MODEM_SYSCON_CLK_FE_APB_FO_S 4 -/* MODEM_SYSCON_CLK_FE_FO : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_FE_FO (BIT(3)) -#define MODEM_SYSCON_CLK_FE_FO_M (BIT(3)) -#define MODEM_SYSCON_CLK_FE_FO_V 0x1 -#define MODEM_SYSCON_CLK_FE_FO_S 3 -/* MODEM_SYSCON_CLK_WIFI_APB_FO : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_WIFI_APB_FO (BIT(2)) -#define MODEM_SYSCON_CLK_WIFI_APB_FO_M (BIT(2)) -#define MODEM_SYSCON_CLK_WIFI_APB_FO_V 0x1 -#define MODEM_SYSCON_CLK_WIFI_APB_FO_S 2 -/* MODEM_SYSCON_CLK_WIFIMAC_FO : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_WIFIMAC_FO (BIT(1)) -#define MODEM_SYSCON_CLK_WIFIMAC_FO_M (BIT(1)) -#define MODEM_SYSCON_CLK_WIFIMAC_FO_V 0x1 -#define MODEM_SYSCON_CLK_WIFIMAC_FO_S 1 -/* MODEM_SYSCON_CLK_WIFIBB_FO : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_WIFIBB_FO (BIT(0)) -#define MODEM_SYSCON_CLK_WIFIBB_FO_M (BIT(0)) -#define MODEM_SYSCON_CLK_WIFIBB_FO_V 0x1 -#define MODEM_SYSCON_CLK_WIFIBB_FO_S 0 - -#define MODEM_SYSCON_CLK_CONF_POWER_ST_REG (DR_REG_MODEM_SYSCON_BASE + 0xC) -/* MODEM_SYSCON_CLK_MODEM_APB_ST_MAP : R/W ;bitpos:[31:28] ;default: 4'h0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_MODEM_APB_ST_MAP 0x0000000F -#define MODEM_SYSCON_CLK_MODEM_APB_ST_MAP_M ((MODEM_SYSCON_CLK_MODEM_APB_ST_MAP_V)<<(MODEM_SYSCON_CLK_MODEM_APB_ST_MAP_S)) -#define MODEM_SYSCON_CLK_MODEM_APB_ST_MAP_V 0xF -#define MODEM_SYSCON_CLK_MODEM_APB_ST_MAP_S 28 -/* MODEM_SYSCON_CLK_MODEM_PERI_ST_MAP : R/W ;bitpos:[27:24] ;default: 4'h0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_MODEM_PERI_ST_MAP 0x0000000F -#define MODEM_SYSCON_CLK_MODEM_PERI_ST_MAP_M ((MODEM_SYSCON_CLK_MODEM_PERI_ST_MAP_V)<<(MODEM_SYSCON_CLK_MODEM_PERI_ST_MAP_S)) -#define MODEM_SYSCON_CLK_MODEM_PERI_ST_MAP_V 0xF -#define MODEM_SYSCON_CLK_MODEM_PERI_ST_MAP_S 24 -/* MODEM_SYSCON_CLK_WIFI_ST_MAP : R/W ;bitpos:[23:20] ;default: 4'h0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_WIFI_ST_MAP 0x0000000F -#define MODEM_SYSCON_CLK_WIFI_ST_MAP_M ((MODEM_SYSCON_CLK_WIFI_ST_MAP_V)<<(MODEM_SYSCON_CLK_WIFI_ST_MAP_S)) -#define MODEM_SYSCON_CLK_WIFI_ST_MAP_V 0xF -#define MODEM_SYSCON_CLK_WIFI_ST_MAP_S 20 -/* MODEM_SYSCON_CLK_BT_ST_MAP : R/W ;bitpos:[19:16] ;default: 4'h0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_BT_ST_MAP 0x0000000F -#define MODEM_SYSCON_CLK_BT_ST_MAP_M ((MODEM_SYSCON_CLK_BT_ST_MAP_V)<<(MODEM_SYSCON_CLK_BT_ST_MAP_S)) -#define MODEM_SYSCON_CLK_BT_ST_MAP_V 0xF -#define MODEM_SYSCON_CLK_BT_ST_MAP_S 16 -/* MODEM_SYSCON_CLK_FE_ST_MAP : R/W ;bitpos:[15:12] ;default: 4'h0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_FE_ST_MAP 0x0000000F -#define MODEM_SYSCON_CLK_FE_ST_MAP_M ((MODEM_SYSCON_CLK_FE_ST_MAP_V)<<(MODEM_SYSCON_CLK_FE_ST_MAP_S)) -#define MODEM_SYSCON_CLK_FE_ST_MAP_V 0xF -#define MODEM_SYSCON_CLK_FE_ST_MAP_S 12 -/* MODEM_SYSCON_CLK_ZB_ST_MAP : R/W ;bitpos:[11:8] ;default: 4'h0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_ZB_ST_MAP 0x0000000F -#define MODEM_SYSCON_CLK_ZB_ST_MAP_M ((MODEM_SYSCON_CLK_ZB_ST_MAP_V)<<(MODEM_SYSCON_CLK_ZB_ST_MAP_S)) -#define MODEM_SYSCON_CLK_ZB_ST_MAP_V 0xF -#define MODEM_SYSCON_CLK_ZB_ST_MAP_S 8 - -#define MODEM_SYSCON_MODEM_RST_CONF_REG (DR_REG_MODEM_SYSCON_BASE + 0x10) -/* MODEM_SYSCON_RST_DATA_DUMP : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_RST_DATA_DUMP (BIT(31)) -#define MODEM_SYSCON_RST_DATA_DUMP_M (BIT(31)) -#define MODEM_SYSCON_RST_DATA_DUMP_V 0x1 -#define MODEM_SYSCON_RST_DATA_DUMP_S 31 -/* MODEM_SYSCON_RST_BLE_TIMER : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_RST_BLE_TIMER (BIT(30)) -#define MODEM_SYSCON_RST_BLE_TIMER_M (BIT(30)) -#define MODEM_SYSCON_RST_BLE_TIMER_V 0x1 -#define MODEM_SYSCON_RST_BLE_TIMER_S 30 -/* MODEM_SYSCON_RST_MODEM_SEC : R/W ;bitpos:[29] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_RST_MODEM_SEC (BIT(29)) -#define MODEM_SYSCON_RST_MODEM_SEC_M (BIT(29)) -#define MODEM_SYSCON_RST_MODEM_SEC_V 0x1 -#define MODEM_SYSCON_RST_MODEM_SEC_S 29 -/* MODEM_SYSCON_RST_MODEM_BAH : R/W ;bitpos:[27] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_RST_MODEM_BAH (BIT(27)) -#define MODEM_SYSCON_RST_MODEM_BAH_M (BIT(27)) -#define MODEM_SYSCON_RST_MODEM_BAH_V 0x1 -#define MODEM_SYSCON_RST_MODEM_BAH_S 27 -/* MODEM_SYSCON_RST_MODEM_CCM : R/W ;bitpos:[26] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_RST_MODEM_CCM (BIT(26)) -#define MODEM_SYSCON_RST_MODEM_CCM_M (BIT(26)) -#define MODEM_SYSCON_RST_MODEM_CCM_V 0x1 -#define MODEM_SYSCON_RST_MODEM_CCM_S 26 -/* MODEM_SYSCON_RST_MODEM_ECB : R/W ;bitpos:[25] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_RST_MODEM_ECB (BIT(25)) -#define MODEM_SYSCON_RST_MODEM_ECB_M (BIT(25)) -#define MODEM_SYSCON_RST_MODEM_ECB_V 0x1 -#define MODEM_SYSCON_RST_MODEM_ECB_S 25 -/* MODEM_SYSCON_RST_ZBMAC : R/W ;bitpos:[24] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_RST_ZBMAC (BIT(24)) -#define MODEM_SYSCON_RST_ZBMAC_M (BIT(24)) -#define MODEM_SYSCON_RST_ZBMAC_V 0x1 -#define MODEM_SYSCON_RST_ZBMAC_S 24 -/* MODEM_SYSCON_RST_ZBMAC_APB : R/W ;bitpos:[23] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_RST_ZBMAC_APB (BIT(23)) -#define MODEM_SYSCON_RST_ZBMAC_APB_M (BIT(23)) -#define MODEM_SYSCON_RST_ZBMAC_APB_V 0x1 -#define MODEM_SYSCON_RST_ZBMAC_APB_S 23 -/* MODEM_SYSCON_RST_ETM : R/W ;bitpos:[22] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_RST_ETM (BIT(22)) -#define MODEM_SYSCON_RST_ETM_M (BIT(22)) -#define MODEM_SYSCON_RST_ETM_V 0x1 -#define MODEM_SYSCON_RST_ETM_S 22 -/* MODEM_SYSCON_RST_BTBB : R/W ;bitpos:[18] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_RST_BTBB (BIT(18)) -#define MODEM_SYSCON_RST_BTBB_M (BIT(18)) -#define MODEM_SYSCON_RST_BTBB_V 0x1 -#define MODEM_SYSCON_RST_BTBB_S 18 -/* MODEM_SYSCON_RST_BTBB_APB : R/W ;bitpos:[17] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_RST_BTBB_APB (BIT(17)) -#define MODEM_SYSCON_RST_BTBB_APB_M (BIT(17)) -#define MODEM_SYSCON_RST_BTBB_APB_V 0x1 -#define MODEM_SYSCON_RST_BTBB_APB_S 17 -/* MODEM_SYSCON_RST_BTMAC : R/W ;bitpos:[16] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_RST_BTMAC (BIT(16)) -#define MODEM_SYSCON_RST_BTMAC_M (BIT(16)) -#define MODEM_SYSCON_RST_BTMAC_V 0x1 -#define MODEM_SYSCON_RST_BTMAC_S 16 -/* MODEM_SYSCON_RST_BTMAC_APB : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_RST_BTMAC_APB (BIT(15)) -#define MODEM_SYSCON_RST_BTMAC_APB_M (BIT(15)) -#define MODEM_SYSCON_RST_BTMAC_APB_V 0x1 -#define MODEM_SYSCON_RST_BTMAC_APB_S 15 -/* MODEM_SYSCON_RST_FE : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_RST_FE (BIT(14)) -#define MODEM_SYSCON_RST_FE_M (BIT(14)) -#define MODEM_SYSCON_RST_FE_V 0x1 -#define MODEM_SYSCON_RST_FE_S 14 -/* MODEM_SYSCON_RST_FE_AHB : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_RST_FE_AHB (BIT(13)) -#define MODEM_SYSCON_RST_FE_AHB_M (BIT(13)) -#define MODEM_SYSCON_RST_FE_AHB_V 0x1 -#define MODEM_SYSCON_RST_FE_AHB_S 13 -/* MODEM_SYSCON_RST_FE_ADC : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_RST_FE_ADC (BIT(12)) -#define MODEM_SYSCON_RST_FE_ADC_M (BIT(12)) -#define MODEM_SYSCON_RST_FE_ADC_V 0x1 -#define MODEM_SYSCON_RST_FE_ADC_S 12 -/* MODEM_SYSCON_RST_FE_DAC : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_RST_FE_DAC (BIT(11)) -#define MODEM_SYSCON_RST_FE_DAC_M (BIT(11)) -#define MODEM_SYSCON_RST_FE_DAC_V 0x1 -#define MODEM_SYSCON_RST_FE_DAC_S 11 -/* MODEM_SYSCON_RST_FE_PWDET_ADC : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_RST_FE_PWDET_ADC (BIT(10)) -#define MODEM_SYSCON_RST_FE_PWDET_ADC_M (BIT(10)) -#define MODEM_SYSCON_RST_FE_PWDET_ADC_V 0x1 -#define MODEM_SYSCON_RST_FE_PWDET_ADC_S 10 -/* MODEM_SYSCON_RST_WIFIMAC : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_RST_WIFIMAC (BIT(9)) -#define MODEM_SYSCON_RST_WIFIMAC_M (BIT(9)) -#define MODEM_SYSCON_RST_WIFIMAC_V 0x1 -#define MODEM_SYSCON_RST_WIFIMAC_S 9 -/* MODEM_SYSCON_RST_WIFIBB : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_RST_WIFIBB (BIT(8)) -#define MODEM_SYSCON_RST_WIFIBB_M (BIT(8)) -#define MODEM_SYSCON_RST_WIFIBB_V 0x1 -#define MODEM_SYSCON_RST_WIFIBB_S 8 - -#define MODEM_SYSCON_CLK_CONF1_REG (DR_REG_MODEM_SYSCON_BASE + 0x14) -/* MODEM_SYSCON_CLK_FE_DAC_EN : R/W ;bitpos:[21] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_FE_DAC_EN (BIT(21)) -#define MODEM_SYSCON_CLK_FE_DAC_EN_M (BIT(21)) -#define MODEM_SYSCON_CLK_FE_DAC_EN_V 0x1 -#define MODEM_SYSCON_CLK_FE_DAC_EN_S 21 -/* MODEM_SYSCON_CLK_FE_ADC_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_FE_ADC_EN (BIT(20)) -#define MODEM_SYSCON_CLK_FE_ADC_EN_M (BIT(20)) -#define MODEM_SYSCON_CLK_FE_ADC_EN_V 0x1 -#define MODEM_SYSCON_CLK_FE_ADC_EN_S 20 -/* MODEM_SYSCON_CLK_FE_PWDET_ADC_EN : R/W ;bitpos:[19] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_FE_PWDET_ADC_EN (BIT(19)) -#define MODEM_SYSCON_CLK_FE_PWDET_ADC_EN_M (BIT(19)) -#define MODEM_SYSCON_CLK_FE_PWDET_ADC_EN_V 0x1 -#define MODEM_SYSCON_CLK_FE_PWDET_ADC_EN_S 19 -/* MODEM_SYSCON_CLK_BTMAC_EN : R/W ;bitpos:[18] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_BTMAC_EN (BIT(18)) -#define MODEM_SYSCON_CLK_BTMAC_EN_M (BIT(18)) -#define MODEM_SYSCON_CLK_BTMAC_EN_V 0x1 -#define MODEM_SYSCON_CLK_BTMAC_EN_S 18 -/* MODEM_SYSCON_CLK_BTBB_EN : R/W ;bitpos:[17] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_BTBB_EN (BIT(17)) -#define MODEM_SYSCON_CLK_BTBB_EN_M (BIT(17)) -#define MODEM_SYSCON_CLK_BTBB_EN_V 0x1 -#define MODEM_SYSCON_CLK_BTBB_EN_S 17 -/* MODEM_SYSCON_CLK_BT_APB_EN : R/W ;bitpos:[16] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_BT_APB_EN (BIT(16)) -#define MODEM_SYSCON_CLK_BT_APB_EN_M (BIT(16)) -#define MODEM_SYSCON_CLK_BT_APB_EN_V 0x1 -#define MODEM_SYSCON_CLK_BT_APB_EN_S 16 -/* MODEM_SYSCON_CLK_FE_APB_EN : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_FE_APB_EN (BIT(15)) -#define MODEM_SYSCON_CLK_FE_APB_EN_M (BIT(15)) -#define MODEM_SYSCON_CLK_FE_APB_EN_V 0x1 -#define MODEM_SYSCON_CLK_FE_APB_EN_S 15 -/* MODEM_SYSCON_CLK_FE_160M_EN : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_FE_160M_EN (BIT(14)) -#define MODEM_SYSCON_CLK_FE_160M_EN_M (BIT(14)) -#define MODEM_SYSCON_CLK_FE_160M_EN_V 0x1 -#define MODEM_SYSCON_CLK_FE_160M_EN_S 14 -/* MODEM_SYSCON_CLK_FE_80M_EN : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_FE_80M_EN (BIT(13)) -#define MODEM_SYSCON_CLK_FE_80M_EN_M (BIT(13)) -#define MODEM_SYSCON_CLK_FE_80M_EN_V 0x1 -#define MODEM_SYSCON_CLK_FE_80M_EN_S 13 -/* MODEM_SYSCON_CLK_FE_40M_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_FE_40M_EN (BIT(12)) -#define MODEM_SYSCON_CLK_FE_40M_EN_M (BIT(12)) -#define MODEM_SYSCON_CLK_FE_40M_EN_V 0x1 -#define MODEM_SYSCON_CLK_FE_40M_EN_S 12 -/* MODEM_SYSCON_CLK_FE_20M_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_FE_20M_EN (BIT(11)) -#define MODEM_SYSCON_CLK_FE_20M_EN_M (BIT(11)) -#define MODEM_SYSCON_CLK_FE_20M_EN_V 0x1 -#define MODEM_SYSCON_CLK_FE_20M_EN_S 11 -/* MODEM_SYSCON_CLK_WIFI_APB_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_WIFI_APB_EN (BIT(10)) -#define MODEM_SYSCON_CLK_WIFI_APB_EN_M (BIT(10)) -#define MODEM_SYSCON_CLK_WIFI_APB_EN_V 0x1 -#define MODEM_SYSCON_CLK_WIFI_APB_EN_S 10 -/* MODEM_SYSCON_CLK_WIFIMAC_EN : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_WIFIMAC_EN (BIT(9)) -#define MODEM_SYSCON_CLK_WIFIMAC_EN_M (BIT(9)) -#define MODEM_SYSCON_CLK_WIFIMAC_EN_V 0x1 -#define MODEM_SYSCON_CLK_WIFIMAC_EN_S 9 -/* MODEM_SYSCON_CLK_WIFIBB_160X1_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_WIFIBB_160X1_EN (BIT(8)) -#define MODEM_SYSCON_CLK_WIFIBB_160X1_EN_M (BIT(8)) -#define MODEM_SYSCON_CLK_WIFIBB_160X1_EN_V 0x1 -#define MODEM_SYSCON_CLK_WIFIBB_160X1_EN_S 8 -/* MODEM_SYSCON_CLK_WIFIBB_80X1_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_WIFIBB_80X1_EN (BIT(7)) -#define MODEM_SYSCON_CLK_WIFIBB_80X1_EN_M (BIT(7)) -#define MODEM_SYSCON_CLK_WIFIBB_80X1_EN_V 0x1 -#define MODEM_SYSCON_CLK_WIFIBB_80X1_EN_S 7 -/* MODEM_SYSCON_CLK_WIFIBB_40X1_EN : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_WIFIBB_40X1_EN (BIT(6)) -#define MODEM_SYSCON_CLK_WIFIBB_40X1_EN_M (BIT(6)) -#define MODEM_SYSCON_CLK_WIFIBB_40X1_EN_V 0x1 -#define MODEM_SYSCON_CLK_WIFIBB_40X1_EN_S 6 -/* MODEM_SYSCON_CLK_WIFIBB_80X_EN : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_WIFIBB_80X_EN (BIT(5)) -#define MODEM_SYSCON_CLK_WIFIBB_80X_EN_M (BIT(5)) -#define MODEM_SYSCON_CLK_WIFIBB_80X_EN_V 0x1 -#define MODEM_SYSCON_CLK_WIFIBB_80X_EN_S 5 -/* MODEM_SYSCON_CLK_WIFIBB_40X_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_WIFIBB_40X_EN (BIT(4)) -#define MODEM_SYSCON_CLK_WIFIBB_40X_EN_M (BIT(4)) -#define MODEM_SYSCON_CLK_WIFIBB_40X_EN_V 0x1 -#define MODEM_SYSCON_CLK_WIFIBB_40X_EN_S 4 -/* MODEM_SYSCON_CLK_WIFIBB_80M_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_WIFIBB_80M_EN (BIT(3)) -#define MODEM_SYSCON_CLK_WIFIBB_80M_EN_M (BIT(3)) -#define MODEM_SYSCON_CLK_WIFIBB_80M_EN_V 0x1 -#define MODEM_SYSCON_CLK_WIFIBB_80M_EN_S 3 -/* MODEM_SYSCON_CLK_WIFIBB_44M_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_WIFIBB_44M_EN (BIT(2)) -#define MODEM_SYSCON_CLK_WIFIBB_44M_EN_M (BIT(2)) -#define MODEM_SYSCON_CLK_WIFIBB_44M_EN_V 0x1 -#define MODEM_SYSCON_CLK_WIFIBB_44M_EN_S 2 -/* MODEM_SYSCON_CLK_WIFIBB_40M_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_WIFIBB_40M_EN (BIT(1)) -#define MODEM_SYSCON_CLK_WIFIBB_40M_EN_M (BIT(1)) -#define MODEM_SYSCON_CLK_WIFIBB_40M_EN_V 0x1 -#define MODEM_SYSCON_CLK_WIFIBB_40M_EN_S 1 -/* MODEM_SYSCON_CLK_WIFIBB_22M_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_WIFIBB_22M_EN (BIT(0)) -#define MODEM_SYSCON_CLK_WIFIBB_22M_EN_M (BIT(0)) -#define MODEM_SYSCON_CLK_WIFIBB_22M_EN_V 0x1 -#define MODEM_SYSCON_CLK_WIFIBB_22M_EN_S 0 - -#define MODEM_SYSCON_WIFI_BB_CFG_REG (DR_REG_MODEM_SYSCON_BASE + 0x18) -/* MODEM_SYSCON_WIFI_BB_CFG : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: .*/ -#define MODEM_SYSCON_WIFI_BB_CFG 0xFFFFFFFF -#define MODEM_SYSCON_WIFI_BB_CFG_M ((MODEM_SYSCON_WIFI_BB_CFG_V)<<(MODEM_SYSCON_WIFI_BB_CFG_S)) -#define MODEM_SYSCON_WIFI_BB_CFG_V 0xFFFFFFFF -#define MODEM_SYSCON_WIFI_BB_CFG_S 0 - -#define MODEM_SYSCON_MEM_RF1_CONF_REG (DR_REG_MODEM_SYSCON_BASE + 0x1C) -/* MODEM_SYSCON_MODEM_RF1_MEM_AUX_CTRL : R/W ;bitpos:[31:0] ;default: 32'h00002070 ; */ -/*description: .*/ -#define MODEM_SYSCON_MODEM_RF1_MEM_AUX_CTRL 0xFFFFFFFF -#define MODEM_SYSCON_MODEM_RF1_MEM_AUX_CTRL_M ((MODEM_SYSCON_MODEM_RF1_MEM_AUX_CTRL_V)<<(MODEM_SYSCON_MODEM_RF1_MEM_AUX_CTRL_S)) -#define MODEM_SYSCON_MODEM_RF1_MEM_AUX_CTRL_V 0xFFFFFFFF -#define MODEM_SYSCON_MODEM_RF1_MEM_AUX_CTRL_S 0 - -#define MODEM_SYSCON_MEM_RF2_CONF_REG (DR_REG_MODEM_SYSCON_BASE + 0x20) -/* MODEM_SYSCON_MODEM_RF2_MEM_AUX_CTRL : R/W ;bitpos:[31:0] ;default: 32'h00000000 ; */ -/*description: .*/ -#define MODEM_SYSCON_MODEM_RF2_MEM_AUX_CTRL 0xFFFFFFFF -#define MODEM_SYSCON_MODEM_RF2_MEM_AUX_CTRL_M ((MODEM_SYSCON_MODEM_RF2_MEM_AUX_CTRL_V)<<(MODEM_SYSCON_MODEM_RF2_MEM_AUX_CTRL_S)) -#define MODEM_SYSCON_MODEM_RF2_MEM_AUX_CTRL_V 0xFFFFFFFF -#define MODEM_SYSCON_MODEM_RF2_MEM_AUX_CTRL_S 0 - -#define MODEM_SYSCON_DATE_REG (DR_REG_MODEM_SYSCON_BASE + 0x24) -/* MODEM_SYSCON_DATE : R/W ;bitpos:[27:0] ;default: 28'h2312050 ; */ -/*description: .*/ -#define MODEM_SYSCON_DATE 0x0FFFFFFF -#define MODEM_SYSCON_DATE_M ((MODEM_SYSCON_DATE_V)<<(MODEM_SYSCON_DATE_S)) -#define MODEM_SYSCON_DATE_V 0xFFFFFFF -#define MODEM_SYSCON_DATE_S 0 - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32c5/mp/include/modem/modem_syscon_struct.h b/components/soc/esp32c5/mp/include/modem/modem_syscon_struct.h deleted file mode 100644 index b7086ad37a..0000000000 --- a/components/soc/esp32c5/mp/include/modem/modem_syscon_struct.h +++ /dev/null @@ -1,174 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#ifdef __cplusplus -extern "C" { -#endif - -typedef volatile struct { - union { - struct { - uint32_t reg_clk_en : 1; - uint32_t reg_modem_ant_force_sel_bt : 1; - uint32_t reg_modem_ant_force_sel_wifi : 1; - uint32_t reg_fpga_debug_clkswitch : 1; - uint32_t reg_fpga_debug_clk80 : 1; - uint32_t reg_fpga_debug_clk40 : 1; - uint32_t reg_fpga_debug_clk20 : 1; - uint32_t reg_fpga_debug_clk10 : 1; - uint32_t reg_modem_mem_mode_force : 1; - uint32_t reserved9 : 23; - }; - uint32_t val; - } test_conf; - union { - struct { - uint32_t reg_pwdet_sar_clock_ena : 1; - uint32_t reg_pwdet_clk_div_num : 8; - uint32_t reg_clk_tx_dac_inv_ena : 1; - uint32_t reg_clk_rx_adc_inv_ena : 1; - uint32_t reg_clk_pwdet_adc_inv_ena : 1; - uint32_t reg_clk_i2c_mst_sel_160m : 1; - uint32_t reserved13 : 8; - uint32_t reg_clk_data_dump_mux : 1; - uint32_t reg_clk_etm_en : 1; - uint32_t reg_clk_zb_apb_en : 1; - uint32_t reg_clk_zbmac_en : 1; - uint32_t reg_clk_modem_sec_ecb_en : 1; - uint32_t reg_clk_modem_sec_ccm_en : 1; - uint32_t reg_clk_modem_sec_bah_en : 1; - uint32_t reg_clk_modem_sec_apb_en : 1; - uint32_t reg_clk_modem_sec_en : 1; - uint32_t reg_clk_ble_timer_en : 1; - uint32_t reg_clk_data_dump_en : 1; - }; - uint32_t val; - } clk_conf; - union { - struct { - uint32_t reg_clk_wifibb_fo : 1; - uint32_t reg_clk_wifimac_fo : 1; - uint32_t reg_clk_wifi_apb_fo : 1; - uint32_t reg_clk_fe_fo : 1; - uint32_t reg_clk_fe_apb_fo : 1; - uint32_t reg_clk_btbb_fo : 1; - uint32_t reg_clk_btmac_fo : 1; - uint32_t reg_clk_bt_apb_fo : 1; - uint32_t reg_clk_zbmac_fo : 1; - uint32_t reg_clk_zbmac_apb_fo : 1; - uint32_t reserved10 : 13; - uint32_t reserved23 : 1; - uint32_t reserved24 : 1; - uint32_t reserved25 : 1; - uint32_t reserved26 : 1; - uint32_t reserved27 : 1; - uint32_t reg_clk_etm_fo : 1; - uint32_t reg_clk_modem_sec_fo : 1; - uint32_t reg_clk_ble_timer_fo : 1; - uint32_t reg_clk_data_dump_fo : 1; - }; - uint32_t val; - } clk_conf_force_on; - union { - struct { - uint32_t reserved0 : 8; - uint32_t reg_clk_zb_st_map : 4; - uint32_t reg_clk_fe_st_map : 4; - uint32_t reg_clk_bt_st_map : 4; - uint32_t reg_clk_wifi_st_map : 4; - uint32_t reg_clk_modem_peri_st_map : 4; - uint32_t reg_clk_modem_apb_st_map : 4; - }; - uint32_t val; - } clk_conf_power_st; - union { - struct { - uint32_t reserved0 : 1; - uint32_t reserved1 : 1; - uint32_t reserved2 : 1; - uint32_t reserved3 : 1; - uint32_t reserved4 : 1; - uint32_t reserved5 : 1; - uint32_t reserved6 : 1; - uint32_t reserved7 : 1; - uint32_t reg_rst_wifibb : 1; - uint32_t reg_rst_wifimac : 1; - uint32_t reg_rst_fe_pwdet_adc : 1; - uint32_t reg_rst_fe_dac : 1; - uint32_t reg_rst_fe_adc : 1; - uint32_t reg_rst_fe_ahb : 1; - uint32_t reg_rst_fe : 1; - uint32_t reg_rst_btmac_apb : 1; - uint32_t reg_rst_btmac : 1; - uint32_t reg_rst_btbb_apb : 1; - uint32_t reg_rst_btbb : 1; - uint32_t reserved19 : 3; - uint32_t reg_rst_etm : 1; - uint32_t reg_rst_zbmac_apb : 1; - uint32_t reg_rst_zbmac : 1; - uint32_t reg_rst_modem_ecb : 1; - uint32_t reg_rst_modem_ccm : 1; - uint32_t reg_rst_modem_bah : 1; - uint32_t reserved28 : 1; - uint32_t reg_rst_modem_sec : 1; - uint32_t reg_rst_ble_timer : 1; - uint32_t reg_rst_data_dump : 1; - }; - uint32_t val; - } modem_rst_conf; - union { - struct { - uint32_t reg_clk_wifibb_22m_en : 1; - uint32_t reg_clk_wifibb_40m_en : 1; - uint32_t reg_clk_wifibb_44m_en : 1; - uint32_t reg_clk_wifibb_80m_en : 1; - uint32_t reg_clk_wifibb_40x_en : 1; - uint32_t reg_clk_wifibb_80x_en : 1; - uint32_t reg_clk_wifibb_40x1_en : 1; - uint32_t reg_clk_wifibb_80x1_en : 1; - uint32_t reg_clk_wifibb_160x1_en : 1; - uint32_t reg_clk_wifimac_en : 1; - uint32_t reg_clk_wifi_apb_en : 1; - uint32_t reg_clk_fe_20m_en : 1; - uint32_t reg_clk_fe_40m_en : 1; - uint32_t reg_clk_fe_80m_en : 1; - uint32_t reg_clk_fe_160m_en : 1; - uint32_t reg_clk_fe_apb_en : 1; - uint32_t reg_clk_bt_apb_en : 1; - uint32_t reg_clk_btbb_en : 1; - uint32_t reg_clk_btmac_en : 1; - uint32_t reg_clk_fe_pwdet_adc_en : 1; - uint32_t reg_clk_fe_adc_en : 1; - uint32_t reg_clk_fe_dac_en : 1; - uint32_t reserved22 : 1; - uint32_t reserved23 : 1; - uint32_t reserved24 : 8; - }; - uint32_t val; - } clk_conf1; - uint32_t wifi_bb_cfg; - uint32_t mem_rf1_conf; - uint32_t mem_rf2_conf; - union { - struct { - uint32_t reg_date : 28; - uint32_t reserved28 : 4; - }; - uint32_t val; - } date; -} modem_syscon_dev_t; - -extern modem_syscon_dev_t MODEM_SYSCON; - -#ifndef __cplusplus -_Static_assert(sizeof(modem_syscon_dev_t) == 0x28, "Invalid size of modem_syscon_dev_t structure"); -#endif - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32c5/mp/include/modem/reg_base.h b/components/soc/esp32c5/mp/include/modem/reg_base.h deleted file mode 100644 index 37b441740c..0000000000 --- a/components/soc/esp32c5/mp/include/modem/reg_base.h +++ /dev/null @@ -1,9 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#pragma once -#define DR_REG_MODEM_SYSCON_BASE 0x600A9C00 -#define DR_REG_MODEM_LPCON_BASE 0x600AF000 From 1b65a7092802550287a42b83b79c0908b7cf31a7 Mon Sep 17 00:00:00 2001 From: Lou Tianhao Date: Tue, 18 Jun 2024 19:49:43 +0800 Subject: [PATCH 2/2] change(esp_hw_support): bypass esp_sleep_pd_config --- components/esp_hw_support/modem_clock.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/components/esp_hw_support/modem_clock.c b/components/esp_hw_support/modem_clock.c index bdbbf2690f..4f19dece52 100644 --- a/components/esp_hw_support/modem_clock.c +++ b/components/esp_hw_support/modem_clock.c @@ -410,10 +410,13 @@ void modem_clock_select_lp_clock_source(periph_module_t module, modem_clock_lpcl default: break; } +#if SOC_LIGHT_SLEEP_SUPPORTED // TODO: [ESP32C5] IDF-8643 modem_clock_lpclk_src_t last_src = MODEM_CLOCK_instance()->lpclk_src[module - PERIPH_MODEM_MODULE_MIN]; +#endif MODEM_CLOCK_instance()->lpclk_src[module - PERIPH_MODEM_MODULE_MIN] = src; portEXIT_CRITICAL_SAFE(&MODEM_CLOCK_instance()->lock); +#if SOC_LIGHT_SLEEP_SUPPORTED // TODO: [ESP32C5] IDF-8643 /* The power domain of the low-power clock source required by the modem * module remains powered on during sleep */ esp_sleep_pd_domain_t pd_domain = (esp_sleep_pd_domain_t) ( \ @@ -430,13 +433,16 @@ void modem_clock_select_lp_clock_source(periph_module_t module, modem_clock_lpcl : ESP_PD_DOMAIN_MAX); esp_sleep_pd_config(pd_domain, ESP_PD_OPTION_OFF); esp_sleep_pd_config(pu_domain, ESP_PD_OPTION_ON); +#endif } void modem_clock_deselect_lp_clock_source(periph_module_t module) { assert(IS_MODEM_MODULE(module)); portENTER_CRITICAL_SAFE(&MODEM_CLOCK_instance()->lock); +#if SOC_LIGHT_SLEEP_SUPPORTED // TODO: [ESP32C5] IDF-8643 modem_clock_lpclk_src_t last_src = MODEM_CLOCK_instance()->lpclk_src[module - PERIPH_MODEM_MODULE_MIN]; +#endif MODEM_CLOCK_instance()->lpclk_src[module - PERIPH_MODEM_MODULE_MIN] = MODEM_CLOCK_LPCLK_SRC_INVALID; switch (module) { @@ -471,6 +477,7 @@ void modem_clock_deselect_lp_clock_source(periph_module_t module) } portEXIT_CRITICAL_SAFE(&MODEM_CLOCK_instance()->lock); +#if SOC_LIGHT_SLEEP_SUPPORTED // TODO: [ESP32C5] IDF-8643 esp_sleep_pd_domain_t pd_domain = (esp_sleep_pd_domain_t) ( \ (last_src == MODEM_CLOCK_LPCLK_SRC_RC_FAST) ? ESP_PD_DOMAIN_RC_FAST \ : (last_src == MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL) ? ESP_PD_DOMAIN_XTAL \ @@ -478,4 +485,5 @@ void modem_clock_deselect_lp_clock_source(periph_module_t module) : (last_src == MODEM_CLOCK_LPCLK_SRC_XTAL32K) ? ESP_PD_DOMAIN_XTAL32K \ : ESP_PD_DOMAIN_MAX); esp_sleep_pd_config(pd_domain, ESP_PD_OPTION_OFF); +#endif }