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rtc_clk: Fix rtc8m calibration failure after cpu/core reset

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Explicitly guarantee 8md256 clk is enabled before calibration
This commit is contained in:
Song Ruo Jing
2022-10-12 12:33:47 +08:00
parent 40cc53b0e0
commit ed3a570e20
1 changed files with 4 additions and 0 deletions
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4
components/soc/esp32/rtc_time.c
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@@ -49,7 +49,10 @@ static uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cyc
REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN, 1); REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN, 1);
} }
bool clk8m_enabled = rtc_clk_8m_enabled();
bool clk8md256_enabled = rtc_clk_8md256_enabled();
if (cal_clk == RTC_CAL_8MD256) { if (cal_clk == RTC_CAL_8MD256) {
rtc_clk_8m_enable(true, true);
SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_D256_EN); SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_D256_EN);
} }
/* Prepare calibration */ /* Prepare calibration */
@@ -100,6 +103,7 @@ static uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cyc
if (cal_clk == RTC_CAL_8MD256) { if (cal_clk == RTC_CAL_8MD256) {
CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_D256_EN); CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_D256_EN);
rtc_clk_8m_enable(clk8m_enabled, clk8md256_enabled);
} }
if (timeout_us == 0) { if (timeout_us == 0) {
/* timed out waiting for calibration */ /* timed out waiting for calibration */