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Merge branch 'feature/enable_ecc_support_in_c61' into 'master'

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feat: enable ecc support in esp32c61

Closes IDF-9235

See merge request espressif/esp-idf!31360
This commit is contained in:
Mahavir Jain
2024-07-11 21:46:10 +08:00
parent 5448703663 a87636cca7
commit f08a851eaa
7 changed files with 341 additions and 3 deletions
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37
components/esp_hw_support/include/soc/esp32c61/esp_crypto_lock.h Normal file
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@ -0,0 +1,37 @@
/*
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
void esp_crypto_ecc_lock_acquire(void);
/**
* @brief Release lock for the ECC cryptography peripheral.
*
*/
void esp_crypto_ecc_lock_release(void);
/**
* @brief Acquire lock for ECDSA cryptography peripheral
*
* Internally also locks the ECC and MPI peripheral, as the ECDSA depends on these peripherals
*/
void esp_crypto_ecdsa_lock_acquire(void);
/**
* @brief Release lock for ECDSA cryptography peripheral
*
* Internally also releases the ECC and MPI peripheral, as the ECDSA depends on these peripherals
*/
void esp_crypto_ecdsa_lock_release(void);
#ifdef __cplusplus
}
#endif

1
components/esp_hw_support/port/esp32c61/CMakeLists.txt
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@ -25,7 +25,6 @@ if(CONFIG_IDF_TARGET_ESP32C61)
"pmu_init.c" "pmu_init.c"
"pmu_sleep.c" "pmu_sleep.c"
"sar_periph_ctrl.c" "sar_periph_ctrl.c"
"esp_crypto_lock.c"
"ocode_init.c" "ocode_init.c"
) )
endif() endif()

46
components/esp_hw_support/port/esp32c61/esp_crypto_lock.c Normal file
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@ -0,0 +1,46 @@
/*
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <sys/lock.h>
#include "esp_crypto_lock.h"
/* Lock overview:
SHA: peripheral independent, but DMA is shared with AES
AES: peripheral independent, but DMA is shared with SHA
MPI/RSA: independent
ECC: independent
HMAC: needs SHA
DS: needs HMAC (which needs SHA), AES and MPI
*/
/* Lock for ECC peripheral */
static _lock_t s_crypto_ecc_lock;
/* Lock for ECDSA peripheral */
static _lock_t s_crypto_ecdsa_lock;
void esp_crypto_ecc_lock_acquire(void)
{
_lock_acquire(&s_crypto_ecc_lock);
}
void esp_crypto_ecc_lock_release(void)
{
_lock_release(&s_crypto_ecc_lock);
}
void esp_crypto_ecdsa_lock_acquire(void)
{
_lock_acquire(&s_crypto_ecdsa_lock);
esp_crypto_ecc_lock_acquire();
}
void esp_crypto_ecdsa_lock_release(void)
{
esp_crypto_ecc_lock_release();
_lock_release(&s_crypto_ecdsa_lock);
}

247
components/hal/esp32c61/include/hal/ecc_ll.h Normal file
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@ -0,0 +1,247 @@
/*
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdbool.h>
#include <string.h>
#include "hal/assert.h"
#include "hal/ecc_types.h"
#include "soc/ecc_mult_reg.h"
#include "soc/pcr_struct.h"
#include "soc/pcr_reg.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
ECC_PARAM_PX = 0x0,
ECC_PARAM_PY,
ECC_PARAM_K,
ECC_PARAM_QX,
ECC_PARAM_QY,
ECC_PARAM_QZ,
} ecc_ll_param_t;
/**
* @brief Enable the bus clock for ECC peripheral module
*
* @param true to enable the module, false to disable the module
*/
static inline void ecc_ll_enable_bus_clock(bool enable)
{
PCR.ecc_conf.ecc_clk_en = enable;
}
/**
* @brief Reset the ECC peripheral module
*/
static inline void ecc_ll_reset_register(void)
{
PCR.ecc_conf.ecc_rst_en = 1;
PCR.ecc_conf.ecc_rst_en = 0;
// Clear reset on ECDSA, otherwise ECC is held in reset
PCR.ecdsa_conf.ecdsa_rst_en = 0;
}
static inline void ecc_ll_power_up(void)
{
/* Power up the ECC peripheral (default state is power-down) */
REG_CLR_BIT(PCR_ECC_PD_CTRL_REG, PCR_ECC_MEM_PD);
REG_CLR_BIT(PCR_ECC_PD_CTRL_REG, PCR_ECC_MEM_FORCE_PD);
}
static inline void ecc_ll_power_down(void)
{
/* Power down the ECC peripheral */
REG_CLR_BIT(PCR_ECC_PD_CTRL_REG, PCR_ECC_MEM_FORCE_PU);
REG_SET_BIT(PCR_ECC_PD_CTRL_REG, PCR_ECC_MEM_PD);
}
static inline void ecc_ll_enable_interrupt(void)
{
REG_SET_FIELD(ECC_MULT_INT_ENA_REG, ECC_MULT_CALC_DONE_INT_ENA, 1);
}
static inline void ecc_ll_disable_interrupt(void)
{
REG_SET_FIELD(ECC_MULT_INT_ENA_REG, ECC_MULT_CALC_DONE_INT_ENA, 0);
}
static inline void ecc_ll_clear_interrupt(void)
{
REG_SET_FIELD(ECC_MULT_INT_CLR_REG, ECC_MULT_CALC_DONE_INT_CLR, 1);
}
static inline void ecc_ll_set_mode(ecc_mode_t mode)
{
switch(mode) {
case ECC_MODE_POINT_MUL:
REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 0);
break;
case ECC_MODE_VERIFY:
REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 2);
break;
case ECC_MODE_VERIFY_THEN_POINT_MUL:
REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 3);
break;
case ECC_MODE_JACOBIAN_POINT_MUL:
REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 4);
break;
case ECC_MODE_POINT_ADD:
REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 5);
break;
case ECC_MODE_JACOBIAN_POINT_VERIFY:
REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 6);
break;
case ECC_MODE_POINT_VERIFY_JACOBIAN_MUL:
REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 7);
break;
case ECC_MODE_MOD_ADD:
REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 8);
break;
case ECC_MODE_MOD_SUB:
REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 9);
break;
case ECC_MODE_MOD_MUL:
REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 10);
break;
case ECC_MODE_INVERSE_MUL:
REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 11);
break;
default:
HAL_ASSERT(false && "Unsupported mode");
break;
}
}
static inline void ecc_ll_set_curve(ecc_curve_t curve)
{
switch(curve) {
case ECC_CURVE_SECP256R1:
REG_SET_BIT(ECC_MULT_CONF_REG, ECC_MULT_KEY_LENGTH);
break;
case ECC_CURVE_SECP192R1:
REG_CLR_BIT(ECC_MULT_CONF_REG, ECC_MULT_KEY_LENGTH);
break;
default:
HAL_ASSERT(false && "Unsupported curve");
return;
}
}
static inline void ecc_ll_set_mod_base(ecc_mod_base_t base)
{
switch(base) {
case ECC_MOD_N:
REG_CLR_BIT(ECC_MULT_CONF_REG, ECC_MULT_MOD_BASE);
break;
case ECC_MOD_P:
REG_SET_BIT(ECC_MULT_CONF_REG, ECC_MULT_MOD_BASE);
break;
default:
HAL_ASSERT(false && "Unsupported curve");
return;
}
}
static inline void ecc_ll_write_param(ecc_ll_param_t param, const uint8_t *buf, uint16_t len)
{
uint32_t reg;
uint32_t word;
switch (param) {
case ECC_PARAM_PX:
reg = ECC_MULT_PX_MEM;
break;
case ECC_PARAM_PY:
reg = ECC_MULT_PY_MEM;
break;
case ECC_PARAM_K:
reg = ECC_MULT_K_MEM;
break;
case ECC_PARAM_QX:
reg = ECC_MULT_QX_MEM;
break;
case ECC_PARAM_QY:
reg = ECC_MULT_QY_MEM;
break;
case ECC_PARAM_QZ:
reg = ECC_MULT_QZ_MEM;
break;
default:
HAL_ASSERT(false && "Invalid parameter");
return;
}
for (int i = 0; i < len; i += 4) {
memcpy(&word, buf + i, 4);
REG_WRITE(reg + i, word);
}
}
static inline void ecc_ll_start_calc(void)
{
REG_SET_BIT(ECC_MULT_CONF_REG, ECC_MULT_START);
}
static inline int ecc_ll_is_calc_finished(void)
{
return REG_GET_FIELD(ECC_MULT_INT_RAW_REG, ECC_MULT_CALC_DONE_INT_RAW);
}
static inline ecc_mode_t ecc_ll_get_mode(void)
{
return (ecc_mode_t)(REG_GET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE));
}
static inline int ecc_ll_get_verification_result(void)
{
return REG_GET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_VERIFICATION_RESULT);
}
static inline ecc_curve_t ecc_ll_get_curve(void)
{
return (ecc_curve_t)(REG_GET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_KEY_LENGTH));
}
static inline ecc_mod_base_t ecc_ll_get_mod_base(void)
{
return (ecc_mod_base_t)(REG_GET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_MOD_BASE));
}
static inline void ecc_ll_read_param(ecc_ll_param_t param, uint8_t *buf, uint16_t len)
{
uint32_t reg;
switch (param) {
case ECC_PARAM_PX:
reg = ECC_MULT_PX_MEM;
break;
case ECC_PARAM_PY:
reg = ECC_MULT_PY_MEM;
break;
case ECC_PARAM_K:
reg = ECC_MULT_K_MEM;
break;
case ECC_PARAM_QX:
reg = ECC_MULT_QX_MEM;
break;
case ECC_PARAM_QY:
reg = ECC_MULT_QY_MEM;
break;
case ECC_PARAM_QZ:
reg = ECC_MULT_QZ_MEM;
break;
default:
HAL_ASSERT(false && "Invalid parameter");
return;
}
memcpy(buf, (void *)reg, len);
}
#ifdef __cplusplus
}
#endif

8
components/soc/esp32c61/include/soc/Kconfig.soc_caps.in
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@ -31,6 +31,14 @@ config SOC_SYSTIMER_SUPPORTED
bool bool
default y default y
config SOC_ECC_SUPPORTED
bool
default y
config SOC_ECC_EXTENDED_MODES_SUPPORTED
bool
default y
config SOC_FLASH_ENC_SUPPORTED config SOC_FLASH_ENC_SUPPORTED
bool bool
default y default y

2
components/soc/esp32c61/include/soc/reg_base.h
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@ -26,7 +26,7 @@
#define DR_REG_AHB_GDMA_BASE 0x60080000 #define DR_REG_AHB_GDMA_BASE 0x60080000
#define DR_REG_GPSPI_BASE 0x60081000 #define DR_REG_GPSPI_BASE 0x60081000
#define DR_REG_SHA_BASE 0x60089000 #define DR_REG_SHA_BASE 0x60089000
#define DR_REG_ECC_BASE 0x6008B000 #define DR_REG_ECC_MULT_BASE 0x6008B000
#define DR_REG_ECDSA_BASE 0x6008E000 #define DR_REG_ECDSA_BASE 0x6008E000
#define DR_REG_IO_MUX_BASE 0x60090000 #define DR_REG_IO_MUX_BASE 0x60090000
#define DR_REG_GPIO_BASE 0x60091000 #define DR_REG_GPIO_BASE 0x60091000

3
components/soc/esp32c61/include/soc/soc_caps.h
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@ -45,7 +45,8 @@
// \#define SOC_SHA_SUPPORTED 1 //TODO: [ESP32C61] IDF-9234 // \#define SOC_SHA_SUPPORTED 1 //TODO: [ESP32C61] IDF-9234
// \#define SOC_HMAC_SUPPORTED 1 //TODO: [ESP32C61] IDF-9323 // \#define SOC_HMAC_SUPPORTED 1 //TODO: [ESP32C61] IDF-9323
// \#define SOC_DIG_SIGN_SUPPORTED 1 //TODO: [ESP32C61] IDF-9325 // \#define SOC_DIG_SIGN_SUPPORTED 1 //TODO: [ESP32C61] IDF-9325
// \#define SOC_ECC_SUPPORTED 1 //TODO: [ESP32C61] IDF-9235 #define SOC_ECC_SUPPORTED 1
#define SOC_ECC_EXTENDED_MODES_SUPPORTED 1
#define SOC_FLASH_ENC_SUPPORTED 1 //TODO: [ESP32C61] IDF-9232 #define SOC_FLASH_ENC_SUPPORTED 1 //TODO: [ESP32C61] IDF-9232
// \#define SOC_SECURE_BOOT_SUPPORTED 1 //TODO: [ESP32C61] IDF-9233 // \#define SOC_SECURE_BOOT_SUPPORTED 1 //TODO: [ESP32C61] IDF-9233
// \#define SOC_BOD_SUPPORTED 1 //TODO: [ESP32C61] IDF-9254 // \#define SOC_BOD_SUPPORTED 1 //TODO: [ESP32C61] IDF-9254