From f0c34575d147263aee9164f4274a55e4bfba6251 Mon Sep 17 00:00:00 2001
From: laokaiyao <laokaiyao@espressif.com>
Date: Fri, 6 Sep 2024 17:22:19 +0800
Subject: [PATCH] refactor(soc): sort esp32c6 soc headers

---
 .../soc/esp32c6/include/soc/dport_access.h    |   1 -
 components/soc/esp32c6/include/soc/soc.h      |   2 +-
 .../soc/esp32c6/include/soc/system_reg.h      |   2 +-
 components/soc/esp32c6/register/soc/.gitkeep  |   0
 .../{include => register}/soc/aes_reg.h       |   0
 .../{include => register}/soc/aes_struct.h    |   0
 .../soc/apb_saradc_reg.h                      |   0
 .../soc/apb_saradc_struct.h                   |   0
 .../soc/assist_debug_reg.h                    |  12 +-
 .../soc/assist_debug_struct.h                 |  18 +-
 .../{include => register}/soc/clint_reg.h     |   0
 .../{include => register}/soc/ds_reg.h        |   0
 .../{include => register}/soc/ds_struct.h     |   0
 .../{include => register}/soc/ecc_mult_reg.h  |   2 +-
 .../soc/ecc_mult_struct.h                     |   2 +-
 .../{include => register}/soc/efuse_reg.h     |   8 +-
 .../{include => register}/soc/efuse_struct.h  |   6 +-
 .../{include => register}/soc/extmem_reg.h    |  36 +--
 .../{include => register}/soc/extmem_struct.h |   8 +-
 .../{include => register}/soc/gdma_reg.h      |   0
 .../{include => register}/soc/gdma_struct.h   |   0
 .../{include => register}/soc/gpio_ext_reg.h  |   0
 .../soc/gpio_ext_struct.h                     |   0
 .../{include => register}/soc/gpio_reg.h      |   0
 .../{include => register}/soc/gpio_struct.h   |   0
 .../soc/hardware_lock_reg.h                   |  10 +-
 .../soc/hardware_lock_struct.h                |  10 +-
 .../{include => register}/soc/hinf_reg.h      |   0
 .../{include => register}/soc/hinf_struct.h   |   0
 .../{include => register}/soc/hmac_reg.h      |   0
 .../{include => register}/soc/hmac_struct.h   |   0
 .../{include => register}/soc/host_reg.h      |   0
 .../{include => register}/soc/host_struct.h   |   0
 .../{include => register}/soc/hp_apm_reg.h    |   0
 .../{include => register}/soc/hp_apm_struct.h |   0
 .../{include => register}/soc/hp_system_reg.h |   2 +-
 .../soc/hp_system_struct.h                    |   2 +-
 .../soc/i2c_ana_mst_reg.h                     |   0
 .../{include => register}/soc/i2c_reg.h       |   0
 .../{include => register}/soc/i2c_struct.h    |   0
 .../{include => register}/soc/i2s_reg.h       |   2 +-
 .../{include => register}/soc/i2s_struct.h    |   2 +-
 .../soc/ieee802154_reg.h                      |   0
 .../soc/ieee802154_struct.h                   |   0
 .../soc/interrupt_matrix_reg.h                |   0
 .../soc/interrupt_matrix_struct.h             |   0
 .../{include => register}/soc/intpri_reg.h    |   0
 .../{include => register}/soc/intpri_struct.h |   0
 .../{include => register}/soc/io_mux_reg.h    |   2 +-
 .../{include => register}/soc/ledc_reg.h      |   0
 .../{include => register}/soc/ledc_struct.h   |   0
 .../soc/lp_analog_peri_reg.h                  |   0
 .../soc/lp_analog_peri_struct.h               |   0
 .../{include => register}/soc/lp_aon_reg.h    |   0
 .../{include => register}/soc/lp_aon_struct.h |   0
 .../{include => register}/soc/lp_apm0_reg.h   |   0
 .../soc/lp_apm0_struct.h                      |   0
 .../{include => register}/soc/lp_apm_reg.h    |   0
 .../{include => register}/soc/lp_apm_struct.h |   0
 .../{include => register}/soc/lp_clkrst_reg.h |   0
 .../soc/lp_clkrst_struct.h                    |   0
 .../soc/lp_i2c_ana_mst_reg.h                  |   0
 .../soc/lp_i2c_ana_mst_struct.h               |   0
 .../{include => register}/soc/lp_i2c_reg.h    |   0
 .../{include => register}/soc/lp_i2c_struct.h |   0
 .../{include => register}/soc/lp_io_reg.h     |   0
 .../{include => register}/soc/lp_io_struct.h  |   0
 .../{include => register}/soc/lp_tee_reg.h    |   0
 .../{include => register}/soc/lp_tee_struct.h |   0
 .../{include => register}/soc/lp_timer_reg.h  |   0
 .../soc/lp_timer_struct.h                     |   0
 .../{include => register}/soc/lp_uart_reg.h   |   8 +-
 .../soc/lp_uart_struct.h                      |  10 +-
 .../{include => register}/soc/lp_wdt_reg.h    |   0
 .../{include => register}/soc/lp_wdt_struct.h |   0
 .../{include => register}/soc/lpperi_reg.h    |   0
 .../{include => register}/soc/lpperi_struct.h |   0
 .../{include => register}/soc/mcpwm_reg.h     |  12 +-
 .../{include => register}/soc/mcpwm_struct.h  |   4 +-
 .../soc/mem_monitor_reg.h                     |   8 +-
 .../soc/mem_monitor_struct.h                  |   8 +-
 .../{include => register}/soc/otp_debug_reg.h | 260 ++++++++---------
 .../soc/otp_debug_struct.h                    | 262 +++++++++---------
 .../{include => register}/soc/parl_io_reg.h   |  10 +-
 .../soc/parl_io_struct.h                      |  10 +-
 .../{include => register}/soc/pau_reg.h       |   0
 .../{include => register}/soc/pau_struct.h    |   0
 .../{include => register}/soc/pcnt_reg.h      |   0
 .../{include => register}/soc/pcnt_struct.h   |   0
 .../{include => register}/soc/pcr_reg.h       |  54 ++--
 .../{include => register}/soc/pcr_struct.h    |  54 ++--
 .../{include => register}/soc/plic_reg.h      |   0
 .../{include => register}/soc/pmu_reg.h       |   0
 .../{include => register}/soc/pmu_struct.h    |   2 +-
 .../{include => register}/soc/reg_base.h      |   0
 .../{include => register}/soc/rmt_reg.h       |   0
 .../{include => register}/soc/rmt_struct.h    |   0
 .../{include => register}/soc/rsa_reg.h       |   0
 .../{include => register}/soc/rsa_struct.h    |   0
 .../{include => register}/soc/sha_reg.h       |   2 +-
 .../{include => register}/soc/sha_struct.h    |   0
 .../{include => register}/soc/slc_reg.h       |   0
 .../{include => register}/soc/slc_struct.h    |   0
 .../{include => register}/soc/soc_etm_reg.h   |   0
 .../soc/soc_etm_struct.h                      |   0
 .../{include => register}/soc/spi_mem_reg.h   |  52 ++--
 .../soc/spi_mem_struct.h                      |   8 +-
 .../{include => register}/soc/spi_reg.h       |   4 +-
 .../{include => register}/soc/spi_struct.h    |   4 +-
 .../{include => register}/soc/systimer_reg.h  |   0
 .../soc/systimer_struct.h                     |   0
 .../{include => register}/soc/tee_reg.h       |   0
 .../{include => register}/soc/tee_struct.h    |   0
 .../soc/timer_group_reg.h                     |   0
 .../soc/timer_group_struct.h                  |   0
 .../{include => register}/soc/trace_reg.h     |   2 +-
 .../{include => register}/soc/trace_struct.h  |   2 +-
 .../{include => register}/soc/twai_reg.h      |   0
 .../{include => register}/soc/twai_struct.h   |   0
 .../{include => register}/soc/uart_reg.h      |  10 +-
 .../{include => register}/soc/uart_struct.h   |  10 +-
 .../{include => register}/soc/uhci_reg.h      |   0
 .../{include => register}/soc/uhci_struct.h   |   0
 .../soc/usb_serial_jtag_reg.h                 |   2 +-
 .../soc/usb_serial_jtag_struct.h              |   0
 .../{include => register}/soc/xts_aes_reg.h   |   6 +-
 126 files changed, 465 insertions(+), 466 deletions(-)
 delete mode 100644 components/soc/esp32c6/register/soc/.gitkeep
 rename components/soc/esp32c6/{include => register}/soc/aes_reg.h (100%)
 rename components/soc/esp32c6/{include => register}/soc/aes_struct.h (100%)
 rename components/soc/esp32c6/{include => register}/soc/apb_saradc_reg.h (100%)
 rename components/soc/esp32c6/{include => register}/soc/apb_saradc_struct.h (100%)
 rename components/soc/esp32c6/{include => register}/soc/assist_debug_reg.h (99%)
 rename components/soc/esp32c6/{include => register}/soc/assist_debug_struct.h (98%)
 rename components/soc/esp32c6/{include => register}/soc/clint_reg.h (100%)
 rename components/soc/esp32c6/{include => register}/soc/ds_reg.h (100%)
 rename components/soc/esp32c6/{include => register}/soc/ds_struct.h (100%)
 rename components/soc/esp32c6/{include => register}/soc/ecc_mult_reg.h (98%)
 rename components/soc/esp32c6/{include => register}/soc/ecc_mult_struct.h (97%)
 rename components/soc/esp32c6/{include => register}/soc/efuse_reg.h (99%)
 rename components/soc/esp32c6/{include => register}/soc/efuse_struct.h (99%)
 rename components/soc/esp32c6/{include => register}/soc/extmem_reg.h (98%)
 rename components/soc/esp32c6/{include => register}/soc/extmem_struct.h (99%)
 rename components/soc/esp32c6/{include => register}/soc/gdma_reg.h (100%)
 rename components/soc/esp32c6/{include => register}/soc/gdma_struct.h (100%)
 rename components/soc/esp32c6/{include => register}/soc/gpio_ext_reg.h (100%)
 rename components/soc/esp32c6/{include => register}/soc/gpio_ext_struct.h (100%)
 rename components/soc/esp32c6/{include => register}/soc/gpio_reg.h (100%)
 rename components/soc/esp32c6/{include => register}/soc/gpio_struct.h (100%)
 rename components/soc/esp32c6/{include => register}/soc/hardware_lock_reg.h (93%)
 rename components/soc/esp32c6/{include => register}/soc/hardware_lock_struct.h (92%)
 rename components/soc/esp32c6/{include => register}/soc/hinf_reg.h (100%)
 rename components/soc/esp32c6/{include => register}/soc/hinf_struct.h (100%)
 rename components/soc/esp32c6/{include => register}/soc/hmac_reg.h (100%)
 rename components/soc/esp32c6/{include => register}/soc/hmac_struct.h (100%)
 rename components/soc/esp32c6/{include => register}/soc/host_reg.h (100%)
 rename components/soc/esp32c6/{include => register}/soc/host_struct.h (100%)
 rename components/soc/esp32c6/{include => register}/soc/hp_apm_reg.h (100%)
 rename components/soc/esp32c6/{include => register}/soc/hp_apm_struct.h (100%)
 rename components/soc/esp32c6/{include => register}/soc/hp_system_reg.h (99%)
 rename components/soc/esp32c6/{include => register}/soc/hp_system_struct.h (99%)
 rename components/soc/esp32c6/{include => register}/soc/i2c_ana_mst_reg.h (100%)
 rename components/soc/esp32c6/{include => register}/soc/i2c_reg.h (100%)
 rename components/soc/esp32c6/{include => register}/soc/i2c_struct.h (100%)
 rename components/soc/esp32c6/{include => register}/soc/i2s_reg.h (99%)
 rename components/soc/esp32c6/{include => register}/soc/i2s_struct.h (99%)
 rename components/soc/esp32c6/{include => register}/soc/ieee802154_reg.h (100%)
 rename components/soc/esp32c6/{include => register}/soc/ieee802154_struct.h (100%)
 rename components/soc/esp32c6/{include => register}/soc/interrupt_matrix_reg.h (100%)
 rename components/soc/esp32c6/{include => register}/soc/interrupt_matrix_struct.h (100%)
 rename components/soc/esp32c6/{include => register}/soc/intpri_reg.h (100%)
 rename components/soc/esp32c6/{include => register}/soc/intpri_struct.h (100%)
 rename components/soc/esp32c6/{include => register}/soc/io_mux_reg.h (99%)
 rename components/soc/esp32c6/{include => register}/soc/ledc_reg.h (100%)
 rename components/soc/esp32c6/{include => register}/soc/ledc_struct.h (100%)
 rename components/soc/esp32c6/{include => register}/soc/lp_analog_peri_reg.h (100%)
 rename components/soc/esp32c6/{include => register}/soc/lp_analog_peri_struct.h (100%)
 rename components/soc/esp32c6/{include => register}/soc/lp_aon_reg.h (100%)
 rename components/soc/esp32c6/{include => register}/soc/lp_aon_struct.h (100%)
 rename components/soc/esp32c6/{include => register}/soc/lp_apm0_reg.h (100%)
 rename components/soc/esp32c6/{include => register}/soc/lp_apm0_struct.h (100%)
 rename components/soc/esp32c6/{include => register}/soc/lp_apm_reg.h (100%)
 rename components/soc/esp32c6/{include => register}/soc/lp_apm_struct.h (100%)
 rename components/soc/esp32c6/{include => register}/soc/lp_clkrst_reg.h (100%)
 rename components/soc/esp32c6/{include => register}/soc/lp_clkrst_struct.h (100%)
 rename components/soc/esp32c6/{include => register}/soc/lp_i2c_ana_mst_reg.h (100%)
 rename components/soc/esp32c6/{include => register}/soc/lp_i2c_ana_mst_struct.h (100%)
 rename components/soc/esp32c6/{include => register}/soc/lp_i2c_reg.h (100%)
 rename components/soc/esp32c6/{include => register}/soc/lp_i2c_struct.h (100%)
 rename components/soc/esp32c6/{include => register}/soc/lp_io_reg.h (100%)
 rename components/soc/esp32c6/{include => register}/soc/lp_io_struct.h (100%)
 rename components/soc/esp32c6/{include => register}/soc/lp_tee_reg.h (100%)
 rename components/soc/esp32c6/{include => register}/soc/lp_tee_struct.h (100%)
 rename components/soc/esp32c6/{include => register}/soc/lp_timer_reg.h (100%)
 rename components/soc/esp32c6/{include => register}/soc/lp_timer_struct.h (100%)
 rename components/soc/esp32c6/{include => register}/soc/lp_uart_reg.h (99%)
 rename components/soc/esp32c6/{include => register}/soc/lp_uart_struct.h (99%)
 rename components/soc/esp32c6/{include => register}/soc/lp_wdt_reg.h (100%)
 rename components/soc/esp32c6/{include => register}/soc/lp_wdt_struct.h (100%)
 rename components/soc/esp32c6/{include => register}/soc/lpperi_reg.h (100%)
 rename components/soc/esp32c6/{include => register}/soc/lpperi_struct.h (100%)
 rename components/soc/esp32c6/{include => register}/soc/mcpwm_reg.h (99%)
 rename components/soc/esp32c6/{include => register}/soc/mcpwm_struct.h (99%)
 rename components/soc/esp32c6/{include => register}/soc/mem_monitor_reg.h (98%)
 rename components/soc/esp32c6/{include => register}/soc/mem_monitor_struct.h (98%)
 rename components/soc/esp32c6/{include => register}/soc/otp_debug_reg.h (91%)
 rename components/soc/esp32c6/{include => register}/soc/otp_debug_struct.h (89%)
 rename components/soc/esp32c6/{include => register}/soc/parl_io_reg.h (98%)
 rename components/soc/esp32c6/{include => register}/soc/parl_io_struct.h (97%)
 rename components/soc/esp32c6/{include => register}/soc/pau_reg.h (100%)
 rename components/soc/esp32c6/{include => register}/soc/pau_struct.h (100%)
 rename components/soc/esp32c6/{include => register}/soc/pcnt_reg.h (100%)
 rename components/soc/esp32c6/{include => register}/soc/pcnt_struct.h (100%)
 rename components/soc/esp32c6/{include => register}/soc/pcr_reg.h (98%)
 rename components/soc/esp32c6/{include => register}/soc/pcr_struct.h (97%)
 rename components/soc/esp32c6/{include => register}/soc/plic_reg.h (100%)
 rename components/soc/esp32c6/{include => register}/soc/pmu_reg.h (100%)
 rename components/soc/esp32c6/{include => register}/soc/pmu_struct.h (99%)
 rename components/soc/esp32c6/{include => register}/soc/reg_base.h (100%)
 rename components/soc/esp32c6/{include => register}/soc/rmt_reg.h (100%)
 rename components/soc/esp32c6/{include => register}/soc/rmt_struct.h (100%)
 rename components/soc/esp32c6/{include => register}/soc/rsa_reg.h (100%)
 rename components/soc/esp32c6/{include => register}/soc/rsa_struct.h (100%)
 rename components/soc/esp32c6/{include => register}/soc/sha_reg.h (98%)
 rename components/soc/esp32c6/{include => register}/soc/sha_struct.h (100%)
 rename components/soc/esp32c6/{include => register}/soc/slc_reg.h (100%)
 rename components/soc/esp32c6/{include => register}/soc/slc_struct.h (100%)
 rename components/soc/esp32c6/{include => register}/soc/soc_etm_reg.h (100%)
 rename components/soc/esp32c6/{include => register}/soc/soc_etm_struct.h (100%)
 rename components/soc/esp32c6/{include => register}/soc/spi_mem_reg.h (99%)
 rename components/soc/esp32c6/{include => register}/soc/spi_mem_struct.h (99%)
 rename components/soc/esp32c6/{include => register}/soc/spi_reg.h (99%)
 rename components/soc/esp32c6/{include => register}/soc/spi_struct.h (99%)
 rename components/soc/esp32c6/{include => register}/soc/systimer_reg.h (100%)
 rename components/soc/esp32c6/{include => register}/soc/systimer_struct.h (100%)
 rename components/soc/esp32c6/{include => register}/soc/tee_reg.h (100%)
 rename components/soc/esp32c6/{include => register}/soc/tee_struct.h (100%)
 rename components/soc/esp32c6/{include => register}/soc/timer_group_reg.h (100%)
 rename components/soc/esp32c6/{include => register}/soc/timer_group_struct.h (100%)
 rename components/soc/esp32c6/{include => register}/soc/trace_reg.h (99%)
 rename components/soc/esp32c6/{include => register}/soc/trace_struct.h (99%)
 rename components/soc/esp32c6/{include => register}/soc/twai_reg.h (100%)
 rename components/soc/esp32c6/{include => register}/soc/twai_struct.h (100%)
 rename components/soc/esp32c6/{include => register}/soc/uart_reg.h (99%)
 rename components/soc/esp32c6/{include => register}/soc/uart_struct.h (99%)
 rename components/soc/esp32c6/{include => register}/soc/uhci_reg.h (100%)
 rename components/soc/esp32c6/{include => register}/soc/uhci_struct.h (100%)
 rename components/soc/esp32c6/{include => register}/soc/usb_serial_jtag_reg.h (99%)
 rename components/soc/esp32c6/{include => register}/soc/usb_serial_jtag_struct.h (100%)
 rename components/soc/esp32c6/{include => register}/soc/xts_aes_reg.h (98%)

diff --git a/components/soc/esp32c6/include/soc/dport_access.h b/components/soc/esp32c6/include/soc/dport_access.h
index 000b58c36a..54eb8a0a35 100644
--- a/components/soc/esp32c6/include/soc/dport_access.h
+++ b/components/soc/esp32c6/include/soc/dport_access.h
@@ -9,7 +9,6 @@
 
 #include <stdint.h>
 #include "soc.h"
-#include "uart_reg.h"
 
 #ifdef __cplusplus
 extern "C" {
diff --git a/components/soc/esp32c6/include/soc/soc.h b/components/soc/esp32c6/include/soc/soc.h
index 6778a1764b..afd44da86c 100644
--- a/components/soc/esp32c6/include/soc/soc.h
+++ b/components/soc/esp32c6/include/soc/soc.h
@@ -12,7 +12,7 @@
 #endif
 
 #include "esp_bit_defs.h"
-#include "reg_base.h"
+#include "soc/reg_base.h"
 
 #define PRO_CPU_NUM (0)
 
diff --git a/components/soc/esp32c6/include/soc/system_reg.h b/components/soc/esp32c6/include/soc/system_reg.h
index 4ed6ac2ac2..17cf94805e 100644
--- a/components/soc/esp32c6/include/soc/system_reg.h
+++ b/components/soc/esp32c6/include/soc/system_reg.h
@@ -7,6 +7,6 @@
 #include "soc/hp_system_reg.h"
 
 // TODO: IDF-5720
-#include "intpri_reg.h"
+#include "soc/intpri_reg.h"
 #define SYSTEM_CPU_INTR_FROM_CPU_0_REG INTPRI_CPU_INTR_FROM_CPU_0_REG
 #define SYSTEM_CPU_INTR_FROM_CPU_0 INTPRI_CPU_INTR_FROM_CPU_0
diff --git a/components/soc/esp32c6/register/soc/.gitkeep b/components/soc/esp32c6/register/soc/.gitkeep
deleted file mode 100644
index e69de29bb2..0000000000
diff --git a/components/soc/esp32c6/include/soc/aes_reg.h b/components/soc/esp32c6/register/soc/aes_reg.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/aes_reg.h
rename to components/soc/esp32c6/register/soc/aes_reg.h
diff --git a/components/soc/esp32c6/include/soc/aes_struct.h b/components/soc/esp32c6/register/soc/aes_struct.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/aes_struct.h
rename to components/soc/esp32c6/register/soc/aes_struct.h
diff --git a/components/soc/esp32c6/include/soc/apb_saradc_reg.h b/components/soc/esp32c6/register/soc/apb_saradc_reg.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/apb_saradc_reg.h
rename to components/soc/esp32c6/register/soc/apb_saradc_reg.h
diff --git a/components/soc/esp32c6/include/soc/apb_saradc_struct.h b/components/soc/esp32c6/register/soc/apb_saradc_struct.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/apb_saradc_struct.h
rename to components/soc/esp32c6/register/soc/apb_saradc_struct.h
diff --git a/components/soc/esp32c6/include/soc/assist_debug_reg.h b/components/soc/esp32c6/register/soc/assist_debug_reg.h
similarity index 99%
rename from components/soc/esp32c6/include/soc/assist_debug_reg.h
rename to components/soc/esp32c6/register/soc/assist_debug_reg.h
index 8e0426dc6f..d2b947d946 100644
--- a/components/soc/esp32c6/include/soc/assist_debug_reg.h
+++ b/components/soc/esp32c6/register/soc/assist_debug_reg.h
@@ -92,7 +92,7 @@ extern "C" {
 #define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_V  0x00000001U
 #define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_S  10
 /** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA : R/W; bitpos: [11]; default: 0;
- *  DBUS busy monitor enbale
+ *  DBUS busy monitor enable
  */
 #define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA    (BIT(11))
 #define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_M  (ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_V << ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_S)
@@ -270,7 +270,7 @@ extern "C" {
 #define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_V  0x00000001U
 #define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_S  10
 /** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS : R/W; bitpos: [11]; default: 0;
- *  DBUS busy monitor interrupt enbale
+ *  DBUS busy monitor interrupt enable
  */
 #define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS    (BIT(11))
 #define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_M  (ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_V << ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_S)
@@ -491,7 +491,7 @@ extern "C" {
  */
 #define ASSIST_DEBUG_CORE_0_SP_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x38)
 /** ASSIST_DEBUG_CORE_0_SP_MIN : R/W; bitpos: [31:0]; default: 0;
- *  core0 sp region configuration regsiter
+ *  core0 sp region configuration register
  */
 #define ASSIST_DEBUG_CORE_0_SP_MIN    0xFFFFFFFFU
 #define ASSIST_DEBUG_CORE_0_SP_MIN_M  (ASSIST_DEBUG_CORE_0_SP_MIN_V << ASSIST_DEBUG_CORE_0_SP_MIN_S)
@@ -515,7 +515,7 @@ extern "C" {
  */
 #define ASSIST_DEBUG_CORE_0_SP_PC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x40)
 /** ASSIST_DEBUG_CORE_0_SP_PC : RO; bitpos: [31:0]; default: 0;
- *  This regsiter stores the PC when trigger stack monitor.
+ *  This register stores the PC when trigger stack monitor.
  */
 #define ASSIST_DEBUG_CORE_0_SP_PC    0xFFFFFFFFU
 #define ASSIST_DEBUG_CORE_0_SP_PC_M  (ASSIST_DEBUG_CORE_0_SP_PC_V << ASSIST_DEBUG_CORE_0_SP_PC_S)
@@ -542,7 +542,7 @@ extern "C" {
 #define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_S  1
 
 /** ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG register
- *  record status regsiter
+ *  record status register
  */
 #define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x48)
 /** ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC : RO; bitpos: [31:0]; default: 0;
@@ -554,7 +554,7 @@ extern "C" {
 #define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_S  0
 
 /** ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG register
- *  record status regsiter
+ *  record status register
  */
 #define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG (DR_REG_ASSIST_DEBUG_BASE + 0x4c)
 /** ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP : RO; bitpos: [31:0]; default: 0;
diff --git a/components/soc/esp32c6/include/soc/assist_debug_struct.h b/components/soc/esp32c6/register/soc/assist_debug_struct.h
similarity index 98%
rename from components/soc/esp32c6/include/soc/assist_debug_struct.h
rename to components/soc/esp32c6/register/soc/assist_debug_struct.h
index 24c28c33ef..9838880bc8 100644
--- a/components/soc/esp32c6/include/soc/assist_debug_struct.h
+++ b/components/soc/esp32c6/register/soc/assist_debug_struct.h
@@ -61,7 +61,7 @@ typedef union {
          */
         uint32_t core_0_iram0_exception_monitor_ena:1;
         /** core_0_dram0_exception_monitor_ena : R/W; bitpos: [11]; default: 0;
-         *  DBUS busy monitor enbale
+         *  DBUS busy monitor enable
          */
         uint32_t core_0_dram0_exception_monitor_ena:1;
         uint32_t reserved_12:20;
@@ -205,7 +205,7 @@ typedef union {
 typedef union {
     struct {
         /** core_0_sp_min : R/W; bitpos: [31:0]; default: 0;
-         *  core0 sp region configuration regsiter
+         *  core0 sp region configuration register
          */
         uint32_t core_0_sp_min:32;
     };
@@ -231,7 +231,7 @@ typedef union {
 typedef union {
     struct {
         /** core_0_sp_pc : RO; bitpos: [31:0]; default: 0;
-         *  This regsiter stores the PC when trigger stack monitor.
+         *  This register stores the PC when trigger stack monitor.
          */
         uint32_t core_0_sp_pc:32;
     };
@@ -348,7 +348,7 @@ typedef union {
          */
         uint32_t core_0_iram0_exception_monitor_rls:1;
         /** core_0_dram0_exception_monitor_rls : R/W; bitpos: [11]; default: 0;
-         *  DBUS busy monitor interrupt enbale
+         *  DBUS busy monitor interrupt enable
          */
         uint32_t core_0_dram0_exception_monitor_rls:1;
         uint32_t reserved_12:20;
@@ -415,7 +415,7 @@ typedef union {
 } assist_debug_core_0_intr_clr_reg_t;
 
 
-/** Group: pc reording configuration register */
+/** Group: pc recording configuration register */
 /** Type of core_0_rcd_en register
  *  record enable configuration register
  */
@@ -435,9 +435,9 @@ typedef union {
 } assist_debug_core_0_rcd_en_reg_t;
 
 
-/** Group: pc reording status register */
+/** Group: pc recording status register */
 /** Type of core_0_rcd_pdebugpc register
- *  record status regsiter
+ *  record status register
  */
 typedef union {
     struct {
@@ -450,7 +450,7 @@ typedef union {
 } assist_debug_core_0_rcd_pdebugpc_reg_t;
 
 /** Type of core_0_rcd_pdebugsp register
- *  record status regsiter
+ *  record status register
  */
 typedef union {
     struct {
@@ -463,7 +463,7 @@ typedef union {
 } assist_debug_core_0_rcd_pdebugsp_reg_t;
 
 
-/** Group: exception monitor regsiter */
+/** Group: exception monitor register */
 /** Type of core_0_iram0_exception_monitor_0 register
  *  exception monitor status register0
  */
diff --git a/components/soc/esp32c6/include/soc/clint_reg.h b/components/soc/esp32c6/register/soc/clint_reg.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/clint_reg.h
rename to components/soc/esp32c6/register/soc/clint_reg.h
diff --git a/components/soc/esp32c6/include/soc/ds_reg.h b/components/soc/esp32c6/register/soc/ds_reg.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/ds_reg.h
rename to components/soc/esp32c6/register/soc/ds_reg.h
diff --git a/components/soc/esp32c6/include/soc/ds_struct.h b/components/soc/esp32c6/register/soc/ds_struct.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/ds_struct.h
rename to components/soc/esp32c6/register/soc/ds_struct.h
diff --git a/components/soc/esp32c6/include/soc/ecc_mult_reg.h b/components/soc/esp32c6/register/soc/ecc_mult_reg.h
similarity index 98%
rename from components/soc/esp32c6/include/soc/ecc_mult_reg.h
rename to components/soc/esp32c6/register/soc/ecc_mult_reg.h
index dca2cc1206..00846e8ed6 100644
--- a/components/soc/esp32c6/include/soc/ecc_mult_reg.h
+++ b/components/soc/esp32c6/register/soc/ecc_mult_reg.h
@@ -64,7 +64,7 @@ extern "C" {
  */
 #define ECC_MULT_CONF_REG (DR_REG_ECC_MULT_BASE + 0x1c)
 /** ECC_MULT_START : R/W/SC; bitpos: [0]; default: 0;
- *  Write 1 to start caculation of ECC Accelerator. This bit will be self-cleared after
+ *  Write 1 to start calculation of ECC Accelerator. This bit will be self-cleared after
  *  the caculatrion is done.
  */
 #define ECC_MULT_START    (BIT(0))
diff --git a/components/soc/esp32c6/include/soc/ecc_mult_struct.h b/components/soc/esp32c6/register/soc/ecc_mult_struct.h
similarity index 97%
rename from components/soc/esp32c6/include/soc/ecc_mult_struct.h
rename to components/soc/esp32c6/register/soc/ecc_mult_struct.h
index c120fb068d..8966532436 100644
--- a/components/soc/esp32c6/include/soc/ecc_mult_struct.h
+++ b/components/soc/esp32c6/register/soc/ecc_mult_struct.h
@@ -77,7 +77,7 @@ typedef union {
 typedef union {
     struct {
         /** start : R/W/SC; bitpos: [0]; default: 0;
-         *  Write 1 to start caculation of ECC Accelerator. This bit will be self-cleared after
+         *  Write 1 to start calculation of ECC Accelerator. This bit will be self-cleared after
          *  the caculatrion is done.
          */
         uint32_t start:1;
diff --git a/components/soc/esp32c6/include/soc/efuse_reg.h b/components/soc/esp32c6/register/soc/efuse_reg.h
similarity index 99%
rename from components/soc/esp32c6/include/soc/efuse_reg.h
rename to components/soc/esp32c6/register/soc/efuse_reg.h
index 882041ac41..b91b0b0ff0 100644
--- a/components/soc/esp32c6/include/soc/efuse_reg.h
+++ b/components/soc/esp32c6/register/soc/efuse_reg.h
@@ -7,7 +7,7 @@
 
 #include <stdint.h>
 #include "soc/soc.h"
-#include "efuse_defs.h"
+#include "soc/efuse_defs.h"
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -264,14 +264,14 @@ extern "C" {
 #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V  0x00000001U
 #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S  20
 /** EFUSE_USB_DREFH : RO; bitpos: [22:21]; default: 0;
- *  Represents the single-end input threhold vrefh, 1.76 V to 2 V with step of 80 mV.
+ *  Represents the single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV.
  */
 #define EFUSE_USB_DREFH    0x00000003U
 #define EFUSE_USB_DREFH_M  (EFUSE_USB_DREFH_V << EFUSE_USB_DREFH_S)
 #define EFUSE_USB_DREFH_V  0x00000003U
 #define EFUSE_USB_DREFH_S  21
 /** EFUSE_USB_DREFL : RO; bitpos: [24:23]; default: 0;
- *  Represents the single-end input threhold vrefl, 1.76 V to 2 V with step of 80 mV.
+ *  Represents the single-end input threshold vrefl, 1.76 V to 2 V with step of 80 mV.
  */
 #define EFUSE_USB_DREFL    0x00000003U
 #define EFUSE_USB_DREFL_M  (EFUSE_USB_DREFL_V << EFUSE_USB_DREFL_S)
@@ -2390,7 +2390,7 @@ extern "C" {
 #define EFUSE_CLK_EN_S  16
 
 /** EFUSE_CONF_REG register
- *  eFuse operation mode configuraiton register
+ *  eFuse operation mode configuration register
  */
 #define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x1cc)
 /** EFUSE_OP_CODE : R/W; bitpos: [15:0]; default: 0;
diff --git a/components/soc/esp32c6/include/soc/efuse_struct.h b/components/soc/esp32c6/register/soc/efuse_struct.h
similarity index 99%
rename from components/soc/esp32c6/include/soc/efuse_struct.h
rename to components/soc/esp32c6/register/soc/efuse_struct.h
index e6971b4d58..c92f02208c 100644
--- a/components/soc/esp32c6/include/soc/efuse_struct.h
+++ b/components/soc/esp32c6/register/soc/efuse_struct.h
@@ -239,11 +239,11 @@ typedef union {
          */
         uint32_t dis_download_manual_encrypt:1;
         /** usb_drefh : RO; bitpos: [22:21]; default: 0;
-         *  Represents the single-end input threhold vrefh, 1.76 V to 2 V with step of 80 mV.
+         *  Represents the single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV.
          */
         uint32_t usb_drefh:2;
         /** usb_drefl : RO; bitpos: [24:23]; default: 0;
-         *  Represents the single-end input threhold vrefl, 1.76 V to 2 V with step of 80 mV.
+         *  Represents the single-end input threshold vrefl, 1.76 V to 2 V with step of 80 mV.
          */
         uint32_t usb_drefl:2;
         /** usb_exchg_pins : RO; bitpos: [25]; default: 0;
@@ -2024,7 +2024,7 @@ typedef union {
 } efuse_clk_reg_t;
 
 /** Type of conf register
- *  eFuse operation mode configuraiton register
+ *  eFuse operation mode configuration register
  */
 typedef union {
     struct {
diff --git a/components/soc/esp32c6/include/soc/extmem_reg.h b/components/soc/esp32c6/register/soc/extmem_reg.h
similarity index 98%
rename from components/soc/esp32c6/include/soc/extmem_reg.h
rename to components/soc/esp32c6/register/soc/extmem_reg.h
index a9cb693586..08a9daf433 100644
--- a/components/soc/esp32c6/include/soc/extmem_reg.h
+++ b/components/soc/esp32c6/register/soc/extmem_reg.h
@@ -243,8 +243,8 @@ ould be used together with CACHE_LOCK_ADDR_REG.*/
 #define EXTMEM_L1_CACHE_SYNC_DONE_S  4
 /* EXTMEM_L1_CACHE_WRITEBACK_INVALIDATE_ENA : R/W/SC ;bitpos:[3] ;default: 1'h0 ; */
 /*description: The bit is used to enable writeback-invalidate operation. It will be cleared by
-hardware after writeback-invalidate operation done. Note that this bit and the o
-ther sync-bits (invalidate_ena, clean_ena, writeback_ena) are mutually exclusive
+hardware after writeback-invalidate operation done. Note that this bit and the
+other sync-bits (invalidate_ena, clean_ena, writeback_ena) are mutually exclusive
 , that is, those bits can not be set to 1 at the same time..*/
 #define EXTMEM_L1_CACHE_WRITEBACK_INVALIDATE_ENA    (BIT(3))
 #define EXTMEM_L1_CACHE_WRITEBACK_INVALIDATE_ENA_M  (BIT(3))
@@ -262,16 +262,16 @@ those bits can not be set to 1 at the same time..*/
 /* EXTMEM_L1_CACHE_CLEAN_ENA : R/W/SC ;bitpos:[1] ;default: 1'h0 ; */
 /*description: The bit is used to enable clean operation. It will be cleared by hardware after
 clean operation done. Note that this bit and the other sync-bits (invalidate_ena
-, writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is, thos
-e bits can not be set to 1 at the same time..*/
+, writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is, those
+bits can not be set to 1 at the same time..*/
 #define EXTMEM_L1_CACHE_CLEAN_ENA    (BIT(1))
 #define EXTMEM_L1_CACHE_CLEAN_ENA_M  (BIT(1))
 #define EXTMEM_L1_CACHE_CLEAN_ENA_V  0x1
 #define EXTMEM_L1_CACHE_CLEAN_ENA_S  1
 /* EXTMEM_L1_CACHE_INVALIDATE_ENA : R/W/SC ;bitpos:[0] ;default: 1'h1 ; */
 /*description: The bit is used to enable invalidate operation. It will be cleared by hardware a
-fter invalidate operation done. Note that this bit and the other sync-bits (clea
-n_ena, writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is,
+after invalidate operation done. Note that this bit and the other sync-bits (clean_ena,
+writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is,
  those bits can not be set to 1 at the same time..*/
 #define EXTMEM_L1_CACHE_INVALIDATE_ENA    (BIT(0))
 #define EXTMEM_L1_CACHE_INVALIDATE_ENA_M  (BIT(0))
@@ -452,15 +452,15 @@ SCT1_ADDR and L1_CACHE_AUTOLOAD_SCT1_ENA..*/
 
 #define EXTMEM_L1_CACHE_ACS_CNT_INT_CLR_REG          (DR_REG_EXTMEM_BASE + 0x15C)
 /* EXTMEM_L1_DBUS_OVF_INT_CLR : WT ;bitpos:[5] ;default: 1'b0 ; */
-/*description: The bit is used to clear counters overflow interrupt and counters in L1-DCache d
-ue to bus1 accesses L1-DCache..*/
+/*description: The bit is used to clear counters overflow interrupt and counters in L1-DCache due
+to bus1 accesses L1-DCache..*/
 #define EXTMEM_L1_DBUS_OVF_INT_CLR    (BIT(5))
 #define EXTMEM_L1_DBUS_OVF_INT_CLR_M  (BIT(5))
 #define EXTMEM_L1_DBUS_OVF_INT_CLR_V  0x1
 #define EXTMEM_L1_DBUS_OVF_INT_CLR_S  5
 /* EXTMEM_L1_IBUS_OVF_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The bit is used to clear counters overflow interrupt and counters in L1-DCache d
-ue to bus0 accesses L1-DCache..*/
+/*description: The bit is used to clear counters overflow interrupt and counters in L1-DCache due
+to bus0 accesses L1-DCache..*/
 #define EXTMEM_L1_IBUS_OVF_INT_CLR    (BIT(4))
 #define EXTMEM_L1_IBUS_OVF_INT_CLR_M  (BIT(4))
 #define EXTMEM_L1_IBUS_OVF_INT_CLR_V  0x1
@@ -526,8 +526,8 @@ o cpu accesses L1-DCache..*/
 
 #define EXTMEM_L1_CACHE_ACS_FAIL_INT_ST_REG          (DR_REG_EXTMEM_BASE + 0x174)
 /* EXTMEM_L1_CACHE_FAIL_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The bit indicates the interrupt status of access fail that occurs in L1-DCache d
-ue to cpu accesses L1-DCache..*/
+/*description: The bit indicates the interrupt status of access fail that occurs in L1-DCache due
+to cpu accesses L1-DCache..*/
 #define EXTMEM_L1_CACHE_FAIL_INT_ST    (BIT(4))
 #define EXTMEM_L1_CACHE_FAIL_INT_ST_M  (BIT(4))
 #define EXTMEM_L1_CACHE_FAIL_INT_ST_V  0x1
@@ -740,7 +740,7 @@ ror occurs..*/
 #define EXTMEM_L1_CACHE_SYNC_ERR_INT_ST_V  0x1
 #define EXTMEM_L1_CACHE_SYNC_ERR_INT_ST_S  13
 /* EXTMEM_L1_CACHE_PLD_ERR_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */
-/*description: The bit indicates the status of the interrupt of L1-Cache preload-operation erro
+/*description: The bit indicates the status of the interrupt of L1-Cache preload-operation error
 r..*/
 #define EXTMEM_L1_CACHE_PLD_ERR_INT_ST    (BIT(11))
 #define EXTMEM_L1_CACHE_PLD_ERR_INT_ST_M  (BIT(11))
@@ -778,7 +778,7 @@ load-operation is done..*/
 
 #define EXTMEM_L1_CACHE_SYNC_RST_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x238)
 /* EXTMEM_L1_CACHE_SYNC_RST : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: set this bit to reset sync-logic inside L1-Cache. Recommend that this should onl
+/*description: set this bit to reset sync-logic inside L1-Cache. Recommend that this should only
 y be used to initialize sync-logic when some fatal error of sync-logic occurs..*/
 #define EXTMEM_L1_CACHE_SYNC_RST    (BIT(4))
 #define EXTMEM_L1_CACHE_SYNC_RST_M  (BIT(4))
@@ -808,7 +808,7 @@ rks in L1-Cache..*/
 #define EXTMEM_L1_UNALLOCATE_BUFFER_CLEAR_REG          (DR_REG_EXTMEM_BASE + 0x244)
 /* EXTMEM_L1_CACHE_UNALLOC_CLR : R/W ;bitpos:[4] ;default: 1'b0 ; */
 /*description: The bit is used to clear the unallocate request buffer of l1 cache where the una
-llocate request is responsed but not completed..*/
+llocate request is responded but not completed..*/
 #define EXTMEM_L1_CACHE_UNALLOC_CLR    (BIT(4))
 #define EXTMEM_L1_CACHE_UNALLOC_CLR_M  (BIT(4))
 #define EXTMEM_L1_CACHE_UNALLOC_CLR_V  0x1
@@ -823,7 +823,7 @@ th the others fields inside this register..*/
 #define EXTMEM_L1_CACHE_MEM_OBJECT_V  0x1
 #define EXTMEM_L1_CACHE_MEM_OBJECT_S  10
 /* EXTMEM_L1_CACHE_TAG_OBJECT : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: Set this bit to set L1-Cache tag memory as object. This bit should be onehot wit
+/*description: Set this bit to set L1-Cache tag memory as object. This bit should be onehot with
 h the others fields inside this register..*/
 #define EXTMEM_L1_CACHE_TAG_OBJECT    (BIT(4))
 #define EXTMEM_L1_CACHE_TAG_OBJECT_M  (BIT(4))
@@ -841,8 +841,8 @@ h the others fields inside this register..*/
 
 #define EXTMEM_L1_CACHE_VADDR_REG          (DR_REG_EXTMEM_BASE + 0x250)
 /* EXTMEM_L1_CACHE_VADDR : R/W ;bitpos:[31:0] ;default: 32'h40000000 ; */
-/*description: Those bits stores the virtual address which will decide where inside the specifi
-ed tag memory object will be accessed..*/
+/*description: Those bits stores the virtual address which will decide where inside the specified
+tag memory object will be accessed..*/
 #define EXTMEM_L1_CACHE_VADDR    0xFFFFFFFF
 #define EXTMEM_L1_CACHE_VADDR_M  ((EXTMEM_L1_CACHE_VADDR_V)<<(EXTMEM_L1_CACHE_VADDR_S))
 #define EXTMEM_L1_CACHE_VADDR_V  0xFFFFFFFF
diff --git a/components/soc/esp32c6/include/soc/extmem_struct.h b/components/soc/esp32c6/register/soc/extmem_struct.h
similarity index 99%
rename from components/soc/esp32c6/include/soc/extmem_struct.h
rename to components/soc/esp32c6/register/soc/extmem_struct.h
index d309e09235..d43c5fcee3 100644
--- a/components/soc/esp32c6/include/soc/extmem_struct.h
+++ b/components/soc/esp32c6/register/soc/extmem_struct.h
@@ -5115,12 +5115,12 @@ typedef union {
     struct {
         /** l1_icache0_unalloc_clr : HRO; bitpos: [0]; default: 0;
          *  The bit is used to clear the unallocate request buffer of l1 icache0 where the
-         *  unallocate request is responsed but not completed.
+         *  unallocate request is responded but not completed.
          */
         uint32_t l1_icache0_unalloc_clr:1;
         /** l1_icache1_unalloc_clr : HRO; bitpos: [1]; default: 0;
          *  The bit is used to clear the unallocate request buffer of l1 icache1 where the
-         *  unallocate request is responsed but not completed.
+         *  unallocate request is responded but not completed.
          */
         uint32_t l1_icache1_unalloc_clr:1;
         /** l1_icache2_unalloc_clr : HRO; bitpos: [2]; default: 0;
@@ -5133,7 +5133,7 @@ typedef union {
         uint32_t l1_icache3_unalloc_clr:1;
         /** l1_cache_unalloc_clr : R/W; bitpos: [4]; default: 0;
          *  The bit is used to clear the unallocate request buffer of l1 cache where the
-         *  unallocate request is responsed but not completed.
+         *  unallocate request is responded but not completed.
          */
         uint32_t l1_cache_unalloc_clr:1;
         uint32_t reserved_5:27;
@@ -5149,7 +5149,7 @@ typedef union {
         uint32_t reserved_0:5;
         /** l2_cache_unalloc_clr : HRO; bitpos: [5]; default: 0;
          *  The bit is used to clear the unallocate request buffer of l2 icache where the
-         *  unallocate request is responsed but not completed.
+         *  unallocate request is responded but not completed.
          */
         uint32_t l2_cache_unalloc_clr:1;
         uint32_t reserved_6:26;
diff --git a/components/soc/esp32c6/include/soc/gdma_reg.h b/components/soc/esp32c6/register/soc/gdma_reg.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/gdma_reg.h
rename to components/soc/esp32c6/register/soc/gdma_reg.h
diff --git a/components/soc/esp32c6/include/soc/gdma_struct.h b/components/soc/esp32c6/register/soc/gdma_struct.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/gdma_struct.h
rename to components/soc/esp32c6/register/soc/gdma_struct.h
diff --git a/components/soc/esp32c6/include/soc/gpio_ext_reg.h b/components/soc/esp32c6/register/soc/gpio_ext_reg.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/gpio_ext_reg.h
rename to components/soc/esp32c6/register/soc/gpio_ext_reg.h
diff --git a/components/soc/esp32c6/include/soc/gpio_ext_struct.h b/components/soc/esp32c6/register/soc/gpio_ext_struct.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/gpio_ext_struct.h
rename to components/soc/esp32c6/register/soc/gpio_ext_struct.h
diff --git a/components/soc/esp32c6/include/soc/gpio_reg.h b/components/soc/esp32c6/register/soc/gpio_reg.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/gpio_reg.h
rename to components/soc/esp32c6/register/soc/gpio_reg.h
diff --git a/components/soc/esp32c6/include/soc/gpio_struct.h b/components/soc/esp32c6/register/soc/gpio_struct.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/gpio_struct.h
rename to components/soc/esp32c6/register/soc/gpio_struct.h
diff --git a/components/soc/esp32c6/include/soc/hardware_lock_reg.h b/components/soc/esp32c6/register/soc/hardware_lock_reg.h
similarity index 93%
rename from components/soc/esp32c6/include/soc/hardware_lock_reg.h
rename to components/soc/esp32c6/register/soc/hardware_lock_reg.h
index a9fbfb8cb0..a80313138c 100644
--- a/components/soc/esp32c6/include/soc/hardware_lock_reg.h
+++ b/components/soc/esp32c6/register/soc/hardware_lock_reg.h
@@ -12,7 +12,7 @@ extern "C" {
 #endif
 
 /** ATOMIC_ADDR_LOCK_REG register
- *  hardware lock regsiter
+ *  hardware lock register
  */
 #define ATOMIC_ADDR_LOCK_REG (DR_REG_ATOMIC_BASE + 0x0)
 /** ATOMIC_LOCK : R/W; bitpos: [1:0]; default: 0;
@@ -24,7 +24,7 @@ extern "C" {
 #define ATOMIC_LOCK_S  0
 
 /** ATOMIC_LR_ADDR_REG register
- *  gloable lr address regsiter
+ *  gloable lr address register
  */
 #define ATOMIC_LR_ADDR_REG (DR_REG_ATOMIC_BASE + 0x4)
 /** ATOMIC_GLOABLE_LR_ADDR : R/W; bitpos: [31:0]; default: 0;
@@ -36,7 +36,7 @@ extern "C" {
 #define ATOMIC_GLOABLE_LR_ADDR_S  0
 
 /** ATOMIC_LR_VALUE_REG register
- *  gloable lr value regsiter
+ *  gloable lr value register
  */
 #define ATOMIC_LR_VALUE_REG (DR_REG_ATOMIC_BASE + 0x8)
 /** ATOMIC_GLOABLE_LR_VALUE : R/W; bitpos: [31:0]; default: 0;
@@ -48,11 +48,11 @@ extern "C" {
 #define ATOMIC_GLOABLE_LR_VALUE_S  0
 
 /** ATOMIC_LOCK_STATUS_REG register
- *  lock status regsiter
+ *  lock status register
  */
 #define ATOMIC_LOCK_STATUS_REG (DR_REG_ATOMIC_BASE + 0xc)
 /** ATOMIC_LOCK_STATUS : RO; bitpos: [1:0]; default: 0;
- *  read hareware lock status for debug
+ *  read hardware lock status for debug
  */
 #define ATOMIC_LOCK_STATUS    0x00000003U
 #define ATOMIC_LOCK_STATUS_M  (ATOMIC_LOCK_STATUS_V << ATOMIC_LOCK_STATUS_S)
diff --git a/components/soc/esp32c6/include/soc/hardware_lock_struct.h b/components/soc/esp32c6/register/soc/hardware_lock_struct.h
similarity index 92%
rename from components/soc/esp32c6/include/soc/hardware_lock_struct.h
rename to components/soc/esp32c6/register/soc/hardware_lock_struct.h
index 0430212e50..cbea0bebea 100644
--- a/components/soc/esp32c6/include/soc/hardware_lock_struct.h
+++ b/components/soc/esp32c6/register/soc/hardware_lock_struct.h
@@ -12,7 +12,7 @@ extern "C" {
 
 /** Group: configuration registers */
 /** Type of addr_lock register
- *  hardware lock regsiter
+ *  hardware lock register
  */
 typedef union {
     struct {
@@ -26,7 +26,7 @@ typedef union {
 } atomic_addr_lock_reg_t;
 
 /** Type of lr_addr register
- *  gloable lr address regsiter
+ *  gloable lr address register
  */
 typedef union {
     struct {
@@ -39,7 +39,7 @@ typedef union {
 } atomic_lr_addr_reg_t;
 
 /** Type of lr_value register
- *  gloable lr value regsiter
+ *  gloable lr value register
  */
 typedef union {
     struct {
@@ -52,12 +52,12 @@ typedef union {
 } atomic_lr_value_reg_t;
 
 /** Type of lock_status register
- *  lock status regsiter
+ *  lock status register
  */
 typedef union {
     struct {
         /** lock_status : RO; bitpos: [1:0]; default: 0;
-         *  read hareware lock status for debug
+         *  read hardware lock status for debug
          */
         uint32_t lock_status:2;
         uint32_t reserved_2:30;
diff --git a/components/soc/esp32c6/include/soc/hinf_reg.h b/components/soc/esp32c6/register/soc/hinf_reg.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/hinf_reg.h
rename to components/soc/esp32c6/register/soc/hinf_reg.h
diff --git a/components/soc/esp32c6/include/soc/hinf_struct.h b/components/soc/esp32c6/register/soc/hinf_struct.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/hinf_struct.h
rename to components/soc/esp32c6/register/soc/hinf_struct.h
diff --git a/components/soc/esp32c6/include/soc/hmac_reg.h b/components/soc/esp32c6/register/soc/hmac_reg.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/hmac_reg.h
rename to components/soc/esp32c6/register/soc/hmac_reg.h
diff --git a/components/soc/esp32c6/include/soc/hmac_struct.h b/components/soc/esp32c6/register/soc/hmac_struct.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/hmac_struct.h
rename to components/soc/esp32c6/register/soc/hmac_struct.h
diff --git a/components/soc/esp32c6/include/soc/host_reg.h b/components/soc/esp32c6/register/soc/host_reg.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/host_reg.h
rename to components/soc/esp32c6/register/soc/host_reg.h
diff --git a/components/soc/esp32c6/include/soc/host_struct.h b/components/soc/esp32c6/register/soc/host_struct.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/host_struct.h
rename to components/soc/esp32c6/register/soc/host_struct.h
diff --git a/components/soc/esp32c6/include/soc/hp_apm_reg.h b/components/soc/esp32c6/register/soc/hp_apm_reg.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/hp_apm_reg.h
rename to components/soc/esp32c6/register/soc/hp_apm_reg.h
diff --git a/components/soc/esp32c6/include/soc/hp_apm_struct.h b/components/soc/esp32c6/register/soc/hp_apm_struct.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/hp_apm_struct.h
rename to components/soc/esp32c6/register/soc/hp_apm_struct.h
diff --git a/components/soc/esp32c6/include/soc/hp_system_reg.h b/components/soc/esp32c6/register/soc/hp_system_reg.h
similarity index 99%
rename from components/soc/esp32c6/include/soc/hp_system_reg.h
rename to components/soc/esp32c6/register/soc/hp_system_reg.h
index 898d0fb0e5..f32f280f23 100644
--- a/components/soc/esp32c6/include/soc/hp_system_reg.h
+++ b/components/soc/esp32c6/register/soc/hp_system_reg.h
@@ -78,7 +78,7 @@ extern "C" {
  *  0: anti-DPA disable. 1~3: anti-DPA enable with different security level. The larger
  *  the number, the stronger the ability to resist DPA attacks and the higher the
  *  security level, but it will increase the computational overhead of the hardware
- *  crypto-accelerators. Only avaliable if HP_SYSTEM_SEC_DPA_CFG_SEL is 0.
+ *  crypto-accelerators. Only available if HP_SYSTEM_SEC_DPA_CFG_SEL is 0.
  */
 #define HP_SYSTEM_SEC_DPA_LEVEL    0x00000003U
 #define HP_SYSTEM_SEC_DPA_LEVEL_M  (HP_SYSTEM_SEC_DPA_LEVEL_V << HP_SYSTEM_SEC_DPA_LEVEL_S)
diff --git a/components/soc/esp32c6/include/soc/hp_system_struct.h b/components/soc/esp32c6/register/soc/hp_system_struct.h
similarity index 99%
rename from components/soc/esp32c6/include/soc/hp_system_struct.h
rename to components/soc/esp32c6/register/soc/hp_system_struct.h
index b174aa4290..20b8eac2f8 100644
--- a/components/soc/esp32c6/include/soc/hp_system_struct.h
+++ b/components/soc/esp32c6/register/soc/hp_system_struct.h
@@ -70,7 +70,7 @@ typedef union {
          *  0: anti-DPA disable. 1~3: anti-DPA enable with different security level. The larger
          *  the number, the stronger the ability to resist DPA attacks and the higher the
          *  security level, but it will increase the computational overhead of the hardware
-         *  crypto-accelerators. Only avaliable if HP_SYSTEM_SEC_DPA_CFG_SEL is 0.
+         *  crypto-accelerators. Only available if HP_SYSTEM_SEC_DPA_CFG_SEL is 0.
          */
         uint32_t sec_dpa_level:2;
         /** sec_dpa_cfg_sel : R/W; bitpos: [2]; default: 0;
diff --git a/components/soc/esp32c6/include/soc/i2c_ana_mst_reg.h b/components/soc/esp32c6/register/soc/i2c_ana_mst_reg.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/i2c_ana_mst_reg.h
rename to components/soc/esp32c6/register/soc/i2c_ana_mst_reg.h
diff --git a/components/soc/esp32c6/include/soc/i2c_reg.h b/components/soc/esp32c6/register/soc/i2c_reg.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/i2c_reg.h
rename to components/soc/esp32c6/register/soc/i2c_reg.h
diff --git a/components/soc/esp32c6/include/soc/i2c_struct.h b/components/soc/esp32c6/register/soc/i2c_struct.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/i2c_struct.h
rename to components/soc/esp32c6/register/soc/i2c_struct.h
diff --git a/components/soc/esp32c6/include/soc/i2s_reg.h b/components/soc/esp32c6/register/soc/i2s_reg.h
similarity index 99%
rename from components/soc/esp32c6/include/soc/i2s_reg.h
rename to components/soc/esp32c6/register/soc/i2s_reg.h
index 89fd5eb844..4f259c1131 100644
--- a/components/soc/esp32c6/include/soc/i2s_reg.h
+++ b/components/soc/esp32c6/register/soc/i2s_reg.h
@@ -361,7 +361,7 @@ extern "C" {
 #define I2S_TX_PCM_BYPASS_V  0x00000001U
 #define I2S_TX_PCM_BYPASS_S  12
 /** I2S_TX_STOP_EN : R/W; bitpos: [13]; default: 1;
- *  Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy
+ *  Set this bit to stop disable output BCK signal and WS signal when tx FIFO is empty
  */
 #define I2S_TX_STOP_EN    (BIT(13))
 #define I2S_TX_STOP_EN_M  (I2S_TX_STOP_EN_V << I2S_TX_STOP_EN_S)
diff --git a/components/soc/esp32c6/include/soc/i2s_struct.h b/components/soc/esp32c6/register/soc/i2s_struct.h
similarity index 99%
rename from components/soc/esp32c6/include/soc/i2s_struct.h
rename to components/soc/esp32c6/register/soc/i2s_struct.h
index f7b7f069ad..b7629e4c98 100644
--- a/components/soc/esp32c6/include/soc/i2s_struct.h
+++ b/components/soc/esp32c6/register/soc/i2s_struct.h
@@ -494,7 +494,7 @@ typedef union {
          */
         uint32_t tx_pcm_bypass:1;
         /** tx_stop_en : R/W; bitpos: [13]; default: 1;
-         *  Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy
+         *  Set this bit to stop disable output BCK signal and WS signal when tx FIFO is empty
          */
         uint32_t tx_stop_en:1;
         uint32_t reserved_14:1;
diff --git a/components/soc/esp32c6/include/soc/ieee802154_reg.h b/components/soc/esp32c6/register/soc/ieee802154_reg.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/ieee802154_reg.h
rename to components/soc/esp32c6/register/soc/ieee802154_reg.h
diff --git a/components/soc/esp32c6/include/soc/ieee802154_struct.h b/components/soc/esp32c6/register/soc/ieee802154_struct.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/ieee802154_struct.h
rename to components/soc/esp32c6/register/soc/ieee802154_struct.h
diff --git a/components/soc/esp32c6/include/soc/interrupt_matrix_reg.h b/components/soc/esp32c6/register/soc/interrupt_matrix_reg.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/interrupt_matrix_reg.h
rename to components/soc/esp32c6/register/soc/interrupt_matrix_reg.h
diff --git a/components/soc/esp32c6/include/soc/interrupt_matrix_struct.h b/components/soc/esp32c6/register/soc/interrupt_matrix_struct.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/interrupt_matrix_struct.h
rename to components/soc/esp32c6/register/soc/interrupt_matrix_struct.h
diff --git a/components/soc/esp32c6/include/soc/intpri_reg.h b/components/soc/esp32c6/register/soc/intpri_reg.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/intpri_reg.h
rename to components/soc/esp32c6/register/soc/intpri_reg.h
diff --git a/components/soc/esp32c6/include/soc/intpri_struct.h b/components/soc/esp32c6/register/soc/intpri_struct.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/intpri_struct.h
rename to components/soc/esp32c6/register/soc/intpri_struct.h
diff --git a/components/soc/esp32c6/include/soc/io_mux_reg.h b/components/soc/esp32c6/register/soc/io_mux_reg.h
similarity index 99%
rename from components/soc/esp32c6/include/soc/io_mux_reg.h
rename to components/soc/esp32c6/register/soc/io_mux_reg.h
index 698a2b5785..0adf0203ef 100644
--- a/components/soc/esp32c6/include/soc/io_mux_reg.h
+++ b/components/soc/esp32c6/register/soc/io_mux_reg.h
@@ -5,7 +5,7 @@
  */
 
 #pragma once
-#include "soc.h"
+#include "soc/soc.h"
 
 /* The following are the bit fields for PERIPHS_IO_MUX_x_U registers */
 /* Output enable in sleep mode */
diff --git a/components/soc/esp32c6/include/soc/ledc_reg.h b/components/soc/esp32c6/register/soc/ledc_reg.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/ledc_reg.h
rename to components/soc/esp32c6/register/soc/ledc_reg.h
diff --git a/components/soc/esp32c6/include/soc/ledc_struct.h b/components/soc/esp32c6/register/soc/ledc_struct.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/ledc_struct.h
rename to components/soc/esp32c6/register/soc/ledc_struct.h
diff --git a/components/soc/esp32c6/include/soc/lp_analog_peri_reg.h b/components/soc/esp32c6/register/soc/lp_analog_peri_reg.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/lp_analog_peri_reg.h
rename to components/soc/esp32c6/register/soc/lp_analog_peri_reg.h
diff --git a/components/soc/esp32c6/include/soc/lp_analog_peri_struct.h b/components/soc/esp32c6/register/soc/lp_analog_peri_struct.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/lp_analog_peri_struct.h
rename to components/soc/esp32c6/register/soc/lp_analog_peri_struct.h
diff --git a/components/soc/esp32c6/include/soc/lp_aon_reg.h b/components/soc/esp32c6/register/soc/lp_aon_reg.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/lp_aon_reg.h
rename to components/soc/esp32c6/register/soc/lp_aon_reg.h
diff --git a/components/soc/esp32c6/include/soc/lp_aon_struct.h b/components/soc/esp32c6/register/soc/lp_aon_struct.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/lp_aon_struct.h
rename to components/soc/esp32c6/register/soc/lp_aon_struct.h
diff --git a/components/soc/esp32c6/include/soc/lp_apm0_reg.h b/components/soc/esp32c6/register/soc/lp_apm0_reg.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/lp_apm0_reg.h
rename to components/soc/esp32c6/register/soc/lp_apm0_reg.h
diff --git a/components/soc/esp32c6/include/soc/lp_apm0_struct.h b/components/soc/esp32c6/register/soc/lp_apm0_struct.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/lp_apm0_struct.h
rename to components/soc/esp32c6/register/soc/lp_apm0_struct.h
diff --git a/components/soc/esp32c6/include/soc/lp_apm_reg.h b/components/soc/esp32c6/register/soc/lp_apm_reg.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/lp_apm_reg.h
rename to components/soc/esp32c6/register/soc/lp_apm_reg.h
diff --git a/components/soc/esp32c6/include/soc/lp_apm_struct.h b/components/soc/esp32c6/register/soc/lp_apm_struct.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/lp_apm_struct.h
rename to components/soc/esp32c6/register/soc/lp_apm_struct.h
diff --git a/components/soc/esp32c6/include/soc/lp_clkrst_reg.h b/components/soc/esp32c6/register/soc/lp_clkrst_reg.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/lp_clkrst_reg.h
rename to components/soc/esp32c6/register/soc/lp_clkrst_reg.h
diff --git a/components/soc/esp32c6/include/soc/lp_clkrst_struct.h b/components/soc/esp32c6/register/soc/lp_clkrst_struct.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/lp_clkrst_struct.h
rename to components/soc/esp32c6/register/soc/lp_clkrst_struct.h
diff --git a/components/soc/esp32c6/include/soc/lp_i2c_ana_mst_reg.h b/components/soc/esp32c6/register/soc/lp_i2c_ana_mst_reg.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/lp_i2c_ana_mst_reg.h
rename to components/soc/esp32c6/register/soc/lp_i2c_ana_mst_reg.h
diff --git a/components/soc/esp32c6/include/soc/lp_i2c_ana_mst_struct.h b/components/soc/esp32c6/register/soc/lp_i2c_ana_mst_struct.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/lp_i2c_ana_mst_struct.h
rename to components/soc/esp32c6/register/soc/lp_i2c_ana_mst_struct.h
diff --git a/components/soc/esp32c6/include/soc/lp_i2c_reg.h b/components/soc/esp32c6/register/soc/lp_i2c_reg.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/lp_i2c_reg.h
rename to components/soc/esp32c6/register/soc/lp_i2c_reg.h
diff --git a/components/soc/esp32c6/include/soc/lp_i2c_struct.h b/components/soc/esp32c6/register/soc/lp_i2c_struct.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/lp_i2c_struct.h
rename to components/soc/esp32c6/register/soc/lp_i2c_struct.h
diff --git a/components/soc/esp32c6/include/soc/lp_io_reg.h b/components/soc/esp32c6/register/soc/lp_io_reg.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/lp_io_reg.h
rename to components/soc/esp32c6/register/soc/lp_io_reg.h
diff --git a/components/soc/esp32c6/include/soc/lp_io_struct.h b/components/soc/esp32c6/register/soc/lp_io_struct.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/lp_io_struct.h
rename to components/soc/esp32c6/register/soc/lp_io_struct.h
diff --git a/components/soc/esp32c6/include/soc/lp_tee_reg.h b/components/soc/esp32c6/register/soc/lp_tee_reg.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/lp_tee_reg.h
rename to components/soc/esp32c6/register/soc/lp_tee_reg.h
diff --git a/components/soc/esp32c6/include/soc/lp_tee_struct.h b/components/soc/esp32c6/register/soc/lp_tee_struct.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/lp_tee_struct.h
rename to components/soc/esp32c6/register/soc/lp_tee_struct.h
diff --git a/components/soc/esp32c6/include/soc/lp_timer_reg.h b/components/soc/esp32c6/register/soc/lp_timer_reg.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/lp_timer_reg.h
rename to components/soc/esp32c6/register/soc/lp_timer_reg.h
diff --git a/components/soc/esp32c6/include/soc/lp_timer_struct.h b/components/soc/esp32c6/register/soc/lp_timer_struct.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/lp_timer_struct.h
rename to components/soc/esp32c6/register/soc/lp_timer_struct.h
diff --git a/components/soc/esp32c6/include/soc/lp_uart_reg.h b/components/soc/esp32c6/register/soc/lp_uart_reg.h
similarity index 99%
rename from components/soc/esp32c6/include/soc/lp_uart_reg.h
rename to components/soc/esp32c6/register/soc/lp_uart_reg.h
index b67fa1b59e..017abf55f8 100644
--- a/components/soc/esp32c6/include/soc/lp_uart_reg.h
+++ b/components/soc/esp32c6/register/soc/lp_uart_reg.h
@@ -100,7 +100,7 @@ extern "C" {
 #define LP_UART_RXFIFO_TOUT_INT_RAW_V  0x00000001U
 #define LP_UART_RXFIFO_TOUT_INT_RAW_S  8
 /** LP_UART_SW_XON_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
- *  This interrupt raw bit turns to high level when receiver recevies Xon char when
+ *  This interrupt raw bit turns to high level when receiver receives Xon char when
  *  uart_sw_flow_con_en is set to 1.
  */
 #define LP_UART_SW_XON_INT_RAW    (BIT(9))
@@ -261,7 +261,7 @@ extern "C" {
 #define LP_UART_TX_BRK_DONE_INT_ST_V  0x00000001U
 #define LP_UART_TX_BRK_DONE_INT_ST_S  12
 /** LP_UART_TX_BRK_IDLE_DONE_INT_ST : RO; bitpos: [13]; default: 0;
- *  This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena
+ *  This is the status bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena
  *  is set to 1.
  */
 #define LP_UART_TX_BRK_IDLE_DONE_INT_ST    (BIT(13))
@@ -671,7 +671,7 @@ extern "C" {
 #define LP_UART_STOP_BIT_NUM_V  0x00000003U
 #define LP_UART_STOP_BIT_NUM_S  4
 /** LP_UART_TXD_BRK : R/W; bitpos: [6]; default: 0;
- *  Set this bit to enbale transmitter to  send NULL when the process of sending data
+ *  Set this bit to enable transmitter to  send NULL when the process of sending data
  *  is done.
  */
 #define LP_UART_TXD_BRK    (BIT(6))
@@ -1151,7 +1151,7 @@ extern "C" {
  */
 #define LP_UART_TOUT_CONF_SYNC_REG (DR_REG_LP_UART_BASE + 0x64)
 /** LP_UART_RX_TOUT_EN : R/W; bitpos: [0]; default: 0;
- *  This is the enble bit for uart receiver's timeout function.
+ *  This is the enable bit for uart receiver's timeout function.
  */
 #define LP_UART_RX_TOUT_EN    (BIT(0))
 #define LP_UART_RX_TOUT_EN_M  (LP_UART_RX_TOUT_EN_V << LP_UART_RX_TOUT_EN_S)
diff --git a/components/soc/esp32c6/include/soc/lp_uart_struct.h b/components/soc/esp32c6/register/soc/lp_uart_struct.h
similarity index 99%
rename from components/soc/esp32c6/include/soc/lp_uart_struct.h
rename to components/soc/esp32c6/register/soc/lp_uart_struct.h
index 122c7d920a..bc9993276f 100644
--- a/components/soc/esp32c6/include/soc/lp_uart_struct.h
+++ b/components/soc/esp32c6/register/soc/lp_uart_struct.h
@@ -49,7 +49,7 @@ typedef union {
 typedef union {
     struct {
         /** rx_tout_en : R/W; bitpos: [0]; default: 0;
-         *  This is the enble bit for uart receiver's timeout function.
+         *  This is the enable bit for uart receiver's timeout function.
          */
         uint32_t rx_tout_en:1;
         /** rx_tout_flow_dis : R/W; bitpos: [1]; default: 0;
@@ -120,7 +120,7 @@ typedef union {
          */
         uint32_t rxfifo_tout:1;
         /** sw_xon : R/WTC/SS; bitpos: [9]; default: 0;
-         *  This interrupt raw bit turns to high level when receiver recevies Xon char when
+         *  This interrupt raw bit turns to high level when receiver receives Xon char when
          *  uart_sw_flow_con_en is set to 1.
          */
         uint32_t sw_xon:1;
@@ -224,7 +224,7 @@ typedef union {
          */
         uint32_t tx_brk_done:1;
         /** tx_brk_idle_done : RO; bitpos: [13]; default: 0;
-         *  This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena
+         *  This is the status bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena
          *  is set to 1.
          */
         uint32_t tx_brk_idle_done:1;
@@ -466,7 +466,7 @@ typedef union {
          */
         uint32_t stop_bit_num:2;
         /** txd_brk : R/W; bitpos: [6]; default: 0;
-         *  Set this bit to enbale transmitter to  send NULL when the process of sending data
+         *  Set this bit to enable transmitter to  send NULL when the process of sending data
          *  is done.
          */
         uint32_t txd_brk:1;
@@ -1115,7 +1115,7 @@ typedef struct lp_uart_dev_t {
     volatile lp_uart_id_reg_t id;
 } lp_uart_dev_t;
 
-// We map the LP_UART instance to the uart_dev_t struct for convinience of using the same HAL/LL. See soc/uart_struct.h
+// We map the LP_UART instance to the uart_dev_t struct for convenience of using the same HAL/LL. See soc/uart_struct.h
 // extern lp_uart_dev_t LP_UART;
 
 #ifndef __cplusplus
diff --git a/components/soc/esp32c6/include/soc/lp_wdt_reg.h b/components/soc/esp32c6/register/soc/lp_wdt_reg.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/lp_wdt_reg.h
rename to components/soc/esp32c6/register/soc/lp_wdt_reg.h
diff --git a/components/soc/esp32c6/include/soc/lp_wdt_struct.h b/components/soc/esp32c6/register/soc/lp_wdt_struct.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/lp_wdt_struct.h
rename to components/soc/esp32c6/register/soc/lp_wdt_struct.h
diff --git a/components/soc/esp32c6/include/soc/lpperi_reg.h b/components/soc/esp32c6/register/soc/lpperi_reg.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/lpperi_reg.h
rename to components/soc/esp32c6/register/soc/lpperi_reg.h
diff --git a/components/soc/esp32c6/include/soc/lpperi_struct.h b/components/soc/esp32c6/register/soc/lpperi_struct.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/lpperi_struct.h
rename to components/soc/esp32c6/register/soc/lpperi_struct.h
diff --git a/components/soc/esp32c6/include/soc/mcpwm_reg.h b/components/soc/esp32c6/register/soc/mcpwm_reg.h
similarity index 99%
rename from components/soc/esp32c6/include/soc/mcpwm_reg.h
rename to components/soc/esp32c6/register/soc/mcpwm_reg.h
index 4eacabbc9c..4de6f5b9f7 100644
--- a/components/soc/esp32c6/include/soc/mcpwm_reg.h
+++ b/components/soc/esp32c6/register/soc/mcpwm_reg.h
@@ -894,7 +894,7 @@ extern "C" {
 #define MCPWM_DB0_RED_S  0
 
 /** MCPWM_CARRIER0_CFG_REG register
- *  Carrier enable and configuratoin
+ *  Carrier enable and configuration
  */
 #define MCPWM_CARRIER0_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x64)
 /** MCPWM_CHOPPER0_EN : R/W; bitpos: [0]; default: 0;
@@ -1575,7 +1575,7 @@ extern "C" {
 #define MCPWM_DB1_RED_S  0
 
 /** MCPWM_CARRIER1_CFG_REG register
- *  Carrier enable and configuratoin
+ *  Carrier enable and configuration
  */
 #define MCPWM_CARRIER1_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x9c)
 /** MCPWM_CHOPPER1_EN : R/W; bitpos: [0]; default: 0;
@@ -2256,7 +2256,7 @@ extern "C" {
 #define MCPWM_DB2_RED_S  0
 
 /** MCPWM_CARRIER2_CFG_REG register
- *  Carrier enable and configuratoin
+ *  Carrier enable and configuration
  */
 #define MCPWM_CARRIER2_CFG_REG(i) (REG_MCPWM_BASE(i) + 0xd4)
 /** MCPWM_CHOPPER2_EN : R/W; bitpos: [0]; default: 0;
@@ -2621,7 +2621,7 @@ extern "C" {
 #define MCPWM_CAP0_MODE_V  0x00000003U
 #define MCPWM_CAP0_MODE_S  1
 /** MCPWM_CAP0_PRESCALE : R/W; bitpos: [10:3]; default: 0;
- *  Value of prescaling on possitive edge of CAP0. Prescale value = PWM_CAP0_PRESCALE +
+ *  Value of prescaling on positive edge of CAP0. Prescale value = PWM_CAP0_PRESCALE +
  *  1
  */
 #define MCPWM_CAP0_PRESCALE    0x000000FFU
@@ -2664,7 +2664,7 @@ extern "C" {
 #define MCPWM_CAP1_MODE_V  0x00000003U
 #define MCPWM_CAP1_MODE_S  1
 /** MCPWM_CAP1_PRESCALE : R/W; bitpos: [10:3]; default: 0;
- *  Value of prescaling on possitive edge of CAP1. Prescale value = PWM_CAP1_PRESCALE +
+ *  Value of prescaling on positive edge of CAP1. Prescale value = PWM_CAP1_PRESCALE +
  *  1
  */
 #define MCPWM_CAP1_PRESCALE    0x000000FFU
@@ -2707,7 +2707,7 @@ extern "C" {
 #define MCPWM_CAP2_MODE_V  0x00000003U
 #define MCPWM_CAP2_MODE_S  1
 /** MCPWM_CAP2_PRESCALE : R/W; bitpos: [10:3]; default: 0;
- *  Value of prescaling on possitive edge of CAP2. Prescale value = PWM_CAP2_PRESCALE +
+ *  Value of prescaling on positive edge of CAP2. Prescale value = PWM_CAP2_PRESCALE +
  *  1
  */
 #define MCPWM_CAP2_PRESCALE    0x000000FFU
diff --git a/components/soc/esp32c6/include/soc/mcpwm_struct.h b/components/soc/esp32c6/register/soc/mcpwm_struct.h
similarity index 99%
rename from components/soc/esp32c6/include/soc/mcpwm_struct.h
rename to components/soc/esp32c6/register/soc/mcpwm_struct.h
index 1a91a623f6..5fe75f3c99 100644
--- a/components/soc/esp32c6/include/soc/mcpwm_struct.h
+++ b/components/soc/esp32c6/register/soc/mcpwm_struct.h
@@ -462,7 +462,7 @@ typedef union {
 } mcpwm_dt_red_cfg_reg_t;
 
 /** Type of carrier_cfg register
- *  Carrier enable and configuratoin
+ *  Carrier enable and configuration
  */
 typedef union {
     struct {
@@ -734,7 +734,7 @@ typedef union {
          */
         uint32_t capn_mode:2;
         /** capn_prescale : R/W; bitpos: [10:3]; default: 0;
-         *  Value of prescaling on possitive edge of CAPn. Prescale value = PWM_CAP0_PRESCALE +
+         *  Value of prescaling on positive edge of CAPn. Prescale value = PWM_CAP0_PRESCALE +
          *  1
          */
         uint32_t capn_prescale:8;
diff --git a/components/soc/esp32c6/include/soc/mem_monitor_reg.h b/components/soc/esp32c6/register/soc/mem_monitor_reg.h
similarity index 98%
rename from components/soc/esp32c6/include/soc/mem_monitor_reg.h
rename to components/soc/esp32c6/register/soc/mem_monitor_reg.h
index fccde61ad7..b75a52af21 100644
--- a/components/soc/esp32c6/include/soc/mem_monitor_reg.h
+++ b/components/soc/esp32c6/register/soc/mem_monitor_reg.h
@@ -12,7 +12,7 @@ extern "C" {
 #endif
 
 /** MEM_MONITOR_LOG_SETTING_REG register
- *  log config regsiter
+ *  log config register
  */
 #define MEM_MONITOR_LOG_SETTING_REG (DR_REG_MEM_MONITOR_BASE + 0x0)
 /** MEM_MONITOR_LOG_ENA : R/W; bitpos: [2:0]; default: 0;
@@ -39,7 +39,7 @@ extern "C" {
 #define MEM_MONITOR_LOG_MEM_LOOP_ENABLE_S  7
 
 /** MEM_MONITOR_LOG_CHECK_DATA_REG register
- *  check data regsiter
+ *  check data register
  */
 #define MEM_MONITOR_LOG_CHECK_DATA_REG (DR_REG_MEM_MONITOR_BASE + 0x4)
 /** MEM_MONITOR_LOG_CHECK_DATA : R/W; bitpos: [31:0]; default: 0;
@@ -64,7 +64,7 @@ extern "C" {
 #define MEM_MONITOR_LOG_DATA_MASK_S  0
 
 /** MEM_MONITOR_LOG_MIN_REG register
- *  log boundary regsiter
+ *  log boundary register
  */
 #define MEM_MONITOR_LOG_MIN_REG (DR_REG_MEM_MONITOR_BASE + 0xc)
 /** MEM_MONITOR_LOG_MIN : R/W; bitpos: [31:0]; default: 0;
@@ -76,7 +76,7 @@ extern "C" {
 #define MEM_MONITOR_LOG_MIN_S  0
 
 /** MEM_MONITOR_LOG_MAX_REG register
- *  log boundary regsiter
+ *  log boundary register
  */
 #define MEM_MONITOR_LOG_MAX_REG (DR_REG_MEM_MONITOR_BASE + 0x10)
 /** MEM_MONITOR_LOG_MAX : R/W; bitpos: [31:0]; default: 0;
diff --git a/components/soc/esp32c6/include/soc/mem_monitor_struct.h b/components/soc/esp32c6/register/soc/mem_monitor_struct.h
similarity index 98%
rename from components/soc/esp32c6/include/soc/mem_monitor_struct.h
rename to components/soc/esp32c6/register/soc/mem_monitor_struct.h
index 6fd735edf5..862959b949 100644
--- a/components/soc/esp32c6/include/soc/mem_monitor_struct.h
+++ b/components/soc/esp32c6/register/soc/mem_monitor_struct.h
@@ -12,7 +12,7 @@ extern "C" {
 
 /** Group: configuration registers */
 /** Type of log_setting register
- *  log config regsiter
+ *  log config register
  */
 typedef union {
     struct {
@@ -35,7 +35,7 @@ typedef union {
 } mem_monitor_log_setting_reg_t;
 
 /** Type of log_check_data register
- *  check data regsiter
+ *  check data register
  */
 typedef union {
     struct {
@@ -63,7 +63,7 @@ typedef union {
 } mem_monitor_log_data_mask_reg_t;
 
 /** Type of log_min register
- *  log boundary regsiter
+ *  log boundary register
  */
 typedef union {
     struct {
@@ -76,7 +76,7 @@ typedef union {
 } mem_monitor_log_min_reg_t;
 
 /** Type of log_max register
- *  log boundary regsiter
+ *  log boundary register
  */
 typedef union {
     struct {
diff --git a/components/soc/esp32c6/include/soc/otp_debug_reg.h b/components/soc/esp32c6/register/soc/otp_debug_reg.h
similarity index 91%
rename from components/soc/esp32c6/include/soc/otp_debug_reg.h
rename to components/soc/esp32c6/register/soc/otp_debug_reg.h
index 6d0e84c69f..49d1754d4f 100644
--- a/components/soc/esp32c6/include/soc/otp_debug_reg.h
+++ b/components/soc/esp32c6/register/soc/otp_debug_reg.h
@@ -12,7 +12,7 @@ extern "C" {
 #endif
 
 /** OTP_DEBUG_WR_DIS_REG register
- *  Otp debuger block0 data register1.
+ *  Otp debugger block0 data register1.
  */
 #define OTP_DEBUG_WR_DIS_REG (DR_REG_OTP_DEBUG_BASE + 0x0)
 /** OTP_DEBUG_BLOCK0_WR_DIS : RO; bitpos: [31:0]; default: 0;
@@ -24,7 +24,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK0_WR_DIS_S  0
 
 /** OTP_DEBUG_BLK0_BACKUP1_W1_REG register
- *  Otp debuger block0 data register2.
+ *  Otp debugger block0 data register2.
  */
 #define OTP_DEBUG_BLK0_BACKUP1_W1_REG (DR_REG_OTP_DEBUG_BASE + 0x4)
 /** OTP_DEBUG_BLOCK0_BACKUP1_W1 : RO; bitpos: [31:0]; default: 0;
@@ -36,7 +36,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK0_BACKUP1_W1_S  0
 
 /** OTP_DEBUG_BLK0_BACKUP1_W2_REG register
- *  Otp debuger block0 data register3.
+ *  Otp debugger block0 data register3.
  */
 #define OTP_DEBUG_BLK0_BACKUP1_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x8)
 /** OTP_DEBUG_BLOCK0_BACKUP1_W2 : RO; bitpos: [31:0]; default: 0;
@@ -48,7 +48,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK0_BACKUP1_W2_S  0
 
 /** OTP_DEBUG_BLK0_BACKUP1_W3_REG register
- *  Otp debuger block0 data register4.
+ *  Otp debugger block0 data register4.
  */
 #define OTP_DEBUG_BLK0_BACKUP1_W3_REG (DR_REG_OTP_DEBUG_BASE + 0xc)
 /** OTP_DEBUG_BLOCK0_BACKUP1_W3 : RO; bitpos: [31:0]; default: 0;
@@ -60,7 +60,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK0_BACKUP1_W3_S  0
 
 /** OTP_DEBUG_BLK0_BACKUP1_W4_REG register
- *  Otp debuger block0 data register5.
+ *  Otp debugger block0 data register5.
  */
 #define OTP_DEBUG_BLK0_BACKUP1_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x10)
 /** OTP_DEBUG_BLOCK0_BACKUP1_W4 : RO; bitpos: [31:0]; default: 0;
@@ -72,7 +72,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK0_BACKUP1_W4_S  0
 
 /** OTP_DEBUG_BLK0_BACKUP1_W5_REG register
- *  Otp debuger block0 data register6.
+ *  Otp debugger block0 data register6.
  */
 #define OTP_DEBUG_BLK0_BACKUP1_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x14)
 /** OTP_DEBUG_BLOCK0_BACKUP1_W5 : RO; bitpos: [31:0]; default: 0;
@@ -84,7 +84,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK0_BACKUP1_W5_S  0
 
 /** OTP_DEBUG_BLK0_BACKUP2_W1_REG register
- *  Otp debuger block0 data register7.
+ *  Otp debugger block0 data register7.
  */
 #define OTP_DEBUG_BLK0_BACKUP2_W1_REG (DR_REG_OTP_DEBUG_BASE + 0x18)
 /** OTP_DEBUG_BLOCK0_BACKUP2_W1 : RO; bitpos: [31:0]; default: 0;
@@ -96,7 +96,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK0_BACKUP2_W1_S  0
 
 /** OTP_DEBUG_BLK0_BACKUP2_W2_REG register
- *  Otp debuger block0 data register8.
+ *  Otp debugger block0 data register8.
  */
 #define OTP_DEBUG_BLK0_BACKUP2_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x1c)
 /** OTP_DEBUG_BLOCK0_BACKUP2_W2 : RO; bitpos: [31:0]; default: 0;
@@ -108,7 +108,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK0_BACKUP2_W2_S  0
 
 /** OTP_DEBUG_BLK0_BACKUP2_W3_REG register
- *  Otp debuger block0 data register9.
+ *  Otp debugger block0 data register9.
  */
 #define OTP_DEBUG_BLK0_BACKUP2_W3_REG (DR_REG_OTP_DEBUG_BASE + 0x20)
 /** OTP_DEBUG_BLOCK0_BACKUP2_W3 : RO; bitpos: [31:0]; default: 0;
@@ -120,7 +120,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK0_BACKUP2_W3_S  0
 
 /** OTP_DEBUG_BLK0_BACKUP2_W4_REG register
- *  Otp debuger block0 data register10.
+ *  Otp debugger block0 data register10.
  */
 #define OTP_DEBUG_BLK0_BACKUP2_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x24)
 /** OTP_DEBUG_BLOCK0_BACKUP2_W4 : RO; bitpos: [31:0]; default: 0;
@@ -132,7 +132,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK0_BACKUP2_W4_S  0
 
 /** OTP_DEBUG_BLK0_BACKUP2_W5_REG register
- *  Otp debuger block0 data register11.
+ *  Otp debugger block0 data register11.
  */
 #define OTP_DEBUG_BLK0_BACKUP2_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x28)
 /** OTP_DEBUG_BLOCK0_BACKUP2_W5 : RO; bitpos: [31:0]; default: 0;
@@ -144,7 +144,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK0_BACKUP2_W5_S  0
 
 /** OTP_DEBUG_BLK0_BACKUP3_W1_REG register
- *  Otp debuger block0 data register12.
+ *  Otp debugger block0 data register12.
  */
 #define OTP_DEBUG_BLK0_BACKUP3_W1_REG (DR_REG_OTP_DEBUG_BASE + 0x2c)
 /** OTP_DEBUG_BLOCK0_BACKUP3_W1 : RO; bitpos: [31:0]; default: 0;
@@ -156,7 +156,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK0_BACKUP3_W1_S  0
 
 /** OTP_DEBUG_BLK0_BACKUP3_W2_REG register
- *  Otp debuger block0 data register13.
+ *  Otp debugger block0 data register13.
  */
 #define OTP_DEBUG_BLK0_BACKUP3_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x30)
 /** OTP_DEBUG_BLOCK0_BACKUP3_W2 : RO; bitpos: [31:0]; default: 0;
@@ -168,7 +168,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK0_BACKUP3_W2_S  0
 
 /** OTP_DEBUG_BLK0_BACKUP3_W3_REG register
- *  Otp debuger block0 data register14.
+ *  Otp debugger block0 data register14.
  */
 #define OTP_DEBUG_BLK0_BACKUP3_W3_REG (DR_REG_OTP_DEBUG_BASE + 0x34)
 /** OTP_DEBUG_BLOCK0_BACKUP3_W3 : RO; bitpos: [31:0]; default: 0;
@@ -180,7 +180,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK0_BACKUP3_W3_S  0
 
 /** OTP_DEBUG_BLK0_BACKUP3_W4_REG register
- *  Otp debuger block0 data register15.
+ *  Otp debugger block0 data register15.
  */
 #define OTP_DEBUG_BLK0_BACKUP3_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x38)
 /** OTP_DEBUG_BLOCK0_BACKUP3_W4 : RO; bitpos: [31:0]; default: 0;
@@ -192,7 +192,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK0_BACKUP3_W4_S  0
 
 /** OTP_DEBUG_BLK0_BACKUP3_W5_REG register
- *  Otp debuger block0 data register16.
+ *  Otp debugger block0 data register16.
  */
 #define OTP_DEBUG_BLK0_BACKUP3_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x3c)
 /** OTP_DEBUG_BLOCK0_BACKUP3_W5 : RO; bitpos: [31:0]; default: 0;
@@ -204,7 +204,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK0_BACKUP3_W5_S  0
 
 /** OTP_DEBUG_BLK0_BACKUP4_W1_REG register
- *  Otp debuger block0 data register17.
+ *  Otp debugger block0 data register17.
  */
 #define OTP_DEBUG_BLK0_BACKUP4_W1_REG (DR_REG_OTP_DEBUG_BASE + 0x40)
 /** OTP_DEBUG_BLOCK0_BACKUP4_W1 : RO; bitpos: [31:0]; default: 0;
@@ -216,7 +216,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK0_BACKUP4_W1_S  0
 
 /** OTP_DEBUG_BLK0_BACKUP4_W2_REG register
- *  Otp debuger block0 data register18.
+ *  Otp debugger block0 data register18.
  */
 #define OTP_DEBUG_BLK0_BACKUP4_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x44)
 /** OTP_DEBUG_BLOCK0_BACKUP4_W2 : RO; bitpos: [31:0]; default: 0;
@@ -228,7 +228,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK0_BACKUP4_W2_S  0
 
 /** OTP_DEBUG_BLK0_BACKUP4_W3_REG register
- *  Otp debuger block0 data register19.
+ *  Otp debugger block0 data register19.
  */
 #define OTP_DEBUG_BLK0_BACKUP4_W3_REG (DR_REG_OTP_DEBUG_BASE + 0x48)
 /** OTP_DEBUG_BLOCK0_BACKUP4_W3 : RO; bitpos: [31:0]; default: 0;
@@ -240,7 +240,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK0_BACKUP4_W3_S  0
 
 /** OTP_DEBUG_BLK0_BACKUP4_W4_REG register
- *  Otp debuger block0 data register20.
+ *  Otp debugger block0 data register20.
  */
 #define OTP_DEBUG_BLK0_BACKUP4_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x4c)
 /** OTP_DEBUG_BLOCK0_BACKUP4_W4 : RO; bitpos: [31:0]; default: 0;
@@ -252,7 +252,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK0_BACKUP4_W4_S  0
 
 /** OTP_DEBUG_BLK0_BACKUP4_W5_REG register
- *  Otp debuger block0 data register21.
+ *  Otp debugger block0 data register21.
  */
 #define OTP_DEBUG_BLK0_BACKUP4_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x50)
 /** OTP_DEBUG_BLOCK0_BACKUP4_W5 : RO; bitpos: [31:0]; default: 0;
@@ -264,7 +264,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK0_BACKUP4_W5_S  0
 
 /** OTP_DEBUG_BLK1_W1_REG register
- *  Otp debuger block1 data register1.
+ *  Otp debugger block1 data register1.
  */
 #define OTP_DEBUG_BLK1_W1_REG (DR_REG_OTP_DEBUG_BASE + 0x54)
 /** OTP_DEBUG_BLOCK1_W1 : RO; bitpos: [31:0]; default: 0;
@@ -276,7 +276,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK1_W1_S  0
 
 /** OTP_DEBUG_BLK1_W2_REG register
- *  Otp debuger block1 data register2.
+ *  Otp debugger block1 data register2.
  */
 #define OTP_DEBUG_BLK1_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x58)
 /** OTP_DEBUG_BLOCK1_W2 : RO; bitpos: [31:0]; default: 0;
@@ -288,7 +288,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK1_W2_S  0
 
 /** OTP_DEBUG_BLK1_W3_REG register
- *  Otp debuger block1 data register3.
+ *  Otp debugger block1 data register3.
  */
 #define OTP_DEBUG_BLK1_W3_REG (DR_REG_OTP_DEBUG_BASE + 0x5c)
 /** OTP_DEBUG_BLOCK1_W3 : RO; bitpos: [31:0]; default: 0;
@@ -300,7 +300,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK1_W3_S  0
 
 /** OTP_DEBUG_BLK1_W4_REG register
- *  Otp debuger block1 data register4.
+ *  Otp debugger block1 data register4.
  */
 #define OTP_DEBUG_BLK1_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x60)
 /** OTP_DEBUG_BLOCK1_W4 : RO; bitpos: [31:0]; default: 0;
@@ -312,7 +312,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK1_W4_S  0
 
 /** OTP_DEBUG_BLK1_W5_REG register
- *  Otp debuger block1 data register5.
+ *  Otp debugger block1 data register5.
  */
 #define OTP_DEBUG_BLK1_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x64)
 /** OTP_DEBUG_BLOCK1_W5 : RO; bitpos: [31:0]; default: 0;
@@ -324,7 +324,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK1_W5_S  0
 
 /** OTP_DEBUG_BLK1_W6_REG register
- *  Otp debuger block1 data register6.
+ *  Otp debugger block1 data register6.
  */
 #define OTP_DEBUG_BLK1_W6_REG (DR_REG_OTP_DEBUG_BASE + 0x68)
 /** OTP_DEBUG_BLOCK1_W6 : RO; bitpos: [31:0]; default: 0;
@@ -336,7 +336,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK1_W6_S  0
 
 /** OTP_DEBUG_BLK1_W7_REG register
- *  Otp debuger block1 data register7.
+ *  Otp debugger block1 data register7.
  */
 #define OTP_DEBUG_BLK1_W7_REG (DR_REG_OTP_DEBUG_BASE + 0x6c)
 /** OTP_DEBUG_BLOCK1_W7 : RO; bitpos: [31:0]; default: 0;
@@ -348,7 +348,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK1_W7_S  0
 
 /** OTP_DEBUG_BLK1_W8_REG register
- *  Otp debuger block1 data register8.
+ *  Otp debugger block1 data register8.
  */
 #define OTP_DEBUG_BLK1_W8_REG (DR_REG_OTP_DEBUG_BASE + 0x70)
 /** OTP_DEBUG_BLOCK1_W8 : RO; bitpos: [31:0]; default: 0;
@@ -360,7 +360,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK1_W8_S  0
 
 /** OTP_DEBUG_BLK1_W9_REG register
- *  Otp debuger block1 data register9.
+ *  Otp debugger block1 data register9.
  */
 #define OTP_DEBUG_BLK1_W9_REG (DR_REG_OTP_DEBUG_BASE + 0x74)
 /** OTP_DEBUG_BLOCK1_W9 : RO; bitpos: [31:0]; default: 0;
@@ -372,7 +372,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK1_W9_S  0
 
 /** OTP_DEBUG_BLK2_W1_REG register
- *  Otp debuger block2 data register1.
+ *  Otp debugger block2 data register1.
  */
 #define OTP_DEBUG_BLK2_W1_REG (DR_REG_OTP_DEBUG_BASE + 0x78)
 /** OTP_DEBUG_BLOCK2_W1 : RO; bitpos: [31:0]; default: 0;
@@ -384,7 +384,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK2_W1_S  0
 
 /** OTP_DEBUG_BLK2_W2_REG register
- *  Otp debuger block2 data register2.
+ *  Otp debugger block2 data register2.
  */
 #define OTP_DEBUG_BLK2_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x7c)
 /** OTP_DEBUG_BLOCK2_W2 : RO; bitpos: [31:0]; default: 0;
@@ -396,7 +396,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK2_W2_S  0
 
 /** OTP_DEBUG_BLK2_W3_REG register
- *  Otp debuger block2 data register3.
+ *  Otp debugger block2 data register3.
  */
 #define OTP_DEBUG_BLK2_W3_REG (DR_REG_OTP_DEBUG_BASE + 0x80)
 /** OTP_DEBUG_BLOCK2_W3 : RO; bitpos: [31:0]; default: 0;
@@ -408,7 +408,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK2_W3_S  0
 
 /** OTP_DEBUG_BLK2_W4_REG register
- *  Otp debuger block2 data register4.
+ *  Otp debugger block2 data register4.
  */
 #define OTP_DEBUG_BLK2_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x84)
 /** OTP_DEBUG_BLOCK2_W4 : RO; bitpos: [31:0]; default: 0;
@@ -420,7 +420,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK2_W4_S  0
 
 /** OTP_DEBUG_BLK2_W5_REG register
- *  Otp debuger block2 data register5.
+ *  Otp debugger block2 data register5.
  */
 #define OTP_DEBUG_BLK2_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x88)
 /** OTP_DEBUG_BLOCK2_W5 : RO; bitpos: [31:0]; default: 0;
@@ -432,7 +432,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK2_W5_S  0
 
 /** OTP_DEBUG_BLK2_W6_REG register
- *  Otp debuger block2 data register6.
+ *  Otp debugger block2 data register6.
  */
 #define OTP_DEBUG_BLK2_W6_REG (DR_REG_OTP_DEBUG_BASE + 0x8c)
 /** OTP_DEBUG_BLOCK2_W6 : RO; bitpos: [31:0]; default: 0;
@@ -444,7 +444,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK2_W6_S  0
 
 /** OTP_DEBUG_BLK2_W7_REG register
- *  Otp debuger block2 data register7.
+ *  Otp debugger block2 data register7.
  */
 #define OTP_DEBUG_BLK2_W7_REG (DR_REG_OTP_DEBUG_BASE + 0x90)
 /** OTP_DEBUG_BLOCK2_W7 : RO; bitpos: [31:0]; default: 0;
@@ -456,7 +456,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK2_W7_S  0
 
 /** OTP_DEBUG_BLK2_W8_REG register
- *  Otp debuger block2 data register8.
+ *  Otp debugger block2 data register8.
  */
 #define OTP_DEBUG_BLK2_W8_REG (DR_REG_OTP_DEBUG_BASE + 0x94)
 /** OTP_DEBUG_BLOCK2_W8 : RO; bitpos: [31:0]; default: 0;
@@ -468,7 +468,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK2_W8_S  0
 
 /** OTP_DEBUG_BLK2_W9_REG register
- *  Otp debuger block2 data register9.
+ *  Otp debugger block2 data register9.
  */
 #define OTP_DEBUG_BLK2_W9_REG (DR_REG_OTP_DEBUG_BASE + 0x98)
 /** OTP_DEBUG_BLOCK2_W9 : RO; bitpos: [31:0]; default: 0;
@@ -480,7 +480,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK2_W9_S  0
 
 /** OTP_DEBUG_BLK2_W10_REG register
- *  Otp debuger block2 data register10.
+ *  Otp debugger block2 data register10.
  */
 #define OTP_DEBUG_BLK2_W10_REG (DR_REG_OTP_DEBUG_BASE + 0x9c)
 /** OTP_DEBUG_BLOCK2_W10 : RO; bitpos: [31:0]; default: 0;
@@ -492,7 +492,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK2_W10_S  0
 
 /** OTP_DEBUG_BLK2_W11_REG register
- *  Otp debuger block2 data register11.
+ *  Otp debugger block2 data register11.
  */
 #define OTP_DEBUG_BLK2_W11_REG (DR_REG_OTP_DEBUG_BASE + 0xa0)
 /** OTP_DEBUG_BLOCK2_W11 : RO; bitpos: [31:0]; default: 0;
@@ -504,7 +504,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK2_W11_S  0
 
 /** OTP_DEBUG_BLK3_W1_REG register
- *  Otp debuger block3 data register1.
+ *  Otp debugger block3 data register1.
  */
 #define OTP_DEBUG_BLK3_W1_REG (DR_REG_OTP_DEBUG_BASE + 0xa4)
 /** OTP_DEBUG_BLOCK3_W1 : RO; bitpos: [31:0]; default: 0;
@@ -516,7 +516,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK3_W1_S  0
 
 /** OTP_DEBUG_BLK3_W2_REG register
- *  Otp debuger block3 data register2.
+ *  Otp debugger block3 data register2.
  */
 #define OTP_DEBUG_BLK3_W2_REG (DR_REG_OTP_DEBUG_BASE + 0xa8)
 /** OTP_DEBUG_BLOCK3_W2 : RO; bitpos: [31:0]; default: 0;
@@ -528,7 +528,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK3_W2_S  0
 
 /** OTP_DEBUG_BLK3_W3_REG register
- *  Otp debuger block3 data register3.
+ *  Otp debugger block3 data register3.
  */
 #define OTP_DEBUG_BLK3_W3_REG (DR_REG_OTP_DEBUG_BASE + 0xac)
 /** OTP_DEBUG_BLOCK3_W3 : RO; bitpos: [31:0]; default: 0;
@@ -540,7 +540,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK3_W3_S  0
 
 /** OTP_DEBUG_BLK3_W4_REG register
- *  Otp debuger block3 data register4.
+ *  Otp debugger block3 data register4.
  */
 #define OTP_DEBUG_BLK3_W4_REG (DR_REG_OTP_DEBUG_BASE + 0xb0)
 /** OTP_DEBUG_BLOCK3_W4 : RO; bitpos: [31:0]; default: 0;
@@ -552,7 +552,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK3_W4_S  0
 
 /** OTP_DEBUG_BLK3_W5_REG register
- *  Otp debuger block3 data register5.
+ *  Otp debugger block3 data register5.
  */
 #define OTP_DEBUG_BLK3_W5_REG (DR_REG_OTP_DEBUG_BASE + 0xb4)
 /** OTP_DEBUG_BLOCK3_W5 : RO; bitpos: [31:0]; default: 0;
@@ -564,7 +564,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK3_W5_S  0
 
 /** OTP_DEBUG_BLK3_W6_REG register
- *  Otp debuger block3 data register6.
+ *  Otp debugger block3 data register6.
  */
 #define OTP_DEBUG_BLK3_W6_REG (DR_REG_OTP_DEBUG_BASE + 0xb8)
 /** OTP_DEBUG_BLOCK3_W6 : RO; bitpos: [31:0]; default: 0;
@@ -576,7 +576,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK3_W6_S  0
 
 /** OTP_DEBUG_BLK3_W7_REG register
- *  Otp debuger block3 data register7.
+ *  Otp debugger block3 data register7.
  */
 #define OTP_DEBUG_BLK3_W7_REG (DR_REG_OTP_DEBUG_BASE + 0xbc)
 /** OTP_DEBUG_BLOCK3_W7 : RO; bitpos: [31:0]; default: 0;
@@ -588,7 +588,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK3_W7_S  0
 
 /** OTP_DEBUG_BLK3_W8_REG register
- *  Otp debuger block3 data register8.
+ *  Otp debugger block3 data register8.
  */
 #define OTP_DEBUG_BLK3_W8_REG (DR_REG_OTP_DEBUG_BASE + 0xc0)
 /** OTP_DEBUG_BLOCK3_W8 : RO; bitpos: [31:0]; default: 0;
@@ -600,7 +600,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK3_W8_S  0
 
 /** OTP_DEBUG_BLK3_W9_REG register
- *  Otp debuger block3 data register9.
+ *  Otp debugger block3 data register9.
  */
 #define OTP_DEBUG_BLK3_W9_REG (DR_REG_OTP_DEBUG_BASE + 0xc4)
 /** OTP_DEBUG_BLOCK3_W9 : RO; bitpos: [31:0]; default: 0;
@@ -612,7 +612,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK3_W9_S  0
 
 /** OTP_DEBUG_BLK3_W10_REG register
- *  Otp debuger block3 data register10.
+ *  Otp debugger block3 data register10.
  */
 #define OTP_DEBUG_BLK3_W10_REG (DR_REG_OTP_DEBUG_BASE + 0xc8)
 /** OTP_DEBUG_BLOCK3_W10 : RO; bitpos: [31:0]; default: 0;
@@ -624,7 +624,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK3_W10_S  0
 
 /** OTP_DEBUG_BLK3_W11_REG register
- *  Otp debuger block3 data register11.
+ *  Otp debugger block3 data register11.
  */
 #define OTP_DEBUG_BLK3_W11_REG (DR_REG_OTP_DEBUG_BASE + 0xcc)
 /** OTP_DEBUG_BLOCK3_W11 : RO; bitpos: [31:0]; default: 0;
@@ -636,7 +636,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK3_W11_S  0
 
 /** OTP_DEBUG_BLK4_W1_REG register
- *  Otp debuger block4 data register1.
+ *  Otp debugger block4 data register1.
  */
 #define OTP_DEBUG_BLK4_W1_REG (DR_REG_OTP_DEBUG_BASE + 0xd0)
 /** OTP_DEBUG_BLOCK4_W1 : RO; bitpos: [31:0]; default: 0;
@@ -648,7 +648,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK4_W1_S  0
 
 /** OTP_DEBUG_BLK4_W2_REG register
- *  Otp debuger block4 data register2.
+ *  Otp debugger block4 data register2.
  */
 #define OTP_DEBUG_BLK4_W2_REG (DR_REG_OTP_DEBUG_BASE + 0xd4)
 /** OTP_DEBUG_BLOCK4_W2 : RO; bitpos: [31:0]; default: 0;
@@ -660,7 +660,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK4_W2_S  0
 
 /** OTP_DEBUG_BLK4_W3_REG register
- *  Otp debuger block4 data register3.
+ *  Otp debugger block4 data register3.
  */
 #define OTP_DEBUG_BLK4_W3_REG (DR_REG_OTP_DEBUG_BASE + 0xd8)
 /** OTP_DEBUG_BLOCK4_W3 : RO; bitpos: [31:0]; default: 0;
@@ -672,7 +672,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK4_W3_S  0
 
 /** OTP_DEBUG_BLK4_W4_REG register
- *  Otp debuger block4 data register4.
+ *  Otp debugger block4 data register4.
  */
 #define OTP_DEBUG_BLK4_W4_REG (DR_REG_OTP_DEBUG_BASE + 0xdc)
 /** OTP_DEBUG_BLOCK4_W4 : RO; bitpos: [31:0]; default: 0;
@@ -684,7 +684,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK4_W4_S  0
 
 /** OTP_DEBUG_BLK4_W5_REG register
- *  Otp debuger block4 data register5.
+ *  Otp debugger block4 data register5.
  */
 #define OTP_DEBUG_BLK4_W5_REG (DR_REG_OTP_DEBUG_BASE + 0xe0)
 /** OTP_DEBUG_BLOCK4_W5 : RO; bitpos: [31:0]; default: 0;
@@ -696,7 +696,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK4_W5_S  0
 
 /** OTP_DEBUG_BLK4_W6_REG register
- *  Otp debuger block4 data register6.
+ *  Otp debugger block4 data register6.
  */
 #define OTP_DEBUG_BLK4_W6_REG (DR_REG_OTP_DEBUG_BASE + 0xe4)
 /** OTP_DEBUG_BLOCK4_W6 : RO; bitpos: [31:0]; default: 0;
@@ -708,7 +708,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK4_W6_S  0
 
 /** OTP_DEBUG_BLK4_W7_REG register
- *  Otp debuger block4 data register7.
+ *  Otp debugger block4 data register7.
  */
 #define OTP_DEBUG_BLK4_W7_REG (DR_REG_OTP_DEBUG_BASE + 0xe8)
 /** OTP_DEBUG_BLOCK4_W7 : RO; bitpos: [31:0]; default: 0;
@@ -720,7 +720,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK4_W7_S  0
 
 /** OTP_DEBUG_BLK4_W8_REG register
- *  Otp debuger block4 data register8.
+ *  Otp debugger block4 data register8.
  */
 #define OTP_DEBUG_BLK4_W8_REG (DR_REG_OTP_DEBUG_BASE + 0xec)
 /** OTP_DEBUG_BLOCK4_W8 : RO; bitpos: [31:0]; default: 0;
@@ -732,7 +732,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK4_W8_S  0
 
 /** OTP_DEBUG_BLK4_W9_REG register
- *  Otp debuger block4 data register9.
+ *  Otp debugger block4 data register9.
  */
 #define OTP_DEBUG_BLK4_W9_REG (DR_REG_OTP_DEBUG_BASE + 0xf0)
 /** OTP_DEBUG_BLOCK4_W9 : RO; bitpos: [31:0]; default: 0;
@@ -744,7 +744,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK4_W9_S  0
 
 /** OTP_DEBUG_BLK4_W10_REG register
- *  Otp debuger block4 data registe10.
+ *  Otp debugger block4 data registe10.
  */
 #define OTP_DEBUG_BLK4_W10_REG (DR_REG_OTP_DEBUG_BASE + 0xf4)
 /** OTP_DEBUG_BLOCK4_W10 : RO; bitpos: [31:0]; default: 0;
@@ -756,7 +756,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK4_W10_S  0
 
 /** OTP_DEBUG_BLK4_W11_REG register
- *  Otp debuger block4 data register11.
+ *  Otp debugger block4 data register11.
  */
 #define OTP_DEBUG_BLK4_W11_REG (DR_REG_OTP_DEBUG_BASE + 0xf8)
 /** OTP_DEBUG_BLOCK4_W11 : RO; bitpos: [31:0]; default: 0;
@@ -768,7 +768,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK4_W11_S  0
 
 /** OTP_DEBUG_BLK5_W1_REG register
- *  Otp debuger block5 data register1.
+ *  Otp debugger block5 data register1.
  */
 #define OTP_DEBUG_BLK5_W1_REG (DR_REG_OTP_DEBUG_BASE + 0xfc)
 /** OTP_DEBUG_BLOCK5_W1 : RO; bitpos: [31:0]; default: 0;
@@ -780,7 +780,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK5_W1_S  0
 
 /** OTP_DEBUG_BLK5_W2_REG register
- *  Otp debuger block5 data register2.
+ *  Otp debugger block5 data register2.
  */
 #define OTP_DEBUG_BLK5_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x100)
 /** OTP_DEBUG_BLOCK5_W2 : RO; bitpos: [31:0]; default: 0;
@@ -792,7 +792,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK5_W2_S  0
 
 /** OTP_DEBUG_BLK5_W3_REG register
- *  Otp debuger block5 data register3.
+ *  Otp debugger block5 data register3.
  */
 #define OTP_DEBUG_BLK5_W3_REG (DR_REG_OTP_DEBUG_BASE + 0x104)
 /** OTP_DEBUG_BLOCK5_W3 : RO; bitpos: [31:0]; default: 0;
@@ -804,7 +804,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK5_W3_S  0
 
 /** OTP_DEBUG_BLK5_W4_REG register
- *  Otp debuger block5 data register4.
+ *  Otp debugger block5 data register4.
  */
 #define OTP_DEBUG_BLK5_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x108)
 /** OTP_DEBUG_BLOCK5_W4 : RO; bitpos: [31:0]; default: 0;
@@ -816,7 +816,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK5_W4_S  0
 
 /** OTP_DEBUG_BLK5_W5_REG register
- *  Otp debuger block5 data register5.
+ *  Otp debugger block5 data register5.
  */
 #define OTP_DEBUG_BLK5_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x10c)
 /** OTP_DEBUG_BLOCK5_W5 : RO; bitpos: [31:0]; default: 0;
@@ -828,7 +828,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK5_W5_S  0
 
 /** OTP_DEBUG_BLK5_W6_REG register
- *  Otp debuger block5 data register6.
+ *  Otp debugger block5 data register6.
  */
 #define OTP_DEBUG_BLK5_W6_REG (DR_REG_OTP_DEBUG_BASE + 0x110)
 /** OTP_DEBUG_BLOCK5_W6 : RO; bitpos: [31:0]; default: 0;
@@ -840,7 +840,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK5_W6_S  0
 
 /** OTP_DEBUG_BLK5_W7_REG register
- *  Otp debuger block5 data register7.
+ *  Otp debugger block5 data register7.
  */
 #define OTP_DEBUG_BLK5_W7_REG (DR_REG_OTP_DEBUG_BASE + 0x114)
 /** OTP_DEBUG_BLOCK5_W7 : RO; bitpos: [31:0]; default: 0;
@@ -852,7 +852,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK5_W7_S  0
 
 /** OTP_DEBUG_BLK5_W8_REG register
- *  Otp debuger block5 data register8.
+ *  Otp debugger block5 data register8.
  */
 #define OTP_DEBUG_BLK5_W8_REG (DR_REG_OTP_DEBUG_BASE + 0x118)
 /** OTP_DEBUG_BLOCK5_W8 : RO; bitpos: [31:0]; default: 0;
@@ -864,7 +864,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK5_W8_S  0
 
 /** OTP_DEBUG_BLK5_W9_REG register
- *  Otp debuger block5 data register9.
+ *  Otp debugger block5 data register9.
  */
 #define OTP_DEBUG_BLK5_W9_REG (DR_REG_OTP_DEBUG_BASE + 0x11c)
 /** OTP_DEBUG_BLOCK5_W9 : RO; bitpos: [31:0]; default: 0;
@@ -876,7 +876,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK5_W9_S  0
 
 /** OTP_DEBUG_BLK5_W10_REG register
- *  Otp debuger block5 data register10.
+ *  Otp debugger block5 data register10.
  */
 #define OTP_DEBUG_BLK5_W10_REG (DR_REG_OTP_DEBUG_BASE + 0x120)
 /** OTP_DEBUG_BLOCK5_W10 : RO; bitpos: [31:0]; default: 0;
@@ -888,7 +888,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK5_W10_S  0
 
 /** OTP_DEBUG_BLK5_W11_REG register
- *  Otp debuger block5 data register11.
+ *  Otp debugger block5 data register11.
  */
 #define OTP_DEBUG_BLK5_W11_REG (DR_REG_OTP_DEBUG_BASE + 0x124)
 /** OTP_DEBUG_BLOCK5_W11 : RO; bitpos: [31:0]; default: 0;
@@ -900,7 +900,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK5_W11_S  0
 
 /** OTP_DEBUG_BLK6_W1_REG register
- *  Otp debuger block6 data register1.
+ *  Otp debugger block6 data register1.
  */
 #define OTP_DEBUG_BLK6_W1_REG (DR_REG_OTP_DEBUG_BASE + 0x128)
 /** OTP_DEBUG_BLOCK6_W1 : RO; bitpos: [31:0]; default: 0;
@@ -912,7 +912,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK6_W1_S  0
 
 /** OTP_DEBUG_BLK6_W2_REG register
- *  Otp debuger block6 data register2.
+ *  Otp debugger block6 data register2.
  */
 #define OTP_DEBUG_BLK6_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x12c)
 /** OTP_DEBUG_BLOCK6_W2 : RO; bitpos: [31:0]; default: 0;
@@ -924,7 +924,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK6_W2_S  0
 
 /** OTP_DEBUG_BLK6_W3_REG register
- *  Otp debuger block6 data register3.
+ *  Otp debugger block6 data register3.
  */
 #define OTP_DEBUG_BLK6_W3_REG (DR_REG_OTP_DEBUG_BASE + 0x130)
 /** OTP_DEBUG_BLOCK6_W3 : RO; bitpos: [31:0]; default: 0;
@@ -936,7 +936,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK6_W3_S  0
 
 /** OTP_DEBUG_BLK6_W4_REG register
- *  Otp debuger block6 data register4.
+ *  Otp debugger block6 data register4.
  */
 #define OTP_DEBUG_BLK6_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x134)
 /** OTP_DEBUG_BLOCK6_W4 : RO; bitpos: [31:0]; default: 0;
@@ -948,7 +948,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK6_W4_S  0
 
 /** OTP_DEBUG_BLK6_W5_REG register
- *  Otp debuger block6 data register5.
+ *  Otp debugger block6 data register5.
  */
 #define OTP_DEBUG_BLK6_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x138)
 /** OTP_DEBUG_BLOCK6_W5 : RO; bitpos: [31:0]; default: 0;
@@ -960,7 +960,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK6_W5_S  0
 
 /** OTP_DEBUG_BLK6_W6_REG register
- *  Otp debuger block6 data register6.
+ *  Otp debugger block6 data register6.
  */
 #define OTP_DEBUG_BLK6_W6_REG (DR_REG_OTP_DEBUG_BASE + 0x13c)
 /** OTP_DEBUG_BLOCK6_W6 : RO; bitpos: [31:0]; default: 0;
@@ -972,7 +972,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK6_W6_S  0
 
 /** OTP_DEBUG_BLK6_W7_REG register
- *  Otp debuger block6 data register7.
+ *  Otp debugger block6 data register7.
  */
 #define OTP_DEBUG_BLK6_W7_REG (DR_REG_OTP_DEBUG_BASE + 0x140)
 /** OTP_DEBUG_BLOCK6_W7 : RO; bitpos: [31:0]; default: 0;
@@ -984,7 +984,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK6_W7_S  0
 
 /** OTP_DEBUG_BLK6_W8_REG register
- *  Otp debuger block6 data register8.
+ *  Otp debugger block6 data register8.
  */
 #define OTP_DEBUG_BLK6_W8_REG (DR_REG_OTP_DEBUG_BASE + 0x144)
 /** OTP_DEBUG_BLOCK6_W8 : RO; bitpos: [31:0]; default: 0;
@@ -996,7 +996,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK6_W8_S  0
 
 /** OTP_DEBUG_BLK6_W9_REG register
- *  Otp debuger block6 data register9.
+ *  Otp debugger block6 data register9.
  */
 #define OTP_DEBUG_BLK6_W9_REG (DR_REG_OTP_DEBUG_BASE + 0x148)
 /** OTP_DEBUG_BLOCK6_W9 : RO; bitpos: [31:0]; default: 0;
@@ -1008,7 +1008,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK6_W9_S  0
 
 /** OTP_DEBUG_BLK6_W10_REG register
- *  Otp debuger block6 data register10.
+ *  Otp debugger block6 data register10.
  */
 #define OTP_DEBUG_BLK6_W10_REG (DR_REG_OTP_DEBUG_BASE + 0x14c)
 /** OTP_DEBUG_BLOCK6_W10 : RO; bitpos: [31:0]; default: 0;
@@ -1020,7 +1020,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK6_W10_S  0
 
 /** OTP_DEBUG_BLK6_W11_REG register
- *  Otp debuger block6 data register11.
+ *  Otp debugger block6 data register11.
  */
 #define OTP_DEBUG_BLK6_W11_REG (DR_REG_OTP_DEBUG_BASE + 0x150)
 /** OTP_DEBUG_BLOCK6_W11 : RO; bitpos: [31:0]; default: 0;
@@ -1032,7 +1032,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK6_W11_S  0
 
 /** OTP_DEBUG_BLK7_W1_REG register
- *  Otp debuger block7 data register1.
+ *  Otp debugger block7 data register1.
  */
 #define OTP_DEBUG_BLK7_W1_REG (DR_REG_OTP_DEBUG_BASE + 0x154)
 /** OTP_DEBUG_BLOCK7_W1 : RO; bitpos: [31:0]; default: 0;
@@ -1044,7 +1044,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK7_W1_S  0
 
 /** OTP_DEBUG_BLK7_W2_REG register
- *  Otp debuger block7 data register2.
+ *  Otp debugger block7 data register2.
  */
 #define OTP_DEBUG_BLK7_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x158)
 /** OTP_DEBUG_BLOCK7_W2 : RO; bitpos: [31:0]; default: 0;
@@ -1056,7 +1056,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK7_W2_S  0
 
 /** OTP_DEBUG_BLK7_W3_REG register
- *  Otp debuger block7 data register3.
+ *  Otp debugger block7 data register3.
  */
 #define OTP_DEBUG_BLK7_W3_REG (DR_REG_OTP_DEBUG_BASE + 0x15c)
 /** OTP_DEBUG_BLOCK7_W3 : RO; bitpos: [31:0]; default: 0;
@@ -1068,7 +1068,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK7_W3_S  0
 
 /** OTP_DEBUG_BLK7_W4_REG register
- *  Otp debuger block7 data register4.
+ *  Otp debugger block7 data register4.
  */
 #define OTP_DEBUG_BLK7_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x160)
 /** OTP_DEBUG_BLOCK7_W4 : RO; bitpos: [31:0]; default: 0;
@@ -1080,7 +1080,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK7_W4_S  0
 
 /** OTP_DEBUG_BLK7_W5_REG register
- *  Otp debuger block7 data register5.
+ *  Otp debugger block7 data register5.
  */
 #define OTP_DEBUG_BLK7_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x164)
 /** OTP_DEBUG_BLOCK7_W5 : RO; bitpos: [31:0]; default: 0;
@@ -1092,7 +1092,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK7_W5_S  0
 
 /** OTP_DEBUG_BLK7_W6_REG register
- *  Otp debuger block7 data register6.
+ *  Otp debugger block7 data register6.
  */
 #define OTP_DEBUG_BLK7_W6_REG (DR_REG_OTP_DEBUG_BASE + 0x168)
 /** OTP_DEBUG_BLOCK7_W6 : RO; bitpos: [31:0]; default: 0;
@@ -1104,7 +1104,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK7_W6_S  0
 
 /** OTP_DEBUG_BLK7_W7_REG register
- *  Otp debuger block7 data register7.
+ *  Otp debugger block7 data register7.
  */
 #define OTP_DEBUG_BLK7_W7_REG (DR_REG_OTP_DEBUG_BASE + 0x16c)
 /** OTP_DEBUG_BLOCK7_W7 : RO; bitpos: [31:0]; default: 0;
@@ -1116,7 +1116,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK7_W7_S  0
 
 /** OTP_DEBUG_BLK7_W8_REG register
- *  Otp debuger block7 data register8.
+ *  Otp debugger block7 data register8.
  */
 #define OTP_DEBUG_BLK7_W8_REG (DR_REG_OTP_DEBUG_BASE + 0x170)
 /** OTP_DEBUG_BLOCK7_W8 : RO; bitpos: [31:0]; default: 0;
@@ -1128,7 +1128,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK7_W8_S  0
 
 /** OTP_DEBUG_BLK7_W9_REG register
- *  Otp debuger block7 data register9.
+ *  Otp debugger block7 data register9.
  */
 #define OTP_DEBUG_BLK7_W9_REG (DR_REG_OTP_DEBUG_BASE + 0x174)
 /** OTP_DEBUG_BLOCK7_W9 : RO; bitpos: [31:0]; default: 0;
@@ -1140,7 +1140,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK7_W9_S  0
 
 /** OTP_DEBUG_BLK7_W10_REG register
- *  Otp debuger block7 data register10.
+ *  Otp debugger block7 data register10.
  */
 #define OTP_DEBUG_BLK7_W10_REG (DR_REG_OTP_DEBUG_BASE + 0x178)
 /** OTP_DEBUG_BLOCK7_W10 : RO; bitpos: [31:0]; default: 0;
@@ -1152,7 +1152,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK7_W10_S  0
 
 /** OTP_DEBUG_BLK7_W11_REG register
- *  Otp debuger block7 data register11.
+ *  Otp debugger block7 data register11.
  */
 #define OTP_DEBUG_BLK7_W11_REG (DR_REG_OTP_DEBUG_BASE + 0x17c)
 /** OTP_DEBUG_BLOCK7_W11 : RO; bitpos: [31:0]; default: 0;
@@ -1164,7 +1164,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK7_W11_S  0
 
 /** OTP_DEBUG_BLK8_W1_REG register
- *  Otp debuger block8 data register1.
+ *  Otp debugger block8 data register1.
  */
 #define OTP_DEBUG_BLK8_W1_REG (DR_REG_OTP_DEBUG_BASE + 0x180)
 /** OTP_DEBUG_BLOCK8_W1 : RO; bitpos: [31:0]; default: 0;
@@ -1176,7 +1176,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK8_W1_S  0
 
 /** OTP_DEBUG_BLK8_W2_REG register
- *  Otp debuger block8 data register2.
+ *  Otp debugger block8 data register2.
  */
 #define OTP_DEBUG_BLK8_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x184)
 /** OTP_DEBUG_BLOCK8_W2 : RO; bitpos: [31:0]; default: 0;
@@ -1188,7 +1188,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK8_W2_S  0
 
 /** OTP_DEBUG_BLK8_W3_REG register
- *  Otp debuger block8 data register3.
+ *  Otp debugger block8 data register3.
  */
 #define OTP_DEBUG_BLK8_W3_REG (DR_REG_OTP_DEBUG_BASE + 0x188)
 /** OTP_DEBUG_BLOCK8_W3 : RO; bitpos: [31:0]; default: 0;
@@ -1200,7 +1200,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK8_W3_S  0
 
 /** OTP_DEBUG_BLK8_W4_REG register
- *  Otp debuger block8 data register4.
+ *  Otp debugger block8 data register4.
  */
 #define OTP_DEBUG_BLK8_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x18c)
 /** OTP_DEBUG_BLOCK8_W4 : RO; bitpos: [31:0]; default: 0;
@@ -1212,7 +1212,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK8_W4_S  0
 
 /** OTP_DEBUG_BLK8_W5_REG register
- *  Otp debuger block8 data register5.
+ *  Otp debugger block8 data register5.
  */
 #define OTP_DEBUG_BLK8_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x190)
 /** OTP_DEBUG_BLOCK8_W5 : RO; bitpos: [31:0]; default: 0;
@@ -1224,7 +1224,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK8_W5_S  0
 
 /** OTP_DEBUG_BLK8_W6_REG register
- *  Otp debuger block8 data register6.
+ *  Otp debugger block8 data register6.
  */
 #define OTP_DEBUG_BLK8_W6_REG (DR_REG_OTP_DEBUG_BASE + 0x194)
 /** OTP_DEBUG_BLOCK8_W6 : RO; bitpos: [31:0]; default: 0;
@@ -1236,7 +1236,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK8_W6_S  0
 
 /** OTP_DEBUG_BLK8_W7_REG register
- *  Otp debuger block8 data register7.
+ *  Otp debugger block8 data register7.
  */
 #define OTP_DEBUG_BLK8_W7_REG (DR_REG_OTP_DEBUG_BASE + 0x198)
 /** OTP_DEBUG_BLOCK8_W7 : RO; bitpos: [31:0]; default: 0;
@@ -1248,7 +1248,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK8_W7_S  0
 
 /** OTP_DEBUG_BLK8_W8_REG register
- *  Otp debuger block8 data register8.
+ *  Otp debugger block8 data register8.
  */
 #define OTP_DEBUG_BLK8_W8_REG (DR_REG_OTP_DEBUG_BASE + 0x19c)
 /** OTP_DEBUG_BLOCK8_W8 : RO; bitpos: [31:0]; default: 0;
@@ -1260,7 +1260,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK8_W8_S  0
 
 /** OTP_DEBUG_BLK8_W9_REG register
- *  Otp debuger block8 data register9.
+ *  Otp debugger block8 data register9.
  */
 #define OTP_DEBUG_BLK8_W9_REG (DR_REG_OTP_DEBUG_BASE + 0x1a0)
 /** OTP_DEBUG_BLOCK8_W9 : RO; bitpos: [31:0]; default: 0;
@@ -1272,7 +1272,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK8_W9_S  0
 
 /** OTP_DEBUG_BLK8_W10_REG register
- *  Otp debuger block8 data register10.
+ *  Otp debugger block8 data register10.
  */
 #define OTP_DEBUG_BLK8_W10_REG (DR_REG_OTP_DEBUG_BASE + 0x1a4)
 /** OTP_DEBUG_BLOCK8_W10 : RO; bitpos: [31:0]; default: 0;
@@ -1284,7 +1284,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK8_W10_S  0
 
 /** OTP_DEBUG_BLK8_W11_REG register
- *  Otp debuger block8 data register11.
+ *  Otp debugger block8 data register11.
  */
 #define OTP_DEBUG_BLK8_W11_REG (DR_REG_OTP_DEBUG_BASE + 0x1a8)
 /** OTP_DEBUG_BLOCK8_W11 : RO; bitpos: [31:0]; default: 0;
@@ -1296,7 +1296,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK8_W11_S  0
 
 /** OTP_DEBUG_BLK9_W1_REG register
- *  Otp debuger block9 data register1.
+ *  Otp debugger block9 data register1.
  */
 #define OTP_DEBUG_BLK9_W1_REG (DR_REG_OTP_DEBUG_BASE + 0x1ac)
 /** OTP_DEBUG_BLOCK9_W1 : RO; bitpos: [31:0]; default: 0;
@@ -1308,7 +1308,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK9_W1_S  0
 
 /** OTP_DEBUG_BLK9_W2_REG register
- *  Otp debuger block9 data register2.
+ *  Otp debugger block9 data register2.
  */
 #define OTP_DEBUG_BLK9_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x1b0)
 /** OTP_DEBUG_BLOCK9_W2 : RO; bitpos: [31:0]; default: 0;
@@ -1320,7 +1320,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK9_W2_S  0
 
 /** OTP_DEBUG_BLK9_W3_REG register
- *  Otp debuger block9 data register3.
+ *  Otp debugger block9 data register3.
  */
 #define OTP_DEBUG_BLK9_W3_REG (DR_REG_OTP_DEBUG_BASE + 0x1b4)
 /** OTP_DEBUG_BLOCK9_W3 : RO; bitpos: [31:0]; default: 0;
@@ -1332,7 +1332,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK9_W3_S  0
 
 /** OTP_DEBUG_BLK9_W4_REG register
- *  Otp debuger block9 data register4.
+ *  Otp debugger block9 data register4.
  */
 #define OTP_DEBUG_BLK9_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x1b8)
 /** OTP_DEBUG_BLOCK9_W4 : RO; bitpos: [31:0]; default: 0;
@@ -1344,7 +1344,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK9_W4_S  0
 
 /** OTP_DEBUG_BLK9_W5_REG register
- *  Otp debuger block9 data register5.
+ *  Otp debugger block9 data register5.
  */
 #define OTP_DEBUG_BLK9_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x1bc)
 /** OTP_DEBUG_BLOCK9_W5 : RO; bitpos: [31:0]; default: 0;
@@ -1356,7 +1356,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK9_W5_S  0
 
 /** OTP_DEBUG_BLK9_W6_REG register
- *  Otp debuger block9 data register6.
+ *  Otp debugger block9 data register6.
  */
 #define OTP_DEBUG_BLK9_W6_REG (DR_REG_OTP_DEBUG_BASE + 0x1c0)
 /** OTP_DEBUG_BLOCK9_W6 : RO; bitpos: [31:0]; default: 0;
@@ -1368,7 +1368,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK9_W6_S  0
 
 /** OTP_DEBUG_BLK9_W7_REG register
- *  Otp debuger block9 data register7.
+ *  Otp debugger block9 data register7.
  */
 #define OTP_DEBUG_BLK9_W7_REG (DR_REG_OTP_DEBUG_BASE + 0x1c4)
 /** OTP_DEBUG_BLOCK9_W7 : RO; bitpos: [31:0]; default: 0;
@@ -1380,7 +1380,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK9_W7_S  0
 
 /** OTP_DEBUG_BLK9_W8_REG register
- *  Otp debuger block9 data register8.
+ *  Otp debugger block9 data register8.
  */
 #define OTP_DEBUG_BLK9_W8_REG (DR_REG_OTP_DEBUG_BASE + 0x1c8)
 /** OTP_DEBUG_BLOCK9_W8 : RO; bitpos: [31:0]; default: 0;
@@ -1392,7 +1392,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK9_W8_S  0
 
 /** OTP_DEBUG_BLK9_W9_REG register
- *  Otp debuger block9 data register9.
+ *  Otp debugger block9 data register9.
  */
 #define OTP_DEBUG_BLK9_W9_REG (DR_REG_OTP_DEBUG_BASE + 0x1cc)
 /** OTP_DEBUG_BLOCK9_W9 : RO; bitpos: [31:0]; default: 0;
@@ -1404,7 +1404,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK9_W9_S  0
 
 /** OTP_DEBUG_BLK9_W10_REG register
- *  Otp debuger block9 data register10.
+ *  Otp debugger block9 data register10.
  */
 #define OTP_DEBUG_BLK9_W10_REG (DR_REG_OTP_DEBUG_BASE + 0x1d0)
 /** OTP_DEBUG_BLOCK9_W10 : RO; bitpos: [31:0]; default: 0;
@@ -1416,7 +1416,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK9_W10_S  0
 
 /** OTP_DEBUG_BLK9_W11_REG register
- *  Otp debuger block9 data register11.
+ *  Otp debugger block9 data register11.
  */
 #define OTP_DEBUG_BLK9_W11_REG (DR_REG_OTP_DEBUG_BASE + 0x1d4)
 /** OTP_DEBUG_BLOCK9_W11 : RO; bitpos: [31:0]; default: 0;
@@ -1428,7 +1428,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK9_W11_S  0
 
 /** OTP_DEBUG_BLK10_W1_REG register
- *  Otp debuger block10 data register1.
+ *  Otp debugger block10 data register1.
  */
 #define OTP_DEBUG_BLK10_W1_REG (DR_REG_OTP_DEBUG_BASE + 0x1d8)
 /** OTP_DEBUG_BLOCK10_W1 : RO; bitpos: [31:0]; default: 0;
@@ -1440,7 +1440,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK10_W1_S  0
 
 /** OTP_DEBUG_BLK10_W2_REG register
- *  Otp debuger block10 data register2.
+ *  Otp debugger block10 data register2.
  */
 #define OTP_DEBUG_BLK10_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x1dc)
 /** OTP_DEBUG_BLOCK10_W2 : RO; bitpos: [31:0]; default: 0;
@@ -1452,7 +1452,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK10_W2_S  0
 
 /** OTP_DEBUG_BLK10_W3_REG register
- *  Otp debuger block10 data register3.
+ *  Otp debugger block10 data register3.
  */
 #define OTP_DEBUG_BLK10_W3_REG (DR_REG_OTP_DEBUG_BASE + 0x1e0)
 /** OTP_DEBUG_BLOCK10_W3 : RO; bitpos: [31:0]; default: 0;
@@ -1464,7 +1464,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK10_W3_S  0
 
 /** OTP_DEBUG_BLK10_W4_REG register
- *  Otp debuger block10 data register4.
+ *  Otp debugger block10 data register4.
  */
 #define OTP_DEBUG_BLK10_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x1e4)
 /** OTP_DEBUG_BLOCK10_W4 : RO; bitpos: [31:0]; default: 0;
@@ -1476,7 +1476,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK10_W4_S  0
 
 /** OTP_DEBUG_BLK10_W5_REG register
- *  Otp debuger block10 data register5.
+ *  Otp debugger block10 data register5.
  */
 #define OTP_DEBUG_BLK10_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x1e8)
 /** OTP_DEBUG_BLOCK10_W5 : RO; bitpos: [31:0]; default: 0;
@@ -1488,7 +1488,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK10_W5_S  0
 
 /** OTP_DEBUG_BLK10_W6_REG register
- *  Otp debuger block10 data register6.
+ *  Otp debugger block10 data register6.
  */
 #define OTP_DEBUG_BLK10_W6_REG (DR_REG_OTP_DEBUG_BASE + 0x1ec)
 /** OTP_DEBUG_BLOCK10_W6 : RO; bitpos: [31:0]; default: 0;
@@ -1500,7 +1500,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK10_W6_S  0
 
 /** OTP_DEBUG_BLK10_W7_REG register
- *  Otp debuger block10 data register7.
+ *  Otp debugger block10 data register7.
  */
 #define OTP_DEBUG_BLK10_W7_REG (DR_REG_OTP_DEBUG_BASE + 0x1f0)
 /** OTP_DEBUG_BLOCK10_W7 : RO; bitpos: [31:0]; default: 0;
@@ -1512,7 +1512,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK10_W7_S  0
 
 /** OTP_DEBUG_BLK10_W8_REG register
- *  Otp debuger block10 data register8.
+ *  Otp debugger block10 data register8.
  */
 #define OTP_DEBUG_BLK10_W8_REG (DR_REG_OTP_DEBUG_BASE + 0x1f4)
 /** OTP_DEBUG_BLOCK10_W8 : RO; bitpos: [31:0]; default: 0;
@@ -1524,7 +1524,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK10_W8_S  0
 
 /** OTP_DEBUG_BLK10_W9_REG register
- *  Otp debuger block10 data register9.
+ *  Otp debugger block10 data register9.
  */
 #define OTP_DEBUG_BLK10_W9_REG (DR_REG_OTP_DEBUG_BASE + 0x1f8)
 /** OTP_DEBUG_BLOCK10_W9 : RO; bitpos: [31:0]; default: 0;
@@ -1536,7 +1536,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK10_W9_S  0
 
 /** OTP_DEBUG_BLK10_W10_REG register
- *  Otp debuger block10 data register10.
+ *  Otp debugger block10 data register10.
  */
 #define OTP_DEBUG_BLK10_W10_REG (DR_REG_OTP_DEBUG_BASE + 0x1fc)
 /** OTP_DEBUG_BLOCK19_W10 : RO; bitpos: [31:0]; default: 0;
@@ -1548,7 +1548,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK19_W10_S  0
 
 /** OTP_DEBUG_BLK10_W11_REG register
- *  Otp debuger block10 data register11.
+ *  Otp debugger block10 data register11.
  */
 #define OTP_DEBUG_BLK10_W11_REG (DR_REG_OTP_DEBUG_BASE + 0x200)
 /** OTP_DEBUG_BLOCK10_W11 : RO; bitpos: [31:0]; default: 0;
@@ -1560,7 +1560,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK10_W11_S  0
 
 /** OTP_DEBUG_CLK_REG register
- *  Otp debuger clk_en configuration register.
+ *  Otp debugger clk_en configuration register.
  */
 #define OTP_DEBUG_CLK_REG (DR_REG_OTP_DEBUG_BASE + 0x204)
 /** OTP_DEBUG_CLK_EN : R/W; bitpos: [0]; default: 0;
diff --git a/components/soc/esp32c6/include/soc/otp_debug_struct.h b/components/soc/esp32c6/register/soc/otp_debug_struct.h
similarity index 89%
rename from components/soc/esp32c6/include/soc/otp_debug_struct.h
rename to components/soc/esp32c6/register/soc/otp_debug_struct.h
index 5b0737475f..8ed1fe2802 100644
--- a/components/soc/esp32c6/include/soc/otp_debug_struct.h
+++ b/components/soc/esp32c6/register/soc/otp_debug_struct.h
@@ -12,7 +12,7 @@ extern "C" {
 
 /** Group: OTP_DEBUG Block0 Write Disable Data */
 /** Type of wr_dis register
- *  Otp debuger block0 data register1.
+ *  Otp debugger block0 data register1.
  */
 typedef union {
     struct {
@@ -27,7 +27,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block0 Backup1 Word1 Data */
 /** Type of blk0_backup1_w1 register
- *  Otp debuger block0 data register2.
+ *  Otp debugger block0 data register2.
  */
 typedef union {
     struct {
@@ -42,7 +42,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block0 Backup1 Word2 Data */
 /** Type of blk0_backup1_w2 register
- *  Otp debuger block0 data register3.
+ *  Otp debugger block0 data register3.
  */
 typedef union {
     struct {
@@ -57,7 +57,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block0 Backup1 Word3 Data */
 /** Type of blk0_backup1_w3 register
- *  Otp debuger block0 data register4.
+ *  Otp debugger block0 data register4.
  */
 typedef union {
     struct {
@@ -72,7 +72,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block0 Backup1 Word4 Data */
 /** Type of blk0_backup1_w4 register
- *  Otp debuger block0 data register5.
+ *  Otp debugger block0 data register5.
  */
 typedef union {
     struct {
@@ -87,7 +87,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block0 Backup1 Word5 Data */
 /** Type of blk0_backup1_w5 register
- *  Otp debuger block0 data register6.
+ *  Otp debugger block0 data register6.
  */
 typedef union {
     struct {
@@ -102,7 +102,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block0 Backup2 Word1 Data */
 /** Type of blk0_backup2_w1 register
- *  Otp debuger block0 data register7.
+ *  Otp debugger block0 data register7.
  */
 typedef union {
     struct {
@@ -117,7 +117,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block0 Backup2 Word2 Data */
 /** Type of blk0_backup2_w2 register
- *  Otp debuger block0 data register8.
+ *  Otp debugger block0 data register8.
  */
 typedef union {
     struct {
@@ -132,7 +132,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block0 Backup2 Word3 Data */
 /** Type of blk0_backup2_w3 register
- *  Otp debuger block0 data register9.
+ *  Otp debugger block0 data register9.
  */
 typedef union {
     struct {
@@ -147,7 +147,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block0 Backup2 Word4 Data */
 /** Type of blk0_backup2_w4 register
- *  Otp debuger block0 data register10.
+ *  Otp debugger block0 data register10.
  */
 typedef union {
     struct {
@@ -162,7 +162,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block0 Backup2 Word5 Data */
 /** Type of blk0_backup2_w5 register
- *  Otp debuger block0 data register11.
+ *  Otp debugger block0 data register11.
  */
 typedef union {
     struct {
@@ -177,7 +177,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block0 Backup3 Word1 Data */
 /** Type of blk0_backup3_w1 register
- *  Otp debuger block0 data register12.
+ *  Otp debugger block0 data register12.
  */
 typedef union {
     struct {
@@ -192,7 +192,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block0 Backup3 Word2 Data */
 /** Type of blk0_backup3_w2 register
- *  Otp debuger block0 data register13.
+ *  Otp debugger block0 data register13.
  */
 typedef union {
     struct {
@@ -207,7 +207,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block0 Backup3 Word3 Data */
 /** Type of blk0_backup3_w3 register
- *  Otp debuger block0 data register14.
+ *  Otp debugger block0 data register14.
  */
 typedef union {
     struct {
@@ -222,7 +222,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block0 Backup3 Word4 Data */
 /** Type of blk0_backup3_w4 register
- *  Otp debuger block0 data register15.
+ *  Otp debugger block0 data register15.
  */
 typedef union {
     struct {
@@ -237,7 +237,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block0 Backup3 Word5 Data */
 /** Type of blk0_backup3_w5 register
- *  Otp debuger block0 data register16.
+ *  Otp debugger block0 data register16.
  */
 typedef union {
     struct {
@@ -252,7 +252,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block0 Backup4 Word1 Data */
 /** Type of blk0_backup4_w1 register
- *  Otp debuger block0 data register17.
+ *  Otp debugger block0 data register17.
  */
 typedef union {
     struct {
@@ -267,7 +267,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block0 Backup4 Word2 Data */
 /** Type of blk0_backup4_w2 register
- *  Otp debuger block0 data register18.
+ *  Otp debugger block0 data register18.
  */
 typedef union {
     struct {
@@ -282,7 +282,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block0 Backup4 Word3 Data */
 /** Type of blk0_backup4_w3 register
- *  Otp debuger block0 data register19.
+ *  Otp debugger block0 data register19.
  */
 typedef union {
     struct {
@@ -297,7 +297,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block0 Backup4 Word4 Data */
 /** Type of blk0_backup4_w4 register
- *  Otp debuger block0 data register20.
+ *  Otp debugger block0 data register20.
  */
 typedef union {
     struct {
@@ -312,7 +312,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block0 Backup4 Word5 Data */
 /** Type of blk0_backup4_w5 register
- *  Otp debuger block0 data register21.
+ *  Otp debugger block0 data register21.
  */
 typedef union {
     struct {
@@ -327,7 +327,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block1 Word1 Data */
 /** Type of blk1_w1 register
- *  Otp debuger block1 data register1.
+ *  Otp debugger block1 data register1.
  */
 typedef union {
     struct {
@@ -342,7 +342,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block1 Word2 Data */
 /** Type of blk1_w2 register
- *  Otp debuger block1 data register2.
+ *  Otp debugger block1 data register2.
  */
 typedef union {
     struct {
@@ -357,7 +357,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block1 Word3 Data */
 /** Type of blk1_w3 register
- *  Otp debuger block1 data register3.
+ *  Otp debugger block1 data register3.
  */
 typedef union {
     struct {
@@ -372,7 +372,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block1 Word4 Data */
 /** Type of blk1_w4 register
- *  Otp debuger block1 data register4.
+ *  Otp debugger block1 data register4.
  */
 typedef union {
     struct {
@@ -387,7 +387,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block1 Word5 Data */
 /** Type of blk1_w5 register
- *  Otp debuger block1 data register5.
+ *  Otp debugger block1 data register5.
  */
 typedef union {
     struct {
@@ -402,7 +402,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block1 Word6 Data */
 /** Type of blk1_w6 register
- *  Otp debuger block1 data register6.
+ *  Otp debugger block1 data register6.
  */
 typedef union {
     struct {
@@ -417,7 +417,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block1 Word7 Data */
 /** Type of blk1_w7 register
- *  Otp debuger block1 data register7.
+ *  Otp debugger block1 data register7.
  */
 typedef union {
     struct {
@@ -432,7 +432,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block1 Word8 Data */
 /** Type of blk1_w8 register
- *  Otp debuger block1 data register8.
+ *  Otp debugger block1 data register8.
  */
 typedef union {
     struct {
@@ -447,7 +447,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block1 Word9 Data */
 /** Type of blk1_w9 register
- *  Otp debuger block1 data register9.
+ *  Otp debugger block1 data register9.
  */
 typedef union {
     struct {
@@ -462,7 +462,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block2 Word1 Data */
 /** Type of blk2_w1 register
- *  Otp debuger block2 data register1.
+ *  Otp debugger block2 data register1.
  */
 typedef union {
     struct {
@@ -477,7 +477,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block2 Word2 Data */
 /** Type of blk2_w2 register
- *  Otp debuger block2 data register2.
+ *  Otp debugger block2 data register2.
  */
 typedef union {
     struct {
@@ -492,7 +492,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block2 Word3 Data */
 /** Type of blk2_w3 register
- *  Otp debuger block2 data register3.
+ *  Otp debugger block2 data register3.
  */
 typedef union {
     struct {
@@ -507,7 +507,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block2 Word4 Data */
 /** Type of blk2_w4 register
- *  Otp debuger block2 data register4.
+ *  Otp debugger block2 data register4.
  */
 typedef union {
     struct {
@@ -522,7 +522,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block2 Word5 Data */
 /** Type of blk2_w5 register
- *  Otp debuger block2 data register5.
+ *  Otp debugger block2 data register5.
  */
 typedef union {
     struct {
@@ -537,7 +537,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block2 Word6 Data */
 /** Type of blk2_w6 register
- *  Otp debuger block2 data register6.
+ *  Otp debugger block2 data register6.
  */
 typedef union {
     struct {
@@ -552,7 +552,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block2 Word7 Data */
 /** Type of blk2_w7 register
- *  Otp debuger block2 data register7.
+ *  Otp debugger block2 data register7.
  */
 typedef union {
     struct {
@@ -567,7 +567,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block2 Word8 Data */
 /** Type of blk2_w8 register
- *  Otp debuger block2 data register8.
+ *  Otp debugger block2 data register8.
  */
 typedef union {
     struct {
@@ -582,7 +582,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block2 Word9 Data */
 /** Type of blk2_w9 register
- *  Otp debuger block2 data register9.
+ *  Otp debugger block2 data register9.
  */
 typedef union {
     struct {
@@ -597,7 +597,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block2 Word10 Data */
 /** Type of blk2_w10 register
- *  Otp debuger block2 data register10.
+ *  Otp debugger block2 data register10.
  */
 typedef union {
     struct {
@@ -612,7 +612,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block2 Word11 Data */
 /** Type of blk2_w11 register
- *  Otp debuger block2 data register11.
+ *  Otp debugger block2 data register11.
  */
 typedef union {
     struct {
@@ -625,7 +625,7 @@ typedef union {
 } otp_debug_blk2_w11_reg_t;
 
 /** Type of blk10_w11 register
- *  Otp debuger block10 data register11.
+ *  Otp debugger block10 data register11.
  */
 typedef union {
     struct {
@@ -640,7 +640,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block3 Word1 Data */
 /** Type of blk3_w1 register
- *  Otp debuger block3 data register1.
+ *  Otp debugger block3 data register1.
  */
 typedef union {
     struct {
@@ -655,7 +655,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block3 Word2 Data */
 /** Type of blk3_w2 register
- *  Otp debuger block3 data register2.
+ *  Otp debugger block3 data register2.
  */
 typedef union {
     struct {
@@ -670,7 +670,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block3 Word3 Data */
 /** Type of blk3_w3 register
- *  Otp debuger block3 data register3.
+ *  Otp debugger block3 data register3.
  */
 typedef union {
     struct {
@@ -685,7 +685,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block3 Word4 Data */
 /** Type of blk3_w4 register
- *  Otp debuger block3 data register4.
+ *  Otp debugger block3 data register4.
  */
 typedef union {
     struct {
@@ -700,7 +700,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block3 Word5 Data */
 /** Type of blk3_w5 register
- *  Otp debuger block3 data register5.
+ *  Otp debugger block3 data register5.
  */
 typedef union {
     struct {
@@ -715,7 +715,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block3 Word6 Data */
 /** Type of blk3_w6 register
- *  Otp debuger block3 data register6.
+ *  Otp debugger block3 data register6.
  */
 typedef union {
     struct {
@@ -730,7 +730,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block3 Word7 Data */
 /** Type of blk3_w7 register
- *  Otp debuger block3 data register7.
+ *  Otp debugger block3 data register7.
  */
 typedef union {
     struct {
@@ -745,7 +745,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block3 Word8 Data */
 /** Type of blk3_w8 register
- *  Otp debuger block3 data register8.
+ *  Otp debugger block3 data register8.
  */
 typedef union {
     struct {
@@ -760,7 +760,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block3 Word9 Data */
 /** Type of blk3_w9 register
- *  Otp debuger block3 data register9.
+ *  Otp debugger block3 data register9.
  */
 typedef union {
     struct {
@@ -775,7 +775,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block3 Word10 Data */
 /** Type of blk3_w10 register
- *  Otp debuger block3 data register10.
+ *  Otp debugger block3 data register10.
  */
 typedef union {
     struct {
@@ -790,7 +790,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block3 Word11 Data */
 /** Type of blk3_w11 register
- *  Otp debuger block3 data register11.
+ *  Otp debugger block3 data register11.
  */
 typedef union {
     struct {
@@ -805,7 +805,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block4 Word1 Data */
 /** Type of blk4_w1 register
- *  Otp debuger block4 data register1.
+ *  Otp debugger block4 data register1.
  */
 typedef union {
     struct {
@@ -820,7 +820,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block4 Word2 Data */
 /** Type of blk4_w2 register
- *  Otp debuger block4 data register2.
+ *  Otp debugger block4 data register2.
  */
 typedef union {
     struct {
@@ -835,7 +835,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block4 Word3 Data */
 /** Type of blk4_w3 register
- *  Otp debuger block4 data register3.
+ *  Otp debugger block4 data register3.
  */
 typedef union {
     struct {
@@ -850,7 +850,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block4 Word4 Data */
 /** Type of blk4_w4 register
- *  Otp debuger block4 data register4.
+ *  Otp debugger block4 data register4.
  */
 typedef union {
     struct {
@@ -865,7 +865,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block4 Word5 Data */
 /** Type of blk4_w5 register
- *  Otp debuger block4 data register5.
+ *  Otp debugger block4 data register5.
  */
 typedef union {
     struct {
@@ -880,7 +880,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block4 Word6 Data */
 /** Type of blk4_w6 register
- *  Otp debuger block4 data register6.
+ *  Otp debugger block4 data register6.
  */
 typedef union {
     struct {
@@ -895,7 +895,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block4 Word7 Data */
 /** Type of blk4_w7 register
- *  Otp debuger block4 data register7.
+ *  Otp debugger block4 data register7.
  */
 typedef union {
     struct {
@@ -910,7 +910,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block4 Word8 Data */
 /** Type of blk4_w8 register
- *  Otp debuger block4 data register8.
+ *  Otp debugger block4 data register8.
  */
 typedef union {
     struct {
@@ -925,7 +925,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block4 Word9 Data */
 /** Type of blk4_w9 register
- *  Otp debuger block4 data register9.
+ *  Otp debugger block4 data register9.
  */
 typedef union {
     struct {
@@ -940,7 +940,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block4 Word10 Data */
 /** Type of blk4_w10 register
- *  Otp debuger block4 data registe10.
+ *  Otp debugger block4 data registe10.
  */
 typedef union {
     struct {
@@ -955,7 +955,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block4 Word11 Data */
 /** Type of blk4_w11 register
- *  Otp debuger block4 data register11.
+ *  Otp debugger block4 data register11.
  */
 typedef union {
     struct {
@@ -970,7 +970,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block5 Word1 Data */
 /** Type of blk5_w1 register
- *  Otp debuger block5 data register1.
+ *  Otp debugger block5 data register1.
  */
 typedef union {
     struct {
@@ -985,7 +985,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block5 Word2 Data */
 /** Type of blk5_w2 register
- *  Otp debuger block5 data register2.
+ *  Otp debugger block5 data register2.
  */
 typedef union {
     struct {
@@ -1000,7 +1000,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block5 Word3 Data */
 /** Type of blk5_w3 register
- *  Otp debuger block5 data register3.
+ *  Otp debugger block5 data register3.
  */
 typedef union {
     struct {
@@ -1015,7 +1015,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block5 Word4 Data */
 /** Type of blk5_w4 register
- *  Otp debuger block5 data register4.
+ *  Otp debugger block5 data register4.
  */
 typedef union {
     struct {
@@ -1030,7 +1030,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block5 Word5 Data */
 /** Type of blk5_w5 register
- *  Otp debuger block5 data register5.
+ *  Otp debugger block5 data register5.
  */
 typedef union {
     struct {
@@ -1045,7 +1045,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block5 Word6 Data */
 /** Type of blk5_w6 register
- *  Otp debuger block5 data register6.
+ *  Otp debugger block5 data register6.
  */
 typedef union {
     struct {
@@ -1060,7 +1060,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block5 Word7 Data */
 /** Type of blk5_w7 register
- *  Otp debuger block5 data register7.
+ *  Otp debugger block5 data register7.
  */
 typedef union {
     struct {
@@ -1075,7 +1075,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block5 Word8 Data */
 /** Type of blk5_w8 register
- *  Otp debuger block5 data register8.
+ *  Otp debugger block5 data register8.
  */
 typedef union {
     struct {
@@ -1090,7 +1090,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block5 Word9 Data */
 /** Type of blk5_w9 register
- *  Otp debuger block5 data register9.
+ *  Otp debugger block5 data register9.
  */
 typedef union {
     struct {
@@ -1105,7 +1105,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block5 Word10 Data */
 /** Type of blk5_w10 register
- *  Otp debuger block5 data register10.
+ *  Otp debugger block5 data register10.
  */
 typedef union {
     struct {
@@ -1120,7 +1120,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block5 Word11 Data */
 /** Type of blk5_w11 register
- *  Otp debuger block5 data register11.
+ *  Otp debugger block5 data register11.
  */
 typedef union {
     struct {
@@ -1135,7 +1135,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block6 Word1 Data */
 /** Type of blk6_w1 register
- *  Otp debuger block6 data register1.
+ *  Otp debugger block6 data register1.
  */
 typedef union {
     struct {
@@ -1150,7 +1150,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block6 Word2 Data */
 /** Type of blk6_w2 register
- *  Otp debuger block6 data register2.
+ *  Otp debugger block6 data register2.
  */
 typedef union {
     struct {
@@ -1165,7 +1165,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block6 Word3 Data */
 /** Type of blk6_w3 register
- *  Otp debuger block6 data register3.
+ *  Otp debugger block6 data register3.
  */
 typedef union {
     struct {
@@ -1180,7 +1180,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block6 Word4 Data */
 /** Type of blk6_w4 register
- *  Otp debuger block6 data register4.
+ *  Otp debugger block6 data register4.
  */
 typedef union {
     struct {
@@ -1195,7 +1195,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block6 Word5 Data */
 /** Type of blk6_w5 register
- *  Otp debuger block6 data register5.
+ *  Otp debugger block6 data register5.
  */
 typedef union {
     struct {
@@ -1210,7 +1210,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block6 Word6 Data */
 /** Type of blk6_w6 register
- *  Otp debuger block6 data register6.
+ *  Otp debugger block6 data register6.
  */
 typedef union {
     struct {
@@ -1225,7 +1225,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block6 Word7 Data */
 /** Type of blk6_w7 register
- *  Otp debuger block6 data register7.
+ *  Otp debugger block6 data register7.
  */
 typedef union {
     struct {
@@ -1240,7 +1240,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block6 Word8 Data */
 /** Type of blk6_w8 register
- *  Otp debuger block6 data register8.
+ *  Otp debugger block6 data register8.
  */
 typedef union {
     struct {
@@ -1255,7 +1255,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block6 Word9 Data */
 /** Type of blk6_w9 register
- *  Otp debuger block6 data register9.
+ *  Otp debugger block6 data register9.
  */
 typedef union {
     struct {
@@ -1270,7 +1270,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block6 Word10 Data */
 /** Type of blk6_w10 register
- *  Otp debuger block6 data register10.
+ *  Otp debugger block6 data register10.
  */
 typedef union {
     struct {
@@ -1285,7 +1285,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block6 Word11 Data */
 /** Type of blk6_w11 register
- *  Otp debuger block6 data register11.
+ *  Otp debugger block6 data register11.
  */
 typedef union {
     struct {
@@ -1300,7 +1300,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block7 Word1 Data */
 /** Type of blk7_w1 register
- *  Otp debuger block7 data register1.
+ *  Otp debugger block7 data register1.
  */
 typedef union {
     struct {
@@ -1315,7 +1315,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block7 Word2 Data */
 /** Type of blk7_w2 register
- *  Otp debuger block7 data register2.
+ *  Otp debugger block7 data register2.
  */
 typedef union {
     struct {
@@ -1330,7 +1330,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block7 Word3 Data */
 /** Type of blk7_w3 register
- *  Otp debuger block7 data register3.
+ *  Otp debugger block7 data register3.
  */
 typedef union {
     struct {
@@ -1345,7 +1345,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block7 Word4 Data */
 /** Type of blk7_w4 register
- *  Otp debuger block7 data register4.
+ *  Otp debugger block7 data register4.
  */
 typedef union {
     struct {
@@ -1360,7 +1360,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block7 Word5 Data */
 /** Type of blk7_w5 register
- *  Otp debuger block7 data register5.
+ *  Otp debugger block7 data register5.
  */
 typedef union {
     struct {
@@ -1375,7 +1375,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block7 Word6 Data */
 /** Type of blk7_w6 register
- *  Otp debuger block7 data register6.
+ *  Otp debugger block7 data register6.
  */
 typedef union {
     struct {
@@ -1390,7 +1390,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block7 Word7 Data */
 /** Type of blk7_w7 register
- *  Otp debuger block7 data register7.
+ *  Otp debugger block7 data register7.
  */
 typedef union {
     struct {
@@ -1405,7 +1405,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block7 Word8 Data */
 /** Type of blk7_w8 register
- *  Otp debuger block7 data register8.
+ *  Otp debugger block7 data register8.
  */
 typedef union {
     struct {
@@ -1420,7 +1420,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block7 Word9 Data */
 /** Type of blk7_w9 register
- *  Otp debuger block7 data register9.
+ *  Otp debugger block7 data register9.
  */
 typedef union {
     struct {
@@ -1435,7 +1435,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block7 Word10 Data */
 /** Type of blk7_w10 register
- *  Otp debuger block7 data register10.
+ *  Otp debugger block7 data register10.
  */
 typedef union {
     struct {
@@ -1450,7 +1450,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block7 Word11 Data */
 /** Type of blk7_w11 register
- *  Otp debuger block7 data register11.
+ *  Otp debugger block7 data register11.
  */
 typedef union {
     struct {
@@ -1465,7 +1465,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block8 Word1 Data */
 /** Type of blk8_w1 register
- *  Otp debuger block8 data register1.
+ *  Otp debugger block8 data register1.
  */
 typedef union {
     struct {
@@ -1480,7 +1480,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block8 Word2 Data */
 /** Type of blk8_w2 register
- *  Otp debuger block8 data register2.
+ *  Otp debugger block8 data register2.
  */
 typedef union {
     struct {
@@ -1495,7 +1495,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block8 Word3 Data */
 /** Type of blk8_w3 register
- *  Otp debuger block8 data register3.
+ *  Otp debugger block8 data register3.
  */
 typedef union {
     struct {
@@ -1510,7 +1510,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block8 Word4 Data */
 /** Type of blk8_w4 register
- *  Otp debuger block8 data register4.
+ *  Otp debugger block8 data register4.
  */
 typedef union {
     struct {
@@ -1525,7 +1525,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block8 Word5 Data */
 /** Type of blk8_w5 register
- *  Otp debuger block8 data register5.
+ *  Otp debugger block8 data register5.
  */
 typedef union {
     struct {
@@ -1540,7 +1540,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block8 Word6 Data */
 /** Type of blk8_w6 register
- *  Otp debuger block8 data register6.
+ *  Otp debugger block8 data register6.
  */
 typedef union {
     struct {
@@ -1555,7 +1555,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block8 Word7 Data */
 /** Type of blk8_w7 register
- *  Otp debuger block8 data register7.
+ *  Otp debugger block8 data register7.
  */
 typedef union {
     struct {
@@ -1570,7 +1570,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block8 Word8 Data */
 /** Type of blk8_w8 register
- *  Otp debuger block8 data register8.
+ *  Otp debugger block8 data register8.
  */
 typedef union {
     struct {
@@ -1585,7 +1585,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block8 Word9 Data */
 /** Type of blk8_w9 register
- *  Otp debuger block8 data register9.
+ *  Otp debugger block8 data register9.
  */
 typedef union {
     struct {
@@ -1600,7 +1600,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block8 Word10 Data */
 /** Type of blk8_w10 register
- *  Otp debuger block8 data register10.
+ *  Otp debugger block8 data register10.
  */
 typedef union {
     struct {
@@ -1615,7 +1615,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block8 Word11 Data */
 /** Type of blk8_w11 register
- *  Otp debuger block8 data register11.
+ *  Otp debugger block8 data register11.
  */
 typedef union {
     struct {
@@ -1630,7 +1630,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block9 Word1 Data */
 /** Type of blk9_w1 register
- *  Otp debuger block9 data register1.
+ *  Otp debugger block9 data register1.
  */
 typedef union {
     struct {
@@ -1645,7 +1645,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block9 Word2 Data */
 /** Type of blk9_w2 register
- *  Otp debuger block9 data register2.
+ *  Otp debugger block9 data register2.
  */
 typedef union {
     struct {
@@ -1660,7 +1660,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block9 Word3 Data */
 /** Type of blk9_w3 register
- *  Otp debuger block9 data register3.
+ *  Otp debugger block9 data register3.
  */
 typedef union {
     struct {
@@ -1675,7 +1675,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block9 Word4 Data */
 /** Type of blk9_w4 register
- *  Otp debuger block9 data register4.
+ *  Otp debugger block9 data register4.
  */
 typedef union {
     struct {
@@ -1690,7 +1690,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block9 Word5 Data */
 /** Type of blk9_w5 register
- *  Otp debuger block9 data register5.
+ *  Otp debugger block9 data register5.
  */
 typedef union {
     struct {
@@ -1705,7 +1705,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block9 Word6 Data */
 /** Type of blk9_w6 register
- *  Otp debuger block9 data register6.
+ *  Otp debugger block9 data register6.
  */
 typedef union {
     struct {
@@ -1720,7 +1720,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block9 Word7 Data */
 /** Type of blk9_w7 register
- *  Otp debuger block9 data register7.
+ *  Otp debugger block9 data register7.
  */
 typedef union {
     struct {
@@ -1735,7 +1735,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block9 Word8 Data */
 /** Type of blk9_w8 register
- *  Otp debuger block9 data register8.
+ *  Otp debugger block9 data register8.
  */
 typedef union {
     struct {
@@ -1750,7 +1750,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block9 Word9 Data */
 /** Type of blk9_w9 register
- *  Otp debuger block9 data register9.
+ *  Otp debugger block9 data register9.
  */
 typedef union {
     struct {
@@ -1765,7 +1765,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block9 Word10 Data */
 /** Type of blk9_w10 register
- *  Otp debuger block9 data register10.
+ *  Otp debugger block9 data register10.
  */
 typedef union {
     struct {
@@ -1780,7 +1780,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block9 Word11 Data */
 /** Type of blk9_w11 register
- *  Otp debuger block9 data register11.
+ *  Otp debugger block9 data register11.
  */
 typedef union {
     struct {
@@ -1795,7 +1795,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block10 Word1 Data */
 /** Type of blk10_w1 register
- *  Otp debuger block10 data register1.
+ *  Otp debugger block10 data register1.
  */
 typedef union {
     struct {
@@ -1810,7 +1810,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block10 Word2 Data */
 /** Type of blk10_w2 register
- *  Otp debuger block10 data register2.
+ *  Otp debugger block10 data register2.
  */
 typedef union {
     struct {
@@ -1825,7 +1825,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block10 Word3 Data */
 /** Type of blk10_w3 register
- *  Otp debuger block10 data register3.
+ *  Otp debugger block10 data register3.
  */
 typedef union {
     struct {
@@ -1840,7 +1840,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block10 Word4 Data */
 /** Type of blk10_w4 register
- *  Otp debuger block10 data register4.
+ *  Otp debugger block10 data register4.
  */
 typedef union {
     struct {
@@ -1855,7 +1855,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block10 Word5 Data */
 /** Type of blk10_w5 register
- *  Otp debuger block10 data register5.
+ *  Otp debugger block10 data register5.
  */
 typedef union {
     struct {
@@ -1870,7 +1870,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block10 Word6 Data */
 /** Type of blk10_w6 register
- *  Otp debuger block10 data register6.
+ *  Otp debugger block10 data register6.
  */
 typedef union {
     struct {
@@ -1885,7 +1885,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block10 Word7 Data */
 /** Type of blk10_w7 register
- *  Otp debuger block10 data register7.
+ *  Otp debugger block10 data register7.
  */
 typedef union {
     struct {
@@ -1900,7 +1900,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block10 Word8 Data */
 /** Type of blk10_w8 register
- *  Otp debuger block10 data register8.
+ *  Otp debugger block10 data register8.
  */
 typedef union {
     struct {
@@ -1915,7 +1915,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block10 Word9 Data */
 /** Type of blk10_w9 register
- *  Otp debuger block10 data register9.
+ *  Otp debugger block10 data register9.
  */
 typedef union {
     struct {
@@ -1930,7 +1930,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block10 Word10 Data */
 /** Type of blk10_w10 register
- *  Otp debuger block10 data register10.
+ *  Otp debugger block10 data register10.
  */
 typedef union {
     struct {
@@ -1945,7 +1945,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Clock_en Configuration Register */
 /** Type of clk register
- *  Otp debuger clk_en configuration register.
+ *  Otp debugger clk_en configuration register.
  */
 typedef union {
     struct {
@@ -1959,7 +1959,7 @@ typedef union {
 } otp_debug_clk_reg_t;
 
 
-/** Group: OTP_DEBUG Apb2otp Enable Singal */
+/** Group: OTP_DEBUG Apb2otp Enable Signal */
 /** Type of apb2otp_en register
  *  Otp_debuger apb2otp enable configuration register.
  */
diff --git a/components/soc/esp32c6/include/soc/parl_io_reg.h b/components/soc/esp32c6/register/soc/parl_io_reg.h
similarity index 98%
rename from components/soc/esp32c6/include/soc/parl_io_reg.h
rename to components/soc/esp32c6/register/soc/parl_io_reg.h
index 7377e9788b..191656298c 100644
--- a/components/soc/esp32c6/include/soc/parl_io_reg.h
+++ b/components/soc/esp32c6/register/soc/parl_io_reg.h
@@ -31,7 +31,7 @@ extern "C" {
 #define PARL_IO_RX_START_V  0x00000001U
 #define PARL_IO_RX_START_S  1
 /** PARL_IO_RX_DATA_BYTELEN : R/W; bitpos: [17:2]; default: 0;
- *  Configures rx receieved data byte length.
+ *  Configures rx received data byte length.
  */
 #define PARL_IO_RX_DATA_BYTELEN    0x0000FFFFU
 #define PARL_IO_RX_DATA_BYTELEN_M  (PARL_IO_RX_DATA_BYTELEN_V << PARL_IO_RX_DATA_BYTELEN_S)
@@ -251,7 +251,7 @@ extern "C" {
 #define PARL_IO_TX_READY_S  31
 
 /** PARL_IO_INT_ENA_REG register
- *  Parallel IO interrupt enable singal configuration register.
+ *  Parallel IO interrupt enable signal configuration register.
  */
 #define PARL_IO_INT_ENA_REG (DR_REG_PARL_IO_BASE + 0x14)
 /** PARL_IO_TX_FIFO_REMPTY_INT_ENA : R/W; bitpos: [0]; default: 0;
@@ -277,7 +277,7 @@ extern "C" {
 #define PARL_IO_TX_EOF_INT_ENA_S  2
 
 /** PARL_IO_INT_RAW_REG register
- *  Parallel IO interrupt raw singal status register.
+ *  Parallel IO interrupt raw signal status register.
  */
 #define PARL_IO_INT_RAW_REG (DR_REG_PARL_IO_BASE + 0x18)
 /** PARL_IO_TX_FIFO_REMPTY_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
@@ -303,7 +303,7 @@ extern "C" {
 #define PARL_IO_TX_EOF_INT_RAW_S  2
 
 /** PARL_IO_INT_ST_REG register
- *  Parallel IO interrupt singal status register.
+ *  Parallel IO interrupt signal status register.
  */
 #define PARL_IO_INT_ST_REG (DR_REG_PARL_IO_BASE + 0x1c)
 /** PARL_IO_TX_FIFO_REMPTY_INT_ST : RO; bitpos: [0]; default: 0;
@@ -329,7 +329,7 @@ extern "C" {
 #define PARL_IO_TX_EOF_INT_ST_S  2
 
 /** PARL_IO_INT_CLR_REG register
- *  Parallel IO interrupt  clear singal configuration register.
+ *  Parallel IO interrupt  clear signal configuration register.
  */
 #define PARL_IO_INT_CLR_REG (DR_REG_PARL_IO_BASE + 0x20)
 /** PARL_IO_TX_FIFO_REMPTY_INT_CLR : WT; bitpos: [0]; default: 0;
diff --git a/components/soc/esp32c6/include/soc/parl_io_struct.h b/components/soc/esp32c6/register/soc/parl_io_struct.h
similarity index 97%
rename from components/soc/esp32c6/include/soc/parl_io_struct.h
rename to components/soc/esp32c6/register/soc/parl_io_struct.h
index 816a7de3ef..e0000ebc56 100644
--- a/components/soc/esp32c6/include/soc/parl_io_struct.h
+++ b/components/soc/esp32c6/register/soc/parl_io_struct.h
@@ -26,7 +26,7 @@ typedef union {
          */
         uint32_t rx_start:1;
         /** rx_data_bytelen : R/W; bitpos: [17:2]; default: 0;
-         *  Configures rx receieved data byte length.
+         *  Configures rx received data byte length.
          */
         uint32_t rx_data_bytelen:16;
         /** rx_sw_en : R/W; bitpos: [18]; default: 0;
@@ -213,7 +213,7 @@ typedef union {
 
 /** Group: PARL_IO Interrupt Configuration and Status */
 /** Type of int_ena register
- *  Parallel IO interrupt enable singal configuration register.
+ *  Parallel IO interrupt enable signal configuration register.
  */
 typedef union {
     struct {
@@ -235,7 +235,7 @@ typedef union {
 } parl_io_int_ena_reg_t;
 
 /** Type of int_raw register
- *  Parallel IO interrupt raw singal status register.
+ *  Parallel IO interrupt raw signal status register.
  */
 typedef union {
     struct {
@@ -257,7 +257,7 @@ typedef union {
 } parl_io_int_raw_reg_t;
 
 /** Type of int_st register
- *  Parallel IO interrupt singal status register.
+ *  Parallel IO interrupt signal status register.
  */
 typedef union {
     struct {
@@ -279,7 +279,7 @@ typedef union {
 } parl_io_int_st_reg_t;
 
 /** Type of int_clr register
- *  Parallel IO interrupt  clear singal configuration register.
+ *  Parallel IO interrupt  clear signal configuration register.
  */
 typedef union {
     struct {
diff --git a/components/soc/esp32c6/include/soc/pau_reg.h b/components/soc/esp32c6/register/soc/pau_reg.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/pau_reg.h
rename to components/soc/esp32c6/register/soc/pau_reg.h
diff --git a/components/soc/esp32c6/include/soc/pau_struct.h b/components/soc/esp32c6/register/soc/pau_struct.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/pau_struct.h
rename to components/soc/esp32c6/register/soc/pau_struct.h
diff --git a/components/soc/esp32c6/include/soc/pcnt_reg.h b/components/soc/esp32c6/register/soc/pcnt_reg.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/pcnt_reg.h
rename to components/soc/esp32c6/register/soc/pcnt_reg.h
diff --git a/components/soc/esp32c6/include/soc/pcnt_struct.h b/components/soc/esp32c6/register/soc/pcnt_struct.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/pcnt_struct.h
rename to components/soc/esp32c6/register/soc/pcnt_struct.h
diff --git a/components/soc/esp32c6/include/soc/pcr_reg.h b/components/soc/esp32c6/register/soc/pcr_reg.h
similarity index 98%
rename from components/soc/esp32c6/include/soc/pcr_reg.h
rename to components/soc/esp32c6/register/soc/pcr_reg.h
index 35a77baaab..466b25f020 100644
--- a/components/soc/esp32c6/include/soc/pcr_reg.h
+++ b/components/soc/esp32c6/register/soc/pcr_reg.h
@@ -201,7 +201,7 @@ extern "C" {
 #define PCR_MSPI_CLK_CONF_REG (DR_REG_PCR_BASE + 0x1c)
 /** PCR_MSPI_FAST_LS_DIV_NUM : R/W; bitpos: [7:0]; default: 0;
  *  Set as one within (0,1,2) to generate div1(default)/div2/div4 of low-speed
- *  clock-source to drive clk_mspi_fast. Only avaiable whe the clck-source is a
+ *  clock-source to drive clk_mspi_fast. Only available when the clck-source is a
  *  low-speed clock-source such as XTAL/FOSC.
  */
 #define PCR_MSPI_FAST_LS_DIV_NUM    0x000000FFU
@@ -210,7 +210,7 @@ extern "C" {
 #define PCR_MSPI_FAST_LS_DIV_NUM_S  0
 /** PCR_MSPI_FAST_HS_DIV_NUM : R/W; bitpos: [15:8]; default: 3;
  *  Set as one within (3,4,5) to generate div4(default)/div5/div6 of high-speed
- *  clock-source to drive clk_mspi_fast. Only avaiable whe the clck-source is a
+ *  clock-source to drive clk_mspi_fast. Only available when the clck-source is a
  *  high-speed clock-source such as SPLL.
  */
 #define PCR_MSPI_FAST_HS_DIV_NUM    0x000000FFU
@@ -1163,7 +1163,7 @@ extern "C" {
 #define PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_V  0x0000000FU
 #define PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_S  0
 /** PCR_PVT_MONITOR_FUNC_CLK_SEL : R/W; bitpos: [20]; default: 0;
- *  set this field to select clock-source. 0: XTAL, 1(default): 160MHz drived by SPLL
+ *  set this field to select clock-source. 0: XTAL, 1(default): 160MHz driven by SPLL
  *  divided by 3.
  */
 #define PCR_PVT_MONITOR_FUNC_CLK_SEL    (BIT(20))
@@ -1666,8 +1666,8 @@ extern "C" {
  */
 #define PCR_CPU_FREQ_CONF_REG (DR_REG_PCR_BASE + 0x118)
 /** PCR_CPU_LS_DIV_NUM : R/W; bitpos: [7:0]; default: 0;
- *  Set as one within (0,1,3) to generate clk_cpu drived by clk_hproot. The clk_cpu is
- *  div1(default)/div2/div4 of clk_hproot. This field is only avaliable for low-speed
+ *  Set as one within (0,1,3) to generate clk_cpu driven by clk_hproot. The clk_cpu is
+ *  div1(default)/div2/div4 of clk_hproot. This field is only available for low-speed
  *  clock-source such as XTAL/FOSC, and should be used together with PCR_AHB_LS_DIV_NUM.
  */
 #define PCR_CPU_LS_DIV_NUM    0x000000FFU
@@ -1675,8 +1675,8 @@ extern "C" {
 #define PCR_CPU_LS_DIV_NUM_V  0x000000FFU
 #define PCR_CPU_LS_DIV_NUM_S  0
 /** PCR_CPU_HS_DIV_NUM : R/W; bitpos: [15:8]; default: 0;
- *  Set as one within (0,1,3) to generate clk_cpu drived by clk_hproot. The clk_cpu is
- *  div1(default)/div2/div4 of clk_hproot. This field is only avaliable for high-speed
+ *  Set as one within (0,1,3) to generate clk_cpu driven by clk_hproot. The clk_cpu is
+ *  div1(default)/div2/div4 of clk_hproot. This field is only available for high-speed
  *  clock-source such as SPLL, and should be used together with PCR_AHB_HS_DIV_NUM.
  */
 #define PCR_CPU_HS_DIV_NUM    0x000000FFU
@@ -1685,7 +1685,7 @@ extern "C" {
 #define PCR_CPU_HS_DIV_NUM_S  8
 /** PCR_CPU_HS_120M_FORCE : R/W; bitpos: [16]; default: 0;
  *  Given that PCR_CPU_HS_DIV_NUM is 0, set this field as 1 to force clk_cpu at 120MHz.
- *  Only avaliable when PCR_CPU_HS_DIV_NUM is 0 and clk_cpu is driven by SPLL.
+ *  Only available when PCR_CPU_HS_DIV_NUM is 0 and clk_cpu is driven by SPLL.
  */
 #define PCR_CPU_HS_120M_FORCE    (BIT(16))
 #define PCR_CPU_HS_120M_FORCE_M  (PCR_CPU_HS_120M_FORCE_V << PCR_CPU_HS_120M_FORCE_S)
@@ -1697,8 +1697,8 @@ extern "C" {
  */
 #define PCR_AHB_FREQ_CONF_REG (DR_REG_PCR_BASE + 0x11c)
 /** PCR_AHB_LS_DIV_NUM : R/W; bitpos: [7:0]; default: 0;
- *  Set as one within (0,1,3,7) to generate clk_ahb drived by clk_hproot. The clk_ahb
- *  is div1(default)/div2/div4/div8 of clk_hproot. This field is only avaliable for
+ *  Set as one within (0,1,3,7) to generate clk_ahb driven by clk_hproot. The clk_ahb
+ *  is div1(default)/div2/div4/div8 of clk_hproot. This field is only available for
  *  low-speed clock-source such as XTAL/FOSC, and should be used together with
  *  PCR_CPU_LS_DIV_NUM.
  */
@@ -1707,8 +1707,8 @@ extern "C" {
 #define PCR_AHB_LS_DIV_NUM_V  0x000000FFU
 #define PCR_AHB_LS_DIV_NUM_S  0
 /** PCR_AHB_HS_DIV_NUM : R/W; bitpos: [15:8]; default: 3;
- *  Set as one within (3,7,15) to generate clk_ahb drived by clk_hproot. The clk_ahb is
- *  div4(default)/div8/div16 of clk_hproot. This field is only avaliable for high-speed
+ *  Set as one within (3,7,15) to generate clk_ahb driven by clk_hproot. The clk_ahb is
+ *  div4(default)/div8/div16 of clk_hproot. This field is only available for high-speed
  *  clock-source such as SPLL, and should be used together with PCR_CPU_HS_DIV_NUM.
  */
 #define PCR_AHB_HS_DIV_NUM    0x000000FFU
@@ -1734,7 +1734,7 @@ extern "C" {
 #define PCR_APB_DECREASE_DIV_NUM_V  0x000000FFU
 #define PCR_APB_DECREASE_DIV_NUM_S  0
 /** PCR_APB_DIV_NUM : R/W; bitpos: [15:8]; default: 0;
- *  Set as one within (0,1,3) to generate clk_apb drived by clk_ahb. The clk_apb is
+ *  Set as one within (0,1,3) to generate clk_apb driven by clk_ahb. The clk_apb is
  *  div1(default)/div2/div4 of clk_ahb.
  */
 #define PCR_APB_DIV_NUM    0x000000FFU
@@ -1766,56 +1766,56 @@ extern "C" {
  */
 #define PCR_PLL_DIV_CLK_EN_REG (DR_REG_PCR_BASE + 0x128)
 /** PCR_PLL_240M_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  This field is used to open 240 MHz clock (div2 of SPLL) drived from SPLL. 0: close,
- *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
+ *  This field is used to open 240 MHz clock (div2 of SPLL) driven from SPLL. 0: close,
+ *  1: open(default). Only available when high-speed clock-source SPLL is active.
  */
 #define PCR_PLL_240M_CLK_EN    (BIT(0))
 #define PCR_PLL_240M_CLK_EN_M  (PCR_PLL_240M_CLK_EN_V << PCR_PLL_240M_CLK_EN_S)
 #define PCR_PLL_240M_CLK_EN_V  0x00000001U
 #define PCR_PLL_240M_CLK_EN_S  0
 /** PCR_PLL_160M_CLK_EN : R/W; bitpos: [1]; default: 1;
- *  This field is used to open 160 MHz clock (div3 of SPLL) drived from SPLL. 0: close,
- *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
+ *  This field is used to open 160 MHz clock (div3 of SPLL) driven from SPLL. 0: close,
+ *  1: open(default). Only available when high-speed clock-source SPLL is active.
  */
 #define PCR_PLL_160M_CLK_EN    (BIT(1))
 #define PCR_PLL_160M_CLK_EN_M  (PCR_PLL_160M_CLK_EN_V << PCR_PLL_160M_CLK_EN_S)
 #define PCR_PLL_160M_CLK_EN_V  0x00000001U
 #define PCR_PLL_160M_CLK_EN_S  1
 /** PCR_PLL_120M_CLK_EN : R/W; bitpos: [2]; default: 1;
- *  This field is used to open 120 MHz clock (div4 of SPLL) drived from SPLL. 0: close,
- *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
+ *  This field is used to open 120 MHz clock (div4 of SPLL) driven from SPLL. 0: close,
+ *  1: open(default). Only available when high-speed clock-source SPLL is active.
  */
 #define PCR_PLL_120M_CLK_EN    (BIT(2))
 #define PCR_PLL_120M_CLK_EN_M  (PCR_PLL_120M_CLK_EN_V << PCR_PLL_120M_CLK_EN_S)
 #define PCR_PLL_120M_CLK_EN_V  0x00000001U
 #define PCR_PLL_120M_CLK_EN_S  2
 /** PCR_PLL_80M_CLK_EN : R/W; bitpos: [3]; default: 1;
- *  This field is used to open 80 MHz clock (div6  of SPLL) drived from SPLL. 0: close,
- *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
+ *  This field is used to open 80 MHz clock (div6  of SPLL) driven from SPLL. 0: close,
+ *  1: open(default). Only available when high-speed clock-source SPLL is active.
  */
 #define PCR_PLL_80M_CLK_EN    (BIT(3))
 #define PCR_PLL_80M_CLK_EN_M  (PCR_PLL_80M_CLK_EN_V << PCR_PLL_80M_CLK_EN_S)
 #define PCR_PLL_80M_CLK_EN_V  0x00000001U
 #define PCR_PLL_80M_CLK_EN_S  3
 /** PCR_PLL_48M_CLK_EN : R/W; bitpos: [4]; default: 1;
- *  This field is used to open 48 MHz clock (div10 of SPLL) drived from SPLL. 0: close,
- *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
+ *  This field is used to open 48 MHz clock (div10 of SPLL) driven from SPLL. 0: close,
+ *  1: open(default). Only available when high-speed clock-source SPLL is active.
  */
 #define PCR_PLL_48M_CLK_EN    (BIT(4))
 #define PCR_PLL_48M_CLK_EN_M  (PCR_PLL_48M_CLK_EN_V << PCR_PLL_48M_CLK_EN_S)
 #define PCR_PLL_48M_CLK_EN_V  0x00000001U
 #define PCR_PLL_48M_CLK_EN_S  4
 /** PCR_PLL_40M_CLK_EN : R/W; bitpos: [5]; default: 1;
- *  This field is used to open 40 MHz clock (div12 of SPLL) drived from SPLL. 0: close,
- *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
+ *  This field is used to open 40 MHz clock (div12 of SPLL) driven from SPLL. 0: close,
+ *  1: open(default). Only available when high-speed clock-source SPLL is active.
  */
 #define PCR_PLL_40M_CLK_EN    (BIT(5))
 #define PCR_PLL_40M_CLK_EN_M  (PCR_PLL_40M_CLK_EN_V << PCR_PLL_40M_CLK_EN_S)
 #define PCR_PLL_40M_CLK_EN_V  0x00000001U
 #define PCR_PLL_40M_CLK_EN_S  5
 /** PCR_PLL_20M_CLK_EN : R/W; bitpos: [6]; default: 1;
- *  This field is used to open 20 MHz clock (div24 of SPLL) drived from SPLL. 0: close,
- *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
+ *  This field is used to open 20 MHz clock (div24 of SPLL) driven from SPLL. 0: close,
+ *  1: open(default). Only available when high-speed clock-source SPLL is active.
  */
 #define PCR_PLL_20M_CLK_EN    (BIT(6))
 #define PCR_PLL_20M_CLK_EN_M  (PCR_PLL_20M_CLK_EN_V << PCR_PLL_20M_CLK_EN_S)
diff --git a/components/soc/esp32c6/include/soc/pcr_struct.h b/components/soc/esp32c6/register/soc/pcr_struct.h
similarity index 97%
rename from components/soc/esp32c6/include/soc/pcr_struct.h
rename to components/soc/esp32c6/register/soc/pcr_struct.h
index f31e632d86..ee74db8ff1 100644
--- a/components/soc/esp32c6/include/soc/pcr_struct.h
+++ b/components/soc/esp32c6/register/soc/pcr_struct.h
@@ -176,13 +176,13 @@ typedef union {
     struct {
         /** mspi_fast_ls_div_num : R/W; bitpos: [7:0]; default: 0;
          *  Set as one within (0,1,2) to generate div1(default)/div2/div4 of low-speed
-         *  clock-source to drive clk_mspi_fast. Only avaiable whe the clck-source is a
+         *  clock-source to drive clk_mspi_fast. Only available when the clck-source is a
          *  low-speed clock-source such as XTAL/FOSC.
          */
         uint32_t mspi_fast_ls_div_num:8;
         /** mspi_fast_hs_div_num : R/W; bitpos: [15:8]; default: 3;
          *  Set as one within (3,4,5) to generate div4(default)/div5/div6 of high-speed
-         *  clock-source to drive clk_mspi_fast. Only avaiable whe the clck-source is a
+         *  clock-source to drive clk_mspi_fast. Only available when the clck-source is a
          *  high-speed clock-source such as SPLL.
          */
         uint32_t mspi_fast_hs_div_num:8;
@@ -1033,7 +1033,7 @@ typedef union {
         uint32_t pvt_monitor_func_clk_div_num:4;
         uint32_t reserved_4:16;
         /** pvt_monitor_func_clk_sel : R/W; bitpos: [20]; default: 0;
-         *  set this field to select clock-source. 0: XTAL, 1(default): 160MHz drived by SPLL
+         *  set this field to select clock-source. 0: XTAL, 1(default): 160MHz driven by SPLL
          *  divided by 3.
          */
         uint32_t pvt_monitor_func_clk_sel:1;
@@ -1499,20 +1499,20 @@ typedef union {
 typedef union {
     struct {
         /** cpu_ls_div_num : R/W; bitpos: [7:0]; default: 0;
-         *  Set as one within (0,1,3) to generate clk_cpu drived by clk_hproot. The clk_cpu is
-         *  div1(default)/div2/div4 of clk_hproot. This field is only avaliable for low-speed
+         *  Set as one within (0,1,3) to generate clk_cpu driven by clk_hproot. The clk_cpu is
+         *  div1(default)/div2/div4 of clk_hproot. This field is only available for low-speed
          *  clock-source such as XTAL/FOSC, and should be used together with PCR_AHB_LS_DIV_NUM.
          */
         uint32_t cpu_ls_div_num:8;
         /** cpu_hs_div_num : R/W; bitpos: [15:8]; default: 0;
-         *  Set as one within (0,1,3) to generate clk_cpu drived by clk_hproot. The clk_cpu is
-         *  div1(default)/div2/div4 of clk_hproot. This field is only avaliable for high-speed
+         *  Set as one within (0,1,3) to generate clk_cpu driven by clk_hproot. The clk_cpu is
+         *  div1(default)/div2/div4 of clk_hproot. This field is only available for high-speed
          *  clock-source such as SPLL, and should be used together with PCR_AHB_HS_DIV_NUM.
          */
         uint32_t cpu_hs_div_num:8;
         /** cpu_hs_120m_force : R/W; bitpos: [16]; default: 0;
          *  Given that PCR_CPU_HS_DIV_NUM is 0, set this field as 1 to force clk_cpu at 120MHz.
-         *  Only avaliable when PCR_CPU_HS_DIV_NUM is 0 and clk_cpu is driven by SPLL.
+         *  Only available when PCR_CPU_HS_DIV_NUM is 0 and clk_cpu is driven by SPLL.
          */
         uint32_t cpu_hs_120m_force:1;
         uint32_t reserved_17:15;
@@ -1526,15 +1526,15 @@ typedef union {
 typedef union {
     struct {
         /** ahb_ls_div_num : R/W; bitpos: [7:0]; default: 0;
-         *  Set as one within (0,1,3,7) to generate clk_ahb drived by clk_hproot. The clk_ahb
-         *  is div1(default)/div2/div4/div8 of clk_hproot. This field is only avaliable for
+         *  Set as one within (0,1,3,7) to generate clk_ahb driven by clk_hproot. The clk_ahb
+         *  is div1(default)/div2/div4/div8 of clk_hproot. This field is only available for
          *  low-speed clock-source such as XTAL/FOSC, and should be used together with
          *  PCR_CPU_LS_DIV_NUM.
          */
         uint32_t ahb_ls_div_num:8;
         /** ahb_hs_div_num : R/W; bitpos: [15:8]; default: 3;
-         *  Set as one within (3,7,15) to generate clk_ahb drived by clk_hproot. The clk_ahb is
-         *  div4(default)/div8/div16 of clk_hproot. This field is only avaliable for high-speed
+         *  Set as one within (3,7,15) to generate clk_ahb driven by clk_hproot. The clk_ahb is
+         *  div4(default)/div8/div16 of clk_hproot. This field is only available for high-speed
          *  clock-source such as SPLL, and should be used together with PCR_CPU_HS_DIV_NUM.
          */
         uint32_t ahb_hs_div_num:8;
@@ -1559,7 +1559,7 @@ typedef union {
          */
         uint32_t apb_decrease_div_num:8;
         /** apb_div_num : R/W; bitpos: [15:8]; default: 0;
-         *  Set as one within (0,1,3) to generate clk_apb drived by clk_ahb. The clk_apb is
+         *  Set as one within (0,1,3) to generate clk_apb driven by clk_ahb. The clk_apb is
          *  div1(default)/div2/div4 of clk_ahb.
          */
         uint32_t apb_div_num:8;
@@ -1574,38 +1574,38 @@ typedef union {
 typedef union {
     struct {
         /** pll_240m_clk_en : R/W; bitpos: [0]; default: 1;
-         *  This field is used to open 240 MHz clock (div2 of SPLL) drived from SPLL. 0: close,
-         *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
+         *  This field is used to open 240 MHz clock (div2 of SPLL) driven from SPLL. 0: close,
+         *  1: open(default). Only available when high-speed clock-source SPLL is active.
          */
         uint32_t pll_240m_clk_en:1;
         /** pll_160m_clk_en : R/W; bitpos: [1]; default: 1;
-         *  This field is used to open 160 MHz clock (div3 of SPLL) drived from SPLL. 0: close,
-         *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
+         *  This field is used to open 160 MHz clock (div3 of SPLL) driven from SPLL. 0: close,
+         *  1: open(default). Only available when high-speed clock-source SPLL is active.
          */
         uint32_t pll_160m_clk_en:1;
         /** pll_120m_clk_en : R/W; bitpos: [2]; default: 1;
-         *  This field is used to open 120 MHz clock (div4 of SPLL) drived from SPLL. 0: close,
-         *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
+         *  This field is used to open 120 MHz clock (div4 of SPLL) driven from SPLL. 0: close,
+         *  1: open(default). Only available when high-speed clock-source SPLL is active.
          */
         uint32_t pll_120m_clk_en:1;
         /** pll_80m_clk_en : R/W; bitpos: [3]; default: 1;
-         *  This field is used to open 80 MHz clock (div6  of SPLL) drived from SPLL. 0: close,
-         *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
+         *  This field is used to open 80 MHz clock (div6  of SPLL) driven from SPLL. 0: close,
+         *  1: open(default). Only available when high-speed clock-source SPLL is active.
          */
         uint32_t pll_80m_clk_en:1;
         /** pll_48m_clk_en : R/W; bitpos: [4]; default: 1;
-         *  This field is used to open 48 MHz clock (div10 of SPLL) drived from SPLL. 0: close,
-         *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
+         *  This field is used to open 48 MHz clock (div10 of SPLL) driven from SPLL. 0: close,
+         *  1: open(default). Only available when high-speed clock-source SPLL is active.
          */
         uint32_t pll_48m_clk_en:1;
         /** pll_40m_clk_en : R/W; bitpos: [5]; default: 1;
-         *  This field is used to open 40 MHz clock (div12 of SPLL) drived from SPLL. 0: close,
-         *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
+         *  This field is used to open 40 MHz clock (div12 of SPLL) driven from SPLL. 0: close,
+         *  1: open(default). Only available when high-speed clock-source SPLL is active.
          */
         uint32_t pll_40m_clk_en:1;
         /** pll_20m_clk_en : R/W; bitpos: [6]; default: 1;
-         *  This field is used to open 20 MHz clock (div24 of SPLL) drived from SPLL. 0: close,
-         *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
+         *  This field is used to open 20 MHz clock (div24 of SPLL) driven from SPLL. 0: close,
+         *  1: open(default). Only available when high-speed clock-source SPLL is active.
          */
         uint32_t pll_20m_clk_en:1;
         uint32_t reserved_7:25;
diff --git a/components/soc/esp32c6/include/soc/plic_reg.h b/components/soc/esp32c6/register/soc/plic_reg.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/plic_reg.h
rename to components/soc/esp32c6/register/soc/plic_reg.h
diff --git a/components/soc/esp32c6/include/soc/pmu_reg.h b/components/soc/esp32c6/register/soc/pmu_reg.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/pmu_reg.h
rename to components/soc/esp32c6/register/soc/pmu_reg.h
diff --git a/components/soc/esp32c6/include/soc/pmu_struct.h b/components/soc/esp32c6/register/soc/pmu_struct.h
similarity index 99%
rename from components/soc/esp32c6/include/soc/pmu_struct.h
rename to components/soc/esp32c6/register/soc/pmu_struct.h
index 5d06311895..db545cfbc5 100644
--- a/components/soc/esp32c6/include/soc/pmu_struct.h
+++ b/components/soc/esp32c6/register/soc/pmu_struct.h
@@ -11,7 +11,7 @@
 extern "C" {
 #endif
 
-#include "soc.h"
+#include "soc/soc.h"
 #include "soc/pmu_reg.h"
 
 typedef union {
diff --git a/components/soc/esp32c6/include/soc/reg_base.h b/components/soc/esp32c6/register/soc/reg_base.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/reg_base.h
rename to components/soc/esp32c6/register/soc/reg_base.h
diff --git a/components/soc/esp32c6/include/soc/rmt_reg.h b/components/soc/esp32c6/register/soc/rmt_reg.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/rmt_reg.h
rename to components/soc/esp32c6/register/soc/rmt_reg.h
diff --git a/components/soc/esp32c6/include/soc/rmt_struct.h b/components/soc/esp32c6/register/soc/rmt_struct.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/rmt_struct.h
rename to components/soc/esp32c6/register/soc/rmt_struct.h
diff --git a/components/soc/esp32c6/include/soc/rsa_reg.h b/components/soc/esp32c6/register/soc/rsa_reg.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/rsa_reg.h
rename to components/soc/esp32c6/register/soc/rsa_reg.h
diff --git a/components/soc/esp32c6/include/soc/rsa_struct.h b/components/soc/esp32c6/register/soc/rsa_struct.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/rsa_struct.h
rename to components/soc/esp32c6/register/soc/rsa_struct.h
diff --git a/components/soc/esp32c6/include/soc/sha_reg.h b/components/soc/esp32c6/register/soc/sha_reg.h
similarity index 98%
rename from components/soc/esp32c6/include/soc/sha_reg.h
rename to components/soc/esp32c6/register/soc/sha_reg.h
index 265f510472..46955176e5 100644
--- a/components/soc/esp32c6/include/soc/sha_reg.h
+++ b/components/soc/esp32c6/register/soc/sha_reg.h
@@ -156,7 +156,7 @@ extern "C" {
 #define SHA_DATE_S  0
 
 /** SHA_H_MEM register
- *  Sha H memory which contains intermediate hash or finial hash.
+ *  Sha H memory which contains intermediate hash or final hash.
  */
 #define SHA_H_MEM (DR_REG_SHA_BASE + 0x40)
 #define SHA_H_MEM_SIZE_BYTES 64
diff --git a/components/soc/esp32c6/include/soc/sha_struct.h b/components/soc/esp32c6/register/soc/sha_struct.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/sha_struct.h
rename to components/soc/esp32c6/register/soc/sha_struct.h
diff --git a/components/soc/esp32c6/include/soc/slc_reg.h b/components/soc/esp32c6/register/soc/slc_reg.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/slc_reg.h
rename to components/soc/esp32c6/register/soc/slc_reg.h
diff --git a/components/soc/esp32c6/include/soc/slc_struct.h b/components/soc/esp32c6/register/soc/slc_struct.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/slc_struct.h
rename to components/soc/esp32c6/register/soc/slc_struct.h
diff --git a/components/soc/esp32c6/include/soc/soc_etm_reg.h b/components/soc/esp32c6/register/soc/soc_etm_reg.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/soc_etm_reg.h
rename to components/soc/esp32c6/register/soc/soc_etm_reg.h
diff --git a/components/soc/esp32c6/include/soc/soc_etm_struct.h b/components/soc/esp32c6/register/soc/soc_etm_struct.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/soc_etm_struct.h
rename to components/soc/esp32c6/register/soc/soc_etm_struct.h
diff --git a/components/soc/esp32c6/include/soc/spi_mem_reg.h b/components/soc/esp32c6/register/soc/spi_mem_reg.h
similarity index 99%
rename from components/soc/esp32c6/include/soc/spi_mem_reg.h
rename to components/soc/esp32c6/register/soc/spi_mem_reg.h
index 81a136b870..56ada6dc46 100644
--- a/components/soc/esp32c6/include/soc/spi_mem_reg.h
+++ b/components/soc/esp32c6/register/soc/spi_mem_reg.h
@@ -98,8 +98,8 @@ he bit will be cleared once the operation done.1: enable 0: disable..*/
 #define SPI_MEM_FLASH_DP_S  21
 /* SPI_MEM_FLASH_RES : R/W/SC ;bitpos:[20] ;default: 1'b0 ; */
 /*description: This bit combined with reg_resandres bit releases Flash from the power-down stat
-e or high performance mode and obtains the devices ID. The bit will be cleared o
-nce the operation done.1: enable 0: disable..*/
+e or high performance mode and obtains the devices ID. The bit will be cleared once
+ the operation done.1: enable 0: disable..*/
 #define SPI_MEM_FLASH_RES    (BIT(20))
 #define SPI_MEM_FLASH_RES_M  (BIT(20))
 #define SPI_MEM_FLASH_RES_V  0x1
@@ -128,9 +128,9 @@ peration done.1: enable 0: disable..*/
 #define SPI_MEM_FLASH_PE_V  0x1
 #define SPI_MEM_FLASH_PE_S  17
 /* SPI_MEM_SLV_ST : RO ;bitpos:[7:4] ;default: 4'b0 ; */
-/*description: The current status of SPI0 slave FSM: mspi_st. 0: idle state, 1: preparation sta
-te, 2: send command state, 3: send address state, 4: wait state, 5: read data st
-ate, 6:write data state, 7: done state, 8: read data end state..*/
+/*description: The current status of SPI0 slave FSM: mspi_st. 0: idle state, 1: preparation state,
+2: send command state, 3: send address state, 4: wait state, 5: read data state
+, 6:write data state, 7: done state, 8: read data end state..*/
 #define SPI_MEM_SLV_ST    0x0000000F
 #define SPI_MEM_SLV_ST_M  ((SPI_MEM_SLV_ST_V)<<(SPI_MEM_SLV_ST_S))
 #define SPI_MEM_SLV_ST_V  0xF
@@ -162,7 +162,7 @@ lways 1. 0: Others..*/
 #define SPI_MEM_DATA_IE_ALWAYS_ON_V  0x1
 #define SPI_MEM_DATA_IE_ALWAYS_ON_S  31
 /* SPI_MEM_DQS_IE_ALWAYS_ON : HRO ;bitpos:[30] ;default: 1'b0 ; */
-/*description: When accesses to flash, 1: the IE signals of pads connected to SPI_DQS are alway
+/*description: When accesses to flash, 1: the IE signals of pads connected to SPI_DQS are always
 s 1. 0: Others..*/
 #define SPI_MEM_DQS_IE_ALWAYS_ON    (BIT(30))
 #define SPI_MEM_DQS_IE_ALWAYS_ON_M  (BIT(30))
@@ -234,14 +234,14 @@ UT and SPI_MEM_FREAD_DOUT. 1: enable 0: disable..*/
 #define SPI_MEM_FASTRD_MODE_V  0x1
 #define SPI_MEM_FASTRD_MODE_S  13
 /* SPI_MEM_TX_CRC_EN : HRO ;bitpos:[11] ;default: 1'b0 ; */
-/*description: For SPI1,  enable crc32 when writing encrypted data to flash. 1: enable 0:disabl
+/*description: For SPI1,  enable crc32 when writing encrypted data to flash. 1: enable 0:disable
 e.*/
 #define SPI_MEM_TX_CRC_EN    (BIT(11))
 #define SPI_MEM_TX_CRC_EN_M  (BIT(11))
 #define SPI_MEM_TX_CRC_EN_V  0x1
 #define SPI_MEM_TX_CRC_EN_S  11
 /* SPI_MEM_FCS_CRC_EN : HRO ;bitpos:[10] ;default: 1'b0 ; */
-/*description: For SPI1,  initialize crc32 module before writing encrypted data to flash. Activ
+/*description: For SPI1,  initialize crc32 module before writing encrypted data to flash. Active
 e low..*/
 #define SPI_MEM_FCS_CRC_EN    (BIT(10))
 #define SPI_MEM_FCS_CRC_EN_M  (BIT(10))
@@ -397,7 +397,7 @@ y the real AXI read data back. 0: When ARSIZE 0~1, MSPI reply SLV_ERR..*/
 /* SPI_MEM_CLK_MODE : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
 /*description: SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delaye
 d one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inacti
-ve 3: SPI clock is alwasy on..*/
+ve 3: SPI clock is always on..*/
 #define SPI_MEM_CLK_MODE    0x00000003
 #define SPI_MEM_CLK_MODE_M  ((SPI_MEM_CLK_MODE_V)<<(SPI_MEM_CLK_MODE_S))
 #define SPI_MEM_CLK_MODE_V  0x3
@@ -427,8 +427,8 @@ whether there is an ECC region or not..*/
 #define SPI_MEM_SPLIT_TRANS_EN_V  0x1
 #define SPI_MEM_SPLIT_TRANS_EN_S  24
 /* SPI_MEM_ECC_16TO18_BYTE_EN : HRO ;bitpos:[14] ;default: 1'b0 ; */
-/*description: Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode whe
-n accesses flash..*/
+/*description: Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when
+ accesses flash..*/
 #define SPI_MEM_ECC_16TO18_BYTE_EN    (BIT(14))
 #define SPI_MEM_ECC_16TO18_BYTE_EN_M  (BIT(14))
 #define SPI_MEM_ECC_16TO18_BYTE_EN_V  0x1
@@ -808,8 +808,8 @@ he register value shall be (bit_num-1)..*/
 #define SPI_MEM_SRAM_RDUMMY_CYCLELEN_V  0x3F
 #define SPI_MEM_SRAM_RDUMMY_CYCLELEN_S  6
 /* SPI_MEM_CACHE_SRAM_USR_RCMD : HRO ;bitpos:[5] ;default: 1'b1 ; */
-/*description: For SPI0, In the external RAM mode cache read external RAM for user define comma
-nd..*/
+/*description: For SPI0, In the external RAM mode cache read external RAM for user define command
+..*/
 #define SPI_MEM_CACHE_SRAM_USR_RCMD    (BIT(5))
 #define SPI_MEM_CACHE_SRAM_USR_RCMD_M  (BIT(5))
 #define SPI_MEM_CACHE_SRAM_USR_RCMD_V  0x1
@@ -1016,7 +1016,7 @@ e for sram..*/
 
 #define SPI_MEM_SRAM_CLK_REG(i)          (REG_SPI_MEM_BASE(i) + 0x50)
 /* SPI_MEM_SCLK_EQU_SYSCLK : HRO ;bitpos:[31] ;default: 1'b0 ; */
-/*description: For SPI0 external RAM  interface, 1: spi_mem_clk is eqaul to system 0: spi_mem_c
+/*description: For SPI0 external RAM  interface, 1: spi_mem_clk is equal to system 0: spi_mem_c
 lk is divided from system clock..*/
 #define SPI_MEM_SCLK_EQU_SYSCLK    (BIT(31))
 #define SPI_MEM_SCLK_EQU_SYSCLK_M  (BIT(31))
@@ -1274,7 +1274,7 @@ out, status_in[15:0] is valid when two bytes of data are read out), SUS/SUS1/SUS
 #define SPI_MEM_FLASH_PES_EN_S  5
 /* SPI_MEM_PES_PER_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */
 /*description: Set this bit to enable PES end triggers PER transfer option. If this bit is 0, a
-pplication should send PER after PES is done..*/
+application should send PER after PES is done..*/
 #define SPI_MEM_PES_PER_EN    (BIT(4))
 #define SPI_MEM_PES_PER_EN_M  (BIT(4))
 #define SPI_MEM_PES_PER_EN_V  0x1
@@ -1296,8 +1296,8 @@ resume command is sent..*/
 #define SPI_MEM_FLASH_PER_WAIT_EN_V  0x1
 #define SPI_MEM_FLASH_PER_WAIT_EN_S  2
 /* SPI_MEM_FLASH_PES : R/W/SC ;bitpos:[1] ;default: 1'b0 ; */
-/*description: program erase suspend bit, program erase suspend operation will be triggered whe
-n the bit is set. The bit will be cleared once the operation done.1: enable 0: d
+/*description: program erase suspend bit, program erase suspend operation will be triggered when
+the bit is set. The bit will be cleared once the operation done.1: enable 0: d
 isable..*/
 #define SPI_MEM_FLASH_PES    (BIT(1))
 #define SPI_MEM_FLASH_PES_M  (BIT(1))
@@ -1541,7 +1541,7 @@ mmand is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles
 #define SPI_MEM_INT_RAW_REG(i)          (REG_SPI_MEM_BASE(i) + 0xC8)
 /* SPI_MEM_BROWN_OUT_INT_RAW : R/WTC/SS ;bitpos:[10] ;default: 1'b0 ; */
 /*description: The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that
-chip is loosing power and RTC module sends out brown out close flash request to
+chip is losing power and RTC module sends out brown out close flash request to
 SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered
  and MSPI returns to idle state. 0: Others..*/
 #define SPI_MEM_BROWN_OUT_INT_RAW    (BIT(10))
@@ -1584,9 +1584,9 @@ et and  SPI_SMEM_ECC_ERR_INT_EN is cleared, this bit is triggered when the error
 his bit is triggered when the error times of SPI0/1 ECC read external RAM are eq
 ual or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and  SP
 I_SMEM_ECC_ERR_INT_EN are set, this bit is triggered when the total error times
-of SPI0/1 ECC read external RAM and flash are equal or bigger than SPI_MEM_ECC_E
-RR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and  SPI_SMEM_ECC_ERR_INT_EN are cleare
-d, this bit will not be triggered..*/
+of SPI0/1 ECC read external RAM and flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM.
+When SPI_FMEM_ECC_ERR_INT_EN and  SPI_SMEM_ECC_ERR_INT_EN are cleared,
+this bit will not be triggered..*/
 #define SPI_MEM_ECC_ERR_INT_RAW    (BIT(5))
 #define SPI_MEM_ECC_ERR_INT_RAW_M  (BIT(5))
 #define SPI_MEM_ECC_ERR_INT_RAW_V  0x1
@@ -2376,8 +2376,8 @@ and RDATA_AFIFO are empty and spi0_mst_st is IDLE..*/
 #define SPI_MEM_ALL_FIFO_EMPTY_V  0x1
 #define SPI_MEM_ALL_FIFO_EMPTY_S  26
 /* SPI_MEM_AXI_ERR_ADDR : R/SS/WTC ;bitpos:[25:0] ;default: 26'h0 ; */
-/*description: This bits show the first AXI write/read invalid error or AXI write flash error a
-ddress. It is cleared by when SPI_MEM_AXI_WADDR_ERR_INT_CLR, SPI_MEM_AXI_WR_FLAS
+/*description: This bits show the first AXI write/read invalid error or AXI write flash error
+address. It is cleared by when SPI_MEM_AXI_WADDR_ERR_INT_CLR, SPI_MEM_AXI_WR_FLAS
 H_ERR_IN_CLR or SPI_MEM_AXI_RADDR_ERR_IN_CLR bit is set..*/
 #define SPI_MEM_AXI_ERR_ADDR    0x03FFFFFF
 #define SPI_MEM_AXI_ERR_ADDR_M  ((SPI_MEM_AXI_ERR_ADDR_V)<<(SPI_MEM_AXI_ERR_ADDR_S))
@@ -2684,7 +2684,7 @@ ations..*/
 #define SPI_MEM_SMEM_TIMING_CALI_V  0x1
 #define SPI_MEM_SMEM_TIMING_CALI_S  1
 /* SPI_MEM_SMEM_TIMING_CLK_ENA : HRO ;bitpos:[0] ;default: 1'b1 ; */
-/*description: For sram, the bit is used to enable timing adjust clock for all reading operatio
+/*description: For sram, the bit is used to enable timing adjust clock for all reading operation
 ns..*/
 #define SPI_MEM_SMEM_TIMING_CLK_ENA    (BIT(0))
 #define SPI_MEM_SMEM_TIMING_CLK_ENA_M  (BIT(0))
@@ -2942,8 +2942,8 @@ SPI core clock cycles..*/
 #define SPI_MEM_SMEM_CS_HOLD_DELAY_V  0x3F
 #define SPI_MEM_SMEM_CS_HOLD_DELAY_S  25
 /* SPI_MEM_SMEM_ECC_16TO18_BYTE_EN : HRO ;bitpos:[16] ;default: 1'b0 ; */
-/*description: Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode whe
-n accesses external RAM..*/
+/*description: Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when
+accesses external RAM..*/
 #define SPI_MEM_SMEM_ECC_16TO18_BYTE_EN    (BIT(16))
 #define SPI_MEM_SMEM_ECC_16TO18_BYTE_EN_M  (BIT(16))
 #define SPI_MEM_SMEM_ECC_16TO18_BYTE_EN_V  0x1
diff --git a/components/soc/esp32c6/include/soc/spi_mem_struct.h b/components/soc/esp32c6/register/soc/spi_mem_struct.h
similarity index 99%
rename from components/soc/esp32c6/include/soc/spi_mem_struct.h
rename to components/soc/esp32c6/register/soc/spi_mem_struct.h
index 9e2f7c1d3b..74588ee027 100644
--- a/components/soc/esp32c6/include/soc/spi_mem_struct.h
+++ b/components/soc/esp32c6/register/soc/spi_mem_struct.h
@@ -69,7 +69,7 @@ typedef volatile struct spi_mem_dev_s {
     } ctrl;
     union {
         struct {
-            uint32_t clk_mode                      :    2;  /*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on.*/
+            uint32_t clk_mode                      :    2;  /*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is always on.*/
             uint32_t cs_hold_dly_res               :    10;  /*After RES/DP/HPM command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 512) SPI_CLK cycles.*/
             uint32_t reserved2                     :    9;  /*reserved*/
             uint32_t reg_ar_size0_1_support_en     :    1;  /*1: MSPI supports ARSIZE 0~3. When ARSIZE =0~2, MSPI read address is 4*n and reply the real AXI read data back. 0: When ARSIZE 0~1, MSPI reply SLV_ERR.*/
@@ -271,7 +271,7 @@ typedef volatile struct spi_mem_dev_s {
             uint32_t sclkcnt_h                     :    8;  /*For SPI0 external RAM  interface, it must be floor((spi_mem_clkcnt_N+1)/2-1).*/
             uint32_t sclkcnt_n                     :    8;  /*For SPI0 external RAM  interface, it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)*/
             uint32_t reserved24                    :    7;  /*reserved*/
-            uint32_t sclk_equ_sysclk               :    1;  /*For SPI0 external RAM  interface, 1: spi_mem_clk is eqaul to system 0: spi_mem_clk is divided from system clock.*/
+            uint32_t sclk_equ_sysclk               :    1;  /*For SPI0 external RAM  interface, 1: spi_mem_clk is equal to system 0: spi_mem_clk is divided from system clock.*/
         };
         uint32_t val;
     } sram_clk;
@@ -388,7 +388,7 @@ typedef volatile struct spi_mem_dev_s {
             uint32_t axi_raddr_err                 :    1;  /*The raw bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. 1: Triggered when AXI read address is invalid by compared to MMU configuration. 0: Others.*/
             uint32_t axi_wr_flash_err              :    1;  /*The raw bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI write flash request is received. 0: Others.*/
             uint32_t axi_waddr_err                 :    1;  /*The raw bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. 1: Triggered when AXI write address is invalid by compared to MMU configuration. 0: Others.*/
-            uint32_t brown_out                     :    1;  /*The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that chip is loosing power and RTC module sends out brown out close flash request to SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered and MSPI returns to idle state. 0: Others.*/
+            uint32_t brown_out                     :    1;  /*The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that chip is losing power and RTC module sends out brown out close flash request to SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered and MSPI returns to idle state. 0: Others.*/
             uint32_t reserved11                    :    21;  /*reserved*/
         };
         uint32_t val;
@@ -1025,7 +1025,7 @@ typedef volatile struct spi_mem_dev_s {
     } mmu_power_ctrl;
     union {
         struct {
-            uint32_t reg_crypt_security_level      :    3;  /*Set the security level of spi mem cryption. 0: Shut off cryption DPA funtion. 1-7: The bigger the number is, the more secure the cryption is. (Note that the performance of cryption will decrease together with this number increasing)*/
+            uint32_t reg_crypt_security_level      :    3;  /*Set the security level of spi mem cryption. 0: Shut off cryption DPA function. 1-7: The bigger the number is, the more secure the cryption is. (Note that the performance of cryption will decrease together with this number increasing)*/
             uint32_t reg_crypt_calc_d_dpa_en       :    1;  /*Only available when SPI_CRYPT_SECURITY_LEVEL is not 0. 1: Enable DPA in the calculation that using key 1 or key 2. 0: Enable DPA only in the calculation that using key 1.*/
             uint32_t reg_crypt_dpa_selectister     :    1;  /*1: MSPI XTS DPA clock gate is controlled by SPI_CRYPT_CALC_D_DPA_EN and SPI_CRYPT_SECURITY_LEVEL. 0: Controlled by efuse bits.*/
             uint32_t reserved5                     :    27;  /*reserved*/
diff --git a/components/soc/esp32c6/include/soc/spi_reg.h b/components/soc/esp32c6/register/soc/spi_reg.h
similarity index 99%
rename from components/soc/esp32c6/include/soc/spi_reg.h
rename to components/soc/esp32c6/register/soc/spi_reg.h
index 544b54abd1..8da5868eaa 100644
--- a/components/soc/esp32c6/include/soc/spi_reg.h
+++ b/components/soc/esp32c6/register/soc/spi_reg.h
@@ -221,7 +221,7 @@ extern "C" {
 #define SPI_CLKDIV_PRE_V  0x0000000FU
 #define SPI_CLKDIV_PRE_S  18
 /** SPI_CLK_EQU_SYSCLK : R/W; bitpos: [31]; default: 1;
- *  In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system
+ *  In the master mode 1: spi_clk is equal to system 0: spi_clk is divided from system
  *  clock. Can be configured in CONF state.
  */
 #define SPI_CLK_EQU_SYSCLK    (BIT(31))
@@ -1944,7 +1944,7 @@ extern "C" {
 /** SPI_CLK_MODE : R/W; bitpos: [1:0]; default: 0;
  *  SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed
  *  one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3:
- *  SPI clock is alwasy on. Can be configured in CONF state.
+ *  SPI clock is always on. Can be configured in CONF state.
  */
 #define SPI_CLK_MODE    0x00000003U
 #define SPI_CLK_MODE_M  (SPI_CLK_MODE_V << SPI_CLK_MODE_S)
diff --git a/components/soc/esp32c6/include/soc/spi_struct.h b/components/soc/esp32c6/register/soc/spi_struct.h
similarity index 99%
rename from components/soc/esp32c6/include/soc/spi_struct.h
rename to components/soc/esp32c6/register/soc/spi_struct.h
index 14b6be86c1..52076bb16c 100644
--- a/components/soc/esp32c6/include/soc/spi_struct.h
+++ b/components/soc/esp32c6/register/soc/spi_struct.h
@@ -511,7 +511,7 @@ typedef union {
         /** clk_mode : R/W; bitpos: [1:0]; default: 0;
          *  SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed
          *  one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3:
-         *  SPI clock is alwasy on. Can be configured in CONF state.
+         *  SPI clock is always on. Can be configured in CONF state.
          */
         uint32_t clk_mode:2;
         /** clk_mode_13 : R/W; bitpos: [2]; default: 0;
@@ -624,7 +624,7 @@ typedef union {
         uint32_t clkdiv_pre:4;
         uint32_t reserved_22:9;
         /** clk_equ_sysclk : R/W; bitpos: [31]; default: 1;
-         *  In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system
+         *  In the master mode 1: spi_clk is equal to system 0: spi_clk is divided from system
          *  clock. Can be configured in CONF state.
          */
         uint32_t clk_equ_sysclk:1;
diff --git a/components/soc/esp32c6/include/soc/systimer_reg.h b/components/soc/esp32c6/register/soc/systimer_reg.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/systimer_reg.h
rename to components/soc/esp32c6/register/soc/systimer_reg.h
diff --git a/components/soc/esp32c6/include/soc/systimer_struct.h b/components/soc/esp32c6/register/soc/systimer_struct.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/systimer_struct.h
rename to components/soc/esp32c6/register/soc/systimer_struct.h
diff --git a/components/soc/esp32c6/include/soc/tee_reg.h b/components/soc/esp32c6/register/soc/tee_reg.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/tee_reg.h
rename to components/soc/esp32c6/register/soc/tee_reg.h
diff --git a/components/soc/esp32c6/include/soc/tee_struct.h b/components/soc/esp32c6/register/soc/tee_struct.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/tee_struct.h
rename to components/soc/esp32c6/register/soc/tee_struct.h
diff --git a/components/soc/esp32c6/include/soc/timer_group_reg.h b/components/soc/esp32c6/register/soc/timer_group_reg.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/timer_group_reg.h
rename to components/soc/esp32c6/register/soc/timer_group_reg.h
diff --git a/components/soc/esp32c6/include/soc/timer_group_struct.h b/components/soc/esp32c6/register/soc/timer_group_struct.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/timer_group_struct.h
rename to components/soc/esp32c6/register/soc/timer_group_struct.h
diff --git a/components/soc/esp32c6/include/soc/trace_reg.h b/components/soc/esp32c6/register/soc/trace_reg.h
similarity index 99%
rename from components/soc/esp32c6/include/soc/trace_reg.h
rename to components/soc/esp32c6/register/soc/trace_reg.h
index a5c3eda9dc..b363fbd1f8 100644
--- a/components/soc/esp32c6/include/soc/trace_reg.h
+++ b/components/soc/esp32c6/register/soc/trace_reg.h
@@ -154,7 +154,7 @@ extern "C" {
 #define TRACE_TRIGGER_OFF_V  0x00000001U
 #define TRACE_TRIGGER_OFF_S  1
 /** TRACE_MEM_LOOP : R/W; bitpos: [2]; default: 1;
- *  if this reg is 1, trace will loop wrtie trace_mem.  If is 0, when mem_current_addr
+ *  if this reg is 1, trace will loop write trace_mem.  If is 0, when mem_current_addr
  *  at mem_end_addr, it will stop at the mem_end_addr
  */
 #define TRACE_MEM_LOOP    (BIT(2))
diff --git a/components/soc/esp32c6/include/soc/trace_struct.h b/components/soc/esp32c6/register/soc/trace_struct.h
similarity index 99%
rename from components/soc/esp32c6/include/soc/trace_struct.h
rename to components/soc/esp32c6/register/soc/trace_struct.h
index 3b8330b6b0..e5bb04d46d 100644
--- a/components/soc/esp32c6/include/soc/trace_struct.h
+++ b/components/soc/esp32c6/register/soc/trace_struct.h
@@ -156,7 +156,7 @@ typedef union {
          */
         uint32_t trigger_off:1;
         /** mem_loop : R/W; bitpos: [2]; default: 1;
-         *  if this reg is 1, trace will loop wrtie trace_mem.  If is 0, when mem_current_addr
+         *  if this reg is 1, trace will loop write trace_mem.  If is 0, when mem_current_addr
          *  at mem_end_addr, it will stop at the mem_end_addr
          */
         uint32_t mem_loop:1;
diff --git a/components/soc/esp32c6/include/soc/twai_reg.h b/components/soc/esp32c6/register/soc/twai_reg.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/twai_reg.h
rename to components/soc/esp32c6/register/soc/twai_reg.h
diff --git a/components/soc/esp32c6/include/soc/twai_struct.h b/components/soc/esp32c6/register/soc/twai_struct.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/twai_struct.h
rename to components/soc/esp32c6/register/soc/twai_struct.h
diff --git a/components/soc/esp32c6/include/soc/uart_reg.h b/components/soc/esp32c6/register/soc/uart_reg.h
similarity index 99%
rename from components/soc/esp32c6/include/soc/uart_reg.h
rename to components/soc/esp32c6/register/soc/uart_reg.h
index abac8d92b1..d85004fcc1 100644
--- a/components/soc/esp32c6/include/soc/uart_reg.h
+++ b/components/soc/esp32c6/register/soc/uart_reg.h
@@ -100,7 +100,7 @@ extern "C" {
 #define UART_RXFIFO_TOUT_INT_RAW_V  0x00000001U
 #define UART_RXFIFO_TOUT_INT_RAW_S  8
 /** UART_SW_XON_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
- *  This interrupt raw bit turns to high level when receiver recevies Xon char when
+ *  This interrupt raw bit turns to high level when receiver receives Xon char when
  *  uart_sw_flow_con_en is set to 1.
  */
 #define UART_SW_XON_INT_RAW    (BIT(9))
@@ -285,7 +285,7 @@ extern "C" {
 #define UART_TX_BRK_DONE_INT_ST_V  0x00000001U
 #define UART_TX_BRK_DONE_INT_ST_S  12
 /** UART_TX_BRK_IDLE_DONE_INT_ST : RO; bitpos: [13]; default: 0;
- *  This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena
+ *  This is the status bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena
  *  is set to 1.
  */
 #define UART_TX_BRK_IDLE_DONE_INT_ST    (BIT(13))
@@ -760,7 +760,7 @@ extern "C" {
 #define UART_STOP_BIT_NUM_V  0x00000003U
 #define UART_STOP_BIT_NUM_S  4
 /** UART_TXD_BRK : R/W; bitpos: [6]; default: 0;
- *  Set this bit to enbale transmitter to  send NULL when the process of sending data
+ *  Set this bit to enable transmitter to  send NULL when the process of sending data
  *  is done.
  */
 #define UART_TXD_BRK    (BIT(6))
@@ -1326,7 +1326,7 @@ extern "C" {
  */
 #define UART_TOUT_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x64)
 /** UART_RX_TOUT_EN : R/W; bitpos: [0]; default: 0;
- *  This is the enble bit for uart receiver's timeout function.
+ *  This is the enable bit for uart receiver's timeout function.
  */
 #define UART_RX_TOUT_EN    (BIT(0))
 #define UART_RX_TOUT_EN_M  (UART_RX_TOUT_EN_V << UART_RX_TOUT_EN_S)
@@ -1450,7 +1450,7 @@ extern "C" {
  */
 #define UART_HIGHPULSE_REG(i) (REG_UART_BASE(i) + 0x80)
 /** UART_HIGHPULSE_MIN_CNT : RO; bitpos: [11:0]; default: 4095;
- *  This register stores  the value of the maxinum duration time for the high level
+ *  This register stores  the value of the maximum duration time for the high level
  *  pulse. It is used in baud rate-detect process.
  */
 #define UART_HIGHPULSE_MIN_CNT    0x00000FFFU
diff --git a/components/soc/esp32c6/include/soc/uart_struct.h b/components/soc/esp32c6/register/soc/uart_struct.h
similarity index 99%
rename from components/soc/esp32c6/include/soc/uart_struct.h
rename to components/soc/esp32c6/register/soc/uart_struct.h
index 674af37135..05d3b740d1 100644
--- a/components/soc/esp32c6/include/soc/uart_struct.h
+++ b/components/soc/esp32c6/register/soc/uart_struct.h
@@ -49,7 +49,7 @@ typedef union {
 typedef union {
     struct {
         /** rx_tout_en : R/W; bitpos: [0]; default: 0;
-         *  This is the enble bit for uart receiver's timeout function.
+         *  This is the enable bit for uart receiver's timeout function.
          */
         uint32_t rx_tout_en:1;
         /** rx_tout_flow_dis : R/W; bitpos: [1]; default: 0;
@@ -120,7 +120,7 @@ typedef union {
          */
         uint32_t rxfifo_tout:1;
         /** sw_xon : R/WTC/SS; bitpos: [9]; default: 0;
-         *  This interrupt raw bit turns to high level when receiver recevies Xon char when
+         *  This interrupt raw bit turns to high level when receiver receives Xon char when
          *  uart_sw_flow_con_en is set to 1.
          */
         uint32_t sw_xon:1;
@@ -238,7 +238,7 @@ typedef union {
          */
         uint32_t tx_brk_done:1;
         /** tx_brk_idle_done : RO; bitpos: [13]; default: 0;
-         *  This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena
+         *  This is the status bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena
          *  is set to 1.
          */
         uint32_t tx_brk_idle_done:1;
@@ -515,7 +515,7 @@ typedef union {
          */
         uint32_t stop_bit_num:2;
         /** txd_brk : R/W; bitpos: [6]; default: 0;
-         *  Set this bit to enbale transmitter to  send NULL when the process of sending data
+         *  Set this bit to enable transmitter to  send NULL when the process of sending data
          *  is done.
          */
         uint32_t txd_brk:1;
@@ -1170,7 +1170,7 @@ typedef union {
 typedef union {
     struct {
         /** highpulse_min_cnt : RO; bitpos: [11:0]; default: 4095;
-         *  This register stores  the value of the maxinum duration time for the high level
+         *  This register stores  the value of the maximum duration time for the high level
          *  pulse. It is used in baud rate-detect process.
          */
         uint32_t highpulse_min_cnt:12;
diff --git a/components/soc/esp32c6/include/soc/uhci_reg.h b/components/soc/esp32c6/register/soc/uhci_reg.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/uhci_reg.h
rename to components/soc/esp32c6/register/soc/uhci_reg.h
diff --git a/components/soc/esp32c6/include/soc/uhci_struct.h b/components/soc/esp32c6/register/soc/uhci_struct.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/uhci_struct.h
rename to components/soc/esp32c6/register/soc/uhci_struct.h
diff --git a/components/soc/esp32c6/include/soc/usb_serial_jtag_reg.h b/components/soc/esp32c6/register/soc/usb_serial_jtag_reg.h
similarity index 99%
rename from components/soc/esp32c6/include/soc/usb_serial_jtag_reg.h
rename to components/soc/esp32c6/register/soc/usb_serial_jtag_reg.h
index eb4b8a1e03..e188eea911 100644
--- a/components/soc/esp32c6/include/soc/usb_serial_jtag_reg.h
+++ b/components/soc/esp32c6/register/soc/usb_serial_jtag_reg.h
@@ -1144,7 +1144,7 @@ extern "C" {
 #define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_V  0x00000001U
 #define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_S  3
 /** USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY : RO; bitpos: [4]; default: 1;
- *  CDC_ACM OUTOUT async FIFO empty signal in read clock domain.
+ *  CDC_ACM OUTPUT async FIFO empty signal in read clock domain.
  */
 #define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY    (BIT(4))
 #define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_M  (USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_V << USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_S)
diff --git a/components/soc/esp32c6/include/soc/usb_serial_jtag_struct.h b/components/soc/esp32c6/register/soc/usb_serial_jtag_struct.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/usb_serial_jtag_struct.h
rename to components/soc/esp32c6/register/soc/usb_serial_jtag_struct.h
diff --git a/components/soc/esp32c6/include/soc/xts_aes_reg.h b/components/soc/esp32c6/register/soc/xts_aes_reg.h
similarity index 98%
rename from components/soc/esp32c6/include/soc/xts_aes_reg.h
rename to components/soc/esp32c6/register/soc/xts_aes_reg.h
index 5d7d7e0b81..6e7cba263a 100644
--- a/components/soc/esp32c6/include/soc/xts_aes_reg.h
+++ b/components/soc/esp32c6/register/soc/xts_aes_reg.h
@@ -32,7 +32,7 @@ s. Please do not use this field..*/
 
 #define XTS_AES_DESTINATION_REG(i)          (REG_SPI_MEM_BASE(i) + 0x344)
 /* XTS_AES_DESTINATION : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: This bit stores the destination parameter which will be used in manual encryptio
+/*description: This bit stores the destination parameter which will be used in manual encryption
 n calculation. 0: flash(default), 1: psram(reserved). Only default value can be
 used..*/
 #define XTS_AES_DESTINATION    (BIT(0))
@@ -54,7 +54,7 @@ size parameter..*/
 /* XTS_AES_TRIGGER : WT ;bitpos:[0] ;default: 1'b0 ; */
 /*description: Set this bit to trigger the process of manual encryption calculation. This actio
 n should only be asserted when manual encryption status is 0. After this action,
- manual encryption status becomes 1. After calculation is done, manual encryptio
+ manual encryption status becomes 1. After calculation is done, manual encryption
 n status becomes 2..*/
 #define XTS_AES_TRIGGER    (BIT(0))
 #define XTS_AES_TRIGGER_M  (BIT(0))
@@ -115,7 +115,7 @@ ing key 1..*/
 #define XTS_AES_CRYPT_CALC_D_DPA_EN_V  0x1
 #define XTS_AES_CRYPT_CALC_D_DPA_EN_S  3
 /* XTS_AES_CRYPT_SECURITY_LEVEL : R/W ;bitpos:[2:0] ;default: 3'd7 ; */
-/*description: Set the security level of spi mem cryption. 0: Shut off cryption DPA funtion. 1-
+/*description: Set the security level of spi mem cryption. 0: Shut off cryption DPA function. 1-
 7: The bigger the number is, the more secure the cryption is. (Note that the per
 formance of cryption will decrease together with this number increasing).*/
 #define XTS_AES_CRYPT_SECURITY_LEVEL    0x00000007