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fix(spi_master): change MOSI pin default idle level to low

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Chen Jichang
2024-07-01 15:44:19 +08:00
parent cb771eaf1b
commit f0e8b606b7
1 changed files with 11 additions and 0 deletions
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11
components/hal/esp32p4/include/hal/spi_ll.h
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@@ -42,6 +42,7 @@ extern "C" {
#define SPI_LL_CPU_MAX_BIT_LEN (16 * 32) //Fifo len: 16 words #define SPI_LL_CPU_MAX_BIT_LEN (16 * 32) //Fifo len: 16 words
#define SPI_LL_SUPPORT_CLK_SRC_PRE_DIV 1 //clock source have divider before peripheral #define SPI_LL_SUPPORT_CLK_SRC_PRE_DIV 1 //clock source have divider before peripheral
#define SPI_LL_CLK_SRC_PRE_DIV_MAX 512//div1(8bit) * div2(8bit but set const 2) #define SPI_LL_CLK_SRC_PRE_DIV_MAX 512//div1(8bit) * div2(8bit but set const 2)
#define SPI_LL_MOSI_FREE_LEVEL 1 //Default level after bus initialized
/** /**
* The data structure holding calculated clock configuration. Since the * The data structure holding calculated clock configuration. Since the
@@ -880,6 +881,16 @@ static inline void spi_ll_set_mosi_delay(spi_dev_t *hw, int delay_mode, int dela
{ {
} }
/**
* Determine and unify the default level of mosi line when bus free
*
* @param hw Beginning address of the peripheral registers.
*/
static inline void spi_ll_set_mosi_free_level(spi_dev_t *hw, bool level)
{
hw->ctrl.d_pol = level; //set default level for MOSI only on IDLE state
}
/** /**
* Set the miso delay applied to the input signal before the internal peripheral. (Preview) * Set the miso delay applied to the input signal before the internal peripheral. (Preview)
* *