From f19e8e6970a8c839a9f78bfeb7fbc14bfd738848 Mon Sep 17 00:00:00 2001 From: "nilesh.kale" Date: Mon, 28 Apr 2025 17:41:05 +0530 Subject: [PATCH] fix: re-enabled ecdsa support for esp32c5-eco2 --- components/hal/ecdsa_hal.c | 10 +- components/hal/efuse_hal.c | 4 +- components/hal/esp32c5/include/hal/ecdsa_ll.h | 31 +- components/hal/esp32c5/include/hal/efuse_ll.h | 15 +- .../hal/esp32c61/include/hal/efuse_ll.h | 4 +- components/hal/esp32h2/include/hal/efuse_ll.h | 4 +- .../hal/esp32h21/include/hal/efuse_ll.h | 4 +- components/hal/esp32h4/include/hal/efuse_ll.h | 4 +- components/hal/esp32p4/include/hal/efuse_ll.h | 4 +- components/hal/include/hal/ecdsa_hal.h | 4 +- components/hal/include/hal/ecdsa_types.h | 2 + components/hal/include/hal/efuse_hal.h | 4 +- .../test_apps/crypto/main/ecdsa/test_ecdsa.c | 4 +- components/mbedtls/port/ecdsa/ecdsa_alt.c | 4 +- .../esp32c5/include/soc/Kconfig.soc_caps.in | 8 + components/soc/esp32c5/include/soc/soc_caps.h | 2 + .../soc/esp32c5/register/soc/ecdsa_reg.h | 78 ++-- .../soc/esp32c5/register/soc/ecdsa_reg_eco2.h | 360 ------------------ .../soc/esp32c5/register/soc/ecdsa_struct.h | 56 ++- .../esp32c5/register/soc/ecdsa_struct_eco2.h | 348 ----------------- 20 files changed, 117 insertions(+), 833 deletions(-) delete mode 100644 components/soc/esp32c5/register/soc/ecdsa_reg_eco2.h delete mode 100644 components/soc/esp32c5/register/soc/ecdsa_struct_eco2.h diff --git a/components/hal/ecdsa_hal.c b/components/hal/ecdsa_hal.c index 5c10802e2c..4ed2d5bfc3 100644 --- a/components/hal/ecdsa_hal.c +++ b/components/hal/ecdsa_hal.c @@ -26,7 +26,7 @@ static void configure_ecdsa_periph(ecdsa_hal_config_t *conf) { if (conf->use_km_key == 0) { - efuse_hal_set_ecdsa_key(conf->efuse_key_blk); + efuse_hal_set_ecdsa_key(conf->curve, conf->efuse_key_blk); #if SOC_KEY_MANAGER_ECDSA_KEY_DEPLOY // Force Key Manager to use eFuse key for XTS-AES operation @@ -49,9 +49,11 @@ static void configure_ecdsa_periph(ecdsa_hal_config_t *conf) #if SOC_ECDSA_SUPPORT_DETERMINISTIC_MODE ecdsa_ll_set_k_type(conf->sign_type); +#if !SOC_ECDSA_SUPPORT_HW_DETERMINISTIC_LOOP if (conf->sign_type == ECDSA_K_TYPE_DETERMINISITIC) { ecdsa_ll_set_deterministic_loop(conf->loop_number); } +#endif /* !SOC_ECDSA_SUPPORT_HW_DETERMINISTIC_LOOP */ #endif } @@ -224,11 +226,9 @@ void ecdsa_hal_export_pubkey(ecdsa_hal_config_t *conf, uint8_t *pub_x, uint8_t * } #endif /* SOC_ECDSA_SUPPORT_EXPORT_PUBKEY */ -#ifdef SOC_ECDSA_SUPPORT_DETERMINISTIC_MODE - +#if SOC_ECDSA_SUPPORT_DETERMINISTIC_MODE && !SOC_ECDSA_SUPPORT_HW_DETERMINISTIC_LOOP bool ecdsa_hal_det_signature_k_check(void) { return (ecdsa_ll_check_k_value() == 0); } - -#endif /* SOC_ECDSA_SUPPORT_DETERMINISTIC_MODE */ +#endif /* SOC_ECDSA_SUPPORT_DETERMINISTIC_MODE && !SOC_ECDSA_SUPPORT_HW_DETERMINISTIC_LOOP */ diff --git a/components/hal/efuse_hal.c b/components/hal/efuse_hal.c index 43a007aca2..afafaac53e 100644 --- a/components/hal/efuse_hal.c +++ b/components/hal/efuse_hal.c @@ -57,9 +57,9 @@ IRAM_ATTR bool efuse_hal_flash_encryption_enabled(void) } #if SOC_EFUSE_ECDSA_KEY -void efuse_hal_set_ecdsa_key(int efuse_blk) +void efuse_hal_set_ecdsa_key(ecdsa_curve_t curve, int efuse_blk) { - efuse_ll_set_ecdsa_key_blk(efuse_blk); + efuse_ll_set_ecdsa_key_blk(curve, efuse_blk); efuse_ll_rs_bypass_update(); diff --git a/components/hal/esp32c5/include/hal/ecdsa_ll.h b/components/hal/esp32c5/include/hal/ecdsa_ll.h index 58bb389aeb..52ddd9e4c3 100644 --- a/components/hal/esp32c5/include/hal/ecdsa_ll.h +++ b/components/hal/esp32c5/include/hal/ecdsa_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -194,11 +194,11 @@ static inline void ecdsa_ll_set_mode(ecdsa_mode_t mode) static inline void ecdsa_ll_set_curve(ecdsa_curve_t curve) { switch (curve) { - case ECDSA_CURVE_SECP256R1: - REG_SET_BIT(ECDSA_CONF_REG, ECDSA_ECC_CURVE); - break; case ECDSA_CURVE_SECP192R1: - REG_CLR_BIT(ECDSA_CONF_REG, ECDSA_ECC_CURVE); + case ECDSA_CURVE_SECP256R1: + case ECDSA_CURVE_SECP384R1: + case ECDSA_CURVE_SM2: + REG_SET_FIELD(ECDSA_CONF_REG, ECDSA_ECC_CURVE, curve); break; default: HAL_ASSERT(false && "Unsupported curve"); @@ -248,16 +248,6 @@ static inline void ecdsa_ll_set_k_type(ecdsa_sign_type_t type) } } -/** - * @brief Set the loop number value that is used for deterministic derivation of K - * - * @param loop_number Loop number for deterministic K - */ -static inline void ecdsa_ll_set_deterministic_loop(uint16_t loop_number) -{ - REG_SET_FIELD(ECDSA_CONF_REG, ECDSA_DETERMINISTIC_LOOP, loop_number); -} - /** * @brief Set the stage of ECDSA operation * @@ -415,17 +405,6 @@ static inline int ecdsa_ll_get_operation_result(void) return REG_GET_BIT(ECDSA_RESULT_REG, ECDSA_OPERATION_RESULT); } -/** - * @brief Check if the k value is greater than the curve order. - * - * @return 0, k value is not greater than the curve order. In this case, the k value is the set k value. - * @return 1, k value is greater than than the curve order. In this case, the k value is the set (k mod n). - */ -static inline int ecdsa_ll_check_k_value(void) -{ - return REG_GET_BIT(ECDSA_RESULT_REG, ECDSA_K_VALUE_WARNING); -} - #ifdef __cplusplus } #endif diff --git a/components/hal/esp32c5/include/hal/efuse_ll.h b/components/hal/esp32c5/include/hal/efuse_ll.h index 0e1434d74e..081f6242b2 100644 --- a/components/hal/esp32c5/include/hal/efuse_ll.h +++ b/components/hal/esp32c5/include/hal/efuse_ll.h @@ -13,6 +13,7 @@ #include "soc/efuse_periph.h" #include "hal/assert.h" #include "rom/efuse.h" +#include "hal/ecdsa_types.h" #ifdef __cplusplus extern "C" { @@ -93,9 +94,19 @@ __attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_ver_pkg( return EFUSE.rd_mac_sys2.pkg_version; } -__attribute__((always_inline)) static inline void efuse_ll_set_ecdsa_key_blk(int efuse_blk) +__attribute__((always_inline)) static inline void efuse_ll_set_ecdsa_key_blk(ecdsa_curve_t curve, int efuse_blk) { - EFUSE.conf.cfg_ecdsa_blk = efuse_blk; + switch (curve) { + case ECDSA_CURVE_SECP192R1: + EFUSE.ecdsa.cfg_ecdsa_p192_blk = efuse_blk; + break; + case ECDSA_CURVE_SECP256R1: + EFUSE.ecdsa.cfg_ecdsa_p256_blk = efuse_blk; + break; + default: + HAL_ASSERT(false && "Unsupported curve"); + break; + } } __attribute__((always_inline)) static inline uint32_t efuse_ll_get_ocode(void) diff --git a/components/hal/esp32c61/include/hal/efuse_ll.h b/components/hal/esp32c61/include/hal/efuse_ll.h index be9c240152..f86f8392ba 100644 --- a/components/hal/esp32c61/include/hal/efuse_ll.h +++ b/components/hal/esp32c61/include/hal/efuse_ll.h @@ -13,6 +13,7 @@ #include "soc/efuse_struct.h" #include "hal/assert.h" #include "rom/efuse.h" +#include "hal/ecdsa_types.h" #ifdef __cplusplus extern "C" { @@ -98,8 +99,9 @@ __attribute__((always_inline)) static inline uint32_t efuse_ll_get_ecdsa_key_blk return EFUSE0.conf.cfg_ecdsa_blk; } -__attribute__((always_inline)) static inline void efuse_ll_set_ecdsa_key_blk(int efuse_blk) +__attribute__((always_inline)) static inline void efuse_ll_set_ecdsa_key_blk(ecdsa_curve_t curve, int efuse_blk) { + (void) curve; EFUSE0.conf.cfg_ecdsa_blk = efuse_blk; } diff --git a/components/hal/esp32h2/include/hal/efuse_ll.h b/components/hal/esp32h2/include/hal/efuse_ll.h index 16226aa463..c120dfe383 100644 --- a/components/hal/esp32h2/include/hal/efuse_ll.h +++ b/components/hal/esp32h2/include/hal/efuse_ll.h @@ -11,6 +11,7 @@ #include "soc/efuse_periph.h" #include "hal/assert.h" #include "rom/efuse.h" +#include "hal/ecdsa_types.h" #ifdef __cplusplus extern "C" { @@ -107,8 +108,9 @@ __attribute__((always_inline)) static inline uint32_t efuse_ll_get_ecdsa_key_blk return EFUSE.conf.cfg_ecdsa_blk; } -__attribute__((always_inline)) static inline void efuse_ll_set_ecdsa_key_blk(int efuse_blk) +__attribute__((always_inline)) static inline void efuse_ll_set_ecdsa_key_blk(ecdsa_curve_t curve, int efuse_blk) { + (void) curve; EFUSE.conf.cfg_ecdsa_blk = efuse_blk; } diff --git a/components/hal/esp32h21/include/hal/efuse_ll.h b/components/hal/esp32h21/include/hal/efuse_ll.h index 59159d9df6..99ac523246 100644 --- a/components/hal/esp32h21/include/hal/efuse_ll.h +++ b/components/hal/esp32h21/include/hal/efuse_ll.h @@ -11,6 +11,7 @@ #include "soc/efuse_periph.h" #include "hal/assert.h" #include "rom/efuse.h" +#include "hal/ecdsa_types.h" //TODO: [ESP32H21] IDF-11556, inherit from h2 @@ -114,8 +115,9 @@ __attribute__((always_inline)) static inline uint32_t efuse_ll_get_ecdsa_key_blk return EFUSE.conf.cfg_ecdsa_blk; } -__attribute__((always_inline)) static inline void efuse_ll_set_ecdsa_key_blk(int efuse_blk) +__attribute__((always_inline)) static inline void efuse_ll_set_ecdsa_key_blk(ecdsa_curve_t curve, int efuse_blk) { + (void) curve; EFUSE.conf.cfg_ecdsa_blk = efuse_blk; } diff --git a/components/hal/esp32h4/include/hal/efuse_ll.h b/components/hal/esp32h4/include/hal/efuse_ll.h index 0530ca9bca..a3e6c26611 100644 --- a/components/hal/esp32h4/include/hal/efuse_ll.h +++ b/components/hal/esp32h4/include/hal/efuse_ll.h @@ -11,6 +11,7 @@ #include "soc/efuse_periph.h" #include "hal/assert.h" #include "rom/efuse.h" +#include "hal/ecdsa_types.h" //TODO: [ESP32H4] IDF-12322 inherited from verification branch, need check @@ -96,9 +97,10 @@ __attribute__((always_inline)) static inline uint32_t efuse_ll_get_ecdsa_key_blk return 0; } -__attribute__((always_inline)) static inline void efuse_ll_set_ecdsa_key_blk(int efuse_blk) +__attribute__((always_inline)) static inline void efuse_ll_set_ecdsa_key_blk(ecdsa_curve_t curve, int efuse_blk) { //ESP32H4 TODO + (void)curve; (void)efuse_blk; } diff --git a/components/hal/esp32p4/include/hal/efuse_ll.h b/components/hal/esp32p4/include/hal/efuse_ll.h index 11fd66c61d..d399f530a8 100644 --- a/components/hal/esp32p4/include/hal/efuse_ll.h +++ b/components/hal/esp32p4/include/hal/efuse_ll.h @@ -11,6 +11,7 @@ #include "soc/efuse_periph.h" #include "hal/assert.h" #include "rom/efuse.h" +#include "hal/ecdsa_types.h" #ifdef __cplusplus extern "C" { @@ -91,8 +92,9 @@ __attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_ver_pkg( return EFUSE.rd_mac_sys_2.pkg_version; } -__attribute__((always_inline)) static inline void efuse_ll_set_ecdsa_key_blk(int efuse_blk) +__attribute__((always_inline)) static inline void efuse_ll_set_ecdsa_key_blk(ecdsa_curve_t curve, int efuse_blk) { + (void) curve; EFUSE.conf.cfg_ecdsa_blk = efuse_blk; } diff --git a/components/hal/include/hal/ecdsa_hal.h b/components/hal/include/hal/ecdsa_hal.h index 6994410375..182ebbe80d 100644 --- a/components/hal/include/hal/ecdsa_hal.h +++ b/components/hal/include/hal/ecdsa_hal.h @@ -98,7 +98,7 @@ void ecdsa_hal_export_pubkey(ecdsa_hal_config_t *conf, uint8_t *pub_x, uint8_t * */ bool ecdsa_hal_get_operation_result(void); -#ifdef SOC_ECDSA_SUPPORT_DETERMINISTIC_MODE +#if SOC_ECDSA_SUPPORT_DETERMINISTIC_MODE && !SOC_ECDSA_SUPPORT_HW_DETERMINISTIC_LOOP /** * @brief Check if the K value derived by the peripheral during deterministic signature generation is valid * @@ -107,7 +107,7 @@ bool ecdsa_hal_get_operation_result(void); */ bool ecdsa_hal_det_signature_k_check(void); -#endif /* SOC_ECDSA_SUPPORT_DETERMINISTIC_MODE */ +#endif /* SOC_ECDSA_SUPPORT_DETERMINISTIC_MODE && !SOC_ECDSA_SUPPORT_HW_DETERMINISTIC_LOOP */ #ifdef __cplusplus } diff --git a/components/hal/include/hal/ecdsa_types.h b/components/hal/include/hal/ecdsa_types.h index c72ae963f7..20caf84a1f 100644 --- a/components/hal/include/hal/ecdsa_types.h +++ b/components/hal/include/hal/ecdsa_types.h @@ -26,6 +26,8 @@ typedef enum { typedef enum { ECDSA_CURVE_SECP192R1, ECDSA_CURVE_SECP256R1, + ECDSA_CURVE_SECP384R1, + ECDSA_CURVE_SM2, } ecdsa_curve_t; /** diff --git a/components/hal/include/hal/efuse_hal.h b/components/hal/include/hal/efuse_hal.h index cfed79f591..c3810acf65 100644 --- a/components/hal/include/hal/efuse_hal.h +++ b/components/hal/include/hal/efuse_hal.h @@ -9,6 +9,7 @@ #include #include #include "soc/soc_caps.h" +#include "hal/ecdsa_types.h" #ifdef __cplusplus extern "C" { @@ -80,9 +81,10 @@ uint32_t efuse_hal_get_chip_ver_pkg(void); * * @note The efuse block must be burnt with key purpose ECDSA_KEY * + * @param curve ECDSA curve type * @param efuse_key_blk Efuse key block number (Must be in [EFUSE_BLK_KEY0...EFUSE_BLK_KEY_MAX - 1] range) */ -void efuse_hal_set_ecdsa_key(int efuse_key_blk); +void efuse_hal_set_ecdsa_key(ecdsa_curve_t curve, int efuse_key_blk); #endif #ifdef __cplusplus diff --git a/components/hal/test_apps/crypto/main/ecdsa/test_ecdsa.c b/components/hal/test_apps/crypto/main/ecdsa/test_ecdsa.c index 8cf5e1dac4..56abd58cb1 100644 --- a/components/hal/test_apps/crypto/main/ecdsa/test_ecdsa.c +++ b/components/hal/test_apps/crypto/main/ecdsa/test_ecdsa.c @@ -198,11 +198,11 @@ void test_ecdsa_sign(bool is_p256, uint8_t* sha, uint8_t* r_le, uint8_t* s_le, b || !memcmp(r_le, zeroes, len) || !memcmp(s_le, zeroes, len); -#ifdef SOC_ECDSA_SUPPORT_DETERMINISTIC_MODE +#if SOC_ECDSA_SUPPORT_DETERMINISTIC_MODE && !SOC_ECDSA_SUPPORT_HW_DETERMINISTIC_LOOP if (k_type == ECDSA_K_TYPE_DETERMINISITIC) { process_again |= !ecdsa_hal_det_signature_k_check(); } -#endif /* SOC_ECDSA_SUPPORT_DETERMINISTIC_MODE */ +#endif /* SOC_ECDSA_SUPPORT_DETERMINISTIC_MODE && !SOC_ECDSA_SUPPORT_HW_DETERMINISTIC_LOOP */ } while(process_again); diff --git a/components/mbedtls/port/ecdsa/ecdsa_alt.c b/components/mbedtls/port/ecdsa/ecdsa_alt.c index 5fca558a6f..8a30aa89fd 100644 --- a/components/mbedtls/port/ecdsa/ecdsa_alt.c +++ b/components/mbedtls/port/ecdsa/ecdsa_alt.c @@ -391,11 +391,11 @@ static int esp_ecdsa_sign(mbedtls_ecp_group *grp, mbedtls_mpi* r, mbedtls_mpi* s || !memcmp(r_le, zeroes, len) || !memcmp(s_le, zeroes, len); -#ifdef SOC_ECDSA_SUPPORT_DETERMINISTIC_MODE +#if SOC_ECDSA_SUPPORT_DETERMINISTIC_MODE && !SOC_ECDSA_SUPPORT_HW_DETERMINISTIC_LOOP if (k_type == ECDSA_K_TYPE_DETERMINISITIC) { process_again |= !ecdsa_hal_det_signature_k_check(); } -#endif /* SOC_ECDSA_SUPPORT_DETERMINISTIC_MODE */ +#endif /* SOC_ECDSA_SUPPORT_DETERMINISTIC_MODE && !SOC_ECDSA_SUPPORT_HW_DETERMINISTIC_LOOP */ } while (process_again); diff --git a/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in index 1767d45aa0..b36ac4c83d 100644 --- a/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in @@ -1051,6 +1051,14 @@ config SOC_ECDSA_SUPPORT_EXPORT_PUBKEY bool default y +config SOC_ECDSA_SUPPORT_DETERMINISTIC_MODE + bool + default y + +config SOC_ECDSA_SUPPORT_HW_DETERMINISTIC_LOOP + bool + default y + config SOC_SDM_GROUPS int default 1 diff --git a/components/soc/esp32c5/include/soc/soc_caps.h b/components/soc/esp32c5/include/soc/soc_caps.h index aacbf2fe1a..8301c855d0 100644 --- a/components/soc/esp32c5/include/soc/soc_caps.h +++ b/components/soc/esp32c5/include/soc/soc_caps.h @@ -423,6 +423,8 @@ /*--------------------------- ECDSA CAPS ---------------------------------------*/ #define SOC_ECDSA_SUPPORT_EXPORT_PUBKEY (1) +#define SOC_ECDSA_SUPPORT_DETERMINISTIC_MODE (1) +#define SOC_ECDSA_SUPPORT_HW_DETERMINISTIC_LOOP (1) /*-------------------------- Sigma Delta Modulator CAPS -----------------*/ #define SOC_SDM_GROUPS 1U diff --git a/components/soc/esp32c5/register/soc/ecdsa_reg.h b/components/soc/esp32c5/register/soc/ecdsa_reg.h index 4893390ced..401786a165 100644 --- a/components/soc/esp32c5/register/soc/ecdsa_reg.h +++ b/components/soc/esp32c5/register/soc/ecdsa_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -23,44 +23,37 @@ extern "C" { #define ECDSA_WORK_MODE_M (ECDSA_WORK_MODE_V << ECDSA_WORK_MODE_S) #define ECDSA_WORK_MODE_V 0x00000003U #define ECDSA_WORK_MODE_S 0 -/** ECDSA_ECC_CURVE : R/W; bitpos: [2]; default: 0; - * The ecc curve select bit of ECDSA Accelerator. 0: P-192. 1: P-256. +/** ECDSA_ECC_CURVE : R/W; bitpos: [3:2]; default: 0; + * The ecc curve select bit of ECDSA Accelerator. 0: P-192. 1: P-256. 2: P-384 3: SM2. */ -#define ECDSA_ECC_CURVE (BIT(2)) +#define ECDSA_ECC_CURVE 0x00000003U #define ECDSA_ECC_CURVE_M (ECDSA_ECC_CURVE_V << ECDSA_ECC_CURVE_S) -#define ECDSA_ECC_CURVE_V 0x00000001U +#define ECDSA_ECC_CURVE_V 0x00000003U #define ECDSA_ECC_CURVE_S 2 -/** ECDSA_SOFTWARE_SET_K : R/W; bitpos: [3]; default: 0; +/** ECDSA_SOFTWARE_SET_K : R/W; bitpos: [4]; default: 0; * The source of k select bit. 0: k is automatically generated by hardware. 1: k is * written by software. */ -#define ECDSA_SOFTWARE_SET_K (BIT(3)) +#define ECDSA_SOFTWARE_SET_K (BIT(4)) #define ECDSA_SOFTWARE_SET_K_M (ECDSA_SOFTWARE_SET_K_V << ECDSA_SOFTWARE_SET_K_S) #define ECDSA_SOFTWARE_SET_K_V 0x00000001U -#define ECDSA_SOFTWARE_SET_K_S 3 -/** ECDSA_SOFTWARE_SET_Z : R/W; bitpos: [4]; default: 0; +#define ECDSA_SOFTWARE_SET_K_S 4 +/** ECDSA_SOFTWARE_SET_Z : R/W; bitpos: [5]; default: 0; * The source of z select bit. 0: z is generated from SHA result. 1: z is written by * software. */ -#define ECDSA_SOFTWARE_SET_Z (BIT(4)) +#define ECDSA_SOFTWARE_SET_Z (BIT(5)) #define ECDSA_SOFTWARE_SET_Z_M (ECDSA_SOFTWARE_SET_Z_V << ECDSA_SOFTWARE_SET_Z_S) #define ECDSA_SOFTWARE_SET_Z_V 0x00000001U -#define ECDSA_SOFTWARE_SET_Z_S 4 -/** ECDSA_DETERMINISTIC_K : R/W; bitpos: [5]; default: 0; +#define ECDSA_SOFTWARE_SET_Z_S 5 +/** ECDSA_DETERMINISTIC_K : R/W; bitpos: [6]; default: 0; * The source of hardware generated k. 0: k is generated by TRNG. 1: k is generated by * deterministic derivation algorithm. */ -#define ECDSA_DETERMINISTIC_K (BIT(5)) +#define ECDSA_DETERMINISTIC_K (BIT(6)) #define ECDSA_DETERMINISTIC_K_M (ECDSA_DETERMINISTIC_K_V << ECDSA_DETERMINISTIC_K_S) #define ECDSA_DETERMINISTIC_K_V 0x00000001U -#define ECDSA_DETERMINISTIC_K_S 5 -/** ECDSA_DETERMINISTIC_LOOP : R/W; bitpos: [21:6]; default: 0; - * The (loop number - 1) value in the deterministic derivation algorithm to derive k. - */ -#define ECDSA_DETERMINISTIC_LOOP 0x0000FFFFU -#define ECDSA_DETERMINISTIC_LOOP_M (ECDSA_DETERMINISTIC_LOOP_V << ECDSA_DETERMINISTIC_LOOP_S) -#define ECDSA_DETERMINISTIC_LOOP_V 0x0000FFFFU -#define ECDSA_DETERMINISTIC_LOOP_S 6 +#define ECDSA_DETERMINISTIC_K_S 6 /** ECDSA_CLK_REG register * ECDSA clock gate register @@ -260,20 +253,12 @@ extern "C" { #define ECDSA_OPERATION_RESULT_M (ECDSA_OPERATION_RESULT_V << ECDSA_OPERATION_RESULT_S) #define ECDSA_OPERATION_RESULT_V 0x00000001U #define ECDSA_OPERATION_RESULT_S 0 -/** ECDSA_K_VALUE_WARNING : RO/SS; bitpos: [1]; default: 0; - * The k value warning bit of ECDSA Accelerator, valid when k value is bigger than the - * curve order, then actually taken k = k mod n. - */ -#define ECDSA_K_VALUE_WARNING (BIT(1)) -#define ECDSA_K_VALUE_WARNING_M (ECDSA_K_VALUE_WARNING_V << ECDSA_K_VALUE_WARNING_S) -#define ECDSA_K_VALUE_WARNING_V 0x00000001U -#define ECDSA_K_VALUE_WARNING_S 1 /** ECDSA_DATE_REG register * Version control register */ #define ECDSA_DATE_REG (DR_REG_ECDSA_BASE + 0xfc) -/** ECDSA_DATE : R/W; bitpos: [27:0]; default: 36725040; +/** ECDSA_DATE : R/W; bitpos: [27:0]; default: 37785984; * ECDSA version control register */ #define ECDSA_DATE 0x0FFFFFFFU @@ -285,13 +270,14 @@ extern "C" { * ECDSA control SHA register */ #define ECDSA_SHA_MODE_REG (DR_REG_ECDSA_BASE + 0x200) -/** ECDSA_SHA_MODE : R/W; bitpos: [2:0]; default: 0; - * The work mode bits of SHA Calculator in ECDSA Accelerator. 1: SHA-224. 2: SHA-256. - * Others: invalid. +/** ECDSA_SHA_MODE : R/W; bitpos: [3:0]; default: 0; + * The work mode bits of SHA Calculator in ECDSA Accelerator. 0: SHA1. 1: SHA-224. 2: + * SHA-256. 3: SHA-384 4: SHA-512. 5: SHA-512224. 6: SHA-512256. 14:SM3. Others: + * invalid. */ -#define ECDSA_SHA_MODE 0x00000007U +#define ECDSA_SHA_MODE 0x0000000FU #define ECDSA_SHA_MODE_M (ECDSA_SHA_MODE_V << ECDSA_SHA_MODE_S) -#define ECDSA_SHA_MODE_V 0x00000007U +#define ECDSA_SHA_MODE_V 0x0000000FU #define ECDSA_SHA_MODE_S 0 /** ECDSA_SHA_START_REG register @@ -337,37 +323,37 @@ extern "C" { * The memory that stores message. */ #define ECDSA_MESSAGE_MEM (DR_REG_ECDSA_BASE + 0x280) -#define ECDSA_MESSAGE_MEM_SIZE_BYTES 32 +#define ECDSA_MESSAGE_MEM_SIZE_BYTES 64 /** ECDSA_R_MEM register * The memory that stores r. */ -#define ECDSA_R_MEM (DR_REG_ECDSA_BASE + 0x340) -#define ECDSA_R_MEM_SIZE_BYTES 32 +#define ECDSA_R_MEM (DR_REG_ECDSA_BASE + 0x3e0) +#define ECDSA_R_MEM_SIZE_BYTES 48 /** ECDSA_S_MEM register * The memory that stores s. */ -#define ECDSA_S_MEM (DR_REG_ECDSA_BASE + 0x360) -#define ECDSA_S_MEM_SIZE_BYTES 32 +#define ECDSA_S_MEM (DR_REG_ECDSA_BASE + 0x410) +#define ECDSA_S_MEM_SIZE_BYTES 48 /** ECDSA_Z_MEM register * The memory that stores software written z. */ -#define ECDSA_Z_MEM (DR_REG_ECDSA_BASE + 0x380) -#define ECDSA_Z_MEM_SIZE_BYTES 32 +#define ECDSA_Z_MEM (DR_REG_ECDSA_BASE + 0x440) +#define ECDSA_Z_MEM_SIZE_BYTES 48 /** ECDSA_QAX_MEM register * The memory that stores x coordinates of QA or software written k. */ -#define ECDSA_QAX_MEM (DR_REG_ECDSA_BASE + 0x3a0) -#define ECDSA_QAX_MEM_SIZE_BYTES 32 +#define ECDSA_QAX_MEM (DR_REG_ECDSA_BASE + 0x470) +#define ECDSA_QAX_MEM_SIZE_BYTES 48 /** ECDSA_QAY_MEM register * The memory that stores y coordinates of QA. */ -#define ECDSA_QAY_MEM (DR_REG_ECDSA_BASE + 0x3c0) -#define ECDSA_QAY_MEM_SIZE_BYTES 32 +#define ECDSA_QAY_MEM (DR_REG_ECDSA_BASE + 0x4a0) +#define ECDSA_QAY_MEM_SIZE_BYTES 48 #ifdef __cplusplus } diff --git a/components/soc/esp32c5/register/soc/ecdsa_reg_eco2.h b/components/soc/esp32c5/register/soc/ecdsa_reg_eco2.h deleted file mode 100644 index 401786a165..0000000000 --- a/components/soc/esp32c5/register/soc/ecdsa_reg_eco2.h +++ /dev/null @@ -1,360 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#include "soc/soc.h" -#ifdef __cplusplus -extern "C" { -#endif - -/** ECDSA_CONF_REG register - * ECDSA configure register - */ -#define ECDSA_CONF_REG (DR_REG_ECDSA_BASE + 0x4) -/** ECDSA_WORK_MODE : R/W; bitpos: [1:0]; default: 0; - * The work mode bits of ECDSA Accelerator. 0: Signature Verify Mode. 1: Signature - * Generate Mode. 2: Export Public Key Mode. 3: invalid. - */ -#define ECDSA_WORK_MODE 0x00000003U -#define ECDSA_WORK_MODE_M (ECDSA_WORK_MODE_V << ECDSA_WORK_MODE_S) -#define ECDSA_WORK_MODE_V 0x00000003U -#define ECDSA_WORK_MODE_S 0 -/** ECDSA_ECC_CURVE : R/W; bitpos: [3:2]; default: 0; - * The ecc curve select bit of ECDSA Accelerator. 0: P-192. 1: P-256. 2: P-384 3: SM2. - */ -#define ECDSA_ECC_CURVE 0x00000003U -#define ECDSA_ECC_CURVE_M (ECDSA_ECC_CURVE_V << ECDSA_ECC_CURVE_S) -#define ECDSA_ECC_CURVE_V 0x00000003U -#define ECDSA_ECC_CURVE_S 2 -/** ECDSA_SOFTWARE_SET_K : R/W; bitpos: [4]; default: 0; - * The source of k select bit. 0: k is automatically generated by hardware. 1: k is - * written by software. - */ -#define ECDSA_SOFTWARE_SET_K (BIT(4)) -#define ECDSA_SOFTWARE_SET_K_M (ECDSA_SOFTWARE_SET_K_V << ECDSA_SOFTWARE_SET_K_S) -#define ECDSA_SOFTWARE_SET_K_V 0x00000001U -#define ECDSA_SOFTWARE_SET_K_S 4 -/** ECDSA_SOFTWARE_SET_Z : R/W; bitpos: [5]; default: 0; - * The source of z select bit. 0: z is generated from SHA result. 1: z is written by - * software. - */ -#define ECDSA_SOFTWARE_SET_Z (BIT(5)) -#define ECDSA_SOFTWARE_SET_Z_M (ECDSA_SOFTWARE_SET_Z_V << ECDSA_SOFTWARE_SET_Z_S) -#define ECDSA_SOFTWARE_SET_Z_V 0x00000001U -#define ECDSA_SOFTWARE_SET_Z_S 5 -/** ECDSA_DETERMINISTIC_K : R/W; bitpos: [6]; default: 0; - * The source of hardware generated k. 0: k is generated by TRNG. 1: k is generated by - * deterministic derivation algorithm. - */ -#define ECDSA_DETERMINISTIC_K (BIT(6)) -#define ECDSA_DETERMINISTIC_K_M (ECDSA_DETERMINISTIC_K_V << ECDSA_DETERMINISTIC_K_S) -#define ECDSA_DETERMINISTIC_K_V 0x00000001U -#define ECDSA_DETERMINISTIC_K_S 6 - -/** ECDSA_CLK_REG register - * ECDSA clock gate register - */ -#define ECDSA_CLK_REG (DR_REG_ECDSA_BASE + 0x8) -/** ECDSA_CLK_GATE_FORCE_ON : R/W; bitpos: [0]; default: 0; - * Write 1 to force on register clock gate. - */ -#define ECDSA_CLK_GATE_FORCE_ON (BIT(0)) -#define ECDSA_CLK_GATE_FORCE_ON_M (ECDSA_CLK_GATE_FORCE_ON_V << ECDSA_CLK_GATE_FORCE_ON_S) -#define ECDSA_CLK_GATE_FORCE_ON_V 0x00000001U -#define ECDSA_CLK_GATE_FORCE_ON_S 0 - -/** ECDSA_INT_RAW_REG register - * ECDSA interrupt raw register, valid in level. - */ -#define ECDSA_INT_RAW_REG (DR_REG_ECDSA_BASE + 0xc) -/** ECDSA_PREP_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0; - * The raw interrupt status bit for the ecdsa_prep_done_int interrupt - */ -#define ECDSA_PREP_DONE_INT_RAW (BIT(0)) -#define ECDSA_PREP_DONE_INT_RAW_M (ECDSA_PREP_DONE_INT_RAW_V << ECDSA_PREP_DONE_INT_RAW_S) -#define ECDSA_PREP_DONE_INT_RAW_V 0x00000001U -#define ECDSA_PREP_DONE_INT_RAW_S 0 -/** ECDSA_PROC_DONE_INT_RAW : RO/WTC/SS; bitpos: [1]; default: 0; - * The raw interrupt status bit for the ecdsa_proc_done_int interrupt - */ -#define ECDSA_PROC_DONE_INT_RAW (BIT(1)) -#define ECDSA_PROC_DONE_INT_RAW_M (ECDSA_PROC_DONE_INT_RAW_V << ECDSA_PROC_DONE_INT_RAW_S) -#define ECDSA_PROC_DONE_INT_RAW_V 0x00000001U -#define ECDSA_PROC_DONE_INT_RAW_S 1 -/** ECDSA_POST_DONE_INT_RAW : RO/WTC/SS; bitpos: [2]; default: 0; - * The raw interrupt status bit for the ecdsa_post_done_int interrupt - */ -#define ECDSA_POST_DONE_INT_RAW (BIT(2)) -#define ECDSA_POST_DONE_INT_RAW_M (ECDSA_POST_DONE_INT_RAW_V << ECDSA_POST_DONE_INT_RAW_S) -#define ECDSA_POST_DONE_INT_RAW_V 0x00000001U -#define ECDSA_POST_DONE_INT_RAW_S 2 -/** ECDSA_SHA_RELEASE_INT_RAW : RO/WTC/SS; bitpos: [3]; default: 0; - * The raw interrupt status bit for the ecdsa_sha_release_int interrupt - */ -#define ECDSA_SHA_RELEASE_INT_RAW (BIT(3)) -#define ECDSA_SHA_RELEASE_INT_RAW_M (ECDSA_SHA_RELEASE_INT_RAW_V << ECDSA_SHA_RELEASE_INT_RAW_S) -#define ECDSA_SHA_RELEASE_INT_RAW_V 0x00000001U -#define ECDSA_SHA_RELEASE_INT_RAW_S 3 - -/** ECDSA_INT_ST_REG register - * ECDSA interrupt status register. - */ -#define ECDSA_INT_ST_REG (DR_REG_ECDSA_BASE + 0x10) -/** ECDSA_PREP_DONE_INT_ST : RO; bitpos: [0]; default: 0; - * The masked interrupt status bit for the ecdsa_prep_done_int interrupt - */ -#define ECDSA_PREP_DONE_INT_ST (BIT(0)) -#define ECDSA_PREP_DONE_INT_ST_M (ECDSA_PREP_DONE_INT_ST_V << ECDSA_PREP_DONE_INT_ST_S) -#define ECDSA_PREP_DONE_INT_ST_V 0x00000001U -#define ECDSA_PREP_DONE_INT_ST_S 0 -/** ECDSA_PROC_DONE_INT_ST : RO; bitpos: [1]; default: 0; - * The masked interrupt status bit for the ecdsa_proc_done_int interrupt - */ -#define ECDSA_PROC_DONE_INT_ST (BIT(1)) -#define ECDSA_PROC_DONE_INT_ST_M (ECDSA_PROC_DONE_INT_ST_V << ECDSA_PROC_DONE_INT_ST_S) -#define ECDSA_PROC_DONE_INT_ST_V 0x00000001U -#define ECDSA_PROC_DONE_INT_ST_S 1 -/** ECDSA_POST_DONE_INT_ST : RO; bitpos: [2]; default: 0; - * The masked interrupt status bit for the ecdsa_post_done_int interrupt - */ -#define ECDSA_POST_DONE_INT_ST (BIT(2)) -#define ECDSA_POST_DONE_INT_ST_M (ECDSA_POST_DONE_INT_ST_V << ECDSA_POST_DONE_INT_ST_S) -#define ECDSA_POST_DONE_INT_ST_V 0x00000001U -#define ECDSA_POST_DONE_INT_ST_S 2 -/** ECDSA_SHA_RELEASE_INT_ST : RO; bitpos: [3]; default: 0; - * The masked interrupt status bit for the ecdsa_sha_release_int interrupt - */ -#define ECDSA_SHA_RELEASE_INT_ST (BIT(3)) -#define ECDSA_SHA_RELEASE_INT_ST_M (ECDSA_SHA_RELEASE_INT_ST_V << ECDSA_SHA_RELEASE_INT_ST_S) -#define ECDSA_SHA_RELEASE_INT_ST_V 0x00000001U -#define ECDSA_SHA_RELEASE_INT_ST_S 3 - -/** ECDSA_INT_ENA_REG register - * ECDSA interrupt enable register. - */ -#define ECDSA_INT_ENA_REG (DR_REG_ECDSA_BASE + 0x14) -/** ECDSA_PREP_DONE_INT_ENA : R/W; bitpos: [0]; default: 0; - * The interrupt enable bit for the ecdsa_prep_done_int interrupt - */ -#define ECDSA_PREP_DONE_INT_ENA (BIT(0)) -#define ECDSA_PREP_DONE_INT_ENA_M (ECDSA_PREP_DONE_INT_ENA_V << ECDSA_PREP_DONE_INT_ENA_S) -#define ECDSA_PREP_DONE_INT_ENA_V 0x00000001U -#define ECDSA_PREP_DONE_INT_ENA_S 0 -/** ECDSA_PROC_DONE_INT_ENA : R/W; bitpos: [1]; default: 0; - * The interrupt enable bit for the ecdsa_proc_done_int interrupt - */ -#define ECDSA_PROC_DONE_INT_ENA (BIT(1)) -#define ECDSA_PROC_DONE_INT_ENA_M (ECDSA_PROC_DONE_INT_ENA_V << ECDSA_PROC_DONE_INT_ENA_S) -#define ECDSA_PROC_DONE_INT_ENA_V 0x00000001U -#define ECDSA_PROC_DONE_INT_ENA_S 1 -/** ECDSA_POST_DONE_INT_ENA : R/W; bitpos: [2]; default: 0; - * The interrupt enable bit for the ecdsa_post_done_int interrupt - */ -#define ECDSA_POST_DONE_INT_ENA (BIT(2)) -#define ECDSA_POST_DONE_INT_ENA_M (ECDSA_POST_DONE_INT_ENA_V << ECDSA_POST_DONE_INT_ENA_S) -#define ECDSA_POST_DONE_INT_ENA_V 0x00000001U -#define ECDSA_POST_DONE_INT_ENA_S 2 -/** ECDSA_SHA_RELEASE_INT_ENA : R/W; bitpos: [3]; default: 0; - * The interrupt enable bit for the ecdsa_sha_release_int interrupt - */ -#define ECDSA_SHA_RELEASE_INT_ENA (BIT(3)) -#define ECDSA_SHA_RELEASE_INT_ENA_M (ECDSA_SHA_RELEASE_INT_ENA_V << ECDSA_SHA_RELEASE_INT_ENA_S) -#define ECDSA_SHA_RELEASE_INT_ENA_V 0x00000001U -#define ECDSA_SHA_RELEASE_INT_ENA_S 3 - -/** ECDSA_INT_CLR_REG register - * ECDSA interrupt clear register. - */ -#define ECDSA_INT_CLR_REG (DR_REG_ECDSA_BASE + 0x18) -/** ECDSA_PREP_DONE_INT_CLR : WT; bitpos: [0]; default: 0; - * Set this bit to clear the ecdsa_prep_done_int interrupt - */ -#define ECDSA_PREP_DONE_INT_CLR (BIT(0)) -#define ECDSA_PREP_DONE_INT_CLR_M (ECDSA_PREP_DONE_INT_CLR_V << ECDSA_PREP_DONE_INT_CLR_S) -#define ECDSA_PREP_DONE_INT_CLR_V 0x00000001U -#define ECDSA_PREP_DONE_INT_CLR_S 0 -/** ECDSA_PROC_DONE_INT_CLR : WT; bitpos: [1]; default: 0; - * Set this bit to clear the ecdsa_proc_done_int interrupt - */ -#define ECDSA_PROC_DONE_INT_CLR (BIT(1)) -#define ECDSA_PROC_DONE_INT_CLR_M (ECDSA_PROC_DONE_INT_CLR_V << ECDSA_PROC_DONE_INT_CLR_S) -#define ECDSA_PROC_DONE_INT_CLR_V 0x00000001U -#define ECDSA_PROC_DONE_INT_CLR_S 1 -/** ECDSA_POST_DONE_INT_CLR : WT; bitpos: [2]; default: 0; - * Set this bit to clear the ecdsa_post_done_int interrupt - */ -#define ECDSA_POST_DONE_INT_CLR (BIT(2)) -#define ECDSA_POST_DONE_INT_CLR_M (ECDSA_POST_DONE_INT_CLR_V << ECDSA_POST_DONE_INT_CLR_S) -#define ECDSA_POST_DONE_INT_CLR_V 0x00000001U -#define ECDSA_POST_DONE_INT_CLR_S 2 -/** ECDSA_SHA_RELEASE_INT_CLR : WT; bitpos: [3]; default: 0; - * Set this bit to clear the ecdsa_sha_release_int interrupt - */ -#define ECDSA_SHA_RELEASE_INT_CLR (BIT(3)) -#define ECDSA_SHA_RELEASE_INT_CLR_M (ECDSA_SHA_RELEASE_INT_CLR_V << ECDSA_SHA_RELEASE_INT_CLR_S) -#define ECDSA_SHA_RELEASE_INT_CLR_V 0x00000001U -#define ECDSA_SHA_RELEASE_INT_CLR_S 3 - -/** ECDSA_START_REG register - * ECDSA start register - */ -#define ECDSA_START_REG (DR_REG_ECDSA_BASE + 0x1c) -/** ECDSA_START : WT; bitpos: [0]; default: 0; - * Write 1 to start calculation of ECDSA Accelerator. This bit will be self-cleared - * after configuration. - */ -#define ECDSA_START (BIT(0)) -#define ECDSA_START_M (ECDSA_START_V << ECDSA_START_S) -#define ECDSA_START_V 0x00000001U -#define ECDSA_START_S 0 -/** ECDSA_LOAD_DONE : WT; bitpos: [1]; default: 0; - * Write 1 to input load done signal of ECDSA Accelerator. This bit will be - * self-cleared after configuration. - */ -#define ECDSA_LOAD_DONE (BIT(1)) -#define ECDSA_LOAD_DONE_M (ECDSA_LOAD_DONE_V << ECDSA_LOAD_DONE_S) -#define ECDSA_LOAD_DONE_V 0x00000001U -#define ECDSA_LOAD_DONE_S 1 -/** ECDSA_GET_DONE : WT; bitpos: [2]; default: 0; - * Write 1 to input get done signal of ECDSA Accelerator. This bit will be - * self-cleared after configuration. - */ -#define ECDSA_GET_DONE (BIT(2)) -#define ECDSA_GET_DONE_M (ECDSA_GET_DONE_V << ECDSA_GET_DONE_S) -#define ECDSA_GET_DONE_V 0x00000001U -#define ECDSA_GET_DONE_S 2 - -/** ECDSA_STATE_REG register - * ECDSA status register - */ -#define ECDSA_STATE_REG (DR_REG_ECDSA_BASE + 0x20) -/** ECDSA_BUSY : RO; bitpos: [1:0]; default: 0; - * The status bits of ECDSA Accelerator. ECDSA is at 0: IDLE, 1: LOAD, 2: GET, 3: BUSY - * state. - */ -#define ECDSA_BUSY 0x00000003U -#define ECDSA_BUSY_M (ECDSA_BUSY_V << ECDSA_BUSY_S) -#define ECDSA_BUSY_V 0x00000003U -#define ECDSA_BUSY_S 0 - -/** ECDSA_RESULT_REG register - * ECDSA result register - */ -#define ECDSA_RESULT_REG (DR_REG_ECDSA_BASE + 0x24) -/** ECDSA_OPERATION_RESULT : RO/SS; bitpos: [0]; default: 0; - * The operation result bit of ECDSA Accelerator, only valid when ECDSA calculation is - * done. - */ -#define ECDSA_OPERATION_RESULT (BIT(0)) -#define ECDSA_OPERATION_RESULT_M (ECDSA_OPERATION_RESULT_V << ECDSA_OPERATION_RESULT_S) -#define ECDSA_OPERATION_RESULT_V 0x00000001U -#define ECDSA_OPERATION_RESULT_S 0 - -/** ECDSA_DATE_REG register - * Version control register - */ -#define ECDSA_DATE_REG (DR_REG_ECDSA_BASE + 0xfc) -/** ECDSA_DATE : R/W; bitpos: [27:0]; default: 37785984; - * ECDSA version control register - */ -#define ECDSA_DATE 0x0FFFFFFFU -#define ECDSA_DATE_M (ECDSA_DATE_V << ECDSA_DATE_S) -#define ECDSA_DATE_V 0x0FFFFFFFU -#define ECDSA_DATE_S 0 - -/** ECDSA_SHA_MODE_REG register - * ECDSA control SHA register - */ -#define ECDSA_SHA_MODE_REG (DR_REG_ECDSA_BASE + 0x200) -/** ECDSA_SHA_MODE : R/W; bitpos: [3:0]; default: 0; - * The work mode bits of SHA Calculator in ECDSA Accelerator. 0: SHA1. 1: SHA-224. 2: - * SHA-256. 3: SHA-384 4: SHA-512. 5: SHA-512224. 6: SHA-512256. 14:SM3. Others: - * invalid. - */ -#define ECDSA_SHA_MODE 0x0000000FU -#define ECDSA_SHA_MODE_M (ECDSA_SHA_MODE_V << ECDSA_SHA_MODE_S) -#define ECDSA_SHA_MODE_V 0x0000000FU -#define ECDSA_SHA_MODE_S 0 - -/** ECDSA_SHA_START_REG register - * ECDSA control SHA register - */ -#define ECDSA_SHA_START_REG (DR_REG_ECDSA_BASE + 0x210) -/** ECDSA_SHA_START : WT; bitpos: [0]; default: 0; - * Write 1 to start the first calculation of SHA Calculator in ECDSA Accelerator. This - * bit will be self-cleared after configuration. - */ -#define ECDSA_SHA_START (BIT(0)) -#define ECDSA_SHA_START_M (ECDSA_SHA_START_V << ECDSA_SHA_START_S) -#define ECDSA_SHA_START_V 0x00000001U -#define ECDSA_SHA_START_S 0 - -/** ECDSA_SHA_CONTINUE_REG register - * ECDSA control SHA register - */ -#define ECDSA_SHA_CONTINUE_REG (DR_REG_ECDSA_BASE + 0x214) -/** ECDSA_SHA_CONTINUE : WT; bitpos: [0]; default: 0; - * Write 1 to start the latter calculation of SHA Calculator in ECDSA Accelerator. This - * bit will be self-cleared after configuration. - */ -#define ECDSA_SHA_CONTINUE (BIT(0)) -#define ECDSA_SHA_CONTINUE_M (ECDSA_SHA_CONTINUE_V << ECDSA_SHA_CONTINUE_S) -#define ECDSA_SHA_CONTINUE_V 0x00000001U -#define ECDSA_SHA_CONTINUE_S 0 - -/** ECDSA_SHA_BUSY_REG register - * ECDSA status register - */ -#define ECDSA_SHA_BUSY_REG (DR_REG_ECDSA_BASE + 0x218) -/** ECDSA_SHA_BUSY : RO; bitpos: [0]; default: 0; - * The busy status bit of SHA Calculator in ECDSA Accelerator. 1:SHA is in - * calculation. 0: SHA is idle. - */ -#define ECDSA_SHA_BUSY (BIT(0)) -#define ECDSA_SHA_BUSY_M (ECDSA_SHA_BUSY_V << ECDSA_SHA_BUSY_S) -#define ECDSA_SHA_BUSY_V 0x00000001U -#define ECDSA_SHA_BUSY_S 0 - -/** ECDSA_MESSAGE_MEM register - * The memory that stores message. - */ -#define ECDSA_MESSAGE_MEM (DR_REG_ECDSA_BASE + 0x280) -#define ECDSA_MESSAGE_MEM_SIZE_BYTES 64 - -/** ECDSA_R_MEM register - * The memory that stores r. - */ -#define ECDSA_R_MEM (DR_REG_ECDSA_BASE + 0x3e0) -#define ECDSA_R_MEM_SIZE_BYTES 48 - -/** ECDSA_S_MEM register - * The memory that stores s. - */ -#define ECDSA_S_MEM (DR_REG_ECDSA_BASE + 0x410) -#define ECDSA_S_MEM_SIZE_BYTES 48 - -/** ECDSA_Z_MEM register - * The memory that stores software written z. - */ -#define ECDSA_Z_MEM (DR_REG_ECDSA_BASE + 0x440) -#define ECDSA_Z_MEM_SIZE_BYTES 48 - -/** ECDSA_QAX_MEM register - * The memory that stores x coordinates of QA or software written k. - */ -#define ECDSA_QAX_MEM (DR_REG_ECDSA_BASE + 0x470) -#define ECDSA_QAX_MEM_SIZE_BYTES 48 - -/** ECDSA_QAY_MEM register - * The memory that stores y coordinates of QA. - */ -#define ECDSA_QAY_MEM (DR_REG_ECDSA_BASE + 0x4a0) -#define ECDSA_QAY_MEM_SIZE_BYTES 48 - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32c5/register/soc/ecdsa_struct.h b/components/soc/esp32c5/register/soc/ecdsa_struct.h index 858a4ffc5f..6659f30a90 100644 --- a/components/soc/esp32c5/register/soc/ecdsa_struct.h +++ b/components/soc/esp32c5/register/soc/ecdsa_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -23,30 +23,26 @@ typedef union { * Generate Mode. 2: Export Public Key Mode. 3: invalid. */ uint32_t work_mode:2; - /** ecc_curve : R/W; bitpos: [2]; default: 0; - * The ecc curve select bit of ECDSA Accelerator. 0: P-192. 1: P-256. + /** ecc_curve : R/W; bitpos: [3:2]; default: 0; + * The ecc curve select bit of ECDSA Accelerator. 0: P-192. 1: P-256. 2: P-384 3: SM2. */ - uint32_t ecc_curve:1; - /** software_set_k : R/W; bitpos: [3]; default: 0; + uint32_t ecc_curve:2; + /** software_set_k : R/W; bitpos: [4]; default: 0; * The source of k select bit. 0: k is automatically generated by hardware. 1: k is * written by software. */ uint32_t software_set_k:1; - /** software_set_z : R/W; bitpos: [4]; default: 0; + /** software_set_z : R/W; bitpos: [5]; default: 0; * The source of z select bit. 0: z is generated from SHA result. 1: z is written by * software. */ uint32_t software_set_z:1; - /** deterministic_k : R/W; bitpos: [5]; default: 0; + /** deterministic_k : R/W; bitpos: [6]; default: 0; * The source of hardware generated k. 0: k is generated by TRNG. 1: k is generated by * deterministic derivation algorithm. */ uint32_t deterministic_k:1; - /** deterministic_loop : R/W; bitpos: [21:6]; default: 0; - * The (loop number - 1) value in the deterministic derivation algorithm to derive k. - */ - uint32_t deterministic_loop:16; - uint32_t reserved_22:10; + uint32_t reserved_7:25; }; uint32_t val; } ecdsa_conf_reg_t; @@ -227,12 +223,7 @@ typedef union { * done. */ uint32_t operation_result:1; - /** k_value_warning : RO/SS; bitpos: [1]; default: 0; - * The k value warning bit of ECDSA Accelerator, valid when k value is bigger than the - * curve order, then actually taken k = k mod n. - */ - uint32_t k_value_warning:1; - uint32_t reserved_2:30; + uint32_t reserved_1:31; }; uint32_t val; } ecdsa_result_reg_t; @@ -244,12 +235,13 @@ typedef union { */ typedef union { struct { - /** sha_mode : R/W; bitpos: [2:0]; default: 0; - * The work mode bits of SHA Calculator in ECDSA Accelerator. 1: SHA-224. 2: SHA-256. - * Others: invalid. + /** sha_mode : R/W; bitpos: [3:0]; default: 0; + * The work mode bits of SHA Calculator in ECDSA Accelerator. 0: SHA1. 1: SHA-224. 2: + * SHA-256. 3: SHA-384 4: SHA-512. 5: SHA-512224. 6: SHA-512256. 14:SM3. Others: + * invalid. */ - uint32_t sha_mode:3; - uint32_t reserved_3:29; + uint32_t sha_mode:4; + uint32_t reserved_4:28; }; uint32_t val; } ecdsa_sha_mode_reg_t; @@ -306,7 +298,7 @@ typedef union { */ typedef union { struct { - /** date : R/W; bitpos: [27:0]; default: 36725040; + /** date : R/W; bitpos: [27:0]; default: 37785984; * ECDSA version control register */ uint32_t date:28; @@ -336,19 +328,19 @@ typedef struct { volatile ecdsa_sha_continue_reg_t sha_continue; volatile ecdsa_sha_busy_reg_t sha_busy; uint32_t reserved_21c[25]; - volatile uint32_t message[8]; - uint32_t reserved_2a0[40]; - volatile uint32_t r[8]; - volatile uint32_t s[8]; - volatile uint32_t z[8]; - volatile uint32_t qax[8]; - volatile uint32_t qay[8]; + volatile uint32_t message[16]; + uint32_t reserved_2c0[72]; + volatile uint32_t r[12]; + volatile uint32_t s[12]; + volatile uint32_t z[12]; + volatile uint32_t qax[12]; + volatile uint32_t qay[12]; } ecdsa_dev_t; extern ecdsa_dev_t ECDSA; #ifndef __cplusplus -_Static_assert(sizeof(ecdsa_dev_t) == 0x3e0, "Invalid size of ecdsa_dev_t structure"); +_Static_assert(sizeof(ecdsa_dev_t) == 0x4d0, "Invalid size of ecdsa_dev_t structure"); #endif #ifdef __cplusplus diff --git a/components/soc/esp32c5/register/soc/ecdsa_struct_eco2.h b/components/soc/esp32c5/register/soc/ecdsa_struct_eco2.h deleted file mode 100644 index 6659f30a90..0000000000 --- a/components/soc/esp32c5/register/soc/ecdsa_struct_eco2.h +++ /dev/null @@ -1,348 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#ifdef __cplusplus -extern "C" { -#endif - -/** Group: Data Memory */ - -/** Group: Configuration registers */ -/** Type of conf register - * ECDSA configure register - */ -typedef union { - struct { - /** work_mode : R/W; bitpos: [1:0]; default: 0; - * The work mode bits of ECDSA Accelerator. 0: Signature Verify Mode. 1: Signature - * Generate Mode. 2: Export Public Key Mode. 3: invalid. - */ - uint32_t work_mode:2; - /** ecc_curve : R/W; bitpos: [3:2]; default: 0; - * The ecc curve select bit of ECDSA Accelerator. 0: P-192. 1: P-256. 2: P-384 3: SM2. - */ - uint32_t ecc_curve:2; - /** software_set_k : R/W; bitpos: [4]; default: 0; - * The source of k select bit. 0: k is automatically generated by hardware. 1: k is - * written by software. - */ - uint32_t software_set_k:1; - /** software_set_z : R/W; bitpos: [5]; default: 0; - * The source of z select bit. 0: z is generated from SHA result. 1: z is written by - * software. - */ - uint32_t software_set_z:1; - /** deterministic_k : R/W; bitpos: [6]; default: 0; - * The source of hardware generated k. 0: k is generated by TRNG. 1: k is generated by - * deterministic derivation algorithm. - */ - uint32_t deterministic_k:1; - uint32_t reserved_7:25; - }; - uint32_t val; -} ecdsa_conf_reg_t; - -/** Type of start register - * ECDSA start register - */ -typedef union { - struct { - /** start : WT; bitpos: [0]; default: 0; - * Write 1 to start calculation of ECDSA Accelerator. This bit will be self-cleared - * after configuration. - */ - uint32_t start:1; - /** load_done : WT; bitpos: [1]; default: 0; - * Write 1 to input load done signal of ECDSA Accelerator. This bit will be - * self-cleared after configuration. - */ - uint32_t load_done:1; - /** get_done : WT; bitpos: [2]; default: 0; - * Write 1 to input get done signal of ECDSA Accelerator. This bit will be - * self-cleared after configuration. - */ - uint32_t get_done:1; - uint32_t reserved_3:29; - }; - uint32_t val; -} ecdsa_start_reg_t; - - -/** Group: Clock and reset registers */ -/** Type of clk register - * ECDSA clock gate register - */ -typedef union { - struct { - /** clk_gate_force_on : R/W; bitpos: [0]; default: 0; - * Write 1 to force on register clock gate. - */ - uint32_t clk_gate_force_on:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} ecdsa_clk_reg_t; - - -/** Group: Interrupt registers */ -/** Type of int_raw register - * ECDSA interrupt raw register, valid in level. - */ -typedef union { - struct { - /** prep_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0; - * The raw interrupt status bit for the ecdsa_prep_done_int interrupt - */ - uint32_t prep_done_int_raw:1; - /** proc_done_int_raw : RO/WTC/SS; bitpos: [1]; default: 0; - * The raw interrupt status bit for the ecdsa_proc_done_int interrupt - */ - uint32_t proc_done_int_raw:1; - /** post_done_int_raw : RO/WTC/SS; bitpos: [2]; default: 0; - * The raw interrupt status bit for the ecdsa_post_done_int interrupt - */ - uint32_t post_done_int_raw:1; - /** sha_release_int_raw : RO/WTC/SS; bitpos: [3]; default: 0; - * The raw interrupt status bit for the ecdsa_sha_release_int interrupt - */ - uint32_t sha_release_int_raw:1; - uint32_t reserved_4:28; - }; - uint32_t val; -} ecdsa_int_raw_reg_t; - -/** Type of int_st register - * ECDSA interrupt status register. - */ -typedef union { - struct { - /** prep_done_int_st : RO; bitpos: [0]; default: 0; - * The masked interrupt status bit for the ecdsa_prep_done_int interrupt - */ - uint32_t prep_done_int_st:1; - /** proc_done_int_st : RO; bitpos: [1]; default: 0; - * The masked interrupt status bit for the ecdsa_proc_done_int interrupt - */ - uint32_t proc_done_int_st:1; - /** post_done_int_st : RO; bitpos: [2]; default: 0; - * The masked interrupt status bit for the ecdsa_post_done_int interrupt - */ - uint32_t post_done_int_st:1; - /** sha_release_int_st : RO; bitpos: [3]; default: 0; - * The masked interrupt status bit for the ecdsa_sha_release_int interrupt - */ - uint32_t sha_release_int_st:1; - uint32_t reserved_4:28; - }; - uint32_t val; -} ecdsa_int_st_reg_t; - -/** Type of int_ena register - * ECDSA interrupt enable register. - */ -typedef union { - struct { - /** prep_done_int_ena : R/W; bitpos: [0]; default: 0; - * The interrupt enable bit for the ecdsa_prep_done_int interrupt - */ - uint32_t prep_done_int_ena:1; - /** proc_done_int_ena : R/W; bitpos: [1]; default: 0; - * The interrupt enable bit for the ecdsa_proc_done_int interrupt - */ - uint32_t proc_done_int_ena:1; - /** post_done_int_ena : R/W; bitpos: [2]; default: 0; - * The interrupt enable bit for the ecdsa_post_done_int interrupt - */ - uint32_t post_done_int_ena:1; - /** sha_release_int_ena : R/W; bitpos: [3]; default: 0; - * The interrupt enable bit for the ecdsa_sha_release_int interrupt - */ - uint32_t sha_release_int_ena:1; - uint32_t reserved_4:28; - }; - uint32_t val; -} ecdsa_int_ena_reg_t; - -/** Type of int_clr register - * ECDSA interrupt clear register. - */ -typedef union { - struct { - /** prep_done_int_clr : WT; bitpos: [0]; default: 0; - * Set this bit to clear the ecdsa_prep_done_int interrupt - */ - uint32_t prep_done_int_clr:1; - /** proc_done_int_clr : WT; bitpos: [1]; default: 0; - * Set this bit to clear the ecdsa_proc_done_int interrupt - */ - uint32_t proc_done_int_clr:1; - /** post_done_int_clr : WT; bitpos: [2]; default: 0; - * Set this bit to clear the ecdsa_post_done_int interrupt - */ - uint32_t post_done_int_clr:1; - /** sha_release_int_clr : WT; bitpos: [3]; default: 0; - * Set this bit to clear the ecdsa_sha_release_int interrupt - */ - uint32_t sha_release_int_clr:1; - uint32_t reserved_4:28; - }; - uint32_t val; -} ecdsa_int_clr_reg_t; - - -/** Group: Status registers */ -/** Type of state register - * ECDSA status register - */ -typedef union { - struct { - /** busy : RO; bitpos: [1:0]; default: 0; - * The status bits of ECDSA Accelerator. ECDSA is at 0: IDLE, 1: LOAD, 2: GET, 3: BUSY - * state. - */ - uint32_t busy:2; - uint32_t reserved_2:30; - }; - uint32_t val; -} ecdsa_state_reg_t; - - -/** Group: Result registers */ -/** Type of result register - * ECDSA result register - */ -typedef union { - struct { - /** operation_result : RO/SS; bitpos: [0]; default: 0; - * The operation result bit of ECDSA Accelerator, only valid when ECDSA calculation is - * done. - */ - uint32_t operation_result:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} ecdsa_result_reg_t; - - -/** Group: SHA register */ -/** Type of sha_mode register - * ECDSA control SHA register - */ -typedef union { - struct { - /** sha_mode : R/W; bitpos: [3:0]; default: 0; - * The work mode bits of SHA Calculator in ECDSA Accelerator. 0: SHA1. 1: SHA-224. 2: - * SHA-256. 3: SHA-384 4: SHA-512. 5: SHA-512224. 6: SHA-512256. 14:SM3. Others: - * invalid. - */ - uint32_t sha_mode:4; - uint32_t reserved_4:28; - }; - uint32_t val; -} ecdsa_sha_mode_reg_t; - -/** Type of sha_start register - * ECDSA control SHA register - */ -typedef union { - struct { - /** sha_start : WT; bitpos: [0]; default: 0; - * Write 1 to start the first calculation of SHA Calculator in ECDSA Accelerator. This - * bit will be self-cleared after configuration. - */ - uint32_t sha_start:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} ecdsa_sha_start_reg_t; - -/** Type of sha_continue register - * ECDSA control SHA register - */ -typedef union { - struct { - /** sha_continue : WT; bitpos: [0]; default: 0; - * Write 1 to start the latter calculation of SHA Calculator in ECDSA Accelerator. This - * bit will be self-cleared after configuration. - */ - uint32_t sha_continue:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} ecdsa_sha_continue_reg_t; - -/** Type of sha_busy register - * ECDSA status register - */ -typedef union { - struct { - /** sha_busy : RO; bitpos: [0]; default: 0; - * The busy status bit of SHA Calculator in ECDSA Accelerator. 1:SHA is in - * calculation. 0: SHA is idle. - */ - uint32_t sha_busy:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} ecdsa_sha_busy_reg_t; - - -/** Group: Version register */ -/** Type of date register - * Version control register - */ -typedef union { - struct { - /** date : R/W; bitpos: [27:0]; default: 37785984; - * ECDSA version control register - */ - uint32_t date:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} ecdsa_date_reg_t; - - -typedef struct { - uint32_t reserved_000; - volatile ecdsa_conf_reg_t conf; - volatile ecdsa_clk_reg_t clk; - volatile ecdsa_int_raw_reg_t int_raw; - volatile ecdsa_int_st_reg_t int_st; - volatile ecdsa_int_ena_reg_t int_ena; - volatile ecdsa_int_clr_reg_t int_clr; - volatile ecdsa_start_reg_t start; - volatile ecdsa_state_reg_t state; - volatile ecdsa_result_reg_t result; - uint32_t reserved_028[53]; - volatile ecdsa_date_reg_t date; - uint32_t reserved_100[64]; - volatile ecdsa_sha_mode_reg_t sha_mode; - uint32_t reserved_204[3]; - volatile ecdsa_sha_start_reg_t sha_start; - volatile ecdsa_sha_continue_reg_t sha_continue; - volatile ecdsa_sha_busy_reg_t sha_busy; - uint32_t reserved_21c[25]; - volatile uint32_t message[16]; - uint32_t reserved_2c0[72]; - volatile uint32_t r[12]; - volatile uint32_t s[12]; - volatile uint32_t z[12]; - volatile uint32_t qax[12]; - volatile uint32_t qay[12]; -} ecdsa_dev_t; - -extern ecdsa_dev_t ECDSA; - -#ifndef __cplusplus -_Static_assert(sizeof(ecdsa_dev_t) == 0x4d0, "Invalid size of ecdsa_dev_t structure"); -#endif - -#ifdef __cplusplus -} -#endif