diff --git a/components/esp_rom/esp32p4/Kconfig.soc_caps.in b/components/esp_rom/esp32p4/Kconfig.soc_caps.in index 1e974a07aa..ec068d6ac8 100644 --- a/components/esp_rom/esp32p4/Kconfig.soc_caps.in +++ b/components/esp_rom/esp32p4/Kconfig.soc_caps.in @@ -50,3 +50,7 @@ config ESP_ROM_WDT_INIT_PATCH config ESP_ROM_HAS_LP_ROM bool default y + +config ESP_ROM_WITHOUT_REGI2C + bool + default y diff --git a/components/esp_rom/esp32p4/esp_rom_caps.h b/components/esp_rom/esp32p4/esp_rom_caps.h index 88dc6bd3b2..3f9478162f 100644 --- a/components/esp_rom/esp32p4/esp_rom_caps.h +++ b/components/esp_rom/esp32p4/esp_rom_caps.h @@ -18,3 +18,4 @@ #define ESP_ROM_HAS_LAYOUT_TABLE (1) // ROM has the layout table #define ESP_ROM_WDT_INIT_PATCH (1) // ROM version does not configure the clock #define ESP_ROM_HAS_LP_ROM (1) // ROM also has a LP ROM placed in LP memory +#define ESP_ROM_WITHOUT_REGI2C (1) // ROM has no regi2c APIs diff --git a/components/esp_rom/patches/esp_rom_regi2c_esp32p4.c b/components/esp_rom/patches/esp_rom_regi2c_esp32p4.c new file mode 100644 index 0000000000..08fff85a74 --- /dev/null +++ b/components/esp_rom/patches/esp_rom_regi2c_esp32p4.c @@ -0,0 +1,194 @@ +/* + * SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "esp_rom_sys.h" +#include "esp_attr.h" +#include "soc/i2c_ana_mst_reg.h" +#include "soc/lpperi_reg.h" +/** + * DIG_REG - 0x6D - BIT10 + * PLL_CPU - 0x67 - BIT11 + * PLL_SDIO - 0x62 - BIT6 + * BIAS - 0x6A - BIT12 + * MSPI_XTAL - 0x63 - BIT9 + * PLL_SYS - 0x66 - BIT5 + * PLLA - 0x6F - BIT8 + * SAR_I2C - 0x69 - BIT7 +*/ + +#define REGI2C_DIG_REG_MST_SEL (BIT(10)) +#define REGI2C_PLL_CPU_MST_SEL (BIT(11)) +#define REGI2C_PLL_SDIO_MST_SEL (BIT(6)) +#define REGI2C_BIAS_MST_SEL (BIT(12)) +#define REGI2C_MSPI_XTAL_MST_SEL (BIT(9)) +#define REGI2C_PLL_SYS_MST_SEL (BIT(5)) +#define REGI2C_PLLA_MST_SEL (BIT(8)) +#define REGI2C_SAR_I2C_MST_SEL (BIT(7)) + +#define I2C_ANA_MST_I2C_CTRL_REG(n) (I2C_ANA_MST_I2C0_CTRL_REG + n*4) // 0: I2C_ANA_MST_I2C0_CTRL_REG; 1: I2C_ANA_MST_I2C1_CTRL_REG + +#define REGI2C_RTC_BUSY (BIT(25)) +#define REGI2C_RTC_BUSY_M (BIT(25)) +#define REGI2C_RTC_BUSY_V 0x1 +#define REGI2C_RTC_BUSY_S 25 + +#define REGI2C_RTC_WR_CNTL (BIT(24)) +#define REGI2C_RTC_WR_CNTL_M (BIT(24)) +#define REGI2C_RTC_WR_CNTL_V 0x1 +#define REGI2C_RTC_WR_CNTL_S 24 + +#define REGI2C_RTC_DATA 0x000000FF +#define REGI2C_RTC_DATA_M ((I2C_RTC_DATA_V)<<(I2C_RTC_DATA_S)) +#define REGI2C_RTC_DATA_V 0xFF +#define REGI2C_RTC_DATA_S 16 + +#define REGI2C_RTC_ADDR 0x000000FF +#define REGI2C_RTC_ADDR_M ((I2C_RTC_ADDR_V)<<(I2C_RTC_ADDR_S)) +#define REGI2C_RTC_ADDR_V 0xFF +#define REGI2C_RTC_ADDR_S 8 + +#define REGI2C_RTC_SLAVE_ID 0x000000FF +#define REGI2C_RTC_SLAVE_ID_M ((I2C_RTC_SLAVE_ID_V)<<(I2C_RTC_SLAVE_ID_S)) +#define REGI2C_RTC_SLAVE_ID_V 0xFF +#define REGI2C_RTC_SLAVE_ID_S 0 + +/* SLAVE */ +#define REGI2C_DIG_REG (0x6d) +#define REGI2C_DIG_REG_HOSTID 0 + +#define REGI2C_CPU_PLL (0x67) +#define REGI2C_CPU_PLL_HOSTID 0 + +#define REGI2C_SDIO_PLL (0x62) +#define REGI2C_SDIO_PLL_HOSTID 0 + +#define REGI2C_BIAS (0x6a) +#define REGI2C_BIAS_HOSTID 0 + +#define REGI2C_MSPI (0x63) +#define REGI2C_MSPI_HOSTID 0 + +#define REGI2C_SYS_PLL (0x66) +#define REGI2C_SYS_PLL_HOSTID 0 + +#define REGI2C_PLLA (0x6f) +#define REGI2C_PLLA_HOSTID 0 + +#define REGI2C_SAR_I2C (0x69) +#define REGI2C_SAR_I2C_HOSTID 0 +/* SLAVE END */ + +uint8_t esp_rom_regi2c_read(uint8_t block, uint8_t host_id, uint8_t reg_add) __attribute__((alias("regi2c_read_impl"))); +uint8_t esp_rom_regi2c_read_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb) __attribute__((alias("regi2c_read_mask_impl"))); +void esp_rom_regi2c_write(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data) __attribute__((alias("regi2c_write_impl"))); +void esp_rom_regi2c_write_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data) __attribute__((alias("regi2c_write_mask_impl"))); + +static IRAM_ATTR uint8_t regi2c_enable_block(uint8_t block) +{ + REG_SET_BIT(LPPERI_CLK_EN_REG, LPPERI_CK_EN_LP_I2CMST); + SET_PERI_REG_MASK(I2C_ANA_MST_CLK160M_REG, I2C_ANA_MST_CLK_I2C_MST_SEL_160M); + REG_SET_FIELD(I2C_ANA_MST_ANA_CONF2_REG, I2C_ANA_MST_ANA_CONF2, 0); + REG_SET_FIELD(I2C_ANA_MST_ANA_CONF1_REG, I2C_ANA_MST_ANA_CONF1, 0); + + switch (block) { + case REGI2C_DIG_REG: + REG_SET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_DIG_REG_MST_SEL); + break; + case REGI2C_CPU_PLL: + REG_SET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_PLL_CPU_MST_SEL); + break; + case REGI2C_SDIO_PLL: + REG_SET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_PLL_SDIO_MST_SEL); + break; + case REGI2C_BIAS: + REG_SET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_BIAS_MST_SEL); + break; + case REGI2C_MSPI: + REG_SET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_MSPI_XTAL_MST_SEL); + break; + case REGI2C_SYS_PLL: + REG_SET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_PLL_SYS_MST_SEL); + break; + case REGI2C_PLLA: + REG_SET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_PLLA_MST_SEL); + break; + case REGI2C_SAR_I2C: + REG_SET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_SAR_I2C_MST_SEL); + break; + } + + return 0; +} + +uint8_t IRAM_ATTR regi2c_read_impl(uint8_t block, uint8_t host_id, uint8_t reg_add) +{ + (void)host_id; + uint8_t i2c_sel = regi2c_enable_block(block); + + while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); // wait i2c idle + uint32_t temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S) + | (reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S; + REG_WRITE(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), temp); + while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); + uint8_t ret = REG_GET_FIELD(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_DATA); + + return ret; +} + +uint8_t IRAM_ATTR regi2c_read_mask_impl(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb) +{ + assert(msb - lsb < 8); + uint8_t i2c_sel = regi2c_enable_block(block); + + (void)host_id; + while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); // wait i2c idle + uint32_t temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S) + | (reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S; + REG_WRITE(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), temp); + while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); + uint32_t data = REG_GET_FIELD(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_DATA); + uint8_t ret = (uint8_t)((data >> lsb) & (~(0xFFFFFFFF << (msb - lsb + 1)))); + + return ret; +} + +void IRAM_ATTR regi2c_write_impl(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data) +{ + (void)host_id; + uint8_t i2c_sel = regi2c_enable_block(block); + + while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); // wait i2c idle + uint32_t temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S) + | ((reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S) + | ((0x1 & REGI2C_RTC_WR_CNTL_V) << REGI2C_RTC_WR_CNTL_S) // 0: READ I2C register; 1: Write I2C register; + | (((uint32_t)data & REGI2C_RTC_DATA_V) << REGI2C_RTC_DATA_S); + REG_WRITE(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), temp); + while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); + +} + +void IRAM_ATTR regi2c_write_mask_impl(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data) +{ + (void)host_id; + assert(msb - lsb < 8); + uint8_t i2c_sel = regi2c_enable_block(block); + + while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); + /*Read the i2c bus register*/ + uint32_t temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S) + | (reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S; + REG_WRITE(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), temp); + while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); + temp = REG_GET_FIELD(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_DATA); + /*Write the i2c bus register*/ + temp &= ((~(0xFFFFFFFF << lsb)) | (0xFFFFFFFF << (msb + 1))); + temp = (((uint32_t)data & (~(0xFFFFFFFF << (msb - lsb + 1)))) << lsb) | temp; + temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S) + | ((reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S) + | ((0x1 & REGI2C_RTC_WR_CNTL_V) << REGI2C_RTC_WR_CNTL_S) + | ((temp & REGI2C_RTC_DATA_V) << REGI2C_RTC_DATA_S); + REG_WRITE(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), temp); + while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); +} diff --git a/components/soc/esp32p4/include/soc/lp_i2c_ana_mst_reg.h b/components/soc/esp32p4/include/soc/lp_i2c_ana_mst_reg.h deleted file mode 100644 index ed40ee7b05..0000000000 --- a/components/soc/esp32p4/include/soc/lp_i2c_ana_mst_reg.h +++ /dev/null @@ -1,135 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#include "soc/soc.h" -#ifdef __cplusplus -extern "C" { -#endif - -/** LP_I2C_ANA_MST_I2C0_CTRL_REG register - * need_des - */ -#define LP_I2C_ANA_MST_I2C0_CTRL_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0x0) -/** LP_I2C_ANA_MST_I2C0_CTRL : R/W; bitpos: [24:0]; default: 0; - * need_des - */ -#define LP_I2C_ANA_MST_I2C0_CTRL 0x01FFFFFFU -#define LP_I2C_ANA_MST_I2C0_CTRL_M (LP_I2C_ANA_MST_I2C0_CTRL_V << LP_I2C_ANA_MST_I2C0_CTRL_S) -#define LP_I2C_ANA_MST_I2C0_CTRL_V 0x01FFFFFFU -#define LP_I2C_ANA_MST_I2C0_CTRL_S 0 -/** LP_I2C_ANA_MST_I2C0_BUSY : RO; bitpos: [25]; default: 0; - * need_des - */ -#define LP_I2C_ANA_MST_I2C0_BUSY (BIT(25)) -#define LP_I2C_ANA_MST_I2C0_BUSY_M (LP_I2C_ANA_MST_I2C0_BUSY_V << LP_I2C_ANA_MST_I2C0_BUSY_S) -#define LP_I2C_ANA_MST_I2C0_BUSY_V 0x00000001U -#define LP_I2C_ANA_MST_I2C0_BUSY_S 25 - -/** LP_I2C_ANA_MST_I2C0_CONF_REG register - * need_des - */ -#define LP_I2C_ANA_MST_I2C0_CONF_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0x4) -/** LP_I2C_ANA_MST_I2C0_CONF : R/W; bitpos: [23:0]; default: 0; - * need_des - */ -#define LP_I2C_ANA_MST_I2C0_CONF 0x00FFFFFFU -#define LP_I2C_ANA_MST_I2C0_CONF_M (LP_I2C_ANA_MST_I2C0_CONF_V << LP_I2C_ANA_MST_I2C0_CONF_S) -#define LP_I2C_ANA_MST_I2C0_CONF_V 0x00FFFFFFU -#define LP_I2C_ANA_MST_I2C0_CONF_S 0 -/** LP_I2C_ANA_MST_I2C0_STATUS : RO; bitpos: [31:24]; default: 7; - * reserved - */ -#define LP_I2C_ANA_MST_I2C0_STATUS 0x000000FFU -#define LP_I2C_ANA_MST_I2C0_STATUS_M (LP_I2C_ANA_MST_I2C0_STATUS_V << LP_I2C_ANA_MST_I2C0_STATUS_S) -#define LP_I2C_ANA_MST_I2C0_STATUS_V 0x000000FFU -#define LP_I2C_ANA_MST_I2C0_STATUS_S 24 - -/** LP_I2C_ANA_MST_I2C0_DATA_REG register - * need_des - */ -#define LP_I2C_ANA_MST_I2C0_DATA_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0x8) -/** LP_I2C_ANA_MST_I2C0_RDATA : RO; bitpos: [7:0]; default: 0; - * need_des - */ -#define LP_I2C_ANA_MST_I2C0_RDATA 0x000000FFU -#define LP_I2C_ANA_MST_I2C0_RDATA_M (LP_I2C_ANA_MST_I2C0_RDATA_V << LP_I2C_ANA_MST_I2C0_RDATA_S) -#define LP_I2C_ANA_MST_I2C0_RDATA_V 0x000000FFU -#define LP_I2C_ANA_MST_I2C0_RDATA_S 0 -/** LP_I2C_ANA_MST_I2C0_CLK_SEL : R/W; bitpos: [10:8]; default: 1; - * need_des - */ -#define LP_I2C_ANA_MST_I2C0_CLK_SEL 0x00000007U -#define LP_I2C_ANA_MST_I2C0_CLK_SEL_M (LP_I2C_ANA_MST_I2C0_CLK_SEL_V << LP_I2C_ANA_MST_I2C0_CLK_SEL_S) -#define LP_I2C_ANA_MST_I2C0_CLK_SEL_V 0x00000007U -#define LP_I2C_ANA_MST_I2C0_CLK_SEL_S 8 -/** LP_I2C_ANA_MST_I2C_MST_SEL : R/W; bitpos: [11]; default: 1; - * need des - */ -#define LP_I2C_ANA_MST_I2C_MST_SEL (BIT(11)) -#define LP_I2C_ANA_MST_I2C_MST_SEL_M (LP_I2C_ANA_MST_I2C_MST_SEL_V << LP_I2C_ANA_MST_I2C_MST_SEL_S) -#define LP_I2C_ANA_MST_I2C_MST_SEL_V 0x00000001U -#define LP_I2C_ANA_MST_I2C_MST_SEL_S 11 - -/** LP_I2C_ANA_MST_ANA_CONF1_REG register - * need_des - */ -#define LP_I2C_ANA_MST_ANA_CONF1_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0xc) -/** LP_I2C_ANA_MST_ANA_CONF1 : R/W; bitpos: [23:0]; default: 0; - * need_des - */ -#define LP_I2C_ANA_MST_ANA_CONF1 0x00FFFFFFU -#define LP_I2C_ANA_MST_ANA_CONF1_M (LP_I2C_ANA_MST_ANA_CONF1_V << LP_I2C_ANA_MST_ANA_CONF1_S) -#define LP_I2C_ANA_MST_ANA_CONF1_V 0x00FFFFFFU -#define LP_I2C_ANA_MST_ANA_CONF1_S 0 - -/** LP_I2C_ANA_MST_NOUSE_REG register - * need_des - */ -#define LP_I2C_ANA_MST_NOUSE_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0x10) -/** LP_I2C_ANA_MST_I2C_MST_NOUSE : R/W; bitpos: [31:0]; default: 0; - * need_des - */ -#define LP_I2C_ANA_MST_I2C_MST_NOUSE 0xFFFFFFFFU -#define LP_I2C_ANA_MST_I2C_MST_NOUSE_M (LP_I2C_ANA_MST_I2C_MST_NOUSE_V << LP_I2C_ANA_MST_I2C_MST_NOUSE_S) -#define LP_I2C_ANA_MST_I2C_MST_NOUSE_V 0xFFFFFFFFU -#define LP_I2C_ANA_MST_I2C_MST_NOUSE_S 0 - -/** LP_I2C_ANA_MST_DEVICE_EN_REG register - * need_des - */ -#define LP_I2C_ANA_MST_DEVICE_EN_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0x14) -/** LP_I2C_ANA_MST_I2C_DEVICE_EN : R/W; bitpos: [11:0]; default: 0; - * need_des - */ -#define LP_I2C_ANA_MST_I2C_DEVICE_EN 0x00000FFFU -#define LP_I2C_ANA_MST_I2C_DEVICE_EN_M (LP_I2C_ANA_MST_I2C_DEVICE_EN_V << LP_I2C_ANA_MST_I2C_DEVICE_EN_S) -#define LP_I2C_ANA_MST_I2C_DEVICE_EN_V 0x00000FFFU -#define LP_I2C_ANA_MST_I2C_DEVICE_EN_S 0 - -/** LP_I2C_ANA_MST_DATE_REG register - * need_des - */ -#define LP_I2C_ANA_MST_DATE_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0x3fc) -/** LP_I2C_ANA_MST_I2C_MAT_DATE : R/W; bitpos: [27:0]; default: 33583873; - * need_des - */ -#define LP_I2C_ANA_MST_I2C_MAT_DATE 0x0FFFFFFFU -#define LP_I2C_ANA_MST_I2C_MAT_DATE_M (LP_I2C_ANA_MST_I2C_MAT_DATE_V << LP_I2C_ANA_MST_I2C_MAT_DATE_S) -#define LP_I2C_ANA_MST_I2C_MAT_DATE_V 0x0FFFFFFFU -#define LP_I2C_ANA_MST_I2C_MAT_DATE_S 0 -/** LP_I2C_ANA_MST_I2C_MAT_CLK_EN : R/W; bitpos: [28]; default: 0; - * need_des - */ -#define LP_I2C_ANA_MST_I2C_MAT_CLK_EN (BIT(28)) -#define LP_I2C_ANA_MST_I2C_MAT_CLK_EN_M (LP_I2C_ANA_MST_I2C_MAT_CLK_EN_V << LP_I2C_ANA_MST_I2C_MAT_CLK_EN_S) -#define LP_I2C_ANA_MST_I2C_MAT_CLK_EN_V 0x00000001U -#define LP_I2C_ANA_MST_I2C_MAT_CLK_EN_S 28 - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/include/soc/lp_i2c_ana_mst_struct.h b/components/soc/esp32p4/include/soc/lp_i2c_ana_mst_struct.h deleted file mode 100644 index 46aedaf634..0000000000 --- a/components/soc/esp32p4/include/soc/lp_i2c_ana_mst_struct.h +++ /dev/null @@ -1,150 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#ifdef __cplusplus -extern "C" { -#endif - -/** Group: configure_register */ -/** Type of i2c0_ctrl register - * need_des - */ -typedef union { - struct { - /** i2c0_ctrl : R/W; bitpos: [24:0]; default: 0; - * need_des - */ - uint32_t i2c0_ctrl:25; - /** i2c0_busy : RO; bitpos: [25]; default: 0; - * need_des - */ - uint32_t i2c0_busy:1; - uint32_t reserved_26:6; - }; - uint32_t val; -} lp_i2c_ana_mst_i2c0_ctrl_reg_t; - -/** Type of i2c0_conf register - * need_des - */ -typedef union { - struct { - /** i2c0_conf : R/W; bitpos: [23:0]; default: 0; - * need_des - */ - uint32_t i2c0_conf:24; - /** i2c0_status : RO; bitpos: [31:24]; default: 7; - * reserved - */ - uint32_t i2c0_status:8; - }; - uint32_t val; -} lp_i2c_ana_mst_i2c0_conf_reg_t; - -/** Type of i2c0_data register - * need_des - */ -typedef union { - struct { - /** i2c0_rdata : RO; bitpos: [7:0]; default: 0; - * need_des - */ - uint32_t i2c0_rdata:8; - /** i2c0_clk_sel : R/W; bitpos: [10:8]; default: 1; - * need_des - */ - uint32_t i2c0_clk_sel:3; - /** i2c_mst_sel : R/W; bitpos: [11]; default: 1; - * need des - */ - uint32_t i2c_mst_sel:1; - uint32_t reserved_12:20; - }; - uint32_t val; -} lp_i2c_ana_mst_i2c0_data_reg_t; - -/** Type of ana_conf1 register - * need_des - */ -typedef union { - struct { - /** ana_conf1 : R/W; bitpos: [23:0]; default: 0; - * need_des - */ - uint32_t ana_conf1:24; - uint32_t reserved_24:8; - }; - uint32_t val; -} lp_i2c_ana_mst_ana_conf1_reg_t; - -/** Type of nouse register - * need_des - */ -typedef union { - struct { - /** i2c_mst_nouse : R/W; bitpos: [31:0]; default: 0; - * need_des - */ - uint32_t i2c_mst_nouse:32; - }; - uint32_t val; -} lp_i2c_ana_mst_nouse_reg_t; - -/** Type of device_en register - * need_des - */ -typedef union { - struct { - /** i2c_device_en : R/W; bitpos: [11:0]; default: 0; - * need_des - */ - uint32_t i2c_device_en:12; - uint32_t reserved_12:20; - }; - uint32_t val; -} lp_i2c_ana_mst_device_en_reg_t; - -/** Type of date register - * need_des - */ -typedef union { - struct { - /** i2c_mat_date : R/W; bitpos: [27:0]; default: 33583873; - * need_des - */ - uint32_t i2c_mat_date:28; - /** i2c_mat_clk_en : R/W; bitpos: [28]; default: 0; - * need_des - */ - uint32_t i2c_mat_clk_en:1; - uint32_t reserved_29:3; - }; - uint32_t val; -} lp_i2c_ana_mst_date_reg_t; - - -typedef struct lp_i2c_ana_mst_dev_t { - volatile lp_i2c_ana_mst_i2c0_ctrl_reg_t i2c0_ctrl; - volatile lp_i2c_ana_mst_i2c0_conf_reg_t i2c0_conf; - volatile lp_i2c_ana_mst_i2c0_data_reg_t i2c0_data; - volatile lp_i2c_ana_mst_ana_conf1_reg_t ana_conf1; - volatile lp_i2c_ana_mst_nouse_reg_t nouse; - volatile lp_i2c_ana_mst_device_en_reg_t device_en; - uint32_t reserved_018[249]; - volatile lp_i2c_ana_mst_date_reg_t date; -} lp_i2c_ana_mst_dev_t; - -extern lp_i2c_ana_mst_dev_t LP_I2C_ANA_MST; - -#ifndef __cplusplus -_Static_assert(sizeof(lp_i2c_ana_mst_dev_t) == 0x400, "Invalid size of lp_i2c_ana_mst_dev_t structure"); -#endif - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/include/soc/reg_base.h b/components/soc/esp32p4/include/soc/reg_base.h index 19b8fb2d80..91c0aa55fe 100644 --- a/components/soc/esp32p4/include/soc/reg_base.h +++ b/components/soc/esp32p4/include/soc/reg_base.h @@ -144,7 +144,7 @@ #define DR_REG_LP_UART_BASE (DR_REG_LPPERIPH_BASE + 0x1000) #define DR_REG_LP_I2C_BASE (DR_REG_LPPERIPH_BASE + 0x2000) #define DR_REG_LP_SPI_BASE (DR_REG_LPPERIPH_BASE + 0x3000) -#define DR_REG_LP_I2C_MST_BASE (DR_REG_LPPERIPH_BASE + 0x4000) +#define DR_REG_I2C_ANA_MST_BASE (DR_REG_LPPERIPH_BASE + 0x4000) #define DR_REG_LP_I2S_BASE (DR_REG_LPPERIPH_BASE + 0x5000) #define DR_REG_LP_ADC_BASE (DR_REG_LPPERIPH_BASE + 0x7000) #define DR_REG_LP_TOUCH_BASE (DR_REG_LPPERIPH_BASE + 0x8000)