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esp32h2beta2: fixed reg base name

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This commit is contained in:
laokaiyao
2022-03-29 11:22:01 +08:00
parent 4652f77a7c
commit f29d329e55
5 changed files with 2200 additions and 457 deletions
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4
components/hal/esp32h2/include/hal/efuse_ll.h
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@@ -10,7 +10,7 @@
#include <stdbool.h> #include <stdbool.h>
#include "soc/efuse_periph.h" #include "soc/efuse_periph.h"
#include "hal/assert.h" #include "hal/assert.h"
#include "esp32c3/rom/efuse.h" #include "esp32h2/rom/efuse.h"
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
@@ -32,7 +32,7 @@ __attribute__((always_inline)) static inline uint32_t efuse_ll_get_wdt_delay_sel
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_mac0(void) __attribute__((always_inline)) static inline uint32_t efuse_ll_get_mac0(void)
{ {
return EFUSE.rd_mac_spi_sys_0; return EFUSE.rd_mac_spi_sys_0.mac_0;
} }
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_mac1(void) __attribute__((always_inline)) static inline uint32_t efuse_ll_get_mac1(void)

7
components/soc/esp32h2/include/rev1/soc/efuse_struct.h
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@@ -167,7 +167,12 @@ typedef volatile struct efuse_dev_s {
}; };
uint32_t val; uint32_t val;
} rd_repeat_data4; } rd_repeat_data4;
uint32_t rd_mac_spi_sys_0; /*BLOCK1 data register $n.*/ union {
struct {
uint32_t mac_0;
};
uint32_t val;
} rd_mac_spi_sys_0; /*BLOCK1 data register $n.*/
union { union {
struct { struct {
uint32_t mac_1: 16; /*Stores the high 16 bits of MAC address.*/ uint32_t mac_1: 16; /*Stores the high 16 bits of MAC address.*/

42
components/soc/esp32h2/include/rev2/soc/clkrst_reg.h
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@@ -15,7 +15,7 @@ extern "C" {
/** SYSTEM_SYSCLK_CONF_REG register /** SYSTEM_SYSCLK_CONF_REG register
* register description * register description
*/ */
#define SYSTEM_SYSCLK_CONF_REG (DR_REG_SYSTEM_BASE + 0x0) #define SYSTEM_SYSCLK_CONF_REG (DR_REG_CLKRST_BASE + 0x0)
/** SYSTEM_CLK_XTAL_FREQ : RO; bitpos: [7:0]; default: 0; /** SYSTEM_CLK_XTAL_FREQ : RO; bitpos: [7:0]; default: 0;
* Need add description * Need add description
*/ */
@@ -41,7 +41,7 @@ extern "C" {
/** SYSTEM_CPUCLK_CONF_REG register /** SYSTEM_CPUCLK_CONF_REG register
* register description * register description
*/ */
#define SYSTEM_CPUCLK_CONF_REG (DR_REG_SYSTEM_BASE + 0x4) #define SYSTEM_CPUCLK_CONF_REG (DR_REG_CLKRST_BASE + 0x4)
/** SYSTEM_CPU_DIV_NUM : R/W; bitpos: [7:0]; default: 0; /** SYSTEM_CPU_DIV_NUM : R/W; bitpos: [7:0]; default: 0;
* Need add description * Need add description
*/ */
@@ -67,7 +67,7 @@ extern "C" {
/** SYSTEM_BUSCLK_CONF_REG register /** SYSTEM_BUSCLK_CONF_REG register
* register description * register description
*/ */
#define SYSTEM_BUSCLK_CONF_REG (DR_REG_SYSTEM_BASE + 0x8) #define SYSTEM_BUSCLK_CONF_REG (DR_REG_CLKRST_BASE + 0x8)
/** SYSTEM_APB_DIV_NUM : R/W; bitpos: [7:0]; default: 0; /** SYSTEM_APB_DIV_NUM : R/W; bitpos: [7:0]; default: 0;
* Need add description * Need add description
*/ */
@@ -86,7 +86,7 @@ extern "C" {
/** SYSTEM_MODCLK_CONF_REG register /** SYSTEM_MODCLK_CONF_REG register
* register description * register description
*/ */
#define SYSTEM_MODCLK_CONF_REG (DR_REG_SYSTEM_BASE + 0xc) #define SYSTEM_MODCLK_CONF_REG (DR_REG_CLKRST_BASE + 0xc)
/** SYSTEM_MODEM_CLK_SEL : R/W; bitpos: [1:0]; default: 1; /** SYSTEM_MODEM_CLK_SEL : R/W; bitpos: [1:0]; default: 1;
* Need add description * Need add description
*/ */
@@ -133,7 +133,7 @@ extern "C" {
/** SYSTEM_CLK_OUT_EN_REG register /** SYSTEM_CLK_OUT_EN_REG register
* register description * register description
*/ */
#define SYSTEM_CLK_OUT_EN_REG (DR_REG_SYSTEM_BASE + 0x10) #define SYSTEM_CLK_OUT_EN_REG (DR_REG_CLKRST_BASE + 0x10)
/** SYSTEM_CLK_8M_BT_OEN : R/W; bitpos: [3]; default: 1; /** SYSTEM_CLK_8M_BT_OEN : R/W; bitpos: [3]; default: 1;
* Need add description * Need add description
*/ */
@@ -208,7 +208,7 @@ extern "C" {
/** SYSTEM_MODEM_CLK_EN_REG register /** SYSTEM_MODEM_CLK_EN_REG register
* register description * register description
*/ */
#define SYSTEM_MODEM_CLK_EN_REG (DR_REG_SYSTEM_BASE + 0x14) #define SYSTEM_MODEM_CLK_EN_REG (DR_REG_CLKRST_BASE + 0x14)
/** SYSTEM_FE_CAL_CLK_EN : R/W; bitpos: [0]; default: 0; /** SYSTEM_FE_CAL_CLK_EN : R/W; bitpos: [0]; default: 0;
* Need add description * Need add description
*/ */
@@ -374,7 +374,7 @@ extern "C" {
/** SYSTEM_MODEM_RST_EN_REG register /** SYSTEM_MODEM_RST_EN_REG register
* register description * register description
*/ */
#define SYSTEM_MODEM_RST_EN_REG (DR_REG_SYSTEM_BASE + 0x18) #define SYSTEM_MODEM_RST_EN_REG (DR_REG_CLKRST_BASE + 0x18)
/** SYSTEM_FE_RST : R/W; bitpos: [0]; default: 0; /** SYSTEM_FE_RST : R/W; bitpos: [0]; default: 0;
* Need add description * Need add description
*/ */
@@ -526,7 +526,7 @@ extern "C" {
/** SYSTEM_PERIP_CLK_CONF_REG register /** SYSTEM_PERIP_CLK_CONF_REG register
* register description * register description
*/ */
#define SYSTEM_PERIP_CLK_CONF_REG (DR_REG_SYSTEM_BASE + 0x1c) #define SYSTEM_PERIP_CLK_CONF_REG (DR_REG_CLKRST_BASE + 0x1c)
/** SYSTEM_SEC_DIV_NUM : R/W; bitpos: [7:0]; default: 1; /** SYSTEM_SEC_DIV_NUM : R/W; bitpos: [7:0]; default: 1;
* Need add description * Need add description
*/ */
@@ -559,7 +559,7 @@ extern "C" {
/** SYSTEM_PERIP_CLK_EN0_REG register /** SYSTEM_PERIP_CLK_EN0_REG register
* register description * register description
*/ */
#define SYSTEM_PERIP_CLK_EN0_REG (DR_REG_SYSTEM_BASE + 0x20) #define SYSTEM_PERIP_CLK_EN0_REG (DR_REG_CLKRST_BASE + 0x20)
/** SYSTEM_TIMERS_CLK_EN : R/W; bitpos: [0]; default: 1; /** SYSTEM_TIMERS_CLK_EN : R/W; bitpos: [0]; default: 1;
* Need add description * Need add description
*/ */
@@ -788,7 +788,7 @@ extern "C" {
/** SYSTEM_PERIP_CLK_EN1_REG register /** SYSTEM_PERIP_CLK_EN1_REG register
* register description * register description
*/ */
#define SYSTEM_PERIP_CLK_EN1_REG (DR_REG_SYSTEM_BASE + 0x24) #define SYSTEM_PERIP_CLK_EN1_REG (DR_REG_CLKRST_BASE + 0x24)
/** SYSTEM_RETENTION_TOP_CLK_EN : R/W; bitpos: [0]; default: 1; /** SYSTEM_RETENTION_TOP_CLK_EN : R/W; bitpos: [0]; default: 1;
* Need add description * Need add description
*/ */
@@ -905,7 +905,7 @@ extern "C" {
/** SYSTEM_PERIP_RST_EN0_REG register /** SYSTEM_PERIP_RST_EN0_REG register
* register description * register description
*/ */
#define SYSTEM_PERIP_RST_EN0_REG (DR_REG_SYSTEM_BASE + 0x28) #define SYSTEM_PERIP_RST_EN0_REG (DR_REG_CLKRST_BASE + 0x28)
/** SYSTEM_TIMERS_RST : R/W; bitpos: [0]; default: 0; /** SYSTEM_TIMERS_RST : R/W; bitpos: [0]; default: 0;
* Need add description * Need add description
*/ */
@@ -1134,7 +1134,7 @@ extern "C" {
/** SYSTEM_PERIP_RST_EN1_REG register /** SYSTEM_PERIP_RST_EN1_REG register
* register description * register description
*/ */
#define SYSTEM_PERIP_RST_EN1_REG (DR_REG_SYSTEM_BASE + 0x2c) #define SYSTEM_PERIP_RST_EN1_REG (DR_REG_CLKRST_BASE + 0x2c)
/** SYSTEM_RETENTION_TOP_RST : R/W; bitpos: [0]; default: 0; /** SYSTEM_RETENTION_TOP_RST : R/W; bitpos: [0]; default: 0;
* Need add description * Need add description
*/ */
@@ -1251,7 +1251,7 @@ extern "C" {
/** SYSTEM_FPGA_DBG_REG register /** SYSTEM_FPGA_DBG_REG register
* register description * register description
*/ */
#define SYSTEM_FPGA_DBG_REG (DR_REG_SYSTEM_BASE + 0x30) #define SYSTEM_FPGA_DBG_REG (DR_REG_CLKRST_BASE + 0x30)
/** SYSTEM_FPGA_DEBUG : R/W; bitpos: [31:0]; default: 4294967295; /** SYSTEM_FPGA_DEBUG : R/W; bitpos: [31:0]; default: 4294967295;
* Need add description * Need add description
*/ */
@@ -1263,7 +1263,7 @@ extern "C" {
/** SYSTEM_REGCLK_CONF_REG register /** SYSTEM_REGCLK_CONF_REG register
* register description * register description
*/ */
#define SYSTEM_REGCLK_CONF_REG (DR_REG_SYSTEM_BASE + 0x34) #define SYSTEM_REGCLK_CONF_REG (DR_REG_CLKRST_BASE + 0x34)
/** SYSTEM_CLK_EN : R/W; bitpos: [0]; default: 0; /** SYSTEM_CLK_EN : R/W; bitpos: [0]; default: 0;
* Need add description * Need add description
*/ */
@@ -1272,17 +1272,17 @@ extern "C" {
#define SYSTEM_CLK_EN_V 0x00000001U #define SYSTEM_CLK_EN_V 0x00000001U
#define SYSTEM_CLK_EN_S 0 #define SYSTEM_CLK_EN_S 0
/** SYSTEM_DATE_REG register /** SYSTEM_CLKRST_DATE_REG register
* register description * register description
*/ */
#define SYSTEM_DATE_REG (DR_REG_SYSTEM_BASE + 0x38) #define SYSTEM_CLKRST_DATE_REG (DR_REG_SYSTEM_BASE + 0x38)
/** SYSTEM_DATE : R/W; bitpos: [27:0]; default: 34672962; /** CLKRST_DATE : R/W; bitpos: [27:0]; default: 34672962;
* Need add description * Need add description
*/ */
#define SYSTEM_DATE 0x0FFFFFFFU #define CLKRST_DATE 0x0FFFFFFFU
#define SYSTEM_DATE_M (SYSTEM_DATE_V << SYSTEM_DATE_S) #define CLKRST_DATE_M (CLKRST_DATE_V << CLKRST_DATE_S)
#define SYSTEM_DATE_V 0x0FFFFFFFU #define CLKRST_DATE_V 0x0FFFFFFFU
#define SYSTEM_DATE_S 0 #define CLKRST_DATE_S 0
#ifdef __cplusplus #ifdef __cplusplus
} }

2516
components/soc/esp32h2/include/rev2/soc/efuse_struct.h
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16
components/soc/esp32h2/include/rev2/soc/system_reg.h
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@@ -1,5 +1,5 @@
/** /**
* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -356,17 +356,17 @@ extern "C" {
#define SYSTEM_MEM_VT_SEL_V 0x00000003U #define SYSTEM_MEM_VT_SEL_V 0x00000003U
#define SYSTEM_MEM_VT_SEL_S 22 #define SYSTEM_MEM_VT_SEL_S 22
/** SYSTEM_SYSTEM_REG_DATE_REG register /** SYSTEM_REG_DATE_REG register
* register description * register description
*/ */
#define SYSTEM_SYSTEM_REG_DATE_REG (DR_REG_SYSTEM_BASE + 0xffc) #define SYSTEM_REG_DATE_REG (DR_REG_SYSTEM_BASE + 0xffc)
/** SYSTEM_SYSTEM_REG_DATE : R/W; bitpos: [27:0]; default: 34615872; /** SYSTEM_REG_DATE : R/W; bitpos: [27:0]; default: 34615872;
* Need add description * Need add description
*/ */
#define SYSTEM_SYSTEM_REG_DATE 0x0FFFFFFFU #define SYSTEM_REG_DATE 0x0FFFFFFFU
#define SYSTEM_SYSTEM_REG_DATE_M (SYSTEM_SYSTEM_REG_DATE_V << SYSTEM_SYSTEM_REG_DATE_S) #define SYSTEM_REG_DATE_M (SYSTEM_REG_DATE_V << SYSTEM_REG_DATE_S)
#define SYSTEM_SYSTEM_REG_DATE_V 0x0FFFFFFFU #define SYSTEM_REG_DATE_V 0x0FFFFFFFU
#define SYSTEM_SYSTEM_REG_DATE_S 0 #define SYSTEM_REG_DATE_S 0
#ifdef __cplusplus #ifdef __cplusplus
} }