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clk_tree: added default clock source for peripheral

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morris
2022-04-13 13:12:30 +08:00
parent 11abb67e65
commit f32a89826c
61 changed files with 578 additions and 215 deletions
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examples/peripherals/lcd/i80_controller/main/i80_controller_example_main.c
+1 -1
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@@ -113,7 +113,7 @@ void app_main(void)
ESP_LOGI(TAG, "Initialize Intel 8080 bus");
esp_lcd_i80_bus_handle_t i80_bus = NULL;
esp_lcd_i80_bus_config_t bus_config = {
.clk_src = LCD_CLK_SRC_PLL160M,
.clk_src = LCD_CLK_SRC_DEFAULT,
.dc_gpio_num = EXAMPLE_PIN_NUM_DC,
.wr_gpio_num = EXAMPLE_PIN_NUM_PCLK,
.data_gpio_nums = {
examples/peripherals/lcd/rgb_panel/main/rgb_lcd_example_main.c
+1 -1
View File
@@ -89,7 +89,7 @@ void app_main(void)
esp_lcd_rgb_panel_config_t panel_config = {
.data_width = 16, // RGB565 in parallel mode, thus 16bit in width
.psram_trans_align = 64,
.clk_src = LCD_CLK_SRC_PLL160M,
.clk_src = LCD_CLK_SRC_DEFAULT,
.disp_gpio_num = EXAMPLE_PIN_NUM_DISP_EN,
.pclk_gpio_num = EXAMPLE_PIN_NUM_PCLK,
.vsync_gpio_num = EXAMPLE_PIN_NUM_VSYNC,