From f3d963a93b86375a472d8a591925e3b8cf95b580 Mon Sep 17 00:00:00 2001 From: wuzhenghui Date: Thu, 21 Mar 2024 16:53:26 +0800 Subject: [PATCH] fix(esp_system): update power domain configuration with slow clock source selection --- components/esp_system/port/soc/esp32p4/clk.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/components/esp_system/port/soc/esp32p4/clk.c b/components/esp_system/port/soc/esp32p4/clk.c index fc03e0d300..c00287e5a1 100644 --- a/components/esp_system/port/soc/esp32p4/clk.c +++ b/components/esp_system/port/soc/esp32p4/clk.c @@ -11,6 +11,7 @@ #include "sdkconfig.h" #include "esp_attr.h" #include "esp_log.h" +#include "esp_sleep.h" #include "esp_clk_internal.h" #include "esp32p4/rom/ets_sys.h" #include "esp32p4/rom/uart.h" @@ -174,6 +175,21 @@ void rtc_clk_select_rtc_slow_clk(void) */ __attribute__((weak)) void esp_perip_clk_init(void) { + soc_rtc_slow_clk_src_t rtc_slow_clk_src = rtc_clk_slow_src_get(); + + if (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC32K) { + esp_sleep_pd_config(ESP_PD_DOMAIN_XTAL32K, ESP_PD_OPTION_AUTO); + esp_sleep_pd_config(ESP_PD_DOMAIN_RC32K, ESP_PD_OPTION_ON); + // RC slow (150K) always ON + } else if (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) { + esp_sleep_pd_config(ESP_PD_DOMAIN_RC32K, ESP_PD_OPTION_AUTO); + esp_sleep_pd_config(ESP_PD_DOMAIN_XTAL32K, ESP_PD_OPTION_ON); + // RC slow (150K) always ON + } else { + esp_sleep_pd_config(ESP_PD_DOMAIN_XTAL32K, ESP_PD_OPTION_AUTO); + esp_sleep_pd_config(ESP_PD_DOMAIN_RC32K, ESP_PD_OPTION_AUTO); + } + ESP_EARLY_LOGW(TAG, "esp_perip_clk_init() has not been implemented yet"); #if 0 // TODO: IDF-5658 uint32_t common_perip_clk, hwcrypto_perip_clk, wifi_bt_sdio_clk = 0;