Merge branch 'feature/remove_aes_rsa_ds_hmac_spport_for_c61' into 'master'

feat: remove suppport for AES, RSA, DS and HMAC in esp32c61

Closes IDF-9326, IDF-9328, IDF-9323, and IDF-9325

See merge request espressif/esp-idf!31798

components/esp_hw_support/include/esp_ds.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -12,6 +12,8 @@
 #include "esp_ds_err.h"
 #include "soc/soc_caps.h"
 
+#ifdef SOC_DIG_SIGN_SUPPORTED
+
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -61,7 +63,7 @@ typedef struct esp_digital_signature_data {
      * alter the DS peripheral results this way, it will just truncate or
      * extend the message and the resulting signature in software.)
      *
-     * @note In IDF, the enum type length is the same as of type unsigned, so they can be used interchangably.
+     * @note In IDF, the enum type length is the same as of type unsigned, so they can be used interchangeably.
      *       See the ROM code for the original declaration of struct \c ets_ds_data_t.
      */
     esp_digital_signature_length_t rsa_length;
@@ -186,7 +188,7 @@ bool esp_ds_is_busy(void);
  *
  * @param signature the destination of the signature, should be (data->rsa_length + 1)*4 bytes long,
           the resultant signature bytes shall be written in little endian format.
- * @param esp_ds_ctx the context object retreived by \c esp_ds_start_sign()
+ * @param esp_ds_ctx the context object retrieved by \c esp_ds_start_sign()
  *
  * @return
  *      - ESP_OK if successful, the ds operation has been finished and the result is written to signature.
@@ -232,3 +234,5 @@ esp_err_t esp_ds_encrypt_params(esp_ds_data_t *data,
 #ifdef __cplusplus
 }
 #endif
+
+#endif

components/esp_system/port/soc/esp32c61/clk.c

@@ -106,6 +106,9 @@ __attribute__((weak)) void esp_clk_init(void)
 
     // Re calculate the ccount to make time calculation correct.
     esp_cpu_set_cycle_count((uint64_t)esp_cpu_get_cycle_count() * new_freq_mhz / old_freq_mhz);
+
+    // Set crypto clock (`clk_sec`) to use 480M SPLL clock
+    REG_SET_FIELD(PCR_SEC_CONF_REG, PCR_SEC_CLK_SEL, 0x2);
 }
 
 static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src)

components/mbedtls/test_apps/main/test_aes_sha_parallel.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -16,7 +16,6 @@
 #include "freertos/task.h"
 #include "freertos/semphr.h"
 
-
 static SemaphoreHandle_t done_sem;
 
 static const unsigned char *one_hundred_bs =  (unsigned char *)
@@ -77,11 +76,11 @@ static void tskRunAES256Test(void *pvParameters)
         memcpy(nonce, iv, 16);
 
         // allocate internal memory
-        uint8_t *chipertext = heap_caps_malloc(SZ, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL);
+        uint8_t *ciphertext = heap_caps_malloc(SZ, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL);
         uint8_t *plaintext = heap_caps_malloc(SZ, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL);
         uint8_t *decryptedtext = heap_caps_malloc(SZ, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL);
 
-        TEST_ASSERT_NOT_NULL(chipertext);
+        TEST_ASSERT_NOT_NULL(ciphertext);
         TEST_ASSERT_NOT_NULL(plaintext);
         TEST_ASSERT_NOT_NULL(decryptedtext);
 
@@ -92,19 +91,19 @@ static void tskRunAES256Test(void *pvParameters)
         memset(decryptedtext, 0x0, SZ);
 
         // Encrypt
-        mbedtls_aes_crypt_cbc(&ctx, MBEDTLS_AES_ENCRYPT, SZ, nonce, plaintext, chipertext);
+        mbedtls_aes_crypt_cbc(&ctx, MBEDTLS_AES_ENCRYPT, SZ, nonce, plaintext, ciphertext);
-        TEST_ASSERT_EQUAL_HEX8_ARRAY(expected_cipher_end, chipertext + SZ - 32, 32);
+        TEST_ASSERT_EQUAL_HEX8_ARRAY(expected_cipher_end, ciphertext + SZ - 32, 32);
 
         // Decrypt
         memcpy(nonce, iv, 16);
         mbedtls_aes_setkey_dec(&ctx, key_256, 256);
-        mbedtls_aes_crypt_cbc(&ctx, MBEDTLS_AES_DECRYPT, SZ, nonce, chipertext, decryptedtext);
+        mbedtls_aes_crypt_cbc(&ctx, MBEDTLS_AES_DECRYPT, SZ, nonce, ciphertext, decryptedtext);
 
         TEST_ASSERT_EQUAL_HEX8_ARRAY(plaintext, decryptedtext, SZ);
 
         mbedtls_aes_free(&ctx);
         free(plaintext);
-        free(chipertext);
+        free(ciphertext);
         free(decryptedtext);
     }
     xSemaphoreGive(done_sem);

components/mbedtls/test_apps/main/test_mbedtls_mpi.c

@@ -1,6 +1,6 @@
 /* mbedTLS bignum (MPI) self-tests as unit tests
  *
- * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -17,6 +17,12 @@
 #include "sdkconfig.h"
 #include "test_utils.h"
 
+#ifdef SOC_MPI_SUPPORTED
+#define RSA_MAX_BIT_LEN SOC_RSA_MAX_BIT_LEN
+#else
+#define RSA_MAX_BIT_LEN 3072
+#endif
+
 #define MBEDTLS_OK 0
 
 /* Debugging function to print an MPI number to stdout. Happens to
@@ -54,7 +60,7 @@ static void test_bignum_mult_variant(const char *a_str, const char *b_str, const
     TEST_ASSERT_FALSE(mbedtls_mpi_read_string(&A, 16, a_str));
     TEST_ASSERT_FALSE(mbedtls_mpi_read_string(&B, 16, b_str));
 
-    /* calulate X = A * B variant */
+    /* calculate X = A * B variant */
     TEST_ASSERT_FALSE(mbedtls_mpi_read_string(&E, 16, e_str));
     if (res_operands_overlap == 0) {
         TEST_ASSERT_FALSE(mbedtls_mpi_mul_mpi(&X, &A, &B));
@@ -72,7 +78,7 @@ static void test_bignum_mult_variant(const char *a_str, const char *b_str, const
 #ifdef CONFIG_MBEDTLS_HARDWARE_MPI
     mbedtls_mpi M;
     /* if mod_bits arg is set, also do a esp_mpi_mul_mod() call */
-    if (mod_bits > 0 && mod_bits <= SOC_RSA_MAX_BIT_LEN) {
+    if (mod_bits > 0 && mod_bits <= RSA_MAX_BIT_LEN) {
         mbedtls_mpi_init(&M);
         for(int i = 0; i < mod_bits; i++) {
             mbedtls_mpi_set_bit(&M, i, 1);
@@ -106,7 +112,7 @@ TEST_CASE("test MPI multiplication", "[bignum]")
     /* Run some trivial numbers tests w/ various high modulo bit counts,
      should make no difference to the result
     */
-    for(int i = 512; i <= SOC_RSA_MAX_BIT_LEN; i+= 512) {
+    for(int i = 512; i <= RSA_MAX_BIT_LEN; i+= 512) {
         test_bignum_mult("10", "100", "1000",
                          i);
     }

components/mbedtls/test_apps/main/test_mbedtls_sha.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -249,7 +249,7 @@ TEST_CASE("mbedtls SHA384 clone", "[mbedtls]")
         TEST_ASSERT_EQUAL(0, mbedtls_sha512_update(&ctx, one_hundred_bs, 100));
         TEST_ASSERT_EQUAL(0, mbedtls_sha512_update(&clone, one_hundred_bs, 100));
     }
-/* intended warning supression: is384 == true */
+/* intended warning suppression: is384 == true */
 #pragma GCC diagnostic push
 #pragma GCC diagnostic ignored "-Wstringop-overflow"
     TEST_ASSERT_EQUAL(0, mbedtls_sha512_finish(&ctx, sha384));

components/soc/esp32c2/include/soc/Kconfig.soc_caps.in

@@ -435,10 +435,6 @@ config SOC_RTCIO_PIN_COUNT
     int
     default 0
 
-config SOC_RSA_MAX_BIT_LEN
-    int
-    default 3072
-
 config SOC_SHA_SUPPORT_RESUME
     bool
     default y

components/soc/esp32c2/include/soc/soc_caps.h

@@ -196,9 +196,6 @@
  * for hold, wake & 32kHz crystal functions - via rtc_cntl_reg */
 #define SOC_RTCIO_PIN_COUNT    (0U)
 
-/*--------------------------- RSA CAPS ---------------------------------------*/
-#define SOC_RSA_MAX_BIT_LEN    (3072)
-
 /*--------------------------- SHA CAPS ---------------------------------------*/
 
 /* Due to very limited availability of the DMA channels, DMA support for the SHA peripheral is disabled */

components/soc/esp32c61/include/soc/Kconfig.soc_caps.in

@@ -75,22 +75,6 @@ config SOC_XTAL_SUPPORT_40M
     bool
     default y
 
-config SOC_AES_SUPPORT_DMA
-    bool
-    default y
-
-config SOC_AES_GDMA
-    bool
-    default y
-
-config SOC_AES_SUPPORT_AES_128
-    bool
-    default y
-
-config SOC_AES_SUPPORT_AES_256
-    bool
-    default y
-
 config SOC_ADC_PERIPH_NUM
     int
     default 1
@@ -179,18 +163,6 @@ config SOC_CPU_PMP_REGION_GRANULARITY
     int
     default 128
 
-config SOC_DS_SIGNATURE_MAX_BIT_LEN
-    int
-    default 3072
-
-config SOC_DS_KEY_PARAM_MD_IV_LENGTH
-    int
-    default 16
-
-config SOC_DS_KEY_CHECK_MAX_WAIT_US
-    int
-    default 1100
-
 config SOC_ETM_GROUPS
     int
     default 1
@@ -303,18 +275,6 @@ config SOC_MPU_REGION_WO_SUPPORTED
     bool
     default n
 
-config SOC_MPI_MEM_BLOCKS_NUM
-    int
-    default 4
-
-config SOC_MPI_OPERATIONS_NUM
-    int
-    default 3
-
-config SOC_RSA_MAX_BIT_LEN
-    int
-    default 3072
-
 config SOC_ECDSA_SUPPORT_EXPORT_PUBKEY
     bool
     default y

components/soc/esp32c61/include/soc/soc_caps.h

@@ -41,10 +41,7 @@
 //  \#define SOC_I2C_SUPPORTED               1    //TODO: [ESP32C61] IDF-9296, IDF-9297
 #define SOC_SYSTIMER_SUPPORTED          1       //TODO: [ESP32C61] IDF-9307, IDF-9308
 //  \#define SOC_SUPPORT_COEXISTENCE         1
-//  \#define SOC_MPI_SUPPORTED               1
 //  \#define SOC_SHA_SUPPORTED               1    //TODO: [ESP32C61] IDF-9234
-//  \#define SOC_HMAC_SUPPORTED              1    //TODO: [ESP32C61] IDF-9323
-//  \#define SOC_DIG_SIGN_SUPPORTED          1    //TODO: [ESP32C61] IDF-9325
 #define SOC_ECC_SUPPORTED               1
 #define SOC_ECC_EXTENDED_MODES_SUPPORTED   1
 #define SOC_FLASH_ENC_SUPPORTED         1
@@ -66,7 +63,6 @@
 //  \#define SOC_TWAI_SUPPORTED              0    //TODO: [ESP32C61] IDF-9336
 //  \#define SOC_ETM_SUPPORTED               0
 //  \#define SOC_LP_CORE_SUPPORTED           0    //TODO: [ESP32C61] IDF-9331
-//  \#define SOC_AES_SUPPORTED               0    //TODO: [ESP32C61] IDF-9328
 //  \#define SOC_SDIO_SLAVE_SUPPORTED        0
 //  \#define SOC_PAU_SUPPORTED               0
 //  \#define SOC_LP_I2C_SUPPORTED            0    //TODO: [ESP32C61] IDF-9330, IDF-9337
@@ -75,15 +71,6 @@
 /*-------------------------- XTAL CAPS ---------------------------------------*/
 #define SOC_XTAL_SUPPORT_40M            1
 
-/*-------------------------- AES CAPS -----------------------------------------*/
-#define SOC_AES_SUPPORT_DMA     (1)
-
-/* Has a centralized DMA, which is shared with all peripherals */
-#define SOC_AES_GDMA            (1)
-
-#define SOC_AES_SUPPORT_AES_128 (1)
-#define SOC_AES_SUPPORT_AES_256 (1)
-
 //TODO: [ESP32C61] IDF-9302, IDF-9303, IDF-9304
 /*-------------------------- ADC CAPS -------------------------------*/
 /*!< SAR ADC Module*/
@@ -157,18 +144,6 @@
 #define SOC_CPU_PMP_REGION_GRANULARITY  128 // TODO IDF-9580 check when doing PMP bringup
 
 
-/*-------------------------- DIGITAL SIGNATURE CAPS ----------------------------------------*/
-//TODO: [ESP32C61] IDF-9325 (Copy from esp32c6, need check)
-/** The maximum length of a Digital Signature in bits. */
-#define SOC_DS_SIGNATURE_MAX_BIT_LEN (3072)
-
-/** Initialization vector (IV) length for the RSA key parameter message digest (MD) in bytes. */
-#define SOC_DS_KEY_PARAM_MD_IV_LENGTH (16)
-
-/** Maximum wait time for DS parameter decryption key. If overdue, then key error.
-    See TRM DS chapter for more details */
-#define SOC_DS_KEY_CHECK_MAX_WAIT_US (1100)
-
 //TODO: [ESP32C61] IDF-9310
 /*-------------------------- GDMA CAPS -------------------------------------*/
 //  \#define SOC_AHB_GDMA_VERSION            1U
@@ -296,14 +271,6 @@
 /*------------------------ USB SERIAL JTAG CAPS ------------------------------*/
 //  \#define SOC_USB_SERIAL_JTAG_SUPPORT_LIGHT_SLEEP     (1)     /*!< Support to maintain minimum usb communication during light sleep */ // TODO: IDF-6395
 
-/*--------------------------- MPI CAPS ---------------------------------------*/
-#define SOC_MPI_MEM_BLOCKS_NUM (4)
-#define SOC_MPI_OPERATIONS_NUM (3)
-
-/*--------------------------- RSA CAPS ---------------------------------------*/
-//TODO: [ESP32C61] IDF-9326
-#define SOC_RSA_MAX_BIT_LEN    (3072)
-
 // TODO: IDF-5353 (Copy from esp32c3, need check)
 /*--------------------------- SHA CAPS ---------------------------------------*/