From c3102e8fb278dc9b0a8a077ff58c065f4c36d119 Mon Sep 17 00:00:00 2001 From: Wu Jian Gang Date: Fri, 19 Aug 2016 18:28:32 +0800 Subject: [PATCH 1/6] ld: seperate/rename eagle.xxx.ld to esp32.xxx.ld --- .../ld/{eagle.fpga32.v7.ld => esp32.common.ld} | 15 --------------- components/esp32/ld/esp32.ld | 14 ++++++++++++++ .../{eagle.fpga32.rom.addr.v7.ld => esp32.rom.ld} | 0 3 files changed, 14 insertions(+), 15 deletions(-) rename components/esp32/ld/{eagle.fpga32.v7.ld => esp32.common.ld} (80%) create mode 100644 components/esp32/ld/esp32.ld rename components/esp32/ld/{eagle.fpga32.rom.addr.v7.ld => esp32.rom.ld} (100%) diff --git a/components/esp32/ld/eagle.fpga32.v7.ld b/components/esp32/ld/esp32.common.ld similarity index 80% rename from components/esp32/ld/eagle.fpga32.v7.ld rename to components/esp32/ld/esp32.common.ld index ca79c52de7..45bcc24f47 100644 --- a/components/esp32/ld/eagle.fpga32.v7.ld +++ b/components/esp32/ld/esp32.common.ld @@ -1,18 +1,3 @@ -/* THESE ARE THE VIRTUAL RUNTIME ADDRESSES */ -/* The load addresses are defined later using the AT statements. */ -MEMORY -{ - /* All these values assume the flash cache is on, and have the blocks this uses subtracted from the length - of the various regions. The 'data access port' dram/drom regions map to the same iram/irom regions but - are connected to the data port of the CPU and eg allow bytewise access. */ - iram0_0_seg (RX) : org = 0x40080000, len = 0x18000 /* IRAM for PRO cpu. Not sure if happy with this, this is MMU area... */ - iram0_2_seg (RX) : org = 0x400D0018, len = 0x330000 /* Even though the segment name is iram, it is actually mapped to flash */ - dram0_0_seg (RW) : org = 0x3FFC0000, len = 0x20000 /* Shared RAM, minus rom bss/data/stack.*/ - drom0_0_seg (R) : org = 0x3F400010, len = 0x800000 -} - -_heap_end = 0x3fffe000; - /* Default entry point: */ ENTRY(call_user_start_cpu0); diff --git a/components/esp32/ld/esp32.ld b/components/esp32/ld/esp32.ld new file mode 100644 index 0000000000..4cb1c99bfa --- /dev/null +++ b/components/esp32/ld/esp32.ld @@ -0,0 +1,14 @@ +/* THESE ARE THE VIRTUAL RUNTIME ADDRESSES */ +/* The load addresses are defined later using the AT statements. */ +MEMORY +{ + /* All these values assume the flash cache is on, and have the blocks this uses subtracted from the length + of the various regions. The 'data access port' dram/drom regions map to the same iram/irom regions but + are connected to the data port of the CPU and eg allow bytewise access. */ + iram0_0_seg (RX) : org = 0x40080000, len = 0x18000 /* IRAM for PRO cpu. Not sure if happy with this, this is MMU area... */ + iram0_2_seg (RX) : org = 0x400D0018, len = 0x330000 /* Even though the segment name is iram, it is actually mapped to flash */ + dram0_0_seg (RW) : org = 0x3FFC0000, len = 0x20000 /* Shared RAM, minus rom bss/data/stack.*/ + drom0_0_seg (R) : org = 0x3F400010, len = 0x800000 +} + +_heap_end = 0x3fffe000; diff --git a/components/esp32/ld/eagle.fpga32.rom.addr.v7.ld b/components/esp32/ld/esp32.rom.ld similarity index 100% rename from components/esp32/ld/eagle.fpga32.rom.addr.v7.ld rename to components/esp32/ld/esp32.rom.ld From 3e8bb67e75a6ac4d3516daedb21bdf3bc2a518f9 Mon Sep 17 00:00:00 2001 From: Wu Jian Gang Date: Fri, 19 Aug 2016 18:40:51 +0800 Subject: [PATCH 2/6] ld: fix ld to use ram as much as possible, rearrange heap_alloc area --- components/esp32/heap_alloc_caps.c | 8 +++----- components/esp32/ld/esp32.ld | 6 +++--- 2 files changed, 6 insertions(+), 8 deletions(-) diff --git a/components/esp32/heap_alloc_caps.c b/components/esp32/heap_alloc_caps.c index 3f63c5d8a1..2d9ad060ef 100644 --- a/components/esp32/heap_alloc_caps.c +++ b/components/esp32/heap_alloc_caps.c @@ -77,9 +77,9 @@ This array is *NOT* const because it gets modified depending on what pools are/a */ static HeapRegionTagged_t regions[]={ { (uint8_t *)0x3F800000, 0x20000, 15, 0}, //SPI SRAM, if available -// { (uint8_t *)0x3FFAE000, 0x2000, 0, 0}, //pool 16 <- can be used for BT <- THIS POOL DOESN'T WORK for some reason! Hw seems fine. ToDo: Figure out. + { (uint8_t *)0x3FFAE000, 0x2000, 0, 0}, //pool 16 <- used for rom code { (uint8_t *)0x3FFB0000, 0x8000, 0, 0}, //pool 15 <- can be used for BT - { (uint8_t *)0x3FFB8000, 0x8000, 0, 0}, //pool 14 + { (uint8_t *)0x3FFB8000, 0x8000, 0, 0}, //pool 14 <- can be used for BT { (uint8_t *)0x3FFC0000, 0x2000, 0, 0}, //pool 10-13, mmu page 0 { (uint8_t *)0x3FFC2000, 0x2000, 0, 0}, //pool 10-13, mmu page 1 { (uint8_t *)0x3FFC4000, 0x2000, 0, 0}, //pool 10-13, mmu page 2 @@ -158,7 +158,6 @@ static void disable_mem_region(void *from, void *to) { ToDo: These are very dependent on the linker script, and the logic involving this works only because we're not using the SPI flash yet! If we enable that, this will break. ToDo: Rewrite by then. */ -extern int _init_start, _text_end; extern int _bss_start, _heap_start; /* @@ -170,12 +169,11 @@ Same with loading of apps. Same with using SPI RAM. void heap_alloc_caps_init() { int i; //Disable the bits of memory where this code is loaded. - disable_mem_region(&_init_start, &_text_end); disable_mem_region(&_bss_start, &_heap_start); disable_mem_region((void*)0x3ffae000, (void*)0x3ffb0000); //knock out ROM data region - disable_mem_region((void*)0x3ffe0000, (void*)0x3ffe8000); //knock out ROM data region disable_mem_region((void*)0x40070000, (void*)0x40078000); //CPU0 cache region disable_mem_region((void*)0x40078000, (void*)0x40080000); //CPU1 cache region + disable_mem_region((void*)0x40080000, (void*)0x400a0000); //pool 2-5 #if 0 enable_spi_sram(); #else diff --git a/components/esp32/ld/esp32.ld b/components/esp32/ld/esp32.ld index 4cb1c99bfa..becbc6baac 100644 --- a/components/esp32/ld/esp32.ld +++ b/components/esp32/ld/esp32.ld @@ -5,10 +5,10 @@ MEMORY /* All these values assume the flash cache is on, and have the blocks this uses subtracted from the length of the various regions. The 'data access port' dram/drom regions map to the same iram/irom regions but are connected to the data port of the CPU and eg allow bytewise access. */ - iram0_0_seg (RX) : org = 0x40080000, len = 0x18000 /* IRAM for PRO cpu. Not sure if happy with this, this is MMU area... */ + iram0_0_seg (RX) : org = 0x40080000, len = 0x20000 /* IRAM for PRO cpu. Not sure if happy with this, this is MMU area... */ iram0_2_seg (RX) : org = 0x400D0018, len = 0x330000 /* Even though the segment name is iram, it is actually mapped to flash */ - dram0_0_seg (RW) : org = 0x3FFC0000, len = 0x20000 /* Shared RAM, minus rom bss/data/stack.*/ + dram0_0_seg (RW) : org = 0x3FFB0000, len = 0x50000 /* Shared RAM, minus rom bss/data/stack.*/ drom0_0_seg (R) : org = 0x3F400010, len = 0x800000 } -_heap_end = 0x3fffe000; +_heap_end = 0x40000000; From ef36779bd365b1093e8d90e88e4d37c657e00f24 Mon Sep 17 00:00:00 2001 From: Wu Jian Gang Date: Fri, 19 Aug 2016 18:45:49 +0800 Subject: [PATCH 3/6] ld: add ld for bt/trace, choose different ld by menuconfig --- components/esp32/Makefile | 20 ++++++++++++++++++-- components/esp32/ld/esp32.bt.ld | 14 ++++++++++++++ components/esp32/ld/esp32.bt.trace.ld | 14 ++++++++++++++ components/esp32/ld/esp32.trace.ld | 14 ++++++++++++++ 4 files changed, 60 insertions(+), 2 deletions(-) create mode 100644 components/esp32/ld/esp32.bt.ld create mode 100644 components/esp32/ld/esp32.bt.trace.ld create mode 100644 components/esp32/ld/esp32.trace.ld diff --git a/components/esp32/Makefile b/components/esp32/Makefile index 8430bf5400..2331f286c6 100644 --- a/components/esp32/Makefile +++ b/components/esp32/Makefile @@ -6,16 +6,32 @@ # lib(subdirectory_name).a in the build directory. This behaviour is entirely configurable, # please read the esp-idf build system document if you need to do this. # +-include $(PROJECT_PATH)/build/include/config/auto.conf LIBS := crypto core net80211 phy rtc pp wpa wps +ifeq ($(CONFIG_MEMMAP_BT),y) + ifeq ($(CONFIG_MEMMAP_TRACEMEM),y) + LINKER_SCRIPTS = -T esp32.bt.trace.ld + else + LINKER_SCRIPTS = -T esp32.bt.ld + endif +else + ifeq ($(CONFIG_MEMMAP_TRACEMEM),y) + LINKER_SCRIPTS = -T esp32.trace.ld + else + LINKER_SCRIPTS = -T esp32.ld + endif +endif + +LINKER_SCRIPTS += -T esp32.common.ld -T esp32.rom.ld + COMPONENT_ADD_LDFLAGS := -lesp32 \ $(abspath libhal.a) \ -L$(abspath lib) \ $(addprefix -l,$(LIBS)) \ -L $(abspath ld) \ - -T eagle.fpga32.v7.ld \ - -T eagle.fpga32.rom.addr.v7.ld + $(LINKER_SCRIPTS) include $(IDF_PATH)/make/component.mk diff --git a/components/esp32/ld/esp32.bt.ld b/components/esp32/ld/esp32.bt.ld new file mode 100644 index 0000000000..90d0f491bc --- /dev/null +++ b/components/esp32/ld/esp32.bt.ld @@ -0,0 +1,14 @@ +/* THESE ARE THE VIRTUAL RUNTIME ADDRESSES */ +/* The load addresses are defined later using the AT statements. */ +MEMORY +{ + /* All these values assume the flash cache is on, and have the blocks this uses subtracted from the length + of the various regions. The 'data access port' dram/drom regions map to the same iram/irom regions but + are connected to the data port of the CPU and eg allow bytewise access. */ + iram0_0_seg (RX) : org = 0x40080000, len = 0x20000 /* IRAM for PRO cpu. Not sure if happy with this, this is MMU area... */ + iram0_2_seg (RX) : org = 0x400D0018, len = 0x330000 /* Even though the segment name is iram, it is actually mapped to flash */ + dram0_0_seg (RW) : org = 0x3FFC0000, len = 0x40000 /* Shared RAM, minus rom bss/data/stack.*/ + drom0_0_seg (R) : org = 0x3F400010, len = 0x800000 +} + +_heap_end = 0x40000000; diff --git a/components/esp32/ld/esp32.bt.trace.ld b/components/esp32/ld/esp32.bt.trace.ld new file mode 100644 index 0000000000..d4d7069eb0 --- /dev/null +++ b/components/esp32/ld/esp32.bt.trace.ld @@ -0,0 +1,14 @@ +/* THESE ARE THE VIRTUAL RUNTIME ADDRESSES */ +/* The load addresses are defined later using the AT statements. */ +MEMORY +{ + /* All these values assume the flash cache is on, and have the blocks this uses subtracted from the length + of the various regions. The 'data access port' dram/drom regions map to the same iram/irom regions but + are connected to the data port of the CPU and eg allow bytewise access. */ + iram0_0_seg (RX) : org = 0x40080000, len = 0x20000 /* IRAM for PRO cpu. Not sure if happy with this, this is MMU area... */ + iram0_2_seg (RX) : org = 0x400D0018, len = 0x330000 /* Even though the segment name is iram, it is actually mapped to flash */ + dram0_0_seg (RW) : org = 0x3FFC0000, len = 0x38000 /* Shared RAM, minus rom bss/data/stack.*/ + drom0_0_seg (R) : org = 0x3F400010, len = 0x800000 +} + +_heap_end = 0x3FFF8000; diff --git a/components/esp32/ld/esp32.trace.ld b/components/esp32/ld/esp32.trace.ld new file mode 100644 index 0000000000..f619f8d984 --- /dev/null +++ b/components/esp32/ld/esp32.trace.ld @@ -0,0 +1,14 @@ +/* THESE ARE THE VIRTUAL RUNTIME ADDRESSES */ +/* The load addresses are defined later using the AT statements. */ +MEMORY +{ + /* All these values assume the flash cache is on, and have the blocks this uses subtracted from the length + of the various regions. The 'data access port' dram/drom regions map to the same iram/irom regions but + are connected to the data port of the CPU and eg allow bytewise access. */ + iram0_0_seg (RX) : org = 0x40080000, len = 0x20000 /* IRAM for PRO cpu. Not sure if happy with this, this is MMU area... */ + iram0_2_seg (RX) : org = 0x400D0018, len = 0x330000 /* Even though the segment name is iram, it is actually mapped to flash */ + dram0_0_seg (RW) : org = 0x3FFB0000, len = 0x48000 /* Shared RAM, minus rom bss/data/stack.*/ + drom0_0_seg (R) : org = 0x3F400010, len = 0x800000 +} + +_heap_end = 0x3FFF8000; From c72248193b23777d20eca4066ef6def1bb6a849a Mon Sep 17 00:00:00 2001 From: Wu Jian Gang Date: Mon, 22 Aug 2016 12:02:20 +0800 Subject: [PATCH 4/6] ld: fix ld for bootloader --- components/bootloader/src/main/Makefile | 2 +- .../src/main/{eagle.bootloader.ld => esp32.bootloader.ld} | 0 2 files changed, 1 insertion(+), 1 deletion(-) rename components/bootloader/src/main/{eagle.bootloader.ld => esp32.bootloader.ld} (100%) diff --git a/components/bootloader/src/main/Makefile b/components/bootloader/src/main/Makefile index 8b7cd6843a..2bb773b9c6 100644 --- a/components/bootloader/src/main/Makefile +++ b/components/bootloader/src/main/Makefile @@ -7,7 +7,7 @@ # please read the esp-idf build system document if you need to do this. # -COMPONENT_ADD_LDFLAGS := -L $(abspath .) -lmain -T eagle.bootloader.ld -T $(IDF_PATH)/components/esp32/ld/eagle.fpga32.rom.addr.v7.ld +COMPONENT_ADD_LDFLAGS := -L $(abspath .) -lmain -T esp32.bootloader.ld -T $(IDF_PATH)/components/esp32/ld/esp32.rom.ld COMPONENT_EXTRA_INCLUDES := $(IDF_PATH)/components/esp32/include include $(IDF_PATH)/make/component.mk diff --git a/components/bootloader/src/main/eagle.bootloader.ld b/components/bootloader/src/main/esp32.bootloader.ld similarity index 100% rename from components/bootloader/src/main/eagle.bootloader.ld rename to components/bootloader/src/main/esp32.bootloader.ld From 28865fcb0db3649c7fb91dccf6dc7789de2c18c0 Mon Sep 17 00:00:00 2001 From: Wu Jian Gang Date: Thu, 25 Aug 2016 11:06:51 +0800 Subject: [PATCH 5/6] mem: knock out bt/trace data region if configed in menuconfig --- components/esp32/heap_alloc_caps.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/components/esp32/heap_alloc_caps.c b/components/esp32/heap_alloc_caps.c index 2d9ad060ef..34e8ba7864 100644 --- a/components/esp32/heap_alloc_caps.c +++ b/components/esp32/heap_alloc_caps.c @@ -171,9 +171,19 @@ void heap_alloc_caps_init() { //Disable the bits of memory where this code is loaded. disable_mem_region(&_bss_start, &_heap_start); disable_mem_region((void*)0x3ffae000, (void*)0x3ffb0000); //knock out ROM data region + disable_mem_region((void*)0x3ffe0000, (void*)0x3ffe8000); //knock out ROM data region disable_mem_region((void*)0x40070000, (void*)0x40078000); //CPU0 cache region disable_mem_region((void*)0x40078000, (void*)0x40080000); //CPU1 cache region disable_mem_region((void*)0x40080000, (void*)0x400a0000); //pool 2-5 + +#if CONFIG_MEMMAP_BT + disable_mem_region((void*)0x3ffb0000, (void*)0x3ffc0000); //knock out BT data region +#endif + +#if CONFIG_MEMMAP_TRACEMEM + disable_mem_region((void*)0x3fff8000, (void*)0x40000000); //knock out trace mem region +#endif + #if 0 enable_spi_sram(); #else From 62296d9dfd8731b1810e3de582e5014b03dc367d Mon Sep 17 00:00:00 2001 From: Wu Jian Gang Date: Thu, 25 Aug 2016 11:59:29 +0800 Subject: [PATCH 6/6] mem: add comments for knock out 0x3ffe0000~0x3ffe8000 TODO: this region should be checked later --- components/esp32/heap_alloc_caps.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/components/esp32/heap_alloc_caps.c b/components/esp32/heap_alloc_caps.c index 34e8ba7864..e816175b94 100644 --- a/components/esp32/heap_alloc_caps.c +++ b/components/esp32/heap_alloc_caps.c @@ -171,17 +171,19 @@ void heap_alloc_caps_init() { //Disable the bits of memory where this code is loaded. disable_mem_region(&_bss_start, &_heap_start); disable_mem_region((void*)0x3ffae000, (void*)0x3ffb0000); //knock out ROM data region - disable_mem_region((void*)0x3ffe0000, (void*)0x3ffe8000); //knock out ROM data region disable_mem_region((void*)0x40070000, (void*)0x40078000); //CPU0 cache region disable_mem_region((void*)0x40078000, (void*)0x40080000); //CPU1 cache region disable_mem_region((void*)0x40080000, (void*)0x400a0000); //pool 2-5 + // TODO: this region should be checked, since we don't need to knock out all region finally + disable_mem_region((void*)0x3ffe0000, (void*)0x3ffe8000); //knock out ROM data region + #if CONFIG_MEMMAP_BT disable_mem_region((void*)0x3ffb0000, (void*)0x3ffc0000); //knock out BT data region #endif #if CONFIG_MEMMAP_TRACEMEM - disable_mem_region((void*)0x3fff8000, (void*)0x40000000); //knock out trace mem region + disable_mem_region((void*)0x3fff8000, (void*)0x40000000); //knock out trace mem region #endif #if 0