From f55ab6f17cdbb7cfe89be03f6432cfbef930eb4c Mon Sep 17 00:00:00 2001 From: wuzhenghui Date: Fri, 12 Jul 2024 15:40:36 +0800 Subject: [PATCH] fix(esp_hw_support): fix cpu_retention cache invalidate mask --- .../lowpower/cpu_retention/port/esp32p4/sleep_cpu_asm.S | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/components/esp_hw_support/lowpower/cpu_retention/port/esp32p4/sleep_cpu_asm.S b/components/esp_hw_support/lowpower/cpu_retention/port/esp32p4/sleep_cpu_asm.S index 046ef61777..f6d8a9d6dd 100644 --- a/components/esp_hw_support/lowpower/cpu_retention/port/esp32p4/sleep_cpu_asm.S +++ b/components/esp_hw_support/lowpower/cpu_retention/port/esp32p4/sleep_cpu_asm.S @@ -10,7 +10,8 @@ #include "sdkconfig.h" #include "soc/cache_reg.h" -#define MTVT (0x307) +#define CACHE_MAP_L1_CACHE_MASK (BIT(0) | BIT(1) | BIT(4)) +#define MTVT (0x307) .section .tcm.data,"aw" .global rv_core_critical_regs_frame @@ -154,7 +155,7 @@ rv_core_critical_regs_restore: /* Core 0 is wakeup core, Invalidate L1 Cache here */ /* Invalidate L1 cache is required here!!! */ la t0, CACHE_SYNC_MAP_REG - li t1, 0x7 /* map l1 i/dcache */ + li t1, CACHE_MAP_L1_CACHE_MASK /* map l1 i/dcache */ sw t1, 0x0(t0) /* set EXTMEM_CACHE_SYNC_MAP_REG bit 4 */ la t2, CACHE_SYNC_ADDR_REG sw zero, 0x0(t2) /* clear EXTMEM_CACHE_SYNC_ADDR_REG */