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mcpwm: rename macros related to soc capbility

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This commit is contained in:
morris
2021-01-07 17:34:59 +08:00
parent be30289364
commit f5ca47c0fc
6 changed files with 59 additions and 41 deletions
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2
components/driver/include/driver/mcpwm.h
View File

@@ -86,7 +86,7 @@ typedef enum {
MCPWM_UNIT_MAX, /*!<Num of MCPWM units on ESP32*/ MCPWM_UNIT_MAX, /*!<Num of MCPWM units on ESP32*/
} mcpwm_unit_t; } mcpwm_unit_t;
_Static_assert(MCPWM_UNIT_MAX == SOC_MCPWM_PERIPH_NUM, "MCPWM unit number not equal to chip capabilities"); _Static_assert(MCPWM_UNIT_MAX == SOC_MCPWM_GROUPS, "MCPWM unit number not equal to chip capabilities");
/** /**
* @brief Select MCPWM timer * @brief Select MCPWM timer

39
components/driver/mcpwm.c
View File

@@ -47,13 +47,14 @@ static const char *MCPWM_TAG = "MCPWM";
} }
#define MCPWM_DRIVER_INIT_ERROR "MCPWM DRIVER NOT INITIALIZED" #define MCPWM_DRIVER_INIT_ERROR "MCPWM DRIVER NOT INITIALIZED"
#define MCPWM_UNIT_NUM_ERROR "MCPWM UNIT NUM ERROR" #define MCPWM_GROUP_NUM_ERROR "MCPWM GROUP NUM ERROR"
#define MCPWM_TIMER_ERROR "MCPWM TIMER NUM ERROR" #define MCPWM_TIMER_ERROR "MCPWM TIMER NUM ERROR"
#define MCPWM_CAPTURE_ERROR "MCPWM CAPTURE NUM ERROR"
#define MCPWM_PARAM_ADDR_ERROR "MCPWM PARAM ADDR ERROR" #define MCPWM_PARAM_ADDR_ERROR "MCPWM PARAM ADDR ERROR"
#define MCPWM_DUTY_TYPE_ERROR "MCPWM DUTY TYPE ERROR" #define MCPWM_DUTY_TYPE_ERROR "MCPWM DUTY TYPE ERROR"
#define MCPWM_GPIO_ERROR "MCPWM GPIO NUM ERROR" #define MCPWM_GPIO_ERROR "MCPWM GPIO NUM ERROR"
#define MCPWM_GEN_ERROR "MCPWM GENERATOR ERROR" #define MCPWM_GEN_ERROR "MCPWM GENERATOR ERROR"
#define MCPWM_DB_ERROR "MCPWM DEADTIME TYPE ERROR" #define MCPWM_DT_ERROR "MCPWM DEADTIME TYPE ERROR"
#define MCPWM_CLK_PRESCL 15 //MCPWM clock prescale #define MCPWM_CLK_PRESCL 15 //MCPWM clock prescale
#define TIMER_CLK_PRESCALE 9 //MCPWM timer prescales #define TIMER_CLK_PRESCALE 9 //MCPWM timer prescales
@@ -62,13 +63,13 @@ static const char *MCPWM_TAG = "MCPWM";
#define OFFSET_FOR_GPIO_IDX_1 6 #define OFFSET_FOR_GPIO_IDX_1 6
#define OFFSET_FOR_GPIO_IDX_2 75 #define OFFSET_FOR_GPIO_IDX_2 75
_Static_assert(SOC_MCPWM_OP_NUM >= SOC_MCPWM_TIMER_NUM, "This driver assumes the timer num equals to the operator num."); _Static_assert(SOC_MCPWM_OPERATORS_PER_GROUP >= SOC_MCPWM_TIMERS_PER_GROUP, "This driver assumes the timer num equals to the operator num.");
_Static_assert(SOC_MCPWM_COMPARATOR_NUM >= SOC_MCPWM_GENERATOR_NUM, "This driver assumes the generator num equals to the generator num."); _Static_assert(SOC_MCPWM_COMPARATORS_PER_OPERATOR >= SOC_MCPWM_GENERATORS_PER_OPERATOR, "This driver assumes the generator num equals to the generator num.");
_Static_assert(SOC_MCPWM_GENERATOR_NUM == 2, "This driver assumes the generator num equals to 2."); _Static_assert(SOC_MCPWM_GENERATORS_PER_OPERATOR == 2, "This driver assumes the generator num equals to 2.");
#define MCPWM_TIMER_ID_CHECK(mcpwm_num, timer_num) do {\ #define MCPWM_TIMER_ID_CHECK(mcpwm_num, timer_num) do {\
MCPWM_CHECK((mcpwm_num) < SOC_MCPWM_PERIPH_NUM, MCPWM_UNIT_NUM_ERROR, ESP_ERR_INVALID_ARG); \ MCPWM_CHECK((mcpwm_num) < SOC_MCPWM_GROUPS, MCPWM_GROUP_NUM_ERROR, ESP_ERR_INVALID_ARG); \
MCPWM_CHECK((timer_num) < SOC_MCPWM_TIMER_NUM, MCPWM_TIMER_ERROR, ESP_ERR_INVALID_ARG); \ MCPWM_CHECK((timer_num) < SOC_MCPWM_TIMERS_PER_GROUP, MCPWM_TIMER_ERROR, ESP_ERR_INVALID_ARG); \
} while(0) } while(0)
#define MCPWM_TIMER_CHECK(mcpwm_num, timer_num) do{\ #define MCPWM_TIMER_CHECK(mcpwm_num, timer_num) do{\
@@ -82,7 +83,7 @@ _Static_assert(SOC_MCPWM_GENERATOR_NUM == 2, "This driver assumes the generator
} while(0) } while(0)
static mcpwm_context_t context[SOC_MCPWM_PERIPH_NUM] = { static mcpwm_context_t context[SOC_MCPWM_GROUPS] = {
CONTEXT_INITIALIZER(), CONTEXT_INITIALIZER(),
CONTEXT_INITIALIZER(), CONTEXT_INITIALIZER(),
}; };
@@ -105,7 +106,7 @@ esp_err_t mcpwm_gpio_init(mcpwm_unit_t mcpwm_num, mcpwm_io_signals_t io_signal,
return ESP_OK; return ESP_OK;
} }
MCPWM_CHECK(mcpwm_num < SOC_MCPWM_PERIPH_NUM, MCPWM_UNIT_NUM_ERROR, ESP_ERR_INVALID_ARG); MCPWM_CHECK(mcpwm_num < SOC_MCPWM_GROUPS, MCPWM_GROUP_NUM_ERROR, ESP_ERR_INVALID_ARG);
MCPWM_CHECK((GPIO_IS_VALID_GPIO(gpio_num)), MCPWM_GPIO_ERROR, ESP_ERR_INVALID_ARG); MCPWM_CHECK((GPIO_IS_VALID_GPIO(gpio_num)), MCPWM_GPIO_ERROR, ESP_ERR_INVALID_ARG);
periph_module_enable(PERIPH_PWM0_MODULE + mcpwm_num); periph_module_enable(PERIPH_PWM0_MODULE + mcpwm_num);
@@ -138,7 +139,7 @@ esp_err_t mcpwm_gpio_init(mcpwm_unit_t mcpwm_num, mcpwm_io_signals_t io_signal,
esp_err_t mcpwm_set_pin(mcpwm_unit_t mcpwm_num, const mcpwm_pin_config_t *mcpwm_pin) esp_err_t mcpwm_set_pin(mcpwm_unit_t mcpwm_num, const mcpwm_pin_config_t *mcpwm_pin)
{ {
MCPWM_CHECK(mcpwm_num < SOC_MCPWM_PERIPH_NUM, MCPWM_UNIT_NUM_ERROR, ESP_ERR_INVALID_ARG); MCPWM_CHECK(mcpwm_num < SOC_MCPWM_GROUPS, MCPWM_GROUP_NUM_ERROR, ESP_ERR_INVALID_ARG);
mcpwm_gpio_init(mcpwm_num, MCPWM0A, mcpwm_pin->mcpwm0a_out_num); //MCPWM0A mcpwm_gpio_init(mcpwm_num, MCPWM0A, mcpwm_pin->mcpwm0a_out_num); //MCPWM0A
mcpwm_gpio_init(mcpwm_num, MCPWM0B, mcpwm_pin->mcpwm0b_out_num); //MCPWM0B mcpwm_gpio_init(mcpwm_num, MCPWM0B, mcpwm_pin->mcpwm0b_out_num); //MCPWM0B
mcpwm_gpio_init(mcpwm_num, MCPWM1A, mcpwm_pin->mcpwm1a_out_num); //MCPWM1A mcpwm_gpio_init(mcpwm_num, MCPWM1A, mcpwm_pin->mcpwm1a_out_num); //MCPWM1A
@@ -274,7 +275,7 @@ esp_err_t mcpwm_init(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num, const mcpw
//update the comparer to keep the same duty rate //update the comparer to keep the same duty rate
mcpwm_hal_operator_update_basic(hal, op); mcpwm_hal_operator_update_basic(hal, op);
for (int gen = 0; gen < SOC_MCPWM_GENERATOR_NUM; gen++) { for (int gen = 0; gen < SOC_MCPWM_GENERATORS_PER_OPERATOR; gen++) {
hal->op[op].gen[gen] = (mcpwm_hal_generator_config_t) { hal->op[op].gen[gen] = (mcpwm_hal_generator_config_t) {
.comparator = gen, //the driver currently always use the comparator A for PWMxA output, and comparator B for PWMxB output .comparator = gen, //the driver currently always use the comparator A for PWMxA output, and comparator B for PWMxB output
.duty_type = mcpwm_conf->duty_mode, .duty_type = mcpwm_conf->duty_mode,
@@ -447,7 +448,7 @@ esp_err_t mcpwm_deadtime_enable(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num,
//the driver currently always use the timer x for operator x //the driver currently always use the timer x for operator x
const int op = timer_num; const int op = timer_num;
MCPWM_TIMER_CHECK(mcpwm_num, timer_num); MCPWM_TIMER_CHECK(mcpwm_num, timer_num);
MCPWM_CHECK(dt_mode < MCPWM_DEADTIME_TYPE_MAX, MCPWM_DB_ERROR, ESP_ERR_INVALID_ARG); MCPWM_CHECK(dt_mode < MCPWM_DEADTIME_TYPE_MAX, MCPWM_DT_ERROR, ESP_ERR_INVALID_ARG);
mcpwm_hal_context_t *hal = &context[mcpwm_num].hal; mcpwm_hal_context_t *hal = &context[mcpwm_num].hal;
mcpwm_hal_deadzone_conf_t deadzone = { mcpwm_hal_deadzone_conf_t deadzone = {
.red = red, .red = red,
@@ -477,7 +478,7 @@ esp_err_t mcpwm_deadtime_disable(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num
esp_err_t mcpwm_fault_init(mcpwm_unit_t mcpwm_num, mcpwm_fault_input_level_t intput_level, mcpwm_fault_signal_t fault_sig) esp_err_t mcpwm_fault_init(mcpwm_unit_t mcpwm_num, mcpwm_fault_input_level_t intput_level, mcpwm_fault_signal_t fault_sig)
{ {
MCPWM_CHECK(mcpwm_num < SOC_MCPWM_PERIPH_NUM, MCPWM_UNIT_NUM_ERROR, ESP_ERR_INVALID_ARG); MCPWM_CHECK(mcpwm_num < SOC_MCPWM_GROUPS, MCPWM_GROUP_NUM_ERROR, ESP_ERR_INVALID_ARG);
mcpwm_critical_enter(mcpwm_num); mcpwm_critical_enter(mcpwm_num);
mcpwm_hal_fault_init(&context[mcpwm_num].hal, fault_sig, intput_level); mcpwm_hal_fault_init(&context[mcpwm_num].hal, fault_sig, intput_level);
@@ -487,7 +488,7 @@ esp_err_t mcpwm_fault_init(mcpwm_unit_t mcpwm_num, mcpwm_fault_input_level_t int
esp_err_t mcpwm_fault_deinit(mcpwm_unit_t mcpwm_num, mcpwm_fault_signal_t fault_sig) esp_err_t mcpwm_fault_deinit(mcpwm_unit_t mcpwm_num, mcpwm_fault_signal_t fault_sig)
{ {
MCPWM_CHECK(mcpwm_num < SOC_MCPWM_PERIPH_NUM, MCPWM_UNIT_NUM_ERROR, ESP_ERR_INVALID_ARG); MCPWM_CHECK(mcpwm_num < SOC_MCPWM_GROUPS, MCPWM_GROUP_NUM_ERROR, ESP_ERR_INVALID_ARG);
mcpwm_critical_enter(mcpwm_num); mcpwm_critical_enter(mcpwm_num);
mcpwm_hal_fault_disable(&context[mcpwm_num].hal, fault_sig); mcpwm_hal_fault_disable(&context[mcpwm_num].hal, fault_sig);
@@ -533,7 +534,7 @@ esp_err_t mcpwm_fault_set_oneshot_mode(mcpwm_unit_t mcpwm_num, mcpwm_timer_t tim
esp_err_t mcpwm_capture_enable(mcpwm_unit_t mcpwm_num, mcpwm_capture_signal_t cap_sig, mcpwm_capture_on_edge_t cap_edge, esp_err_t mcpwm_capture_enable(mcpwm_unit_t mcpwm_num, mcpwm_capture_signal_t cap_sig, mcpwm_capture_on_edge_t cap_edge,
uint32_t num_of_pulse) uint32_t num_of_pulse)
{ {
MCPWM_CHECK(mcpwm_num < SOC_MCPWM_PERIPH_NUM, MCPWM_UNIT_NUM_ERROR, ESP_ERR_INVALID_ARG); MCPWM_CHECK(mcpwm_num < SOC_MCPWM_GROUPS, MCPWM_GROUP_NUM_ERROR, ESP_ERR_INVALID_ARG);
mcpwm_hal_init_config_t init_config = { mcpwm_hal_init_config_t init_config = {
.host_id = mcpwm_num, .host_id = mcpwm_num,
}; };
@@ -555,7 +556,7 @@ esp_err_t mcpwm_capture_enable(mcpwm_unit_t mcpwm_num, mcpwm_capture_signal_t ca
esp_err_t mcpwm_capture_disable(mcpwm_unit_t mcpwm_num, mcpwm_capture_signal_t cap_sig) esp_err_t mcpwm_capture_disable(mcpwm_unit_t mcpwm_num, mcpwm_capture_signal_t cap_sig)
{ {
MCPWM_CHECK(mcpwm_num < SOC_MCPWM_PERIPH_NUM, MCPWM_UNIT_NUM_ERROR, ESP_ERR_INVALID_ARG); MCPWM_CHECK(mcpwm_num < SOC_MCPWM_GROUPS, MCPWM_GROUP_NUM_ERROR, ESP_ERR_INVALID_ARG);
mcpwm_critical_enter(mcpwm_num); mcpwm_critical_enter(mcpwm_num);
mcpwm_hal_capture_disable(&context[mcpwm_num].hal, cap_sig); mcpwm_hal_capture_disable(&context[mcpwm_num].hal, cap_sig);
@@ -565,7 +566,7 @@ esp_err_t mcpwm_capture_disable(mcpwm_unit_t mcpwm_num, mcpwm_capture_signal_t c
uint32_t mcpwm_capture_signal_get_value(mcpwm_unit_t mcpwm_num, mcpwm_capture_signal_t cap_sig) uint32_t mcpwm_capture_signal_get_value(mcpwm_unit_t mcpwm_num, mcpwm_capture_signal_t cap_sig)
{ {
MCPWM_CHECK(mcpwm_num < SOC_MCPWM_PERIPH_NUM, MCPWM_UNIT_NUM_ERROR, ESP_ERR_INVALID_ARG); MCPWM_CHECK(mcpwm_num < SOC_MCPWM_GROUPS, MCPWM_GROUP_NUM_ERROR, ESP_ERR_INVALID_ARG);
uint32_t captured_value; uint32_t captured_value;
mcpwm_hal_capture_get_result(&context[mcpwm_num].hal, cap_sig, &captured_value, NULL); mcpwm_hal_capture_get_result(&context[mcpwm_num].hal, cap_sig, &captured_value, NULL);
@@ -574,7 +575,7 @@ uint32_t mcpwm_capture_signal_get_value(mcpwm_unit_t mcpwm_num, mcpwm_capture_si
uint32_t mcpwm_capture_signal_get_edge(mcpwm_unit_t mcpwm_num, mcpwm_capture_signal_t cap_sig) uint32_t mcpwm_capture_signal_get_edge(mcpwm_unit_t mcpwm_num, mcpwm_capture_signal_t cap_sig)
{ {
MCPWM_CHECK(mcpwm_num < SOC_MCPWM_PERIPH_NUM, MCPWM_UNIT_NUM_ERROR, ESP_ERR_INVALID_ARG); MCPWM_CHECK(mcpwm_num < SOC_MCPWM_GROUPS, MCPWM_GROUP_NUM_ERROR, ESP_ERR_INVALID_ARG);
mcpwm_capture_on_edge_t edge; mcpwm_capture_on_edge_t edge;
mcpwm_hal_capture_get_result(&context[mcpwm_num].hal, cap_sig, NULL, &edge); mcpwm_hal_capture_get_result(&context[mcpwm_num].hal, cap_sig, NULL, &edge);
return (edge == MCPWM_NEG_EDGE ? 2 : 1); return (edge == MCPWM_NEG_EDGE ? 2 : 1);
@@ -609,7 +610,7 @@ esp_err_t mcpwm_sync_disable(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num)
esp_err_t mcpwm_isr_register(mcpwm_unit_t mcpwm_num, void (*fn)(void *), void *arg, int intr_alloc_flags, intr_handle_t *handle) esp_err_t mcpwm_isr_register(mcpwm_unit_t mcpwm_num, void (*fn)(void *), void *arg, int intr_alloc_flags, intr_handle_t *handle)
{ {
esp_err_t ret; esp_err_t ret;
MCPWM_CHECK(mcpwm_num < SOC_MCPWM_PERIPH_NUM, MCPWM_UNIT_NUM_ERROR, ESP_ERR_INVALID_ARG); MCPWM_CHECK(mcpwm_num < SOC_MCPWM_GROUPS, MCPWM_GROUP_NUM_ERROR, ESP_ERR_INVALID_ARG);
MCPWM_CHECK(fn != NULL, MCPWM_PARAM_ADDR_ERROR, ESP_ERR_INVALID_ARG); MCPWM_CHECK(fn != NULL, MCPWM_PARAM_ADDR_ERROR, ESP_ERR_INVALID_ARG);
ret = esp_intr_alloc((ETS_PWM0_INTR_SOURCE + mcpwm_num), intr_alloc_flags, fn, arg, handle); ret = esp_intr_alloc((ETS_PWM0_INTR_SOURCE + mcpwm_num), intr_alloc_flags, fn, arg, handle);
return ret; return ret;

10
components/hal/include/hal/mcpwm_hal.h
View File

@@ -87,8 +87,8 @@ typedef struct {
/// Configuration of each operator /// Configuration of each operator
typedef struct { typedef struct {
mcpwm_hal_generator_config_t gen[SOC_MCPWM_GENERATOR_NUM]; ///< Configuration of the generators mcpwm_hal_generator_config_t gen[SOC_MCPWM_GENERATORS_PER_OPERATOR]; ///< Configuration of the generators
float duty[SOC_MCPWM_COMPARATOR_NUM]; ///< Duty rate for each comparator, 10 means 10%. float duty[SOC_MCPWM_COMPARATORS_PER_OPERATOR]; ///< Duty rate for each comparator, 10 means 10%.
int timer; ///< The timer this operator is using int timer; ///< The timer this operator is using
} mcpwm_hal_operator_config_t; } mcpwm_hal_operator_config_t;
@@ -102,8 +102,8 @@ typedef struct {
typedef struct { typedef struct {
mcpwm_dev_t *dev; ///< Beginning address of the MCPWM peripheral registers. Call `mcpwm_hal_init` to initialize it. mcpwm_dev_t *dev; ///< Beginning address of the MCPWM peripheral registers. Call `mcpwm_hal_init` to initialize it.
uint32_t prescale; ///< Prescale from the 160M clock to MCPWM main clock. uint32_t prescale; ///< Prescale from the 160M clock to MCPWM main clock.
mcpwm_hal_timer_config_t timer[SOC_MCPWM_TIMER_NUM]; ///< Configuration of the timers mcpwm_hal_timer_config_t timer[SOC_MCPWM_TIMERS_PER_GROUP]; ///< Configuration of the timers
mcpwm_hal_operator_config_t op[SOC_MCPWM_OP_NUM]; ///< Configuration of the operators mcpwm_hal_operator_config_t op[SOC_MCPWM_OPERATORS_PER_GROUP]; ///< Configuration of the operators
} mcpwm_hal_context_t; } mcpwm_hal_context_t;
/// Configuration of the carrier /// Configuration of the carrier
@@ -125,7 +125,7 @@ typedef struct {
typedef struct { typedef struct {
uint32_t cbc_enabled_mask; ///< Whether the cycle-by-cycle fault handling is enabled on each fault signal. BIT(n) stands for signal n. uint32_t cbc_enabled_mask; ///< Whether the cycle-by-cycle fault handling is enabled on each fault signal. BIT(n) stands for signal n.
uint32_t ost_enabled_mask; ///< Whether the oneshot fault handling is enabled on each on each fault signal. BIT(n) stands for signal n. uint32_t ost_enabled_mask; ///< Whether the oneshot fault handling is enabled on each on each fault signal. BIT(n) stands for signal n.
mcpwm_output_action_t action_on_fault[SOC_MCPWM_GENERATOR_NUM]; ///< Action to perform on each generator when any one of the fault signal triggers. mcpwm_output_action_t action_on_fault[SOC_MCPWM_GENERATORS_PER_OPERATOR]; ///< Action to perform on each generator when any one of the fault signal triggers.
} mcpwm_hal_fault_conf_t; } mcpwm_hal_fault_conf_t;
/// Configuration of the synchronization of each clock /// Configuration of the synchronization of each clock

14
components/hal/mcpwm_hal.c
View File

@@ -70,10 +70,10 @@ void mcpwm_hal_operator_update_basic(mcpwm_hal_context_t *hal, int op)
{ {
mcpwm_hal_operator_config_t *op_conf = &hal->op[op]; mcpwm_hal_operator_config_t *op_conf = &hal->op[op];
mcpwm_ll_operator_select_timer(hal->dev, op, op_conf->timer); mcpwm_ll_operator_select_timer(hal->dev, op, op_conf->timer);
for (int cmp = 0; cmp < SOC_MCPWM_COMPARATOR_NUM; cmp++) { for (int cmp = 0; cmp < SOC_MCPWM_COMPARATORS_PER_OPERATOR; cmp++) {
mcpwm_hal_operator_update_comparator(hal, op, cmp); mcpwm_hal_operator_update_comparator(hal, op, cmp);
} }
for (int gen = 0; gen < SOC_MCPWM_GENERATOR_NUM; gen++) { for (int gen = 0; gen < SOC_MCPWM_GENERATORS_PER_OPERATOR; gen++) {
mcpwm_hal_operator_update_generator(hal, op, gen); mcpwm_hal_operator_update_generator(hal, op, gen);
} }
} }
@@ -166,21 +166,21 @@ void mcpwm_hal_fault_init(mcpwm_hal_context_t *hal, int fault_sig, bool level)
void mcpwm_hal_operator_update_fault(mcpwm_hal_context_t *hal, int op, const mcpwm_hal_fault_conf_t *fault_conf) void mcpwm_hal_operator_update_fault(mcpwm_hal_context_t *hal, int op, const mcpwm_hal_fault_conf_t *fault_conf)
{ {
for (int fault_sig = 0; fault_sig < SOC_MCPWM_FAULT_SIG_NUM; fault_sig++) { for (int fault_sig = 0; fault_sig < SOC_MCPWM_FAULT_DETECTORS_PER_GROUP; fault_sig++) {
bool enabled = (fault_conf->cbc_enabled_mask & BIT(fault_sig)) ? true : false; bool enabled = (fault_conf->cbc_enabled_mask & BIT(fault_sig)) ? true : false;
mcpwm_ll_fault_cbc_enable_signal(hal->dev, op, fault_sig, enabled); mcpwm_ll_fault_cbc_enable_signal(hal->dev, op, fault_sig, enabled);
} }
for (int fault_sig = 0; fault_sig < SOC_MCPWM_FAULT_SIG_NUM; fault_sig++) { for (int fault_sig = 0; fault_sig < SOC_MCPWM_FAULT_DETECTORS_PER_GROUP; fault_sig++) {
bool enabled = (fault_conf->ost_enabled_mask & BIT(fault_sig)) ? true : false; bool enabled = (fault_conf->ost_enabled_mask & BIT(fault_sig)) ? true : false;
mcpwm_ll_fault_oneshot_enable_signal(hal->dev, op, fault_sig, enabled); mcpwm_ll_fault_oneshot_enable_signal(hal->dev, op, fault_sig, enabled);
} }
if (fault_conf->cbc_enabled_mask) { if (fault_conf->cbc_enabled_mask) {
for (int gen = 0; gen < SOC_MCPWM_GENERATOR_NUM; gen++) { for (int gen = 0; gen < SOC_MCPWM_GENERATORS_PER_OPERATOR; gen++) {
mcpwm_ll_fault_set_cyc_action(hal->dev, op, gen, fault_conf->action_on_fault[gen], fault_conf->action_on_fault[gen]); mcpwm_ll_fault_set_cyc_action(hal->dev, op, gen, fault_conf->action_on_fault[gen], fault_conf->action_on_fault[gen]);
} }
} }
if (fault_conf->ost_enabled_mask) { if (fault_conf->ost_enabled_mask) {
for (int gen = 0; gen < SOC_MCPWM_GENERATOR_NUM; gen++) { for (int gen = 0; gen < SOC_MCPWM_GENERATORS_PER_OPERATOR; gen++) {
mcpwm_ll_fault_set_oneshot_action(hal->dev, op, gen, fault_conf->action_on_fault[gen], fault_conf->action_on_fault[gen]); mcpwm_ll_fault_set_oneshot_action(hal->dev, op, gen, fault_conf->action_on_fault[gen], fault_conf->action_on_fault[gen]);
} }
} }
@@ -193,7 +193,7 @@ void mcpwm_hal_fault_oneshot_clear(mcpwm_hal_context_t *hal, int op)
void mcpwm_hal_fault_disable(mcpwm_hal_context_t *hal, int fault_sig) void mcpwm_hal_fault_disable(mcpwm_hal_context_t *hal, int fault_sig)
{ {
for (int op = 0; op < SOC_MCPWM_OP_NUM; op++) { for (int op = 0; op < SOC_MCPWM_OPERATORS_PER_GROUP; op++) {
if (mcpwm_ll_fault_oneshot_signal_enabled(hal->dev, op, fault_sig)) { if (mcpwm_ll_fault_oneshot_signal_enabled(hal->dev, op, fault_sig)) {
mcpwm_ll_fault_clear_ost(hal->dev, op); mcpwm_ll_fault_clear_ost(hal->dev, op);
} }

16
components/soc/esp32/include/soc/soc_caps.h
View File

@@ -150,12 +150,16 @@
#define SOC_LEDC_TIMER_BIT_WIDE_NUM (20) #define SOC_LEDC_TIMER_BIT_WIDE_NUM (20)
/*-------------------------- MCPWM CAPS --------------------------------------*/ /*-------------------------- MCPWM CAPS --------------------------------------*/
#define SOC_MCPWM_PERIPH_NUM 2 ///< MCPWM peripheral number #define SOC_MCPWM_GROUPS (2) ///< 2 MCPWM groups on the chip (i.e., the number of independent MCPWM peripherals)
#define SOC_MCPWM_TIMER_NUM 3 ///< Timer that each peripheral has #define SOC_MCPWM_TIMERS_PER_GROUP (3) ///< The number of timers that each group has
#define SOC_MCPWM_OP_NUM 3 ///< Operator that each peripheral has #define SOC_MCPWM_OPERATORS_PER_GROUP (3) ///< The number of operators that each group has
#define SOC_MCPWM_COMPARATOR_NUM 2 ///< Comparator that each operator has #define SOC_MCPWM_COMPARATORS_PER_OPERATOR (2) ///< The number of comparators that each operator has
#define SOC_MCPWM_GENERATOR_NUM 2 ///< Generator that each operator has #define SOC_MCPWM_GENERATORS_PER_OPERATOR (2) ///< The number of generators that each operator has
#define SOC_MCPWM_FAULT_SIG_NUM 3 ///< Fault signal number that each peripheral has #define SOC_MCPWM_FAULT_DETECTORS_PER_GROUP (3) ///< The number of fault signal detectors that each group has
#define SOC_MCPWM_CAPTURE_TIMERS_PER_GROUP (1) ///< The number of capture timers that each group has
#define SOC_MCPWM_CAPTURE_CHANNELS_PER_TIMER (3) ///< The number of capture channels that each capture timer has
#define SOC_MCPWM_EXT_SYNCERS_PER_GROUP (3) ///< The number of external syncers that each group has
#define SOC_MCPWM_BASE_CLK_HZ (160000000ULL) ///< Base Clock frequency of 160MHz
/*-------------------------- MPU CAPS ----------------------------------------*/ /*-------------------------- MPU CAPS ----------------------------------------*/
//TODO: correct the caller and remove unsupported lines //TODO: correct the caller and remove unsupported lines

13
components/soc/esp32s3/include/soc/soc_caps.h
View File

@@ -10,6 +10,7 @@
#define SOC_TWAI_SUPPORTED 1 #define SOC_TWAI_SUPPORTED 1
#define SOC_GDMA_SUPPORTED 1 #define SOC_GDMA_SUPPORTED 1
#define SOC_I80_LCD_SUPPORTED 1 #define SOC_I80_LCD_SUPPORTED 1
#define SOC_MCPWM_SUPPORTED 1
#define SOC_DEDICATED_GPIO_SUPPORTED 1 #define SOC_DEDICATED_GPIO_SUPPORTED 1
#define SOC_CPU_CORES_NUM 2 #define SOC_CPU_CORES_NUM 2
#define SOC_CACHE_SUPPORT_WRAP 1 #define SOC_CACHE_SUPPORT_WRAP 1
@@ -52,6 +53,18 @@
/*-------------------------- LEDC CAPS ---------------------------------------*/ /*-------------------------- LEDC CAPS ---------------------------------------*/
#include "ledc_caps.h" #include "ledc_caps.h"
/*-------------------------- MCPWM CAPS --------------------------------------*/
#define SOC_MCPWM_GROUPS (2) ///< 2 MCPWM groups on the chip (i.e., the number of independent MCPWM peripherals)
#define SOC_MCPWM_TIMERS_PER_GROUP (3) ///< The number of timers that each group has
#define SOC_MCPWM_OPERATORS_PER_GROUP (3) ///< The number of operators that each group has
#define SOC_MCPWM_COMPARATORS_PER_OPERATOR (2) ///< The number of comparators that each operator has
#define SOC_MCPWM_GENERATORS_PER_OPERATOR (2) ///< The number of generators that each operator has
#define SOC_MCPWM_FAULT_DETECTORS_PER_GROUP (3) ///< The number of fault signal detectors that each group has
#define SOC_MCPWM_CAPTURE_TIMERS_PER_GROUP (1) ///< The number of capture timers that each group has
#define SOC_MCPWM_CAPTURE_CHANNELS_PER_TIMER (3) ///< The number of capture channels that each capture timer has
#define SOC_MCPWM_EXT_SYNCERS_PER_GROUP (3) ///< The number of external syncers that each group has
#define SOC_MCPWM_BASE_CLK_HZ (160000000ULL) ///< Base Clock frequency of 160MHz
/*-------------------------- MPU CAPS ----------------------------------------*/ /*-------------------------- MPU CAPS ----------------------------------------*/
#include "mpu_caps.h" #include "mpu_caps.h"