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Merge branch 'feature/c3_IDF-2554' into 'master'

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global: Uses CCOUNT API instead of XTHAL macro

Closes IDF-2554

See merge request espressif/esp-idf!11954
This commit is contained in:
Angus Gratton
2021-01-13 12:55:21 +08:00
parent 820639cede dada7cd035
commit f683db7aea
27 changed files with 78 additions and 47 deletions
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components/esp_system/port/soc/esp32/clk.c
+2 -2
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@@ -16,8 +16,8 @@
#include "soc/rtc.h"
#include "soc/dport_reg.h"
#include "soc/dport_access.h"
#include "xtensa/core-macros.h"
#include "soc/i2s_reg.h"
#include "hal/cpu_hal.h"
#include "driver/periph_ctrl.h"
#include "bootloader_clock.h"
#include "hal/wdt_hal.h"
@@ -195,7 +195,7 @@ static void select_rtc_slow_clk(slow_clk_sel_t slow_clk)
rtc_clk_cpu_freq_set_config(&new_config);
// Re calculate the ccount to make time calculation correct.
XTHAL_SET_CCOUNT( (uint64_t)XTHAL_GET_CCOUNT() * new_freq_mhz / old_freq_mhz );
cpu_hal_set_cycle_count( (uint64_t)cpu_hal_get_cycle_count() * new_freq_mhz / old_freq_mhz );
}
/* This function is not exposed as an API at this point.
components/esp_system/port/soc/esp32c3/clk.c
+3 -4
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@@ -30,9 +30,9 @@
#include "soc/rtc.h"
#include "soc/rtc_periph.h"
#include "soc/i2s_reg.h"
#include "hal/cpu_hal.h"
#include "hal/wdt_hal.h"
#include "driver/periph_ctrl.h"
//#include "xtensa/core-macros.h"
#include "bootloader_clock.h"
#include "soc/syscon_reg.h"
#include "esp_rom_uart.h"
@@ -118,7 +118,7 @@ static const char *TAG = "clk";
rtc_cpu_freq_config_t old_config, new_config;
rtc_clk_cpu_freq_get_config(&old_config);
//const uint32_t old_freq_mhz = old_config.freq_mhz;
const uint32_t old_freq_mhz = old_config.freq_mhz;
const uint32_t new_freq_mhz = CONFIG_ESP32C3_DEFAULT_CPU_FREQ_MHZ;
bool res = rtc_clk_cpu_freq_mhz_to_config(new_freq_mhz, &new_config);
@@ -131,8 +131,7 @@ static const char *TAG = "clk";
rtc_clk_cpu_freq_set_config(&new_config);
// Re calculate the ccount to make time calculation correct.
// TODO ESP32-C3 IDF-2554 apply same adjustment
//XTHAL_SET_CCOUNT( (uint64_t)XTHAL_GET_CCOUNT() * new_freq_mhz / old_freq_mhz );
cpu_hal_set_cycle_count( (uint64_t)cpu_hal_get_cycle_count() * new_freq_mhz / old_freq_mhz );
}
static void select_rtc_slow_clk(slow_clk_sel_t slow_clk)
components/esp_system/port/soc/esp32s2/clk.c
+3 -3
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@@ -28,11 +28,11 @@
#include "soc/dport_access.h"
#include "soc/soc.h"
#include "soc/rtc.h"
#include "hal/wdt_hal.h"
#include "soc/rtc_periph.h"
#include "soc/i2s_reg.h"
#include "hal/cpu_hal.h"
#include "hal/wdt_hal.h"
#include "driver/periph_ctrl.h"
#include "xtensa/core-macros.h"
#include "bootloader_clock.h"
#include "soc/syscon_reg.h"
@@ -138,7 +138,7 @@ static void select_rtc_slow_clk(slow_clk_sel_t slow_clk);
rtc_clk_cpu_freq_set_config(&new_config);
// Re calculate the ccount to make time calculation correct.
XTHAL_SET_CCOUNT( (uint64_t)XTHAL_GET_CCOUNT() * new_freq_mhz / old_freq_mhz );
cpu_hal_set_cycle_count( (uint64_t)cpu_hal_get_cycle_count() * new_freq_mhz / old_freq_mhz );
}
static void select_rtc_slow_clk(slow_clk_sel_t slow_clk)
components/esp_system/port/soc/esp32s3/clk.c
+3 -3
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@@ -29,11 +29,11 @@
#include "soc/dport_access.h"
#include "soc/soc.h"
#include "soc/rtc.h"
#include "hal/wdt_hal.h"
#include "soc/rtc_periph.h"
#include "soc/i2s_reg.h"
#include "hal/cpu_hal.h"
#include "hal/wdt_hal.h"
#include "driver/periph_ctrl.h"
#include "xtensa/core-macros.h"
#include "bootloader_clock.h"
#include "soc/syscon_reg.h"
@@ -134,7 +134,7 @@ static void select_rtc_slow_clk(slow_clk_sel_t slow_clk);
rtc_clk_cpu_freq_set_config(&new_config);
// Re calculate the ccount to make time calculation correct.
XTHAL_SET_CCOUNT( (uint64_t)XTHAL_GET_CCOUNT() * new_freq_mhz / old_freq_mhz );
cpu_hal_set_cycle_count( (uint64_t)cpu_hal_get_cycle_count() * new_freq_mhz / old_freq_mhz );
}
static void select_rtc_slow_clk(slow_clk_sel_t slow_clk)