From f6d96f33bb0e379b10dce3c4560c62fcc496bfbc Mon Sep 17 00:00:00 2001
From: fuzhibo <fuzhibo@espressif.com>
Date: Mon, 12 Apr 2021 14:29:13 +0800
Subject: [PATCH] bugfix: add .rodata section for riscv ulp for esp32s2

---
 components/ulp/ld/esp32s2.ulp.riscv.ld | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/components/ulp/ld/esp32s2.ulp.riscv.ld b/components/ulp/ld/esp32s2.ulp.riscv.ld
index a0733bff7f..2134f8dd17 100644
--- a/components/ulp/ld/esp32s2.ulp.riscv.ld
+++ b/components/ulp/ld/esp32s2.ulp.riscv.ld
@@ -17,6 +17,12 @@ SECTIONS
         *(.text*)
     } >ram
 
+    .rodata ALIGN(4):
+    {
+        *(.rodata)
+        *(.rodata*)
+    } > ram
+
     .data ALIGN(4):
     {
         *(.data)