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Merge branch 'fix/fix_esp32c5_ulp_examples' into 'master'

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fix(examples): fix esp32c5 ulp examples

Closes IDF-12084 and IDF-10034

See merge request espressif/esp-idf!36802
This commit is contained in:
Wu Zheng Hui
2025-02-10 21:27:16 +08:00
parent 974910d4f8 c0f98621d7
commit f7feecf63b
7 changed files with 30 additions and 6 deletions
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14
components/hal/esp32c5/include/hal/lp_core_ll.h
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@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -55,6 +55,18 @@ static inline void lp_core_ll_reset_register(void)
/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance /// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
#define lp_core_ll_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; lp_core_ll_reset_register(__VA_ARGS__) #define lp_core_ll_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; lp_core_ll_reset_register(__VA_ARGS__)
/**
* @brief Enable fast access of LP memory
*
* @note When fast access is activated, LP-core cannot access LP mem during deep sleep
*
* @param enable Enable if true, disable if false
*/
static inline void lp_core_ll_fast_lp_mem_enable(bool enable)
{
LP_AON.lpbus.fast_mem_mux_sel = enable;
LP_AON.lpbus.fast_mem_mux_sel_update = 1;
}
/** /**
* @brief Trigger a LP_CORE_LL_WAKEUP_SOURCE_HP_CPU wake-up on the lp core * @brief Trigger a LP_CORE_LL_WAKEUP_SOURCE_HP_CPU wake-up on the lp core

4
components/soc/esp32c5/include/soc/Kconfig.soc_caps.in
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@@ -1443,6 +1443,10 @@ config SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH
int int
default 12 default 12
config SOC_RTC_MEM_SUPPORT_SPEED_MODE_SWITCH
bool
default y
config SOC_PM_SUPPORT_WIFI_WAKEUP config SOC_PM_SUPPORT_WIFI_WAKEUP
bool bool
default y default y

4
components/soc/esp32c5/include/soc/clk_tree_defs.h
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@@ -253,9 +253,7 @@ typedef enum {
typedef enum { typedef enum {
LP_UART_SCLK_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< LP_UART source clock is RC_FAST */ LP_UART_SCLK_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< LP_UART source clock is RC_FAST */
LP_UART_SCLK_XTAL_D2 = SOC_MOD_CLK_XTAL_D2, /*!< LP_UART source clock is XTAL_D2 */ LP_UART_SCLK_XTAL_D2 = SOC_MOD_CLK_XTAL_D2, /*!< LP_UART source clock is XTAL_D2 */
LP_UART_SCLK_DEFAULT = SOC_MOD_CLK_RC_FAST, /*!< LP_UART source clock default choice is RC_FAST */
//TODO: IDF-10034
LP_UART_SCLK_DEFAULT = SOC_MOD_CLK_XTAL_D2, /*!< LP_UART source clock default choice is XTAL_D2 */
} soc_periph_lp_uart_clk_src_t; } soc_periph_lp_uart_clk_src_t;
//////////////////////////////////////////////////MCPWM///////////////////////////////////////////////////////////////// //////////////////////////////////////////////////MCPWM/////////////////////////////////////////////////////////////////

3
components/soc/esp32c5/include/soc/soc_caps.h
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@@ -583,6 +583,9 @@
/*--------------- WIFI LIGHT SLEEP CLOCK WIDTH CAPS --------------------------*/ /*--------------- WIFI LIGHT SLEEP CLOCK WIDTH CAPS --------------------------*/
#define SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH (12) #define SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH (12)
/*-------------------------- RTC MEM CAPS ----------------------------*/
#define SOC_RTC_MEM_SUPPORT_SPEED_MODE_SWITCH 1
/*-------------------------- Power Management CAPS ----------------------------*/ /*-------------------------- Power Management CAPS ----------------------------*/
#define SOC_PM_SUPPORT_WIFI_WAKEUP (1) #define SOC_PM_SUPPORT_WIFI_WAKEUP (1)
#define SOC_PM_SUPPORT_BEACON_WAKEUP (1) #define SOC_PM_SUPPORT_BEACON_WAKEUP (1)

4
components/soc/esp32c6/include/soc/Kconfig.soc_caps.in
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@@ -1383,6 +1383,10 @@ config SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH
int int
default 12 default 12
config SOC_RTC_MEM_SUPPORT_SPEED_MODE_SWITCH
bool
default y
config SOC_PM_SUPPORT_WIFI_WAKEUP config SOC_PM_SUPPORT_WIFI_WAKEUP
bool bool
default y default y

3
components/soc/esp32c6/include/soc/soc_caps.h
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@@ -541,6 +541,9 @@
/*--------------- WIFI LIGHT SLEEP CLOCK WIDTH CAPS --------------------------*/ /*--------------- WIFI LIGHT SLEEP CLOCK WIDTH CAPS --------------------------*/
#define SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH (12) #define SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH (12)
/*-------------------------- RTC MEM CAPS ----------------------------*/
#define SOC_RTC_MEM_SUPPORT_SPEED_MODE_SWITCH 1
// TODO: IDF-5351 (Copy from esp32c3, need check) // TODO: IDF-5351 (Copy from esp32c3, need check)
/*-------------------------- Power Management CAPS ----------------------------*/ /*-------------------------- Power Management CAPS ----------------------------*/
#define SOC_PM_SUPPORT_WIFI_WAKEUP (1) #define SOC_PM_SUPPORT_WIFI_WAKEUP (1)

4
components/ulp/lp_core/lp_core.c
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@@ -95,10 +95,10 @@ esp_err_t ulp_lp_core_run(ulp_lp_core_cfg_t* cfg)
lp_core_ll_enable_bus_clock(true); lp_core_ll_enable_bus_clock(true);
} }
#if CONFIG_IDF_TARGET_ESP32C6 #if SOC_RTC_MEM_SUPPORT_SPEED_MODE_SWITCH
/* Disable fast LP mem access to allow LP core to access LP memory during sleep */ /* Disable fast LP mem access to allow LP core to access LP memory during sleep */
lp_core_ll_fast_lp_mem_enable(false); lp_core_ll_fast_lp_mem_enable(false);
#endif //CONFIG_IDF_TARGET_ESP32C6 #endif
/* Enable stall at sleep request*/ /* Enable stall at sleep request*/
lp_core_ll_stall_at_sleep_request(true); lp_core_ll_stall_at_sleep_request(true);