diff --git a/components/esp_system/port/soc/esp32/highint_hdl.S b/components/esp_system/port/soc/esp32/highint_hdl.S index 22209cb49d..65f9eaebcf 100644 --- a/components/esp_system/port/soc/esp32/highint_hdl.S +++ b/components/esp_system/port/soc/esp32/highint_hdl.S @@ -70,6 +70,7 @@ Interrupt , a high-priority interrupt, is used for several things: #define TIMG1_WDT_STG1_HOLD_OFFSET TIMG1_REG_OFFSET(TIMG_WDTCONFIG3_REG(1)) #define TIMG1_WDT_FEED_OFFSET TIMG1_REG_OFFSET(TIMG_WDTFEED_REG(1)) #define UART0_DATA_REG (0x3FF40078) +#define ETS_TG1_WDT_LEVEL_INTR_SOURCE 20 .macro wdt_clr_intr_status dev movi a2, \dev diff --git a/components/soc/esp32/include/soc/interrupts.h b/components/soc/esp32/include/soc/interrupts.h new file mode 100644 index 0000000000..ca48293a73 --- /dev/null +++ b/components/soc/esp32/include/soc/interrupts.h @@ -0,0 +1,95 @@ +/* + * SPDX-FileCopyrightText: 2018-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once +#include + +#ifdef __cplusplus +extern "C" +{ +#endif + +//Interrupt hardware source table +//This table is decided by hardware, don't touch this. +typedef enum { + ETS_WIFI_MAC_INTR_SOURCE = 0, /**< interrupt of WiFi MAC, level*/ + ETS_WIFI_MAC_NMI_SOURCE, /**< interrupt of WiFi MAC, NMI, use if MAC have bug to fix in NMI*/ + ETS_WIFI_BB_INTR_SOURCE, /**< interrupt of WiFi BB, level, we can do some calibartion*/ + ETS_BT_MAC_INTR_SOURCE, /**< will be cancelled*/ + ETS_BT_BB_INTR_SOURCE, /**< interrupt of BT BB, level*/ + ETS_BT_BB_NMI_SOURCE, /**< interrupt of BT BB, NMI, use if BB have bug to fix in NMI*/ + ETS_RWBT_INTR_SOURCE, /**< interrupt of RWBT, level*/ + ETS_RWBLE_INTR_SOURCE, /**< interrupt of RWBLE, level*/ + ETS_RWBT_NMI_SOURCE, /**< interrupt of RWBT, NMI, use if RWBT have bug to fix in NMI*/ + ETS_RWBLE_NMI_SOURCE, /**< interrupt of RWBLE, NMI, use if RWBT have bug to fix in NMI*/ + ETS_SLC0_INTR_SOURCE, /**< interrupt of SLC0, level*/ + ETS_SLC1_INTR_SOURCE, /**< interrupt of SLC1, level*/ + ETS_UHCI0_INTR_SOURCE, /**< interrupt of UHCI0, level*/ + ETS_UHCI1_INTR_SOURCE, /**< interrupt of UHCI1, level*/ + ETS_TG0_T0_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, TIMER0, level, we would like use EDGE for timer if permission*/ + ETS_TG0_T1_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, TIMER1, level, we would like use EDGE for timer if permission*/ + ETS_TG0_WDT_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, WATCHDOG, level*/ + ETS_TG0_LACT_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, LACT, level*/ + ETS_TG1_T0_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, TIMER0, level, we would like use EDGE for timer if permission*/ + ETS_TG1_T1_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, TIMER1, level, we would like use EDGE for timer if permission*/ + ETS_TG1_WDT_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, WATCHDOG, level*/ + ETS_TG1_LACT_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, LACT, level*/ + ETS_GPIO_INTR_SOURCE, /**< interrupt of GPIO, level*/ + ETS_GPIO_NMI_SOURCE, /**< interrupt of GPIO, NMI*/ + ETS_FROM_CPU_INTR0_SOURCE, /**< interrupt0 generated from a CPU, level*/ /* Used for FreeRTOS */ + ETS_FROM_CPU_INTR1_SOURCE, /**< interrupt1 generated from a CPU, level*/ /* Used for FreeRTOS */ + ETS_FROM_CPU_INTR2_SOURCE, /**< interrupt2 generated from a CPU, level*/ /* Used for IPC_ISR */ + ETS_FROM_CPU_INTR3_SOURCE, /**< interrupt3 generated from a CPU, level*/ /* Used for IPC_ISR */ + ETS_SPI0_INTR_SOURCE, /**< interrupt of SPI0, level, SPI0 is for Cache Access, do not use this*/ + ETS_SPI1_INTR_SOURCE, /**< interrupt of SPI1, level, SPI1 is for flash read/write, do not use this*/ + ETS_SPI2_INTR_SOURCE, /**< interrupt of SPI2, level*/ + ETS_SPI3_INTR_SOURCE, /**< interrupt of SPI3, level*/ + ETS_I2S0_INTR_SOURCE, /**< interrupt of I2S0, level*/ + ETS_I2S1_INTR_SOURCE, /**< interrupt of I2S1, level*/ + ETS_UART0_INTR_SOURCE, /**< interrupt of UART0, level*/ + ETS_UART1_INTR_SOURCE, /**< interrupt of UART1, level*/ + ETS_UART2_INTR_SOURCE, /**< interrupt of UART2, level*/ + ETS_SDIO_HOST_INTR_SOURCE, /**< interrupt of SD/SDIO/MMC HOST, level*/ + ETS_ETH_MAC_INTR_SOURCE, /**< interrupt of ethernet mac, level*/ + ETS_PWM0_INTR_SOURCE, /**< interrupt of PWM0, level, Reserved*/ + ETS_PWM1_INTR_SOURCE, /**< interrupt of PWM1, level, Reserved*/ + + ETS_LEDC_INTR_SOURCE = 43, /**< interrupt of LED PWM, level*/ + ETS_EFUSE_INTR_SOURCE, /**< interrupt of efuse, level, not likely to use*/ + ETS_TWAI_INTR_SOURCE, /**< interrupt of twai, level*/ + ETS_RTC_CORE_INTR_SOURCE, /**< interrupt of rtc core, level, include rtc watchdog*/ + ETS_RMT_INTR_SOURCE, /**< interrupt of remote controller, level*/ + ETS_PCNT_INTR_SOURCE, /**< interrupt of pluse count, level*/ + ETS_I2C_EXT0_INTR_SOURCE, /**< interrupt of I2C controller1, level*/ + ETS_I2C_EXT1_INTR_SOURCE, /**< interrupt of I2C controller0, level*/ + ETS_RSA_INTR_SOURCE, /**< interrupt of RSA accelerator, level*/ + ETS_SPI1_DMA_INTR_SOURCE, /**< interrupt of SPI1 DMA, SPI1 is for flash read/write, do not use this*/ + ETS_SPI2_DMA_INTR_SOURCE, /**< interrupt of SPI2 DMA, level*/ + ETS_SPI3_DMA_INTR_SOURCE, /**< interrupt of SPI3 DMA, level*/ + ETS_WDT_INTR_SOURCE, /**< will be cancelled*/ + ETS_TIMER1_INTR_SOURCE, /**< will be cancelled*/ + ETS_TIMER2_INTR_SOURCE, /**< will be cancelled*/ + ETS_TG0_T0_EDGE_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, TIMER0, EDGE*/ + ETS_TG0_T1_EDGE_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, TIMER1, EDGE*/ + ETS_TG0_WDT_EDGE_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, WATCH DOG, EDGE*/ + ETS_TG0_LACT_EDGE_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, LACT, EDGE*/ + ETS_TG1_T0_EDGE_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, TIMER0, EDGE*/ + ETS_TG1_T1_EDGE_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, TIMER1, EDGE*/ + ETS_TG1_WDT_EDGE_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, WATCHDOG, EDGE*/ + ETS_TG1_LACT_EDGE_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, LACT, EDGE*/ + ETS_MMU_IA_INTR_SOURCE, /**< interrupt of MMU Invalid Access, LEVEL*/ + ETS_MPU_IA_INTR_SOURCE, /**< interrupt of MPU Invalid Access, LEVEL*/ + ETS_CACHE_IA_INTR_SOURCE, /**< interrupt of Cache Invalied Access, LEVEL*/ + ETS_MAX_INTR_SOURCE, /**< total number of interrupt sources*/ +} periph_interrput_t; + +#define ETS_CAN_INTR_SOURCE ETS_TWAI_INTR_SOURCE + +extern const char *const esp_isr_names[ETS_MAX_INTR_SOURCE]; + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32/include/soc/soc.h b/components/soc/esp32/include/soc/soc.h index 7a3036c421..d02aa8277e 100644 --- a/components/soc/esp32/include/soc/soc.h +++ b/components/soc/esp32/include/soc/soc.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2010-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2010-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -10,6 +10,7 @@ #include #include "esp_assert.h" #include "soc/soc_caps.h" +#include "soc/interrupts.h" #endif #include "esp_bit_defs.h" @@ -219,78 +220,6 @@ // Start (highest address) of ROM boot stack, only relevant during early boot #define SOC_ROM_STACK_START 0x3ffe3f20 -//Interrupt hardware source table -//This table is decided by hardware, don't touch this. -#define ETS_WIFI_MAC_INTR_SOURCE 0/**< interrupt of WiFi MAC, level*/ -#define ETS_WIFI_MAC_NMI_SOURCE 1/**< interrupt of WiFi MAC, NMI, use if MAC have bug to fix in NMI*/ -#define ETS_WIFI_BB_INTR_SOURCE 2/**< interrupt of WiFi BB, level, we can do some calibartion*/ -#define ETS_BT_MAC_INTR_SOURCE 3/**< will be cancelled*/ -#define ETS_BT_BB_INTR_SOURCE 4/**< interrupt of BT BB, level*/ -#define ETS_BT_BB_NMI_SOURCE 5/**< interrupt of BT BB, NMI, use if BB have bug to fix in NMI*/ -#define ETS_RWBT_INTR_SOURCE 6/**< interrupt of RWBT, level*/ -#define ETS_RWBLE_INTR_SOURCE 7/**< interrupt of RWBLE, level*/ -#define ETS_RWBT_NMI_SOURCE 8/**< interrupt of RWBT, NMI, use if RWBT have bug to fix in NMI*/ -#define ETS_RWBLE_NMI_SOURCE 9/**< interrupt of RWBLE, NMI, use if RWBT have bug to fix in NMI*/ -#define ETS_SLC0_INTR_SOURCE 10/**< interrupt of SLC0, level*/ -#define ETS_SLC1_INTR_SOURCE 11/**< interrupt of SLC1, level*/ -#define ETS_UHCI0_INTR_SOURCE 12/**< interrupt of UHCI0, level*/ -#define ETS_UHCI1_INTR_SOURCE 13/**< interrupt of UHCI1, level*/ -#define ETS_TG0_T0_LEVEL_INTR_SOURCE 14/**< interrupt of TIMER_GROUP0, TIMER0, level, we would like use EDGE for timer if permission*/ -#define ETS_TG0_T1_LEVEL_INTR_SOURCE 15/**< interrupt of TIMER_GROUP0, TIMER1, level, we would like use EDGE for timer if permission*/ -#define ETS_TG0_WDT_LEVEL_INTR_SOURCE 16/**< interrupt of TIMER_GROUP0, WATCHDOG, level*/ -#define ETS_TG0_LACT_LEVEL_INTR_SOURCE 17/**< interrupt of TIMER_GROUP0, LACT, level*/ -#define ETS_TG1_T0_LEVEL_INTR_SOURCE 18/**< interrupt of TIMER_GROUP1, TIMER0, level, we would like use EDGE for timer if permission*/ -#define ETS_TG1_T1_LEVEL_INTR_SOURCE 19/**< interrupt of TIMER_GROUP1, TIMER1, level, we would like use EDGE for timer if permission*/ -#define ETS_TG1_WDT_LEVEL_INTR_SOURCE 20/**< interrupt of TIMER_GROUP1, WATCHDOG, level*/ -#define ETS_TG1_LACT_LEVEL_INTR_SOURCE 21/**< interrupt of TIMER_GROUP1, LACT, level*/ -#define ETS_GPIO_INTR_SOURCE 22/**< interrupt of GPIO, level*/ -#define ETS_GPIO_NMI_SOURCE 23/**< interrupt of GPIO, NMI*/ -#define ETS_FROM_CPU_INTR0_SOURCE 24/**< interrupt0 generated from a CPU, level*/ /* Used for FreeRTOS */ -#define ETS_FROM_CPU_INTR1_SOURCE 25/**< interrupt1 generated from a CPU, level*/ /* Used for FreeRTOS */ -#define ETS_FROM_CPU_INTR2_SOURCE 26/**< interrupt2 generated from a CPU, level*/ /* Used for IPC_ISR */ -#define ETS_FROM_CPU_INTR3_SOURCE 27/**< interrupt3 generated from a CPU, level*/ /* Used for IPC_ISR */ -#define ETS_SPI0_INTR_SOURCE 28/**< interrupt of SPI0, level, SPI0 is for Cache Access, do not use this*/ -#define ETS_SPI1_INTR_SOURCE 29/**< interrupt of SPI1, level, SPI1 is for flash read/write, do not use this*/ -#define ETS_SPI2_INTR_SOURCE 30/**< interrupt of SPI2, level*/ -#define ETS_SPI3_INTR_SOURCE 31/**< interrupt of SPI3, level*/ -#define ETS_I2S0_INTR_SOURCE 32/**< interrupt of I2S0, level*/ -#define ETS_I2S1_INTR_SOURCE 33/**< interrupt of I2S1, level*/ -#define ETS_UART0_INTR_SOURCE 34/**< interrupt of UART0, level*/ -#define ETS_UART1_INTR_SOURCE 35/**< interrupt of UART1, level*/ -#define ETS_UART2_INTR_SOURCE 36/**< interrupt of UART2, level*/ -#define ETS_SDIO_HOST_INTR_SOURCE 37/**< interrupt of SD/SDIO/MMC HOST, level*/ -#define ETS_ETH_MAC_INTR_SOURCE 38/**< interrupt of ethernet mac, level*/ -#define ETS_PWM0_INTR_SOURCE 39/**< interrupt of PWM0, level, Reserved*/ -#define ETS_PWM1_INTR_SOURCE 40/**< interrupt of PWM1, level, Reserved*/ -#define ETS_LEDC_INTR_SOURCE 43/**< interrupt of LED PWM, level*/ -#define ETS_EFUSE_INTR_SOURCE 44/**< interrupt of efuse, level, not likely to use*/ -#define ETS_TWAI_INTR_SOURCE 45/**< interrupt of twai, level*/ -#define ETS_CAN_INTR_SOURCE ETS_TWAI_INTR_SOURCE -#define ETS_RTC_CORE_INTR_SOURCE 46/**< interrupt of rtc core, level, include rtc watchdog*/ -#define ETS_RMT_INTR_SOURCE 47/**< interrupt of remote controller, level*/ -#define ETS_PCNT_INTR_SOURCE 48/**< interrupt of pluse count, level*/ -#define ETS_I2C_EXT0_INTR_SOURCE 49/**< interrupt of I2C controller1, level*/ -#define ETS_I2C_EXT1_INTR_SOURCE 50/**< interrupt of I2C controller0, level*/ -#define ETS_RSA_INTR_SOURCE 51/**< interrupt of RSA accelerator, level*/ -#define ETS_SPI1_DMA_INTR_SOURCE 52/**< interrupt of SPI1 DMA, SPI1 is for flash read/write, do not use this*/ -#define ETS_SPI2_DMA_INTR_SOURCE 53/**< interrupt of SPI2 DMA, level*/ -#define ETS_SPI3_DMA_INTR_SOURCE 54/**< interrupt of SPI3 DMA, level*/ -#define ETS_WDT_INTR_SOURCE 55/**< will be cancelled*/ -#define ETS_TIMER1_INTR_SOURCE 56/**< will be cancelled*/ -#define ETS_TIMER2_INTR_SOURCE 57/**< will be cancelled*/ -#define ETS_TG0_T0_EDGE_INTR_SOURCE 58/**< interrupt of TIMER_GROUP0, TIMER0, EDGE*/ -#define ETS_TG0_T1_EDGE_INTR_SOURCE 59/**< interrupt of TIMER_GROUP0, TIMER1, EDGE*/ -#define ETS_TG0_WDT_EDGE_INTR_SOURCE 60/**< interrupt of TIMER_GROUP0, WATCH DOG, EDGE*/ -#define ETS_TG0_LACT_EDGE_INTR_SOURCE 61/**< interrupt of TIMER_GROUP0, LACT, EDGE*/ -#define ETS_TG1_T0_EDGE_INTR_SOURCE 62/**< interrupt of TIMER_GROUP1, TIMER0, EDGE*/ -#define ETS_TG1_T1_EDGE_INTR_SOURCE 63/**< interrupt of TIMER_GROUP1, TIMER1, EDGE*/ -#define ETS_TG1_WDT_EDGE_INTR_SOURCE 64/**< interrupt of TIMER_GROUP1, WATCHDOG, EDGE*/ -#define ETS_TG1_LACT_EDGE_INTR_SOURCE 65/**< interrupt of TIMER_GROUP0, LACT, EDGE*/ -#define ETS_MMU_IA_INTR_SOURCE 66/**< interrupt of MMU Invalid Access, LEVEL*/ -#define ETS_MPU_IA_INTR_SOURCE 67/**< interrupt of MPU Invalid Access, LEVEL*/ -#define ETS_CACHE_IA_INTR_SOURCE 68/**< interrupt of Cache Invalied Access, LEVEL*/ -#define ETS_MAX_INTR_SOURCE 69/**< total number of interrupt sources*/ - #if CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_5 //interrupt cpu using table, Please see the core-isa.h /************************************************************************************************************* diff --git a/components/soc/esp32/interrupts.c b/components/soc/esp32/interrupts.c index 76b3032a19..ef9be42e7e 100644 --- a/components/soc/esp32/interrupts.c +++ b/components/soc/esp32/interrupts.c @@ -48,8 +48,8 @@ const char * const esp_isr_names[ETS_MAX_INTR_SOURCE] = { [38] = "ETH_MAC", [39] = "PWM0", [40] = "PWM1", - [41] = "PWM2", - [42] = "PWM3", + [41] = "RESERVED", + [42] = "RESERVED", [43] = "LEDC", [44] = "EFUSE", [45] = "TWAI", diff --git a/components/soc/esp32c2/include/soc/interrupts.h b/components/soc/esp32c2/include/soc/interrupts.h new file mode 100644 index 0000000000..9e9ca04c91 --- /dev/null +++ b/components/soc/esp32c2/include/soc/interrupts.h @@ -0,0 +1,68 @@ +/* + * SPDX-FileCopyrightText: 2018-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once +#include + +#ifdef __cplusplus +extern "C" +{ +#endif + +//Interrupt hardware source table +//This table is decided by hardware, don't touch this. +typedef enum { + ETS_WIFI_MAC_INTR_SOURCE = 0, /**< interrupt of WiFi MAC, level*/ + ETS_WIFI_MAC_NMI_SOURCE, /**< interrupt of WiFi MAC, NMI, use if MAC have bug to fix in NMI*/ + ETS_WIFI_PWR_INTR_SOURCE, /**< */ + ETS_WIFI_BB_INTR_SOURCE, /**< interrupt of WiFi BB, level, we can do some calibartion*/ + ETS_BT_MAC_INTR_SOURCE, /**< will be cancelled*/ + ETS_BT_BB_INTR_SOURCE, /**< interrupt of BT BB, level*/ + ETS_BT_BB_NMI_SOURCE, /**< interrupt of BT BB, NMI, use if BB have bug to fix in NMI*/ + ETS_LP_TIMER_SOURCE, /**< interrupt of RWBT, level*/ + ETS_COEX_SOURCE, /**< interrupt of RWBLE, level*/ + ETS_BLE_TIMER_SOURCE, /**< interrupt of RWBT, NMI, use if RWBT have bug to fix in NMI*/ + ETS_BLE_SEC_SOURCE, /**< interrupt of RWBLE, NMI, use if RWBT have bug to fix in NMI*/ + ETS_I2C_MASTER_SOURCE, /**< interrupt of I2C Master, level*/ + ETS_APB_CTRL_INTR_SOURCE, /**< interrupt of APB ctrl, ?*/ + ETS_GPIO_INTR_SOURCE, /**< interrupt of GPIO, level*/ + ETS_GPIO_NMI_SOURCE, /**< interrupt of GPIO, NMI*/ + ETS_SPI1_INTR_SOURCE, /**< interrupt of SPI1, level, SPI1 is for flash read/write, do not use this*/ + ETS_SPI2_INTR_SOURCE, /**< interrupt of SPI2, level*/ + ETS_UART0_INTR_SOURCE, /**< interrupt of UART0, level*/ + ETS_UART1_INTR_SOURCE, /**< interrupt of UART1, level*/ + ETS_LEDC_INTR_SOURCE, /**< interrupt of LED PWM, level*/ + ETS_EFUSE_INTR_SOURCE, /**< interrupt of efuse, level, not likely to use*/ + ETS_RTC_CORE_INTR_SOURCE, /**< interrupt of rtc core, level, include rtc watchdog*/ + ETS_I2C_EXT0_INTR_SOURCE, /**< interrupt of I2C controller1, level*/ + ETS_TG0_T0_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, TIMER0, level*/ + ETS_TG0_WDT_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, WATCH DOG, level*/ + ETS_CACHE_IA_INTR_SOURCE, /**< interrupt of Cache Invalied Access, LEVEL*/ + ETS_SYSTIMER_TARGET0_EDGE_INTR_SOURCE, /**< interrupt of system timer 0, EDGE*/ + ETS_SYSTIMER_TARGET1_EDGE_INTR_SOURCE, /**< interrupt of system timer 1, EDGE*/ + ETS_SYSTIMER_TARGET2_EDGE_INTR_SOURCE, /**< interrupt of system timer 2, EDGE*/ + ETS_SPI_MEM_REJECT_CACHE_INTR_SOURCE, /**< interrupt of SPI0 Cache access and SPI1 access rejected, LEVEL*/ + ETS_ICACHE_PRELOAD0_INTR_SOURCE, /**< interrupt of ICache perload operation, LEVEL*/ + ETS_ICACHE_SYNC0_INTR_SOURCE, /**< interrupt of instruction cache sync done, LEVEL*/ + ETS_APB_ADC_INTR_SOURCE, /**< interrupt of APB ADC, LEVEL*/ + ETS_DMA_CH0_INTR_SOURCE, /**< interrupt of general DMA channel 0, LEVEL*/ + ETS_SHA_INTR_SOURCE, /**< interrupt of SHA accelerator, level*/ + ETS_ECC_INTR_SOURCE, /**< interrupt of ECC accelerator, level*/ + ETS_FROM_CPU_INTR0_SOURCE, /**< interrupt0 generated from a CPU, level*/ /* Used for FreeRTOS */ + ETS_FROM_CPU_INTR1_SOURCE, /**< interrupt1 generated from a CPU, level*/ /* Used for FreeRTOS */ + ETS_FROM_CPU_INTR2_SOURCE, /**< interrupt2 generated from a CPU, level*/ /* Used for DPORT Access */ + ETS_FROM_CPU_INTR3_SOURCE, /**< interrupt3 generated from a CPU, level*/ /* Used for DPORT Access */ + ETS_ASSIST_DEBUG_INTR_SOURCE, /**< interrupt of Assist debug module, LEVEL*/ + ETS_CORE0_PIF_PMS_SIZE_INTR_SOURCE, + ETS_CACHE_CORE0_ACS_INTR_SOURCE, + ETS_MAX_INTR_SOURCE, +} periph_interrput_t; + +extern const char * const esp_isr_names[ETS_MAX_INTR_SOURCE]; + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c2/include/soc/periph_defs.h b/components/soc/esp32c2/include/soc/periph_defs.h index fc3e9b5602..fffb80134a 100644 --- a/components/soc/esp32c2/include/soc/periph_defs.h +++ b/components/soc/esp32c2/include/soc/periph_defs.h @@ -1,11 +1,13 @@ /* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ #pragma once +#include "soc/interrupts.h" + #ifdef __cplusplus extern "C" { #endif @@ -38,53 +40,6 @@ typedef enum { PERIPH_MODULE_MAX } periph_module_t; -typedef enum { - ETS_WIFI_MAC_INTR_SOURCE = 0, /**< interrupt of WiFi MAC, level*/ - ETS_WIFI_MAC_NMI_SOURCE, /**< interrupt of WiFi MAC, NMI, use if MAC have bug to fix in NMI*/ - ETS_WIFI_PWR_INTR_SOURCE, /**< */ - ETS_WIFI_BB_INTR_SOURCE, /**< interrupt of WiFi BB, level, we can do some calibartion*/ - ETS_BT_MAC_INTR_SOURCE, /**< will be cancelled*/ - ETS_BT_BB_INTR_SOURCE, /**< interrupt of BT BB, level*/ - ETS_BT_BB_NMI_SOURCE, /**< interrupt of BT BB, NMI, use if BB have bug to fix in NMI*/ - ETS_LP_TIMER_SOURCE, /**< interrupt of RWBT, level*/ - ETS_COEX_SOURCE, /**< interrupt of RWBLE, level*/ - ETS_BLE_TIMER_SOURCE, /**< interrupt of RWBT, NMI, use if RWBT have bug to fix in NMI*/ - ETS_BLE_SEC_SOURCE, /**< interrupt of RWBLE, NMI, use if RWBT have bug to fix in NMI*/ - ETS_I2C_MASTER_SOURCE, /**< interrupt of I2C Master, level*/ - ETS_APB_CTRL_INTR_SOURCE, /**< interrupt of APB ctrl, ?*/ - ETS_GPIO_INTR_SOURCE, /**< interrupt of GPIO, level*/ - ETS_GPIO_NMI_SOURCE, /**< interrupt of GPIO, NMI*/ - ETS_SPI1_INTR_SOURCE, /**< interrupt of SPI1, level, SPI1 is for flash read/write, do not use this*/ - ETS_SPI2_INTR_SOURCE, /**< interrupt of SPI2, level*/ - ETS_UART0_INTR_SOURCE, /**< interrupt of UART0, level*/ - ETS_UART1_INTR_SOURCE, /**< interrupt of UART1, level*/ - ETS_LEDC_INTR_SOURCE, /**< interrupt of LED PWM, level*/ - ETS_EFUSE_INTR_SOURCE, /**< interrupt of efuse, level, not likely to use*/ - ETS_RTC_CORE_INTR_SOURCE, /**< interrupt of rtc core, level, include rtc watchdog*/ - ETS_I2C_EXT0_INTR_SOURCE, /**< interrupt of I2C controller1, level*/ - ETS_TG0_T0_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, TIMER0, level*/ - ETS_TG0_WDT_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, WATCH DOG, level*/ - ETS_CACHE_IA_INTR_SOURCE, /**< interrupt of Cache Invalied Access, LEVEL*/ - ETS_SYSTIMER_TARGET0_EDGE_INTR_SOURCE, /**< interrupt of system timer 0, EDGE*/ - ETS_SYSTIMER_TARGET1_EDGE_INTR_SOURCE, /**< interrupt of system timer 1, EDGE*/ - ETS_SYSTIMER_TARGET2_EDGE_INTR_SOURCE, /**< interrupt of system timer 2, EDGE*/ - ETS_SPI_MEM_REJECT_CACHE_INTR_SOURCE, /**< interrupt of SPI0 Cache access and SPI1 access rejected, LEVEL*/ - ETS_ICACHE_PRELOAD0_INTR_SOURCE, /**< interrupt of ICache perload operation, LEVEL*/ - ETS_ICACHE_SYNC0_INTR_SOURCE, /**< interrupt of instruction cache sync done, LEVEL*/ - ETS_APB_ADC_INTR_SOURCE, /**< interrupt of APB ADC, LEVEL*/ - ETS_DMA_CH0_INTR_SOURCE, /**< interrupt of general DMA channel 0, LEVEL*/ - ETS_SHA_INTR_SOURCE, /**< interrupt of SHA accelerator, level*/ - ETS_ECC_INTR_SOURCE, /**< interrupt of ECC accelerator, level*/ - ETS_FROM_CPU_INTR0_SOURCE, /**< interrupt0 generated from a CPU, level*/ /* Used for FreeRTOS */ - ETS_FROM_CPU_INTR1_SOURCE, /**< interrupt1 generated from a CPU, level*/ /* Used for FreeRTOS */ - ETS_FROM_CPU_INTR2_SOURCE, /**< interrupt2 generated from a CPU, level*/ /* Used for DPORT Access */ - ETS_FROM_CPU_INTR3_SOURCE, /**< interrupt3 generated from a CPU, level*/ /* Used for DPORT Access */ - ETS_ASSIST_DEBUG_INTR_SOURCE, /**< interrupt of Assist debug module, LEVEL*/ - ETS_CORE0_PIF_PMS_SIZE_INTR_SOURCE, - ETS_CACHE_CORE0_ACS_INTR_SOURCE, - ETS_MAX_INTR_SOURCE, -} periph_interrput_t; - #ifdef __cplusplus } #endif diff --git a/components/soc/esp32c3/include/soc/interrupts.h b/components/soc/esp32c3/include/soc/interrupts.h new file mode 100644 index 0000000000..645a7c310c --- /dev/null +++ b/components/soc/esp32c3/include/soc/interrupts.h @@ -0,0 +1,87 @@ +/* + * SPDX-FileCopyrightText: 2018-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once +#include + +#ifdef __cplusplus +extern "C" +{ +#endif + +//Interrupt hardware source table +//This table is decided by hardware, don't touch this. +typedef enum { + ETS_WIFI_MAC_INTR_SOURCE = 0, /**< interrupt of WiFi MAC, level*/ + ETS_WIFI_MAC_NMI_SOURCE, /**< interrupt of WiFi MAC, NMI, use if MAC have bug to fix in NMI*/ + ETS_WIFI_PWR_INTR_SOURCE, /**< */ + ETS_WIFI_BB_INTR_SOURCE, /**< interrupt of WiFi BB, level, we can do some calibartion*/ + ETS_BT_MAC_INTR_SOURCE, /**< will be cancelled*/ + ETS_BT_BB_INTR_SOURCE, /**< interrupt of BT BB, level*/ + ETS_BT_BB_NMI_SOURCE, /**< interrupt of BT BB, NMI, use if BB have bug to fix in NMI*/ + ETS_RWBT_INTR_SOURCE, /**< interrupt of RWBT, level*/ + ETS_RWBLE_INTR_SOURCE, /**< interrupt of RWBLE, level*/ + ETS_RWBT_NMI_SOURCE, /**< interrupt of RWBT, NMI, use if RWBT have bug to fix in NMI*/ + ETS_RWBLE_NMI_SOURCE, /**< interrupt of RWBLE, NMI, use if RWBT have bug to fix in NMI*/ + ETS_I2C_MASTER_SOURCE, /**< interrupt of I2C Master, level*/ + ETS_SLC0_INTR_SOURCE, /**< interrupt of SLC0, level*/ + ETS_SLC1_INTR_SOURCE, /**< interrupt of SLC1, level*/ + ETS_APB_CTRL_INTR_SOURCE, /**< interrupt of APB ctrl, ?*/ + ETS_UHCI0_INTR_SOURCE, /**< interrupt of UHCI0, level*/ + ETS_GPIO_INTR_SOURCE, /**< interrupt of GPIO, level*/ + ETS_GPIO_NMI_SOURCE, /**< interrupt of GPIO, NMI*/ + ETS_SPI1_INTR_SOURCE, /**< interrupt of SPI1, level, SPI1 is for flash read/write, do not use this*/ + ETS_SPI2_INTR_SOURCE, /**< interrupt of SPI2, level*/ + ETS_I2S1_INTR_SOURCE, /**< interrupt of I2S1, level*/ + ETS_UART0_INTR_SOURCE, /**< interrupt of UART0, level*/ + ETS_UART1_INTR_SOURCE, /**< interrupt of UART1, level*/ + ETS_LEDC_INTR_SOURCE, /**< interrupt of LED PWM, level*/ + ETS_EFUSE_INTR_SOURCE, /**< interrupt of efuse, level, not likely to use*/ + ETS_TWAI_INTR_SOURCE, /**< interrupt of can, level*/ + ETS_USB_SERIAL_JTAG_INTR_SOURCE, /**< interrupt of USJ, level*/ + ETS_RTC_CORE_INTR_SOURCE, /**< interrupt of rtc core, level, include rtc watchdog*/ + ETS_RMT_INTR_SOURCE, /**< interrupt of remote controller, level*/ + ETS_I2C_EXT0_INTR_SOURCE, /**< interrupt of I2C controller1, level*/ + ETS_TIMER1_INTR_SOURCE, + ETS_TIMER2_INTR_SOURCE, + ETS_TG0_T0_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, TIMER0, level*/ + ETS_TG0_WDT_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, WATCH DOG, level*/ + ETS_TG1_T0_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, TIMER0, level*/ + ETS_TG1_WDT_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, WATCHDOG, level*/ + ETS_CACHE_IA_INTR_SOURCE, /**< interrupt of Cache Invalied Access, LEVEL*/ + ETS_SYSTIMER_TARGET0_EDGE_INTR_SOURCE, /**< interrupt of system timer 0, EDGE*/ + ETS_SYSTIMER_TARGET1_EDGE_INTR_SOURCE, /**< interrupt of system timer 1, EDGE*/ + ETS_SYSTIMER_TARGET2_EDGE_INTR_SOURCE, /**< interrupt of system timer 2, EDGE*/ + ETS_SPI_MEM_REJECT_CACHE_INTR_SOURCE, /**< interrupt of SPI0 Cache access and SPI1 access rejected, LEVEL*/ + ETS_ICACHE_PRELOAD0_INTR_SOURCE, /**< interrupt of ICache perload operation, LEVEL*/ + ETS_ICACHE_SYNC0_INTR_SOURCE, /**< interrupt of instruction cache sync done, LEVEL*/ + ETS_APB_ADC_INTR_SOURCE, /**< interrupt of APB ADC, LEVEL*/ + ETS_DMA_CH0_INTR_SOURCE, /**< interrupt of general DMA channel 0, LEVEL*/ + ETS_DMA_CH1_INTR_SOURCE, /**< interrupt of general DMA channel 1, LEVEL*/ + ETS_DMA_CH2_INTR_SOURCE, /**< interrupt of general DMA channel 2, LEVEL*/ + ETS_RSA_INTR_SOURCE, /**< interrupt of RSA accelerator, level*/ + ETS_AES_INTR_SOURCE, /**< interrupt of AES accelerator, level*/ + ETS_SHA_INTR_SOURCE, /**< interrupt of SHA accelerator, level*/ + ETS_FROM_CPU_INTR0_SOURCE, /**< interrupt0 generated from a CPU, level*/ /* Used for FreeRTOS */ + ETS_FROM_CPU_INTR1_SOURCE, /**< interrupt1 generated from a CPU, level*/ /* Used for FreeRTOS */ + ETS_FROM_CPU_INTR2_SOURCE, /**< interrupt2 generated from a CPU, level*/ + ETS_FROM_CPU_INTR3_SOURCE, /**< interrupt3 generated from a CPU, level*/ + ETS_ASSIST_DEBUG_INTR_SOURCE, /**< interrupt of Assist debug module, LEVEL*/ + ETS_DMA_APBPERI_PMS_INTR_SOURCE, + ETS_CORE0_IRAM0_PMS_INTR_SOURCE, + ETS_CORE0_DRAM0_PMS_INTR_SOURCE, + ETS_CORE0_PIF_PMS_INTR_SOURCE, + ETS_CORE0_PIF_PMS_SIZE_INTR_SOURCE, + ETS_BAK_PMS_VIOLATE_INTR_SOURCE, + ETS_CACHE_CORE0_ACS_INTR_SOURCE, + ETS_MAX_INTR_SOURCE, +} periph_interrput_t; + +extern const char * const esp_isr_names[ETS_MAX_INTR_SOURCE]; + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c3/include/soc/periph_defs.h b/components/soc/esp32c3/include/soc/periph_defs.h index b066b2962b..063e4f9506 100644 --- a/components/soc/esp32c3/include/soc/periph_defs.h +++ b/components/soc/esp32c3/include/soc/periph_defs.h @@ -1,11 +1,13 @@ /* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ #pragma once +#include "soc/interrupts.h" + #ifdef __cplusplus extern "C" { #endif @@ -43,72 +45,6 @@ typedef enum { PERIPH_MODULE_MAX } periph_module_t; -typedef enum { - ETS_WIFI_MAC_INTR_SOURCE = 0, /**< interrupt of WiFi MAC, level*/ - ETS_WIFI_MAC_NMI_SOURCE, /**< interrupt of WiFi MAC, NMI, use if MAC have bug to fix in NMI*/ - ETS_WIFI_PWR_INTR_SOURCE, /**< */ - ETS_WIFI_BB_INTR_SOURCE, /**< interrupt of WiFi BB, level, we can do some calibartion*/ - ETS_BT_MAC_INTR_SOURCE, /**< will be cancelled*/ - ETS_BT_BB_INTR_SOURCE, /**< interrupt of BT BB, level*/ - ETS_BT_BB_NMI_SOURCE, /**< interrupt of BT BB, NMI, use if BB have bug to fix in NMI*/ - ETS_RWBT_INTR_SOURCE, /**< interrupt of RWBT, level*/ - ETS_RWBLE_INTR_SOURCE, /**< interrupt of RWBLE, level*/ - ETS_RWBT_NMI_SOURCE, /**< interrupt of RWBT, NMI, use if RWBT have bug to fix in NMI*/ - ETS_RWBLE_NMI_SOURCE, /**< interrupt of RWBLE, NMI, use if RWBT have bug to fix in NMI*/ - ETS_I2C_MASTER_SOURCE, /**< interrupt of I2C Master, level*/ - ETS_SLC0_INTR_SOURCE, /**< interrupt of SLC0, level*/ - ETS_SLC1_INTR_SOURCE, /**< interrupt of SLC1, level*/ - ETS_APB_CTRL_INTR_SOURCE, /**< interrupt of APB ctrl, ?*/ - ETS_UHCI0_INTR_SOURCE, /**< interrupt of UHCI0, level*/ - ETS_GPIO_INTR_SOURCE, /**< interrupt of GPIO, level*/ - ETS_GPIO_NMI_SOURCE, /**< interrupt of GPIO, NMI*/ - ETS_SPI1_INTR_SOURCE, /**< interrupt of SPI1, level, SPI1 is for flash read/write, do not use this*/ - ETS_SPI2_INTR_SOURCE, /**< interrupt of SPI2, level*/ - ETS_I2S1_INTR_SOURCE, /**< interrupt of I2S1, level*/ - ETS_UART0_INTR_SOURCE, /**< interrupt of UART0, level*/ - ETS_UART1_INTR_SOURCE, /**< interrupt of UART1, level*/ - ETS_LEDC_INTR_SOURCE, /**< interrupt of LED PWM, level*/ - ETS_EFUSE_INTR_SOURCE, /**< interrupt of efuse, level, not likely to use*/ - ETS_TWAI_INTR_SOURCE, /**< interrupt of can, level*/ - ETS_USB_SERIAL_JTAG_INTR_SOURCE, /**< interrupt of USJ, level*/ - ETS_RTC_CORE_INTR_SOURCE, /**< interrupt of rtc core, level, include rtc watchdog*/ - ETS_RMT_INTR_SOURCE, /**< interrupt of remote controller, level*/ - ETS_I2C_EXT0_INTR_SOURCE, /**< interrupt of I2C controller1, level*/ - ETS_TIMER1_INTR_SOURCE, - ETS_TIMER2_INTR_SOURCE, - ETS_TG0_T0_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, TIMER0, level*/ - ETS_TG0_WDT_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, WATCH DOG, level*/ - ETS_TG1_T0_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, TIMER0, level*/ - ETS_TG1_WDT_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, WATCHDOG, level*/ - ETS_CACHE_IA_INTR_SOURCE, /**< interrupt of Cache Invalied Access, LEVEL*/ - ETS_SYSTIMER_TARGET0_EDGE_INTR_SOURCE, /**< interrupt of system timer 0, EDGE*/ - ETS_SYSTIMER_TARGET1_EDGE_INTR_SOURCE, /**< interrupt of system timer 1, EDGE*/ - ETS_SYSTIMER_TARGET2_EDGE_INTR_SOURCE, /**< interrupt of system timer 2, EDGE*/ - ETS_SPI_MEM_REJECT_CACHE_INTR_SOURCE, /**< interrupt of SPI0 Cache access and SPI1 access rejected, LEVEL*/ - ETS_ICACHE_PRELOAD0_INTR_SOURCE, /**< interrupt of ICache perload operation, LEVEL*/ - ETS_ICACHE_SYNC0_INTR_SOURCE, /**< interrupt of instruction cache sync done, LEVEL*/ - ETS_APB_ADC_INTR_SOURCE, /**< interrupt of APB ADC, LEVEL*/ - ETS_DMA_CH0_INTR_SOURCE, /**< interrupt of general DMA channel 0, LEVEL*/ - ETS_DMA_CH1_INTR_SOURCE, /**< interrupt of general DMA channel 1, LEVEL*/ - ETS_DMA_CH2_INTR_SOURCE, /**< interrupt of general DMA channel 2, LEVEL*/ - ETS_RSA_INTR_SOURCE, /**< interrupt of RSA accelerator, level*/ - ETS_AES_INTR_SOURCE, /**< interrupt of AES accelerator, level*/ - ETS_SHA_INTR_SOURCE, /**< interrupt of SHA accelerator, level*/ - ETS_FROM_CPU_INTR0_SOURCE, /**< interrupt0 generated from a CPU, level*/ /* Used for FreeRTOS */ - ETS_FROM_CPU_INTR1_SOURCE, /**< interrupt1 generated from a CPU, level*/ /* Used for FreeRTOS */ - ETS_FROM_CPU_INTR2_SOURCE, /**< interrupt2 generated from a CPU, level*/ - ETS_FROM_CPU_INTR3_SOURCE, /**< interrupt3 generated from a CPU, level*/ - ETS_ASSIST_DEBUG_INTR_SOURCE, /**< interrupt of Assist debug module, LEVEL*/ - ETS_DMA_APBPERI_PMS_INTR_SOURCE, - ETS_CORE0_IRAM0_PMS_INTR_SOURCE, - ETS_CORE0_DRAM0_PMS_INTR_SOURCE, - ETS_CORE0_PIF_PMS_INTR_SOURCE, - ETS_CORE0_PIF_PMS_SIZE_INTR_SOURCE, - ETS_BAK_PMS_VIOLATE_INTR_SOURCE, - ETS_CACHE_CORE0_ACS_INTR_SOURCE, - ETS_MAX_INTR_SOURCE, -} periph_interrput_t; - #ifdef __cplusplus } #endif diff --git a/components/soc/esp32c6/include/soc/interrupts.h b/components/soc/esp32c6/include/soc/interrupts.h new file mode 100644 index 0000000000..ec930fef51 --- /dev/null +++ b/components/soc/esp32c6/include/soc/interrupts.h @@ -0,0 +1,102 @@ +/* + * SPDX-FileCopyrightText: 2018-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once +#include + +#ifdef __cplusplus +extern "C" +{ +#endif + +//Interrupt hardware source table +//This table is decided by hardware, don't touch this. +typedef enum { + ETS_WIFI_MAC_INTR_SOURCE = 0, /**< interrupt of WiFi MAC, level*/ + ETS_WIFI_MAC_NMI_SOURCE, /**< interrupt of WiFi MAC, NMI, use if MAC have bug to fix in NMI*/ + ETS_WIFI_PWR_INTR_SOURCE, /**< */ + ETS_WIFI_BB_INTR_SOURCE, /**< interrupt of WiFi BB, level, we can do some calibartion*/ + ETS_BT_MAC_INTR_SOURCE, /**< will be cancelled*/ + ETS_BT_BB_INTR_SOURCE, /**< interrupt of BT BB, level*/ + ETS_BT_BB_NMI_SOURCE, /**< interrupt of BT BB, NMI, use if BB have bug to fix in NMI*/ + ETS_LP_TIMER_INTR_SOURCE, + ETS_COEX_INTR_SOURCE, + ETS_BLE_TIMER_INTR_SOURCE, + ETS_BLE_SEC_INTR_SOURCE, + ETS_I2C_MASTER_SOURCE, /**< interrupt of I2C Master, level*/ + ETS_ZB_MAC_SOURCE, + ETS_PMU_INTR_SOURCE, + ETS_EFUSE_INTR_SOURCE, /**< interrupt of efuse, level, not likely to use*/ + ETS_LP_RTC_TIMER_INTR_SOURCE, + ETS_LP_UART_INTR_SOURCE, + ETS_LP_I2C_INTR_SOURCE, + ETS_LP_WDT_INTR_SOURCE, + ETS_LP_PERI_TIMEOUT_INTR_SOURCE, + ETS_LP_APM_M0_INTR_SOURCE, + ETS_LP_APM_M1_INTR_SOURCE, + ETS_FROM_CPU_INTR0_SOURCE, /**< interrupt0 generated from a CPU, level*/ /* Used for FreeRTOS */ + ETS_FROM_CPU_INTR1_SOURCE, /**< interrupt1 generated from a CPU, level*/ /* Used for FreeRTOS */ + ETS_FROM_CPU_INTR2_SOURCE, /**< interrupt2 generated from a CPU, level*/ + ETS_FROM_CPU_INTR3_SOURCE, /**< interrupt3 generated from a CPU, level*/ + ETS_ASSIST_DEBUG_INTR_SOURCE, /**< interrupt of Assist debug module, LEVEL*/ + ETS_TRACE_INTR_SOURCE, + ETS_CACHE_INTR_SOURCE, + ETS_CPU_PERI_TIMEOUT_INTR_SOURCE, + ETS_GPIO_INTR_SOURCE, /**< interrupt of GPIO, level*/ + ETS_GPIO_NMI_SOURCE, /**< interrupt of GPIO, NMI*/ + ETS_PAU_INTR_SOURCE, + ETS_HP_PERI_TIMEOUT_INTR_SOURCE, + ETS_MODEM_PERI_TIMEOUT_INTR_SOURCE, + ETS_HP_APM_M0_INTR_SOURCE, + ETS_HP_APM_M1_INTR_SOURCE, + ETS_HP_APM_M2_INTR_SOURCE, + ETS_HP_APM_M3_INTR_SOURCE, + ETS_LP_APM0_INTR_SOURCE, + ETS_MSPI_INTR_SOURCE, + ETS_I2S1_INTR_SOURCE, /**< interrupt of I2S1, level*/ + ETS_UHCI0_INTR_SOURCE, /**< interrupt of UHCI0, level*/ + ETS_UART0_INTR_SOURCE, /**< interrupt of UART0, level*/ + ETS_UART1_INTR_SOURCE, /**< interrupt of UART1, level*/ + ETS_LEDC_INTR_SOURCE, /**< interrupt of LED PWM, level*/ + ETS_TWAI0_INTR_SOURCE, /**< interrupt of can0, level*/ + ETS_TWAI1_INTR_SOURCE, /**< interrupt of can1, level*/ + ETS_USB_SERIAL_JTAG_INTR_SOURCE, /**< interrupt of USB, level*/ + ETS_RMT_INTR_SOURCE, /**< interrupt of remote controller, level*/ + ETS_I2C_EXT0_INTR_SOURCE, /**< interrupt of I2C controller1, level*/ + ETS_TG0_T0_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, TIMER0, level*/ + ETS_TG0_T1_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, TIMER1, level*/ + ETS_TG0_WDT_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, WATCH DOG, level*/ + ETS_TG1_T0_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, TIMER0, level*/ + ETS_TG1_T1_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, TIMER1, level*/ + ETS_TG1_WDT_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, WATCHDOG, level*/ + ETS_SYSTIMER_TARGET0_EDGE_INTR_SOURCE, /**< interrupt of system timer 0, EDGE*/ + ETS_SYSTIMER_TARGET1_EDGE_INTR_SOURCE, /**< interrupt of system timer 1, EDGE*/ + ETS_SYSTIMER_TARGET2_EDGE_INTR_SOURCE, /**< interrupt of system timer 2, EDGE*/ + ETS_APB_ADC_INTR_SOURCE, /**< interrupt of APB ADC, LEVEL*/ + ETS_MCPWM0_INTR_SOURCE, /**< interrupt of MCPWM0, LEVEL*/ + ETS_PCNT_INTR_SOURCE, + ETS_PARL_IO_INTR_SOURCE, + ETS_SLC0_INTR_SOURCE, + ETS_SLC_INTR_SOURCE, + ETS_DMA_IN_CH0_INTR_SOURCE, /**< interrupt of general DMA IN channel 0, LEVEL*/ + ETS_DMA_IN_CH1_INTR_SOURCE, /**< interrupt of general DMA IN channel 1, LEVEL*/ + ETS_DMA_IN_CH2_INTR_SOURCE, /**< interrupt of general DMA IN channel 2, LEVEL*/ + ETS_DMA_OUT_CH0_INTR_SOURCE, /**< interrupt of general DMA OUT channel 0, LEVEL*/ + ETS_DMA_OUT_CH1_INTR_SOURCE, /**< interrupt of general DMA OUT channel 1, LEVEL*/ + ETS_DMA_OUT_CH2_INTR_SOURCE, /**< interrupt of general DMA OUT channel 2, LEVEL*/ + ETS_GSPI2_INTR_SOURCE, + ETS_AES_INTR_SOURCE, /**< interrupt of AES accelerator, level*/ + ETS_SHA_INTR_SOURCE, /**< interrupt of SHA accelerator, level*/ + ETS_RSA_INTR_SOURCE, /**< interrupt of RSA accelerator, level*/ + ETS_ECC_INTR_SOURCE, /**< interrupt of ECC accelerator, level*/ + ETS_MAX_INTR_SOURCE, +} periph_interrput_t; + +extern const char * const esp_isr_names[ETS_MAX_INTR_SOURCE]; + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/periph_defs.h b/components/soc/esp32c6/include/soc/periph_defs.h index d4ef7c9663..55adbd39c8 100644 --- a/components/soc/esp32c6/include/soc/periph_defs.h +++ b/components/soc/esp32c6/include/soc/periph_defs.h @@ -6,6 +6,8 @@ #pragma once +#include "soc/interrupts.h" + #ifdef __cplusplus extern "C" { #endif @@ -63,87 +65,6 @@ typedef enum { #define PERIPH_MODEM_MODULE_NUM (PERIPH_MODEM_MODULE_MAX - PERIPH_MODEM_MODULE_MIN + 1) #define IS_MODEM_MODULE(periph) ((periph>=PERIPH_MODEM_MODULE_MIN) && (periph<=PERIPH_MODEM_MODULE_MAX)) -typedef enum { - ETS_WIFI_MAC_INTR_SOURCE = 0, /**< interrupt of WiFi MAC, level*/ - ETS_WIFI_MAC_NMI_SOURCE, /**< interrupt of WiFi MAC, NMI, use if MAC have bug to fix in NMI*/ - ETS_WIFI_PWR_INTR_SOURCE, /**< */ - ETS_WIFI_BB_INTR_SOURCE, /**< interrupt of WiFi BB, level, we can do some calibartion*/ - ETS_BT_MAC_INTR_SOURCE, /**< will be cancelled*/ - ETS_BT_BB_INTR_SOURCE, /**< interrupt of BT BB, level*/ - ETS_BT_BB_NMI_SOURCE, /**< interrupt of BT BB, NMI, use if BB have bug to fix in NMI*/ - ETS_LP_TIMER_INTR_SOURCE, - ETS_COEX_INTR_SOURCE, - ETS_BLE_TIMER_INTR_SOURCE, - ETS_BLE_SEC_INTR_SOURCE, - ETS_I2C_MASTER_SOURCE, /**< interrupt of I2C Master, level*/ - ETS_ZB_MAC_SOURCE, - ETS_PMU_INTR_SOURCE, - ETS_EFUSE_INTR_SOURCE, /**< interrupt of efuse, level, not likely to use*/ - ETS_LP_RTC_TIMER_INTR_SOURCE, - ETS_LP_UART_INTR_SOURCE, - ETS_LP_I2C_INTR_SOURCE, - ETS_LP_WDT_INTR_SOURCE, - ETS_LP_PERI_TIMEOUT_INTR_SOURCE, - ETS_LP_APM_M0_INTR_SOURCE, - ETS_LP_APM_M1_INTR_SOURCE, - ETS_FROM_CPU_INTR0_SOURCE, /**< interrupt0 generated from a CPU, level*/ /* Used for FreeRTOS */ - ETS_FROM_CPU_INTR1_SOURCE, /**< interrupt1 generated from a CPU, level*/ /* Used for FreeRTOS */ - ETS_FROM_CPU_INTR2_SOURCE, /**< interrupt2 generated from a CPU, level*/ - ETS_FROM_CPU_INTR3_SOURCE, /**< interrupt3 generated from a CPU, level*/ - ETS_ASSIST_DEBUG_INTR_SOURCE, /**< interrupt of Assist debug module, LEVEL*/ - ETS_TRACE_INTR_SOURCE, - ETS_CACHE_INTR_SOURCE, - ETS_CPU_PERI_TIMEOUT_INTR_SOURCE, - ETS_GPIO_INTR_SOURCE, /**< interrupt of GPIO, level*/ - ETS_GPIO_NMI_SOURCE, /**< interrupt of GPIO, NMI*/ - ETS_PAU_INTR_SOURCE, - ETS_HP_PERI_TIMEOUT_INTR_SOURCE, - ETS_MODEM_PERI_TIMEOUT_INTR_SOURCE, - ETS_HP_APM_M0_INTR_SOURCE, - ETS_HP_APM_M1_INTR_SOURCE, - ETS_HP_APM_M2_INTR_SOURCE, - ETS_HP_APM_M3_INTR_SOURCE, - ETS_LP_APM0_INTR_SOURCE, - ETS_MSPI_INTR_SOURCE, - ETS_I2S1_INTR_SOURCE, /**< interrupt of I2S1, level*/ - ETS_UHCI0_INTR_SOURCE, /**< interrupt of UHCI0, level*/ - ETS_UART0_INTR_SOURCE, /**< interrupt of UART0, level*/ - ETS_UART1_INTR_SOURCE, /**< interrupt of UART1, level*/ - ETS_LEDC_INTR_SOURCE, /**< interrupt of LED PWM, level*/ - ETS_TWAI0_INTR_SOURCE, /**< interrupt of can0, level*/ - ETS_TWAI1_INTR_SOURCE, /**< interrupt of can1, level*/ - ETS_USB_SERIAL_JTAG_INTR_SOURCE, /**< interrupt of USB, level*/ - ETS_RMT_INTR_SOURCE, /**< interrupt of remote controller, level*/ - ETS_I2C_EXT0_INTR_SOURCE, /**< interrupt of I2C controller1, level*/ - ETS_TG0_T0_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, TIMER0, level*/ - ETS_TG0_T1_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, TIMER1, level*/ - ETS_TG0_WDT_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, WATCH DOG, level*/ - ETS_TG1_T0_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, TIMER0, level*/ - ETS_TG1_T1_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, TIMER1, level*/ - ETS_TG1_WDT_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, WATCHDOG, level*/ - ETS_SYSTIMER_TARGET0_EDGE_INTR_SOURCE, /**< interrupt of system timer 0, EDGE*/ - ETS_SYSTIMER_TARGET1_EDGE_INTR_SOURCE, /**< interrupt of system timer 1, EDGE*/ - ETS_SYSTIMER_TARGET2_EDGE_INTR_SOURCE, /**< interrupt of system timer 2, EDGE*/ - ETS_APB_ADC_INTR_SOURCE, /**< interrupt of APB ADC, LEVEL*/ - ETS_MCPWM0_INTR_SOURCE, /**< interrupt of MCPWM0, LEVEL*/ - ETS_PCNT_INTR_SOURCE, - ETS_PARL_IO_INTR_SOURCE, - ETS_SLC0_INTR_SOURCE, - ETS_SLC_INTR_SOURCE, - ETS_DMA_IN_CH0_INTR_SOURCE, /**< interrupt of general DMA IN channel 0, LEVEL*/ - ETS_DMA_IN_CH1_INTR_SOURCE, /**< interrupt of general DMA IN channel 1, LEVEL*/ - ETS_DMA_IN_CH2_INTR_SOURCE, /**< interrupt of general DMA IN channel 2, LEVEL*/ - ETS_DMA_OUT_CH0_INTR_SOURCE, /**< interrupt of general DMA OUT channel 0, LEVEL*/ - ETS_DMA_OUT_CH1_INTR_SOURCE, /**< interrupt of general DMA OUT channel 1, LEVEL*/ - ETS_DMA_OUT_CH2_INTR_SOURCE, /**< interrupt of general DMA OUT channel 2, LEVEL*/ - ETS_GSPI2_INTR_SOURCE, - ETS_AES_INTR_SOURCE, /**< interrupt of AES accelerator, level*/ - ETS_SHA_INTR_SOURCE, /**< interrupt of SHA accelerator, level*/ - ETS_RSA_INTR_SOURCE, /**< interrupt of RSA accelerator, level*/ - ETS_ECC_INTR_SOURCE, /**< interrupt of ECC accelerator, level*/ - ETS_MAX_INTR_SOURCE, -} periph_interrput_t; - #ifdef __cplusplus } #endif diff --git a/components/soc/esp32h2/include/soc/interrupts.h b/components/soc/esp32h2/include/soc/interrupts.h new file mode 100644 index 0000000000..aabe612f83 --- /dev/null +++ b/components/soc/esp32h2/include/soc/interrupts.h @@ -0,0 +1,90 @@ +/* + * SPDX-FileCopyrightText: 2018-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once +#include + +#ifdef __cplusplus +extern "C" +{ +#endif + +//Interrupt hardware source table +//This table is decided by hardware, don't touch this. +typedef enum { + ETS_PMU_INTR_SOURCE = 0, + ETS_EFUSE_INTR_SOURCE, /**< interrupt of efuse, level, not likely to use*/ + ETS_LP_RTC_TIMER_INTR_SOURCE, + ETS_LP_BLE_TIMER_INTR_SOURCE, + ETS_LP_WDT_INTR_SOURCE, + ETS_LP_PERI_TIMEOUT_INTR_SOURCE, + ETS_LP_APM_M0_INTR_SOURCE, + ETS_FROM_CPU_INTR0_SOURCE, /**< interrupt0 generated from a CPU, level*/ /* Used for FreeRTOS */ + ETS_FROM_CPU_INTR1_SOURCE, /**< interrupt1 generated from a CPU, level*/ /* Used for FreeRTOS */ + ETS_FROM_CPU_INTR2_SOURCE, /**< interrupt2 generated from a CPU, level*/ + ETS_FROM_CPU_INTR3_SOURCE, /**< interrupt3 generated from a CPU, level*/ + ETS_ASSIST_DEBUG_INTR_SOURCE, /**< interrupt of Assist debug module, LEVEL*/ + ETS_TRACE_INTR_SOURCE, + ETS_CACHE_INTR_SOURCE, + ETS_CPU_PERI_TIMEOUT_INTR_SOURCE, + ETS_BT_MAC_INTR_SOURCE, + ETS_BT_BB_INTR_SOURCE, + ETS_BT_BB_NMI_INTR_SOURCE, + ETS_COEX_INTR_SOURCE, + ETS_BLE_TIMER_INTR_SOURCE, + ETS_BLE_SEC_INTR_SOURCE, + ETS_ZB_MAC_INTR_SOURCE, + ETS_GPIO_INTR_SOURCE, /**< interrupt of GPIO, level*/ + ETS_GPIO_NMI_SOURCE, /**< interrupt of GPIO, NMI*/ + ETS_PAU_INTR_SOURCE, + ETS_HP_PERI_TIMEOUT_INTR_SOURCE, + ETS_HP_APM_M0_INTR_SOURCE, + ETS_HP_APM_M1_INTR_SOURCE, + ETS_HP_APM_M2_INTR_SOURCE, + ETS_HP_APM_M3_INTR_SOURCE, + ETS_MSPI_INTR_SOURCE, + ETS_I2S1_INTR_SOURCE, /**< interrupt of I2S1, level*/ + ETS_UHCI0_INTR_SOURCE, /**< interrupt of UHCI0, level*/ + ETS_UART0_INTR_SOURCE, /**< interrupt of UART0, level*/ + ETS_UART1_INTR_SOURCE, /**< interrupt of UART1, level*/ + ETS_LEDC_INTR_SOURCE, /**< interrupt of LED PWM, level*/ + ETS_TWAI0_INTR_SOURCE, /**< interrupt of can0, level*/ + ETS_USB_SERIAL_JTAG_INTR_SOURCE, /**< interrupt of USB, level*/ + ETS_RMT_INTR_SOURCE, /**< interrupt of remote controller, level*/ + ETS_I2C_EXT0_INTR_SOURCE, /**< interrupt of I2C controller0, level*/ + ETS_I2C_EXT1_INTR_SOURCE, /**< interrupt of I2C controller1, level*/ + ETS_TG0_T0_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, TIMER0, level*/ + ETS_TG0_WDT_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, WATCH DOG, level*/ + ETS_TG1_T0_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, TIMER0, level*/ + ETS_TG1_WDT_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, WATCHDOG, level*/ + ETS_SYSTIMER_TARGET0_EDGE_INTR_SOURCE, /**< interrupt of system timer 0, EDGE*/ + ETS_SYSTIMER_TARGET1_EDGE_INTR_SOURCE, /**< interrupt of system timer 1, EDGE*/ + ETS_SYSTIMER_TARGET2_EDGE_INTR_SOURCE, /**< interrupt of system timer 2, EDGE*/ + ETS_APB_ADC_INTR_SOURCE, /**< interrupt of APB ADC, LEVEL*/ + ETS_MCPWM0_INTR_SOURCE, + ETS_PCNT_INTR_SOURCE, + ETS_PARL_IO_TX_INTR_SOURCE, + ETS_PARL_IO_RX_INTR_SOURCE, + ETS_DMA_IN_CH0_INTR_SOURCE, /**< interrupt of general DMA IN channel 0, LEVEL*/ + ETS_DMA_IN_CH1_INTR_SOURCE, /**< interrupt of general DMA IN channel 1, LEVEL*/ + ETS_DMA_IN_CH2_INTR_SOURCE, /**< interrupt of general DMA IN channel 2, LEVEL*/ + ETS_DMA_OUT_CH0_INTR_SOURCE, /**< interrupt of general DMA OUT channel 0, LEVEL*/ + ETS_DMA_OUT_CH1_INTR_SOURCE, /**< interrupt of general DMA OUT channel 1, LEVEL*/ + ETS_DMA_OUT_CH2_INTR_SOURCE, /**< interrupt of general DMA OUT channel 2, LEVEL*/ + ETS_GSPI2_INTR_SOURCE, + ETS_AES_INTR_SOURCE, /**< interrupt of AES accelerator, level*/ + ETS_SHA_INTR_SOURCE, /**< interrupt of SHA accelerator, level*/ + ETS_RSA_INTR_SOURCE, /**< interrupt of RSA accelerator, level*/ + ETS_ECC_INTR_SOURCE, /**< interrupt of ECC accelerator, level*/ + ETS_ECDSA_INTR_SOURCE, /**< interrupt of ECDSA accelerator, level*/ + ETS_MAX_INTR_SOURCE, +} periph_interrput_t; + +extern const char * const esp_isr_names[ETS_MAX_INTR_SOURCE]; + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/periph_defs.h b/components/soc/esp32h2/include/soc/periph_defs.h index a51c09f208..23ad1eb5a7 100644 --- a/components/soc/esp32h2/include/soc/periph_defs.h +++ b/components/soc/esp32h2/include/soc/periph_defs.h @@ -6,6 +6,8 @@ #pragma once +#include "soc/interrupts.h" + #ifdef __cplusplus extern "C" { #endif @@ -56,75 +58,6 @@ typedef enum { #define PERIPH_MODEM_MODULE_NUM (PERIPH_MODEM_MODULE_MAX - PERIPH_MODEM_MODULE_MIN + 1) #define IS_MODEM_MODULE(periph) ((periph>=PERIPH_MODEM_MODULE_MIN) && (periph<=PERIPH_MODEM_MODULE_MAX)) -typedef enum { - ETS_PMU_INTR_SOURCE = 0, - ETS_EFUSE_INTR_SOURCE, /**< interrupt of efuse, level, not likely to use*/ - ETS_LP_RTC_TIMER_INTR_SOURCE, - ETS_LP_BLE_TIMER_INTR_SOURCE, - ETS_LP_WDT_INTR_SOURCE, - ETS_LP_PERI_TIMEOUT_INTR_SOURCE, - ETS_LP_APM_M0_INTR_SOURCE, - ETS_FROM_CPU_INTR0_SOURCE, /**< interrupt0 generated from a CPU, level*/ /* Used for FreeRTOS */ - ETS_FROM_CPU_INTR1_SOURCE, /**< interrupt1 generated from a CPU, level*/ /* Used for FreeRTOS */ - ETS_FROM_CPU_INTR2_SOURCE, /**< interrupt2 generated from a CPU, level*/ - ETS_FROM_CPU_INTR3_SOURCE, /**< interrupt3 generated from a CPU, level*/ - ETS_ASSIST_DEBUG_INTR_SOURCE, /**< interrupt of Assist debug module, LEVEL*/ - ETS_TRACE_INTR_SOURCE, - ETS_CACHE_INTR_SOURCE, - ETS_CPU_PERI_TIMEOUT_INTR_SOURCE, - ETS_BT_MAC_INTR_SOURCE, - ETS_BT_BB_INTR_SOURCE, - ETS_BT_BB_NMI_INTR_SOURCE, - ETS_COEX_INTR_SOURCE, - ETS_BLE_TIMER_INTR_SOURCE, - ETS_BLE_SEC_INTR_SOURCE, - ETS_ZB_MAC_INTR_SOURCE, - ETS_GPIO_INTR_SOURCE, /**< interrupt of GPIO, level*/ - ETS_GPIO_NMI_SOURCE, /**< interrupt of GPIO, NMI*/ - ETS_PAU_INTR_SOURCE, - ETS_HP_PERI_TIMEOUT_INTR_SOURCE, - ETS_HP_APM_M0_INTR_SOURCE, - ETS_HP_APM_M1_INTR_SOURCE, - ETS_HP_APM_M2_INTR_SOURCE, - ETS_HP_APM_M3_INTR_SOURCE, - ETS_MSPI_INTR_SOURCE, - ETS_I2S1_INTR_SOURCE, /**< interrupt of I2S1, level*/ - ETS_UHCI0_INTR_SOURCE, /**< interrupt of UHCI0, level*/ - ETS_UART0_INTR_SOURCE, /**< interrupt of UART0, level*/ - ETS_UART1_INTR_SOURCE, /**< interrupt of UART1, level*/ - ETS_LEDC_INTR_SOURCE, /**< interrupt of LED PWM, level*/ - ETS_TWAI0_INTR_SOURCE, /**< interrupt of can0, level*/ - ETS_USB_SERIAL_JTAG_INTR_SOURCE, /**< interrupt of USB, level*/ - ETS_RMT_INTR_SOURCE, /**< interrupt of remote controller, level*/ - ETS_I2C_EXT0_INTR_SOURCE, /**< interrupt of I2C controller0, level*/ - ETS_I2C_EXT1_INTR_SOURCE, /**< interrupt of I2C controller1, level*/ - ETS_TG0_T0_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, TIMER0, level*/ - ETS_TG0_WDT_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, WATCH DOG, level*/ - ETS_TG1_T0_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, TIMER0, level*/ - ETS_TG1_WDT_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, WATCHDOG, level*/ - ETS_SYSTIMER_TARGET0_EDGE_INTR_SOURCE, /**< interrupt of system timer 0, EDGE*/ - ETS_SYSTIMER_TARGET1_EDGE_INTR_SOURCE, /**< interrupt of system timer 1, EDGE*/ - ETS_SYSTIMER_TARGET2_EDGE_INTR_SOURCE, /**< interrupt of system timer 2, EDGE*/ - ETS_APB_ADC_INTR_SOURCE, /**< interrupt of APB ADC, LEVEL*/ - ETS_MCPWM0_INTR_SOURCE, - ETS_PCNT_INTR_SOURCE, - ETS_PARL_IO_TX_INTR_SOURCE, - ETS_PARL_IO_RX_INTR_SOURCE, - ETS_DMA_IN_CH0_INTR_SOURCE, /**< interrupt of general DMA IN channel 0, LEVEL*/ - ETS_DMA_IN_CH1_INTR_SOURCE, /**< interrupt of general DMA IN channel 1, LEVEL*/ - ETS_DMA_IN_CH2_INTR_SOURCE, /**< interrupt of general DMA IN channel 2, LEVEL*/ - ETS_DMA_OUT_CH0_INTR_SOURCE, /**< interrupt of general DMA OUT channel 0, LEVEL*/ - ETS_DMA_OUT_CH1_INTR_SOURCE, /**< interrupt of general DMA OUT channel 1, LEVEL*/ - ETS_DMA_OUT_CH2_INTR_SOURCE, /**< interrupt of general DMA OUT channel 2, LEVEL*/ - ETS_GSPI2_INTR_SOURCE, - ETS_AES_INTR_SOURCE, /**< interrupt of AES accelerator, level*/ - ETS_SHA_INTR_SOURCE, /**< interrupt of SHA accelerator, level*/ - ETS_RSA_INTR_SOURCE, /**< interrupt of RSA accelerator, level*/ - ETS_ECC_INTR_SOURCE, /**< interrupt of ECC accelerator, level*/ - ETS_ECDSA_INTR_SOURCE, /**< interrupt of ECDSA accelerator, level*/ - ETS_MAX_INTR_SOURCE, -} periph_interrput_t; - #ifdef __cplusplus } #endif diff --git a/components/soc/esp32p4/include/soc/interrupts.h b/components/soc/esp32p4/include/soc/interrupts.h new file mode 100644 index 0000000000..9595519827 --- /dev/null +++ b/components/soc/esp32p4/include/soc/interrupts.h @@ -0,0 +1,161 @@ +/* + * SPDX-FileCopyrightText: 2018-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once +#include + +#ifdef __cplusplus +extern "C" +{ +#endif + +//Interrupt hardware source table +//This table is decided by hardware, don't touch this. +typedef enum { + ETS_LP_RTC_INTR_SOURCE = 0, + ETS_LP_WDT_INTR_SOURCE, + ETS_LP_TIMER_REG0_INTR_SOURCE, + ETS_LP_TIMER_REG1_INTR_SOURCE, + ETS_MB_HP_INTR_SOURCE, + ETS_MB_LP_INTR_SOURCE, + ETS_PMU_0_INTR_SOURCE, + ETS_PMU_1_INTR_SOURCE, + ETS_LP_ANAPERI_INTR_SOURCE, + ETS_LP_ADC_INTR_SOURCE, + ETS_LP_GPIO_INTR_SOURCE, + ETS_LP_I2C_INTR_SOURCE, + ETS_LP_I2S_INTR_SOURCE, + ETS_LP_SPI_INTR_SOURCE, + ETS_LP_TOUCH_INTR_SOURCE, + ETS_LP_TSENS_INTR_SOURCE, + ETS_LP_UART_INTR_SOURCE, + ETS_LP_EFUSE_INTR_SOURCE, + ETS_LP_SW_INTR_SOURCE, + ETS_LP_SYSREG_INTR_SOURCE, + ETS_LP_HUK_INTR_SOURCE, + ETS_SYS_ICM_INTR_SOURCE, + ETS_USB_DEVICE_INTR_SOURCE, + ETS_SDIO_HOST_INTR_SOURCE, + ETS_GDMA_INTR_SOURCE, + ETS_SPI2_INTR_SOURCE, + ETS_SPI3_INTR_SOURCE, + ETS_I2S0_INTR_SOURCE, + ETS_I2S1_INTR_SOURCE, + ETS_I2S2_INTR_SOURCE, + ETS_UHCI0_INTR_SOURCE, + ETS_UART0_INTR_SOURCE, + ETS_UART1_INTR_SOURCE, + ETS_UART2_INTR_SOURCE, + ETS_UART3_INTR_SOURCE, + ETS_UART4_INTR_SOURCE, + ETS_LCD_CAM_INTR_SOURCE, + ETS_ADC_INTR_SOURCE, + ETS_PWM0_INTR_SOURCE, + ETS_PWM1_INTR_SOURCE, + ETS_CAN0_INTR_SOURCE, + ETS_CAN1_INTR_SOURCE, + ETS_CAN2_INTR_SOURCE, + ETS_RMT_INTR_SOURCE, + ETS_I2C0_INTR_SOURCE, + ETS_I2C1_INTR_SOURCE, + ETS_TIMERGROUP0_T0_INTR_SOURCE, + ETS_TIMERGROUP0_T1_INTR_SOURCE, + ETS_TIMERGROUP0_WDT_INTR_SOURCE, + ETS_TIMERGROUP1_T0_INTR_SOURCE, + ETS_TIMERGROUP1_T1_INTR_SOURCE, + ETS_TIMERGROUP1_WDT_INTR_SOURCE, + ETS_LEDC_INTR_SOURCE, + ETS_SYSTIMER_TARGET0_INTR_SOURCE, + ETS_SYSTIMER_TARGET1_INTR_SOURCE, + ETS_SYSTIMER_TARGET2_INTR_SOURCE, + ETS_AHB_PDMA_IN_CH0_INTR_SOURCE, + ETS_AHB_PDMA_IN_CH1_INTR_SOURCE, + ETS_AHB_PDMA_IN_CH2_INTR_SOURCE, + ETS_AHB_PDMA_OUT_CH0_INTR_SOURCE, + ETS_AHB_PDMA_OUT_CH1_INTR_SOURCE, + ETS_AHB_PDMA_OUT_CH2_INTR_SOURCE, + ETS_AXI_PDMA_IN_CH0_INTR_SOURCE, + ETS_AXI_PDMA_IN_CH1_INTR_SOURCE, + ETS_AXI_PDMA_IN_CH2_INTR_SOURCE, + ETS_AXI_PDMA_OUT_CH0_INTR_SOURCE, + ETS_AXI_PDMA_OUT_CH1_INTR_SOURCE, + + ETS_AXI_PDMA_OUT_CH2_INTR_SOURCE, + ETS_RSA_INTA_SOURCE, + ETS_AES_INTR_SOURCE, + ETS_SHA_INTR_SOURCE, + ETS_ECC_INTR_SOURCE, + ETS_ECDSA_INTR_SOURCE, + ETS_KM_INTR_SOURCE, + ETS_GPIO_INTR0_SOURCE, + + ETS_GPIO_INTR1_SOURCE, + ETS_GPIO_INTR2_SOURCE, + ETS_GPIO_INTR3_SOURCE, + ETS_GPIO_PAD_COMP_INTR_SOURCE, + ETS_CPU_INT_FROM_CPU0_INTR_SOURCE, + ETS_CPU_INT_FROM_CPU1_INTR_SOURCE, + ETS_CPU_INT_FROM_CPU2_INTR_SOURCE, + ETS_CPU_INT_FROM_CPU3_INTR_SOURCE, + ETS_CACHE_INTR_SOURCE, + ETS_MSPI_INTR_SOURCE, + ETS_CSI_BRIDGE_INTR_SOURCE, + + ETS_DSI_BRIDGE_INTR_SOURCE, + ETS_CSI_INTR_SOURCE, + ETS_DSI_INTR_SOURCE, + ETS_GMII_PHY_INTR_SOURCE, + ETS_LPI_INTR_SOURCE, + ETS_PMT_INTR_SOURCE, + ETS_SBD_INTR_SOURCE, + ETS_USB_OTG_INTR_SOURCE, + ETS_USB_OTG_ENDP_MULTI_PROC_INTR_SOURCE, + + ETS_JPEG_INTR_SOURCE, + ETS_PPA_INTR_SOURCE, + ETS_CORE0_TRACE_INTR_SOURCE, + ETS_CORE1_TRACE_INTR_SOURCE, + ETS_HP_CORE_CTRL_INTR_SOURCE, + ETS_ISP_INTR_SOURCE, + ETS_I3C_MST_INTR_SOURCE, + ETS_I3C_SLV_INTR_SOURCE, + ETS_USB_OTG11_CH0_INTR_SOURCE, + ETS_DMA2D_IN_CH0_INTR_SOURCE, + + ETS_DMA2D_IN_CH1_INTR_SOURCE, + ETS_DMA2D_OUT_CH0_INTR_SOURCE, + ETS_DMA2D_OUT_CH1_INTR_SOURCE, + ETS_DMA2D_OUT_CH2_INTR_SOURCE, + ETS_PSRAM_MSPI_INTR_SOURCE, + ETS_HP_SYSREG_INTR_SOURCE, + ETS_PCNT_INTR_SOURCE, + + ETS_HP_PAU_INTR_SOURCE, + ETS_HP_PARLIO_RX_INTR_SOURCE, + ETS_HP_PARLIO_TX_INTR_SOURCE, + ETS_H264_DMA2D_OUT_CH0_INTR_SOURCE, + ETS_H264_DMA2D_OUT_CH1_INTR_SOURCE, + ETS_H264_DMA2D_OUT_CH2_INTR_SOURCE, + ETS_H264_DMA2D_OUT_CH3_INTR_SOURCE, + ETS_H264_DMA2D_OUT_CH4_INTR_SOURCE, + ETS_H264_DMA2D_IN_CH0_INTR_SOURCE, + ETS_H264_DMA2D_IN_CH1_INTR_SOURCE, + + ETS_H264_DMA2D_IN_CH2_INTR_SOURCE, + ETS_H264_DMA2D_IN_CH3_INTR_SOURCE, + ETS_H264_DMA2D_IN_CH4_INTR_SOURCE, + ETS_H264_DMA2D_IN_CH5_INTR_SOURCE, + ETS_H264_REG_INTR_SOURCE, + ETS_ASSIST_DEBUG_INTR_SOURCE, + + ETS_MAX_INTR_SOURCE, /**< number of interrupt sources */ +} periph_interrput_t; + +extern const char *const esp_isr_names[ETS_MAX_INTR_SOURCE]; + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/include/soc/periph_defs.h b/components/soc/esp32p4/include/soc/periph_defs.h index 39db325006..3084156421 100644 --- a/components/soc/esp32p4/include/soc/periph_defs.h +++ b/components/soc/esp32p4/include/soc/periph_defs.h @@ -6,6 +6,8 @@ #pragma once +#include "soc/interrupts.h" + #ifdef __cplusplus extern "C" { #endif @@ -78,146 +80,6 @@ typedef enum { LP_PERIPH_MODULE_MAX, } lp_periph_module_t; -typedef enum { - ETS_LP_RTC_INTR_SOURCE = 0, - ETS_LP_WDT_INTR_SOURCE, - ETS_LP_TIMER_REG0_INTR_SOURCE, - ETS_LP_TIMER_REG1_INTR_SOURCE, - ETS_MB_HP_INTR_SOURCE, - ETS_MB_LP_INTR_SOURCE, - ETS_PMU_0_INTR_SOURCE, - ETS_PMU_1_INTR_SOURCE, - ETS_LP_ANAPERI_INTR_SOURCE, - ETS_LP_ADC_INTR_SOURCE, - ETS_LP_GPIO_INTR_SOURCE, - ETS_LP_I2C_INTR_SOURCE, - ETS_LP_I2S_INTR_SOURCE, - ETS_LP_SPI_INTR_SOURCE, - ETS_LP_TOUCH_INTR_SOURCE, - ETS_LP_TSENS_INTR_SOURCE, - ETS_LP_UART_INTR_SOURCE, - ETS_LP_EFUSE_INTR_SOURCE, - ETS_LP_SW_INTR_SOURCE, - ETS_LP_SYSREG_INTR_SOURCE, - ETS_LP_HUK_INTR_SOURCE, - ETS_SYS_ICM_INTR_SOURCE, - ETS_USB_DEVICE_INTR_SOURCE, - ETS_SDIO_HOST_INTR_SOURCE, - ETS_GDMA_INTR_SOURCE, - ETS_SPI2_INTR_SOURCE, - ETS_SPI3_INTR_SOURCE, - ETS_I2S0_INTR_SOURCE, - ETS_I2S1_INTR_SOURCE, - ETS_I2S2_INTR_SOURCE, - ETS_UHCI0_INTR_SOURCE, - ETS_UART0_INTR_SOURCE, - ETS_UART1_INTR_SOURCE, - ETS_UART2_INTR_SOURCE, - ETS_UART3_INTR_SOURCE, - ETS_UART4_INTR_SOURCE, - ETS_LCD_CAM_INTR_SOURCE, - ETS_ADC_INTR_SOURCE, - ETS_PWM0_INTR_SOURCE, - ETS_PWM1_INTR_SOURCE, - ETS_CAN0_INTR_SOURCE, - ETS_CAN1_INTR_SOURCE, - ETS_CAN2_INTR_SOURCE, - ETS_RMT_INTR_SOURCE, - ETS_I2C0_INTR_SOURCE, - ETS_I2C1_INTR_SOURCE, - ETS_TIMERGROUP0_T0_INTR_SOURCE, - ETS_TIMERGROUP0_T1_INTR_SOURCE, - ETS_TIMERGROUP0_WDT_INTR_SOURCE, - ETS_TIMERGROUP1_T0_INTR_SOURCE, - ETS_TIMERGROUP1_T1_INTR_SOURCE, - ETS_TIMERGROUP1_WDT_INTR_SOURCE, - ETS_LEDC_INTR_SOURCE, - ETS_SYSTIMER_TARGET0_INTR_SOURCE, - ETS_SYSTIMER_TARGET1_INTR_SOURCE, - ETS_SYSTIMER_TARGET2_INTR_SOURCE, - ETS_AHB_PDMA_IN_CH0_INTR_SOURCE, - ETS_AHB_PDMA_IN_CH1_INTR_SOURCE, - ETS_AHB_PDMA_IN_CH2_INTR_SOURCE, - ETS_AHB_PDMA_OUT_CH0_INTR_SOURCE, - ETS_AHB_PDMA_OUT_CH1_INTR_SOURCE, - ETS_AHB_PDMA_OUT_CH2_INTR_SOURCE, - ETS_AXI_PDMA_IN_CH0_INTR_SOURCE, - ETS_AXI_PDMA_IN_CH1_INTR_SOURCE, - ETS_AXI_PDMA_IN_CH2_INTR_SOURCE, - ETS_AXI_PDMA_OUT_CH0_INTR_SOURCE, - ETS_AXI_PDMA_OUT_CH1_INTR_SOURCE, - - ETS_AXI_PDMA_OUT_CH2_INTR_SOURCE, - ETS_RSA_INTA_SOURCE, - ETS_AES_INTR_SOURCE, - ETS_SHA_INTR_SOURCE, - ETS_ECC_INTR_SOURCE, - ETS_ECDSA_INTR_SOURCE, - ETS_KM_INTR_SOURCE, - ETS_GPIO_INTR0_SOURCE, - - ETS_GPIO_INTR1_SOURCE, - ETS_GPIO_INTR2_SOURCE, - ETS_GPIO_INTR3_SOURCE, - ETS_GPIO_PAD_COMP_INTR_SOURCE, - ETS_CPU_INT_FROM_CPU0_INTR_SOURCE, - ETS_CPU_INT_FROM_CPU1_INTR_SOURCE, - ETS_CPU_INT_FROM_CPU2_INTR_SOURCE, - ETS_CPU_INT_FROM_CPU3_INTR_SOURCE, - ETS_CACHE_INTR_SOURCE, - ETS_MSPI_INTR_SOURCE, - ETS_CSI_BRIDGE_INTR_SOURCE, - - ETS_DSI_BRIDGE_INTR_SOURCE, - ETS_CSI_INTR_SOURCE, - ETS_DSI_INTR_SOURCE, - ETS_GMII_PHY_INTR_SOURCE, - ETS_LPI_INTR_SOURCE, - ETS_PMT_INTR_SOURCE, - ETS_SBD_INTR_SOURCE, - ETS_USB_OTG_INTR_SOURCE, - ETS_USB_OTG_ENDP_MULTI_PROC_INTR_SOURCE, - - ETS_JPEG_INTR_SOURCE, - ETS_PPA_INTR_SOURCE, - ETS_CORE0_TRACE_INTR_SOURCE, - ETS_CORE1_TRACE_INTR_SOURCE, - ETS_HP_CORE_CTRL_INTR_SOURCE, - ETS_ISP_INTR_SOURCE, - ETS_I3C_MST_INTR_SOURCE, - ETS_I3C_SLV_INTR_SOURCE, - ETS_USB_OTG11_CH0_INTR_SOURCE, - ETS_DMA2D_IN_CH0_INTR_SOURCE, - - ETS_DMA2D_IN_CH1_INTR_SOURCE, - ETS_DMA2D_OUT_CH0_INTR_SOURCE, - ETS_DMA2D_OUT_CH1_INTR_SOURCE, - ETS_DMA2D_OUT_CH2_INTR_SOURCE, - ETS_PSRAM_MSPI_INTR_SOURCE, - ETS_HP_SYSREG_INTR_SOURCE, - ETS_PCNT_INTR_SOURCE, - - ETS_HP_PAU_INTR_SOURCE, - ETS_HP_PARLIO_RX_INTR_SOURCE, - ETS_HP_PARLIO_TX_INTR_SOURCE, - ETS_H264_DMA2D_OUT_CH0_INTR_SOURCE, - ETS_H264_DMA2D_OUT_CH1_INTR_SOURCE, - ETS_H264_DMA2D_OUT_CH2_INTR_SOURCE, - ETS_H264_DMA2D_OUT_CH3_INTR_SOURCE, - ETS_H264_DMA2D_OUT_CH4_INTR_SOURCE, - ETS_H264_DMA2D_IN_CH0_INTR_SOURCE, - ETS_H264_DMA2D_IN_CH1_INTR_SOURCE, - - ETS_H264_DMA2D_IN_CH2_INTR_SOURCE, - ETS_H264_DMA2D_IN_CH3_INTR_SOURCE, - ETS_H264_DMA2D_IN_CH4_INTR_SOURCE, - ETS_H264_DMA2D_IN_CH5_INTR_SOURCE, - ETS_H264_REG_INTR_SOURCE, - ETS_ASSIST_DEBUG_INTR_SOURCE, - - ETS_MAX_INTR_SOURCE, /**< number of interrupt sources */ -} periph_interrput_t; - #ifdef __cplusplus } #endif diff --git a/components/soc/esp32s2/include/soc/interrupts.h b/components/soc/esp32s2/include/soc/interrupts.h new file mode 100644 index 0000000000..0afc8efde2 --- /dev/null +++ b/components/soc/esp32s2/include/soc/interrupts.h @@ -0,0 +1,120 @@ +/* + * SPDX-FileCopyrightText: 2018-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once +#include + +#ifdef __cplusplus +extern "C" +{ +#endif + +//Interrupt hardware source table +//This table is decided by hardware, don't touch this. +typedef enum { + ETS_WIFI_MAC_INTR_SOURCE = 0, /**< interrupt of WiFi MAC, level*/ + ETS_WIFI_MAC_NMI_SOURCE, /**< interrupt of WiFi MAC, NMI, use if MAC have bug to fix in NMI*/ + ETS_WIFI_PWR_INTR_SOURCE, /**< */ + ETS_WIFI_BB_INTR_SOURCE, /**< interrupt of WiFi BB, level, we can do some calibartion*/ + ETS_BT_MAC_INTR_SOURCE, /**< will be cancelled*/ + ETS_BT_BB_INTR_SOURCE, /**< interrupt of BT BB, level*/ + ETS_BT_BB_NMI_SOURCE, /**< interrupt of BT BB, NMI, use if BB have bug to fix in NMI*/ + ETS_RWBT_INTR_SOURCE, /**< interrupt of RWBT, level*/ + ETS_RWBLE_INTR_SOURCE, /**< interrupt of RWBLE, level*/ + ETS_RWBT_NMI_SOURCE, /**< interrupt of RWBT, NMI, use if RWBT have bug to fix in NMI*/ + ETS_RWBLE_NMI_SOURCE, /**< interrupt of RWBLE, NMI, use if RWBT have bug to fix in NMI*/ + ETS_SLC0_INTR_SOURCE, /**< interrupt of SLC0, level*/ + ETS_SLC1_INTR_SOURCE, /**< interrupt of SLC1, level*/ + ETS_UHCI0_INTR_SOURCE, /**< interrupt of UHCI0, level*/ + ETS_UHCI1_INTR_SOURCE, /**< interrupt of UHCI1, level*/ + ETS_TG0_T0_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, TIMER0, level, we would like use EDGE for timer if permission*/ + + ETS_TG0_T1_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, TIMER1, level, we would like use EDGE for timer if permission*/ + ETS_TG0_WDT_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, WATCHDOG, level*/ + ETS_TG0_LACT_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, LACT, level*/ + ETS_TG1_T0_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, TIMER0, level, we would like use EDGE for timer if permission*/ + ETS_TG1_T1_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, TIMER1, level, we would like use EDGE for timer if permission*/ + ETS_TG1_WDT_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, WATCHDOG, level*/ + ETS_TG1_LACT_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, LACT, level*/ + ETS_GPIO_INTR_SOURCE, /**< interrupt of GPIO, level*/ + ETS_GPIO_NMI_SOURCE, /**< interrupt of GPIO, NMI*/ + ETS_GPIO_INTR_SOURCE2, /**< interrupt of GPIO, level*/ + ETS_GPIO_NMI_SOURCE2, /**< interrupt of GPIO, NMI*/ + ETS_DEDICATED_GPIO_INTR_SOURCE, /**< interrupt of dedicated GPIO, level*/ + ETS_FROM_CPU_INTR0_SOURCE, /**< interrupt0 generated from a CPU, level*/ /* Used for FreeRTOS */ + ETS_FROM_CPU_INTR1_SOURCE, /**< interrupt1 generated from a CPU, level*/ /* Used for FreeRTOS */ + ETS_FROM_CPU_INTR2_SOURCE, /**< interrupt2 generated from a CPU, level*/ + ETS_FROM_CPU_INTR3_SOURCE, /**< interrupt3 generated from a CPU, level*/ + + ETS_SPI1_INTR_SOURCE = 32, /**< interrupt of SPI1, level, SPI1 is for flash read/write, do not use this*/ + ETS_SPI2_INTR_SOURCE, /**< interrupt of SPI2, level*/ + ETS_SPI3_INTR_SOURCE, /**< interrupt of SPI3, level*/ + ETS_I2S0_INTR_SOURCE, /**< interrupt of I2S0, level*/ + ETS_UART0_INTR_SOURCE = 37, /**< interrupt of UART0, level*/ + ETS_UART1_INTR_SOURCE, /**< interrupt of UART1, level*/ + ETS_UART2_INTR_SOURCE, /**< interrupt of UART2, level*/ + ETS_SDIO_HOST_INTR_SOURCE, /**< interrupt of SD/SDIO/MMC HOST, level*/ + ETS_LEDC_INTR_SOURCE = 45, /**< interrupt of LED PWM, level*/ + ETS_EFUSE_INTR_SOURCE, /**< interrupt of efuse, level, not likely to use*/ + ETS_TWAI_INTR_SOURCE , /**< interrupt of twai, level*/ + + ETS_USB_INTR_SOURCE = 48, /**< interrupt of USB, level*/ + ETS_RTC_CORE_INTR_SOURCE, /**< interrupt of rtc core, level, include rtc watchdog*/ + ETS_RMT_INTR_SOURCE, /**< interrupt of remote controller, level*/ + ETS_PCNT_INTR_SOURCE, /**< interrupt of pluse count, level*/ + ETS_I2C_EXT0_INTR_SOURCE, /**< interrupt of I2C controller1, level*/ + ETS_I2C_EXT1_INTR_SOURCE, /**< interrupt of I2C controller0, level*/ + ETS_RSA_INTR_SOURCE, /**< interrupt of RSA accelerator, level*/ + ETS_SHA_INTR_SOURCE, /**< interrupt of SHA accelerator, level*/ + ETS_AES_INTR_SOURCE, /**< interrupt of AES accelerator, level*/ + ETS_SPI2_DMA_INTR_SOURCE, /**< interrupt of SPI2 DMA, level*/ + ETS_SPI3_DMA_INTR_SOURCE, /**< interrupt of SPI3 DMA, level*/ + ETS_WDT_INTR_SOURCE, /**< will be cancelled*/ + ETS_TIMER1_INTR_SOURCE, /**< will be cancelled*/ + ETS_TIMER2_INTR_SOURCE, /**< will be cancelled*/ + ETS_TG0_T0_EDGE_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, TIMER0, EDGE*/ + ETS_TG0_T1_EDGE_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, TIMER1, EDGE*/ + + ETS_TG0_WDT_EDGE_INTR_SOURCE = 64, /**< interrupt of TIMER_GROUP0, WATCH DOG, EDGE*/ + ETS_TG0_LACT_EDGE_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, LACT, EDGE*/ + ETS_TG1_T0_EDGE_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, TIMER0, EDGE*/ + ETS_TG1_T1_EDGE_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, TIMER1, EDGE*/ + ETS_TG1_WDT_EDGE_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, WATCHDOG, EDGE*/ + ETS_TG1_LACT_EDGE_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, LACT, EDGE*/ + ETS_CACHE_IA_INTR_SOURCE, /**< interrupt of Cache Invalied Access, LEVEL*/ + ETS_SYSTIMER_TARGET0_EDGE_INTR_SOURCE, /**< interrupt of system timer 0, EDGE*/ + ETS_SYSTIMER_TARGET1_EDGE_INTR_SOURCE, /**< interrupt of system timer 1, EDGE*/ + ETS_SYSTIMER_TARGET2_EDGE_INTR_SOURCE, /**< interrupt of system timer 2, EDGE*/ + ETS_ASSIST_DEBUG_INTR_SOURCE, /**< interrupt of Assist debug module, LEVEL*/ + ETS_PMS_PRO_IRAM0_ILG_INTR_SOURCE, /**< interrupt of illegal IRAM1 access, LEVEL*/ + ETS_PMS_PRO_DRAM0_ILG_INTR_SOURCE, /**< interrupt of illegal DRAM0 access, LEVEL*/ + ETS_PMS_PRO_DPORT_ILG_INTR_SOURCE, /**< interrupt of illegal DPORT access, LEVEL*/ + ETS_PMS_PRO_AHB_ILG_INTR_SOURCE, /**< interrupt of illegal AHB access, LEVEL*/ + ETS_PMS_PRO_CACHE_ILG_INTR_SOURCE, /**< interrupt of illegal CACHE access, LEVEL*/ + + ETS_PMS_DMA_APB_I_ILG_INTR_SOURCE = 80, /**< interrupt of illegal APB access, LEVEL*/ + ETS_PMS_DMA_RX_I_ILG_INTR_SOURCE, /**< interrupt of illegal DMA RX access, LEVEL*/ + ETS_PMS_DMA_TX_I_ILG_INTR_SOURCE, /**< interrupt of illegal DMA TX access, LEVEL*/ + ETS_SPI_MEM_REJECT_CACHE_INTR_SOURCE, /**< interrupt of SPI0 Cache access and SPI1 access rejected, LEVEL*/ + ETS_DMA_COPY_INTR_SOURCE, /**< interrupt of DMA copy, LEVEL*/ + ETS_SPI4_DMA_INTR_SOURCE, /**< interrupt of SPI4 DMA, LEVEL*/ + ETS_SPI4_INTR_SOURCE, /**< interrupt of SPI4, LEVEL*/ + ETS_ICACHE_PRELOAD_INTR_SOURCE, /**< interrupt of ICache perload operation, LEVEL*/ + ETS_DCACHE_PRELOAD_INTR_SOURCE, /**< interrupt of DCache preload operation, LEVEL*/ + ETS_APB_ADC_INTR_SOURCE, /**< interrupt of APB ADC, LEVEL*/ + ETS_CRYPTO_DMA_INTR_SOURCE, /**< interrupt of encrypted DMA, LEVEL*/ + ETS_CPU_PERI_ERROR_INTR_SOURCE, /**< interrupt of CPU peripherals error, LEVEL*/ + ETS_APB_PERI_ERROR_INTR_SOURCE, /**< interrupt of APB peripherals error, LEVEL*/ + ETS_DCACHE_SYNC_INTR_SOURCE, /**< interrupt of data cache sync done, LEVEL*/ + ETS_ICACHE_SYNC_INTR_SOURCE, /**< interrupt of instruction cache sync done, LEVEL*/ + ETS_MAX_INTR_SOURCE, /**< number of interrupt sources */ +} periph_interrput_t; + +extern const char * const esp_isr_names[ETS_MAX_INTR_SOURCE]; + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32s2/include/soc/periph_defs.h b/components/soc/esp32s2/include/soc/periph_defs.h index f0532bdbef..9616810f32 100644 --- a/components/soc/esp32s2/include/soc/periph_defs.h +++ b/components/soc/esp32s2/include/soc/periph_defs.h @@ -1,11 +1,13 @@ /* - * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ #pragma once +#include "soc/interrupts.h" + #ifdef __cplusplus extern "C" { #endif @@ -46,105 +48,6 @@ typedef enum { PERIPH_MODULE_MAX } periph_module_t; -typedef enum { - ETS_WIFI_MAC_INTR_SOURCE = 0, /**< interrupt of WiFi MAC, level*/ - ETS_WIFI_MAC_NMI_SOURCE, /**< interrupt of WiFi MAC, NMI, use if MAC have bug to fix in NMI*/ - ETS_WIFI_PWR_INTR_SOURCE, /**< */ - ETS_WIFI_BB_INTR_SOURCE, /**< interrupt of WiFi BB, level, we can do some calibartion*/ - ETS_BT_MAC_INTR_SOURCE, /**< will be cancelled*/ - ETS_BT_BB_INTR_SOURCE, /**< interrupt of BT BB, level*/ - ETS_BT_BB_NMI_SOURCE, /**< interrupt of BT BB, NMI, use if BB have bug to fix in NMI*/ - ETS_RWBT_INTR_SOURCE, /**< interrupt of RWBT, level*/ - ETS_RWBLE_INTR_SOURCE, /**< interrupt of RWBLE, level*/ - ETS_RWBT_NMI_SOURCE, /**< interrupt of RWBT, NMI, use if RWBT have bug to fix in NMI*/ - ETS_RWBLE_NMI_SOURCE, /**< interrupt of RWBLE, NMI, use if RWBT have bug to fix in NMI*/ - ETS_SLC0_INTR_SOURCE, /**< interrupt of SLC0, level*/ - ETS_SLC1_INTR_SOURCE, /**< interrupt of SLC1, level*/ - ETS_UHCI0_INTR_SOURCE, /**< interrupt of UHCI0, level*/ - ETS_UHCI1_INTR_SOURCE, /**< interrupt of UHCI1, level*/ - ETS_TG0_T0_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, TIMER0, level, we would like use EDGE for timer if permission*/ - - ETS_TG0_T1_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, TIMER1, level, we would like use EDGE for timer if permission*/ - ETS_TG0_WDT_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, WATCHDOG, level*/ - ETS_TG0_LACT_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, LACT, level*/ - ETS_TG1_T0_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, TIMER0, level, we would like use EDGE for timer if permission*/ - ETS_TG1_T1_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, TIMER1, level, we would like use EDGE for timer if permission*/ - ETS_TG1_WDT_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, WATCHDOG, level*/ - ETS_TG1_LACT_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, LACT, level*/ - ETS_GPIO_INTR_SOURCE, /**< interrupt of GPIO, level*/ - ETS_GPIO_NMI_SOURCE, /**< interrupt of GPIO, NMI*/ - ETS_GPIO_INTR_SOURCE2, /**< interrupt of GPIO, level*/ - ETS_GPIO_NMI_SOURCE2, /**< interrupt of GPIO, NMI*/ - ETS_DEDICATED_GPIO_INTR_SOURCE, /**< interrupt of dedicated GPIO, level*/ - ETS_FROM_CPU_INTR0_SOURCE, /**< interrupt0 generated from a CPU, level*/ /* Used for FreeRTOS */ - ETS_FROM_CPU_INTR1_SOURCE, /**< interrupt1 generated from a CPU, level*/ /* Used for FreeRTOS */ - ETS_FROM_CPU_INTR2_SOURCE, /**< interrupt2 generated from a CPU, level*/ - ETS_FROM_CPU_INTR3_SOURCE, /**< interrupt3 generated from a CPU, level*/ - - ETS_SPI1_INTR_SOURCE = 32, /**< interrupt of SPI1, level, SPI1 is for flash read/write, do not use this*/ - ETS_SPI2_INTR_SOURCE, /**< interrupt of SPI2, level*/ - ETS_SPI3_INTR_SOURCE, /**< interrupt of SPI3, level*/ - ETS_I2S0_INTR_SOURCE, /**< interrupt of I2S0, level*/ - ETS_UART0_INTR_SOURCE = 37, /**< interrupt of UART0, level*/ - ETS_UART1_INTR_SOURCE, /**< interrupt of UART1, level*/ - ETS_UART2_INTR_SOURCE, /**< interrupt of UART2, level*/ - ETS_SDIO_HOST_INTR_SOURCE, /**< interrupt of SD/SDIO/MMC HOST, level*/ - ETS_LEDC_INTR_SOURCE = 45, /**< interrupt of LED PWM, level*/ - ETS_EFUSE_INTR_SOURCE, /**< interrupt of efuse, level, not likely to use*/ - ETS_TWAI_INTR_SOURCE , /**< interrupt of twai, level*/ - - ETS_USB_INTR_SOURCE = 48, /**< interrupt of USB, level*/ - ETS_RTC_CORE_INTR_SOURCE, /**< interrupt of rtc core, level, include rtc watchdog*/ - ETS_RMT_INTR_SOURCE, /**< interrupt of remote controller, level*/ - ETS_PCNT_INTR_SOURCE, /**< interrupt of pluse count, level*/ - ETS_I2C_EXT0_INTR_SOURCE, /**< interrupt of I2C controller1, level*/ - ETS_I2C_EXT1_INTR_SOURCE, /**< interrupt of I2C controller0, level*/ - ETS_RSA_INTR_SOURCE, /**< interrupt of RSA accelerator, level*/ - ETS_SHA_INTR_SOURCE, /**< interrupt of SHA accelerator, level*/ - ETS_AES_INTR_SOURCE, /**< interrupt of AES accelerator, level*/ - ETS_SPI2_DMA_INTR_SOURCE, /**< interrupt of SPI2 DMA, level*/ - ETS_SPI3_DMA_INTR_SOURCE, /**< interrupt of SPI3 DMA, level*/ - ETS_WDT_INTR_SOURCE, /**< will be cancelled*/ - ETS_TIMER1_INTR_SOURCE, /**< will be cancelled*/ - ETS_TIMER2_INTR_SOURCE, /**< will be cancelled*/ - ETS_TG0_T0_EDGE_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, TIMER0, EDGE*/ - ETS_TG0_T1_EDGE_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, TIMER1, EDGE*/ - - ETS_TG0_WDT_EDGE_INTR_SOURCE = 64, /**< interrupt of TIMER_GROUP0, WATCH DOG, EDGE*/ - ETS_TG0_LACT_EDGE_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, LACT, EDGE*/ - ETS_TG1_T0_EDGE_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, TIMER0, EDGE*/ - ETS_TG1_T1_EDGE_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, TIMER1, EDGE*/ - ETS_TG1_WDT_EDGE_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, WATCHDOG, EDGE*/ - ETS_TG1_LACT_EDGE_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, LACT, EDGE*/ - ETS_CACHE_IA_INTR_SOURCE, /**< interrupt of Cache Invalied Access, LEVEL*/ - ETS_SYSTIMER_TARGET0_EDGE_INTR_SOURCE, /**< interrupt of system timer 0, EDGE*/ - ETS_SYSTIMER_TARGET1_EDGE_INTR_SOURCE, /**< interrupt of system timer 1, EDGE*/ - ETS_SYSTIMER_TARGET2_EDGE_INTR_SOURCE, /**< interrupt of system timer 2, EDGE*/ - ETS_ASSIST_DEBUG_INTR_SOURCE, /**< interrupt of Assist debug module, LEVEL*/ - ETS_PMS_PRO_IRAM0_ILG_INTR_SOURCE, /**< interrupt of illegal IRAM1 access, LEVEL*/ - ETS_PMS_PRO_DRAM0_ILG_INTR_SOURCE, /**< interrupt of illegal DRAM0 access, LEVEL*/ - ETS_PMS_PRO_DPORT_ILG_INTR_SOURCE, /**< interrupt of illegal DPORT access, LEVEL*/ - ETS_PMS_PRO_AHB_ILG_INTR_SOURCE, /**< interrupt of illegal AHB access, LEVEL*/ - ETS_PMS_PRO_CACHE_ILG_INTR_SOURCE, /**< interrupt of illegal CACHE access, LEVEL*/ - - ETS_PMS_DMA_APB_I_ILG_INTR_SOURCE = 80, /**< interrupt of illegal APB access, LEVEL*/ - ETS_PMS_DMA_RX_I_ILG_INTR_SOURCE, /**< interrupt of illegal DMA RX access, LEVEL*/ - ETS_PMS_DMA_TX_I_ILG_INTR_SOURCE, /**< interrupt of illegal DMA TX access, LEVEL*/ - ETS_SPI_MEM_REJECT_CACHE_INTR_SOURCE, /**< interrupt of SPI0 Cache access and SPI1 access rejected, LEVEL*/ - ETS_DMA_COPY_INTR_SOURCE, /**< interrupt of DMA copy, LEVEL*/ - ETS_SPI4_DMA_INTR_SOURCE, /**< interrupt of SPI4 DMA, LEVEL*/ - ETS_SPI4_INTR_SOURCE, /**< interrupt of SPI4, LEVEL*/ - ETS_ICACHE_PRELOAD_INTR_SOURCE, /**< interrupt of ICache perload operation, LEVEL*/ - ETS_DCACHE_PRELOAD_INTR_SOURCE, /**< interrupt of DCache preload operation, LEVEL*/ - ETS_APB_ADC_INTR_SOURCE, /**< interrupt of APB ADC, LEVEL*/ - ETS_CRYPTO_DMA_INTR_SOURCE, /**< interrupt of encrypted DMA, LEVEL*/ - ETS_CPU_PERI_ERROR_INTR_SOURCE, /**< interrupt of CPU peripherals error, LEVEL*/ - ETS_APB_PERI_ERROR_INTR_SOURCE, /**< interrupt of APB peripherals error, LEVEL*/ - ETS_DCACHE_SYNC_INTR_SOURCE, /**< interrupt of data cache sync done, LEVEL*/ - ETS_ICACHE_SYNC_INTR_SOURCE, /**< interrupt of instruction cache sync done, LEVEL*/ - ETS_MAX_INTR_SOURCE, /**< number of interrupt sources */ -} periph_interrput_t; - #ifdef __cplusplus } #endif diff --git a/components/soc/esp32s3/include/soc/interrupts.h b/components/soc/esp32s3/include/soc/interrupts.h new file mode 100644 index 0000000000..44d2923c2d --- /dev/null +++ b/components/soc/esp32s3/include/soc/interrupts.h @@ -0,0 +1,122 @@ +/* + * SPDX-FileCopyrightText: 2018-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once +#include + +#ifdef __cplusplus +extern "C" +{ +#endif + +//Interrupt hardware source table +//This table is decided by hardware, don't touch this. +typedef enum { + ETS_WIFI_MAC_INTR_SOURCE = 0, /**< interrupt of WiFi MAC, level*/ + ETS_WIFI_MAC_NMI_SOURCE, /**< interrupt of WiFi MAC, NMI, use if MAC have bug to fix in NMI*/ + ETS_WIFI_PWR_INTR_SOURCE, /**< */ + ETS_WIFI_BB_INTR_SOURCE, /**< interrupt of WiFi BB, level, we can do some calibartion*/ + ETS_BT_MAC_INTR_SOURCE, /**< will be cancelled*/ + ETS_BT_BB_INTR_SOURCE, /**< interrupt of BT BB, level*/ + ETS_BT_BB_NMI_SOURCE, /**< interrupt of BT BB, NMI, use if BB have bug to fix in NMI*/ + ETS_RWBT_INTR_SOURCE, /**< interrupt of RWBT, level*/ + ETS_RWBLE_INTR_SOURCE, /**< interrupt of RWBLE, level*/ + ETS_RWBT_NMI_SOURCE, /**< interrupt of RWBT, NMI, use if RWBT have bug to fix in NMI*/ + ETS_RWBLE_NMI_SOURCE, /**< interrupt of RWBLE, NMI, use if RWBT have bug to fix in NMI*/ + ETS_I2C_MASTER_SOURCE, /**< interrupt of I2C Master, level*/ + ETS_SLC0_INTR_SOURCE, /**< interrupt of SLC0, level*/ + ETS_SLC1_INTR_SOURCE, /**< interrupt of SLC1, level*/ + ETS_UHCI0_INTR_SOURCE, /**< interrupt of UHCI0, level*/ + ETS_UHCI1_INTR_SOURCE, /**< interrupt of UHCI1, level*/ + + ETS_GPIO_INTR_SOURCE = 16, /**< interrupt of GPIO, level*/ + ETS_GPIO_NMI_SOURCE, /**< interrupt of GPIO, NMI*/ + ETS_GPIO_INTR_SOURCE2, /**< interrupt of GPIO, level*/ + ETS_GPIO_NMI_SOURCE2, /**< interrupt of GPIO, NMI*/ + ETS_SPI1_INTR_SOURCE, /**< interrupt of SPI1, level, SPI1 is for flash read/write, do not use this*/ + ETS_SPI2_INTR_SOURCE, /**< interrupt of SPI2, level*/ + ETS_SPI3_INTR_SOURCE, /**< interrupt of SPI3, level*/ + ETS_LCD_CAM_INTR_SOURCE = 24, /**< interrupt of LCD camera, level*/ + ETS_I2S0_INTR_SOURCE, /**< interrupt of I2S0, level*/ + ETS_I2S1_INTR_SOURCE, /**< interrupt of I2S1, level*/ + ETS_UART0_INTR_SOURCE, /**< interrupt of UART0, level*/ + ETS_UART1_INTR_SOURCE, /**< interrupt of UART1, level*/ + ETS_UART2_INTR_SOURCE, /**< interrupt of UART2, level*/ + ETS_SDIO_HOST_INTR_SOURCE, /**< interrupt of SD/SDIO/MMC HOST, level*/ + ETS_PWM0_INTR_SOURCE, /**< interrupt of PWM0, level, Reserved*/ + ETS_PWM1_INTR_SOURCE, /**< interrupt of PWM1, level, Reserved*/ + ETS_LEDC_INTR_SOURCE = 35, /**< interrupt of LED PWM, level*/ + ETS_EFUSE_INTR_SOURCE, /**< interrupt of efuse, level, not likely to use*/ + ETS_TWAI_INTR_SOURCE, /**< interrupt of can, level*/ + ETS_USB_INTR_SOURCE, /**< interrupt of USB, level*/ + ETS_RTC_CORE_INTR_SOURCE, /**< interrupt of rtc core, level, include rtc watchdog*/ + ETS_RMT_INTR_SOURCE, /**< interrupt of remote controller, level*/ + ETS_PCNT_INTR_SOURCE, /**< interrupt of pluse count, level*/ + ETS_I2C_EXT0_INTR_SOURCE, /**< interrupt of I2C controller1, level*/ + ETS_I2C_EXT1_INTR_SOURCE, /**< interrupt of I2C controller0, level*/ + ETS_SPI2_DMA_INTR_SOURCE, /**< interrupt of SPI2 DMA, level*/ + ETS_SPI3_DMA_INTR_SOURCE, /**< interrupt of SPI3 DMA, level*/ + ETS_WDT_INTR_SOURCE = 47, /**< will be cancelled*/ + + ETS_TIMER1_INTR_SOURCE = 48, + ETS_TIMER2_INTR_SOURCE, + ETS_TG0_T0_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, TIMER0, EDGE*/ + ETS_TG0_T1_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, TIMER1, EDGE*/ + ETS_TG0_WDT_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, WATCH DOG, EDGE*/ + ETS_TG1_T0_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, TIMER0, EDGE*/ + ETS_TG1_T1_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, TIMER1, EDGE*/ + ETS_TG1_WDT_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, WATCHDOG, EDGE*/ + ETS_CACHE_IA_INTR_SOURCE, /**< interrupt of Cache Invalied Access, LEVEL*/ + ETS_SYSTIMER_TARGET0_EDGE_INTR_SOURCE, /**< interrupt of system timer 0, EDGE*/ + ETS_SYSTIMER_TARGET1_EDGE_INTR_SOURCE, /**< interrupt of system timer 1, EDGE*/ + ETS_SYSTIMER_TARGET2_EDGE_INTR_SOURCE, /**< interrupt of system timer 2, EDGE*/ + ETS_SPI_MEM_REJECT_CACHE_INTR_SOURCE, /**< interrupt of SPI0 Cache access and SPI1 access rejected, LEVEL*/ + ETS_DCACHE_PRELOAD0_INTR_SOURCE, /**< interrupt of DCache preload operation, LEVEL*/ + ETS_ICACHE_PRELOAD0_INTR_SOURCE, /**< interrupt of ICache perload operation, LEVEL*/ + ETS_DCACHE_SYNC0_INTR_SOURCE, /**< interrupt of data cache sync done, LEVEL*/ + ETS_ICACHE_SYNC0_INTR_SOURCE, /**< interrupt of instruction cache sync done, LEVEL*/ + ETS_APB_ADC_INTR_SOURCE, /**< interrupt of APB ADC, LEVEL*/ + ETS_DMA_IN_CH0_INTR_SOURCE, /**< interrupt of general DMA RX channel 0, LEVEL*/ + ETS_DMA_IN_CH1_INTR_SOURCE, /**< interrupt of general DMA RX channel 1, LEVEL*/ + ETS_DMA_IN_CH2_INTR_SOURCE, /**< interrupt of general DMA RX channel 2, LEVEL*/ + ETS_DMA_IN_CH3_INTR_SOURCE, /**< interrupt of general DMA RX channel 3, LEVEL*/ + ETS_DMA_IN_CH4_INTR_SOURCE, /**< interrupt of general DMA RX channel 4, LEVEL*/ + ETS_DMA_OUT_CH0_INTR_SOURCE, /**< interrupt of general DMA TX channel 0, LEVEL*/ + ETS_DMA_OUT_CH1_INTR_SOURCE, /**< interrupt of general DMA TX channel 1, LEVEL*/ + ETS_DMA_OUT_CH2_INTR_SOURCE, /**< interrupt of general DMA TX channel 2, LEVEL*/ + ETS_DMA_OUT_CH3_INTR_SOURCE, /**< interrupt of general DMA TX channel 3, LEVEL*/ + ETS_DMA_OUT_CH4_INTR_SOURCE, /**< interrupt of general DMA TX channel 4, LEVEL*/ + ETS_RSA_INTR_SOURCE, /**< interrupt of RSA accelerator, level*/ + ETS_AES_INTR_SOURCE, /**< interrupt of AES accelerator, level*/ + ETS_SHA_INTR_SOURCE, /**< interrupt of SHA accelerator, level*/ + ETS_FROM_CPU_INTR0_SOURCE, /**< interrupt0 generated from a CPU, level*/ /* Used for FreeRTOS */ + ETS_FROM_CPU_INTR1_SOURCE, /**< interrupt1 generated from a CPU, level*/ /* Used for FreeRTOS */ + ETS_FROM_CPU_INTR2_SOURCE, /**< interrupt2 generated from a CPU, level*/ /* Used for IPC_ISR */ + ETS_FROM_CPU_INTR3_SOURCE, /**< interrupt3 generated from a CPU, level*/ /* Used for IPC_ISR */ + ETS_ASSIST_DEBUG_INTR_SOURCE, /**< interrupt of Assist debug module, LEVEL*/ + ETS_DMA_APBPERI_PMS_INTR_SOURCE, + ETS_CORE0_IRAM0_PMS_INTR_SOURCE, + ETS_CORE0_DRAM0_PMS_INTR_SOURCE, + ETS_CORE0_PIF_PMS_INTR_SOURCE, + ETS_CORE0_PIF_PMS_SIZE_INTR_SOURCE, + ETS_CORE1_IRAM0_PMS_INTR_SOURCE, + ETS_CORE1_DRAM0_PMS_INTR_SOURCE, + ETS_CORE1_PIF_PMS_INTR_SOURCE, + ETS_CORE1_PIF_PMS_SIZE_INTR_SOURCE, + ETS_BACKUP_PMS_VIOLATE_INTR_SOURCE, + ETS_CACHE_CORE0_ACS_INTR_SOURCE, + ETS_CACHE_CORE1_ACS_INTR_SOURCE, + ETS_USB_SERIAL_JTAG_INTR_SOURCE, + ETS_PERI_BACKUP_INTR_SOURCE, + ETS_DMA_EXTMEM_REJECT_SOURCE, + ETS_MAX_INTR_SOURCE, /**< number of interrupt sources */ +} periph_interrput_t; + +extern const char * const esp_isr_names[ETS_MAX_INTR_SOURCE]; + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32s3/include/soc/periph_defs.h b/components/soc/esp32s3/include/soc/periph_defs.h index 0d16f7fda7..ca93c51cbe 100644 --- a/components/soc/esp32s3/include/soc/periph_defs.h +++ b/components/soc/esp32s3/include/soc/periph_defs.h @@ -1,11 +1,13 @@ /* - * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ #pragma once +#include "soc/interrupts.h" + #ifdef __cplusplus extern "C" { #endif @@ -55,107 +57,6 @@ typedef enum { PERIPH_MODULE_MAX } periph_module_t; -typedef enum { - ETS_WIFI_MAC_INTR_SOURCE = 0, /**< interrupt of WiFi MAC, level*/ - ETS_WIFI_MAC_NMI_SOURCE, /**< interrupt of WiFi MAC, NMI, use if MAC have bug to fix in NMI*/ - ETS_WIFI_PWR_INTR_SOURCE, /**< */ - ETS_WIFI_BB_INTR_SOURCE, /**< interrupt of WiFi BB, level, we can do some calibartion*/ - ETS_BT_MAC_INTR_SOURCE, /**< will be cancelled*/ - ETS_BT_BB_INTR_SOURCE, /**< interrupt of BT BB, level*/ - ETS_BT_BB_NMI_SOURCE, /**< interrupt of BT BB, NMI, use if BB have bug to fix in NMI*/ - ETS_RWBT_INTR_SOURCE, /**< interrupt of RWBT, level*/ - ETS_RWBLE_INTR_SOURCE, /**< interrupt of RWBLE, level*/ - ETS_RWBT_NMI_SOURCE, /**< interrupt of RWBT, NMI, use if RWBT have bug to fix in NMI*/ - ETS_RWBLE_NMI_SOURCE, /**< interrupt of RWBLE, NMI, use if RWBT have bug to fix in NMI*/ - ETS_I2C_MASTER_SOURCE, /**< interrupt of I2C Master, level*/ - ETS_SLC0_INTR_SOURCE, /**< interrupt of SLC0, level*/ - ETS_SLC1_INTR_SOURCE, /**< interrupt of SLC1, level*/ - ETS_UHCI0_INTR_SOURCE, /**< interrupt of UHCI0, level*/ - ETS_UHCI1_INTR_SOURCE, /**< interrupt of UHCI1, level*/ - - ETS_GPIO_INTR_SOURCE = 16, /**< interrupt of GPIO, level*/ - ETS_GPIO_NMI_SOURCE, /**< interrupt of GPIO, NMI*/ - ETS_GPIO_INTR_SOURCE2, /**< interrupt of GPIO, level*/ - ETS_GPIO_NMI_SOURCE2, /**< interrupt of GPIO, NMI*/ - ETS_SPI1_INTR_SOURCE, /**< interrupt of SPI1, level, SPI1 is for flash read/write, do not use this*/ - ETS_SPI2_INTR_SOURCE, /**< interrupt of SPI2, level*/ - ETS_SPI3_INTR_SOURCE, /**< interrupt of SPI3, level*/ - ETS_LCD_CAM_INTR_SOURCE = 24, /**< interrupt of LCD camera, level*/ - ETS_I2S0_INTR_SOURCE, /**< interrupt of I2S0, level*/ - ETS_I2S1_INTR_SOURCE, /**< interrupt of I2S1, level*/ - ETS_UART0_INTR_SOURCE, /**< interrupt of UART0, level*/ - ETS_UART1_INTR_SOURCE, /**< interrupt of UART1, level*/ - ETS_UART2_INTR_SOURCE, /**< interrupt of UART2, level*/ - ETS_SDIO_HOST_INTR_SOURCE, /**< interrupt of SD/SDIO/MMC HOST, level*/ - ETS_PWM0_INTR_SOURCE, /**< interrupt of PWM0, level, Reserved*/ - ETS_PWM1_INTR_SOURCE, /**< interrupt of PWM1, level, Reserved*/ - ETS_LEDC_INTR_SOURCE = 35, /**< interrupt of LED PWM, level*/ - ETS_EFUSE_INTR_SOURCE, /**< interrupt of efuse, level, not likely to use*/ - ETS_TWAI_INTR_SOURCE, /**< interrupt of can, level*/ - ETS_USB_INTR_SOURCE, /**< interrupt of USB, level*/ - ETS_RTC_CORE_INTR_SOURCE, /**< interrupt of rtc core, level, include rtc watchdog*/ - ETS_RMT_INTR_SOURCE, /**< interrupt of remote controller, level*/ - ETS_PCNT_INTR_SOURCE, /**< interrupt of pluse count, level*/ - ETS_I2C_EXT0_INTR_SOURCE, /**< interrupt of I2C controller1, level*/ - ETS_I2C_EXT1_INTR_SOURCE, /**< interrupt of I2C controller0, level*/ - ETS_SPI2_DMA_INTR_SOURCE, /**< interrupt of SPI2 DMA, level*/ - ETS_SPI3_DMA_INTR_SOURCE, /**< interrupt of SPI3 DMA, level*/ - ETS_WDT_INTR_SOURCE = 47, /**< will be cancelled*/ - - ETS_TIMER1_INTR_SOURCE = 48, - ETS_TIMER2_INTR_SOURCE, - ETS_TG0_T0_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, TIMER0, EDGE*/ - ETS_TG0_T1_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, TIMER1, EDGE*/ - ETS_TG0_WDT_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, WATCH DOG, EDGE*/ - ETS_TG1_T0_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, TIMER0, EDGE*/ - ETS_TG1_T1_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, TIMER1, EDGE*/ - ETS_TG1_WDT_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, WATCHDOG, EDGE*/ - ETS_CACHE_IA_INTR_SOURCE, /**< interrupt of Cache Invalied Access, LEVEL*/ - ETS_SYSTIMER_TARGET0_EDGE_INTR_SOURCE, /**< interrupt of system timer 0, EDGE*/ - ETS_SYSTIMER_TARGET1_EDGE_INTR_SOURCE, /**< interrupt of system timer 1, EDGE*/ - ETS_SYSTIMER_TARGET2_EDGE_INTR_SOURCE, /**< interrupt of system timer 2, EDGE*/ - ETS_SPI_MEM_REJECT_CACHE_INTR_SOURCE, /**< interrupt of SPI0 Cache access and SPI1 access rejected, LEVEL*/ - ETS_DCACHE_PRELOAD0_INTR_SOURCE, /**< interrupt of DCache preload operation, LEVEL*/ - ETS_ICACHE_PRELOAD0_INTR_SOURCE, /**< interrupt of ICache perload operation, LEVEL*/ - ETS_DCACHE_SYNC0_INTR_SOURCE, /**< interrupt of data cache sync done, LEVEL*/ - ETS_ICACHE_SYNC0_INTR_SOURCE, /**< interrupt of instruction cache sync done, LEVEL*/ - ETS_APB_ADC_INTR_SOURCE, /**< interrupt of APB ADC, LEVEL*/ - ETS_DMA_IN_CH0_INTR_SOURCE, /**< interrupt of general DMA RX channel 0, LEVEL*/ - ETS_DMA_IN_CH1_INTR_SOURCE, /**< interrupt of general DMA RX channel 1, LEVEL*/ - ETS_DMA_IN_CH2_INTR_SOURCE, /**< interrupt of general DMA RX channel 2, LEVEL*/ - ETS_DMA_IN_CH3_INTR_SOURCE, /**< interrupt of general DMA RX channel 3, LEVEL*/ - ETS_DMA_IN_CH4_INTR_SOURCE, /**< interrupt of general DMA RX channel 4, LEVEL*/ - ETS_DMA_OUT_CH0_INTR_SOURCE, /**< interrupt of general DMA TX channel 0, LEVEL*/ - ETS_DMA_OUT_CH1_INTR_SOURCE, /**< interrupt of general DMA TX channel 1, LEVEL*/ - ETS_DMA_OUT_CH2_INTR_SOURCE, /**< interrupt of general DMA TX channel 2, LEVEL*/ - ETS_DMA_OUT_CH3_INTR_SOURCE, /**< interrupt of general DMA TX channel 3, LEVEL*/ - ETS_DMA_OUT_CH4_INTR_SOURCE, /**< interrupt of general DMA TX channel 4, LEVEL*/ - ETS_RSA_INTR_SOURCE, /**< interrupt of RSA accelerator, level*/ - ETS_AES_INTR_SOURCE, /**< interrupt of AES accelerator, level*/ - ETS_SHA_INTR_SOURCE, /**< interrupt of SHA accelerator, level*/ - ETS_FROM_CPU_INTR0_SOURCE, /**< interrupt0 generated from a CPU, level*/ /* Used for FreeRTOS */ - ETS_FROM_CPU_INTR1_SOURCE, /**< interrupt1 generated from a CPU, level*/ /* Used for FreeRTOS */ - ETS_FROM_CPU_INTR2_SOURCE, /**< interrupt2 generated from a CPU, level*/ /* Used for IPC_ISR */ - ETS_FROM_CPU_INTR3_SOURCE, /**< interrupt3 generated from a CPU, level*/ /* Used for IPC_ISR */ - ETS_ASSIST_DEBUG_INTR_SOURCE, /**< interrupt of Assist debug module, LEVEL*/ - ETS_DMA_APBPERI_PMS_INTR_SOURCE, - ETS_CORE0_IRAM0_PMS_INTR_SOURCE, - ETS_CORE0_DRAM0_PMS_INTR_SOURCE, - ETS_CORE0_PIF_PMS_INTR_SOURCE, - ETS_CORE0_PIF_PMS_SIZE_INTR_SOURCE, - ETS_CORE1_IRAM0_PMS_INTR_SOURCE, - ETS_CORE1_DRAM0_PMS_INTR_SOURCE, - ETS_CORE1_PIF_PMS_INTR_SOURCE, - ETS_CORE1_PIF_PMS_SIZE_INTR_SOURCE, - ETS_BACKUP_PMS_VIOLATE_INTR_SOURCE, - ETS_CACHE_CORE0_ACS_INTR_SOURCE, - ETS_CACHE_CORE1_ACS_INTR_SOURCE, - ETS_USB_SERIAL_JTAG_INTR_SOURCE, - ETS_PERI_BACKUP_INTR_SOURCE, - ETS_DMA_EXTMEM_REJECT_SOURCE, - ETS_MAX_INTR_SOURCE, /**< number of interrupt sources */ -} periph_interrput_t; - #ifdef __cplusplus } #endif diff --git a/components/soc/include/soc/interrupts.h b/components/soc/include/soc/interrupts.h deleted file mode 100644 index cb2527eeb8..0000000000 --- a/components/soc/include/soc/interrupts.h +++ /dev/null @@ -1,29 +0,0 @@ -// Copyright 2018 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at - -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - -#pragma once -#include "stdint.h" -#include "soc/soc.h" -#include "soc/periph_defs.h" - -#ifdef __cplusplus -extern "C" -{ -#endif - -extern const char * const esp_isr_names[ETS_MAX_INTR_SOURCE]; - -#ifdef __cplusplus -} -#endif diff --git a/tools/ci/check_copyright_ignore.txt b/tools/ci/check_copyright_ignore.txt index ae5ef72d2c..dffcfec2c9 100644 --- a/tools/ci/check_copyright_ignore.txt +++ b/tools/ci/check_copyright_ignore.txt @@ -914,7 +914,6 @@ components/soc/include/soc/dedic_gpio_periph.h components/soc/include/soc/emac_periph.h components/soc/include/soc/gpio_periph.h components/soc/include/soc/i2c_periph.h -components/soc/include/soc/interrupts.h components/soc/include/soc/ledc_periph.h components/soc/lldesc.c components/soc/soc_include_legacy_warn.c