forked from espressif/esp-idf
change(esp_hw_support): only do mpll disable in lightsleep process
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@@ -368,6 +368,7 @@ TCM_IRAM_ATTR uint32_t pmu_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt,
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// the return process, which results in dirty cachelines in L1 Cache again.
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pmu_sleep_cache_sync_items(SMMU_GID_DEFAULT, CACHE_SYNC_WRITEBACK, CACHE_MAP_L1_DCACHE, 0, 0);
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if (!dslp) {
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#if CONFIG_SPIRAM
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psram_ctrlr_ll_wait_all_transaction_done();
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#endif
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@@ -386,6 +387,7 @@ TCM_IRAM_ATTR uint32_t pmu_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt,
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#endif
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rtc_clk_mpll_disable();
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}
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}
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#if CONFIG_SPIRAM && CONFIG_ESP_LDO_RESERVE_PSRAM
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@@ -438,7 +440,7 @@ TCM_IRAM_ATTR bool pmu_sleep_finish(bool dslp)
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pmu_ll_imm_set_pad_slp_sel(PMU_instance()->hal->dev, false);
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if (s_mpll_freq_mhz_before_sleep) {
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if (s_mpll_freq_mhz_before_sleep && !dslp) {
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rtc_clk_mpll_enable();
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rtc_clk_mpll_configure(clk_hal_xtal_get_freq_mhz(), s_mpll_freq_mhz_before_sleep);
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#if CONFIG_SPIRAM
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