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feat(spi_master): p4 document update

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This commit is contained in:
wanlei
2023-08-31 20:48:34 +08:00
parent eb75aa462e
commit fc20b96a45
3 changed files with 81 additions and 85 deletions
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2
docs/docs_not_updated/esp32p4.txt
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@@ -117,7 +117,6 @@ api-reference/peripherals/ana_cmpr.rst
api-reference/peripherals/secure_element.rst api-reference/peripherals/secure_element.rst
api-reference/peripherals/ledc.rst api-reference/peripherals/ledc.rst
api-reference/peripherals/temp_sensor.rst api-reference/peripherals/temp_sensor.rst
api-reference/peripherals/spi_features.rst
api-reference/peripherals/sdio_slave.rst api-reference/peripherals/sdio_slave.rst
api-reference/peripherals/clk_tree.rst api-reference/peripherals/clk_tree.rst
api-reference/peripherals/spi_flash/xip_from_psram.inc api-reference/peripherals/spi_flash/xip_from_psram.inc
@@ -136,7 +135,6 @@ api-reference/peripherals/ds.rst
api-reference/peripherals/i2c.rst api-reference/peripherals/i2c.rst
api-reference/peripherals/dedic_gpio.rst api-reference/peripherals/dedic_gpio.rst
api-reference/peripherals/sd_pullup_requirements.rst api-reference/peripherals/sd_pullup_requirements.rst
api-reference/peripherals/spi_master.rst
api-reference/peripherals/index.rst api-reference/peripherals/index.rst
api-reference/peripherals/sdmmc_host.rst api-reference/peripherals/sdmmc_host.rst
api-reference/peripherals/uart.rst api-reference/peripherals/uart.rst

69
docs/en/api-reference/peripherals/spi_master.rst
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@@ -182,28 +182,28 @@ Supported line modes for {IDF_TARGET_NAME} are listed as follows, to make use of
- 1 - 1
- 1 - 1
- 2 - 2
- {SPI_TRANS_MODE_DIO} - SPI_TRANS_MODE_DIO
- {SPICOMMON_BUSFLAG_DUAL} - SPICOMMON_BUSFLAG_DUAL
* - Dual I/O * - Dual I/O
- 1 - 1
- 2 - 2
- 2 - 2
- * {SPI_TRANS_MODE_DIO} - SPI_TRANS_MODE_DIO
* {SPI_TRANS_MULTILINE_ADDR} SPI_TRANS_MULTILINE_ADDR
- - SPICOMMON_BUSFLAG_DUAL
* - Quad Output * - Quad Output
- 1 - 1
- 1 - 1
- 4 - 4
- {SPI_TRANS_MODE_QIO} - SPI_TRANS_MODE_QIO
- {SPICOMMON_BUSFLAG_QUAD} - SPICOMMON_BUSFLAG_QUAD
* - Quad I/O * - Quad I/O
- 1 - 1
- 4 - 4
- 4 - 4
- * {SPI_TRANS_MODE_QIO} - SPI_TRANS_MODE_QIO
* {SPI_TRANS_MULTILINE_ADDR} SPI_TRANS_MULTILINE_ADDR
- {SPICOMMON_BUSFLAG_QUAD} - SPICOMMON_BUSFLAG_QUAD
.. only:: SOC_SPI_SUPPORT_OCT .. only:: SOC_SPI_SUPPORT_OCT
@@ -227,42 +227,42 @@ Supported line modes for {IDF_TARGET_NAME} are listed as follows, to make use of
- 1 - 1
- 1 - 1
- 2 - 2
- {SPI_TRANS_MODE_DIO} - SPI_TRANS_MODE_DIO
- {SPICOMMON_BUSFLAG_DUAL} - SPICOMMON_BUSFLAG_DUAL
* - Dual I/O * - Dual I/O
- 1 - 1
- 2 - 2
- 2 - 2
- * {SPI_TRANS_MODE_DIO} - SPI_TRANS_MODE_DIO
* {SPI_TRANS_MULTILINE_ADDR} SPI_TRANS_MULTILINE_ADDR
- - SPICOMMON_BUSFLAG_DUAL
* - Quad Output * - Quad Output
- 1 - 1
- 1 - 1
- 4 - 4
- {SPI_TRANS_MODE_QIO} - SPI_TRANS_MODE_QIO
- {SPICOMMON_BUSFLAG_QUAD} - SPICOMMON_BUSFLAG_QUAD
* - Quad I/O * - Quad I/O
- 1 - 1
- 4 - 4
- 4 - 4
- * {SPI_TRANS_MODE_QIO} - SPI_TRANS_MODE_QIO
* {SPI_TRANS_MULTILINE_ADDR} SPI_TRANS_MULTILINE_ADDR
- {SPICOMMON_BUSFLAG_QUAD} - SPICOMMON_BUSFLAG_QUAD
* - Octal Output * - Octal Output
- 1 - 1
- 1 - 1
- 8 - 8
- {SPI_TRANS_MODE_OCT} - SPI_TRANS_MODE_OCT
- {SPICOMMON_BUSFLAG_OCTAL} - SPICOMMON_BUSFLAG_OCTAL
* - OPI * - OPI
- 8 - 8
- 8 - 8
- 8 - 8
- * {SPI_TRANS_MODE_OCT} - SPI_TRANS_MODE_OCT
* {SPI_TRANS_MULTILINE_ADDR} SPI_TRANS_MULTILINE_ADDR
* {SPI_TRANS_MULTILINE_CMD} SPI_TRANS_MULTILINE_CMD
- {SPICOMMON_BUSFLAG_OCTAL} - SPICOMMON_BUSFLAG_OCTAL
Command and Address Phases Command and Address Phases
^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^
@@ -292,7 +292,7 @@ If using more than one data line to transmit, please set ``SPI_DEVICE_HALFDUPLEX
Half-duplex transactions with both Read and Write phases are not supported when using DMA. For details and workarounds, see :ref:`spi_known_issues`. Half-duplex transactions with both Read and Write phases are not supported when using DMA. For details and workarounds, see :ref:`spi_known_issues`.
.. only:: esp32s3 or esp32c3 or esp32c2 or esp32c6 or esp32h2 .. only:: not SOC_SPI_HD_BOTH_INOUT_SUPPORTED
.. note:: .. note::
@@ -473,12 +473,12 @@ GPIO Matrix and IO_MUX
.. only:: not esp32 .. only:: not esp32
{IDF_TARGET_SPI2_IOMUX_PIN_CS:default="N/A", esp32s2="10", esp32s3="10", esp32c2="10", esp32c3="10", esp32c6="16", esp32h2="1"} {IDF_TARGET_SPI2_IOMUX_PIN_CS:default="N/A", esp32s2="10", esp32s3="10", esp32c2="10", esp32c3="10", esp32c6="16", esp32h2="1", esp32p4="7"}
{IDF_TARGET_SPI2_IOMUX_PIN_CLK:default="N/A", esp32s2="12", esp32s3="12", esp32c2="6", esp32c3="6", esp32c6="6", esp32h2="4"} {IDF_TARGET_SPI2_IOMUX_PIN_CLK:default="N/A", esp32s2="12", esp32s3="12", esp32c2="6", esp32c3="6", esp32c6="6", esp32h2="4", esp32p4="9"}
{IDF_TARGET_SPI2_IOMUX_PIN_MOSI:default="N/A", esp32s2="11" esp32s3="11", esp32c2="7" esp32c3="7", esp32c6="7", esp32h2="5"} {IDF_TARGET_SPI2_IOMUX_PIN_MOSI:default="N/A", esp32s2="11" esp32s3="11", esp32c2="7" esp32c3="7", esp32c6="7", esp32h2="5", esp32p4="8"}
{IDF_TARGET_SPI2_IOMUX_PIN_MISO:default="N/A", esp32s2="13" esp32s3="13", esp32c2="2" esp32c3="2", esp32c6="2", esp32h2="0"} {IDF_TARGET_SPI2_IOMUX_PIN_MISO:default="N/A", esp32s2="13" esp32s3="13", esp32c2="2" esp32c3="2", esp32c6="2", esp32h2="0", esp32p4="10"}
{IDF_TARGET_SPI2_IOMUX_PIN_HD:default="N/A", esp32s2="9" esp32s3="9", esp32c2="4" esp32c3="4", esp32c6="4", esp32h2="3"} {IDF_TARGET_SPI2_IOMUX_PIN_HD:default="N/A", esp32s2="9" esp32s3="9", esp32c2="4" esp32c3="4", esp32c6="4", esp32h2="3", esp32p4="6"}
{IDF_TARGET_SPI2_IOMUX_PIN_WP:default="N/A", esp32s2="14" esp32s3="14", esp32c2="5" esp32c3="5", esp32c6="5", esp32h2="2"} {IDF_TARGET_SPI2_IOMUX_PIN_WP:default="N/A", esp32s2="14" esp32s3="14", esp32c2="5" esp32c3="5", esp32c6="5", esp32h2="2", esp32p4="11"}
Most of the chip's peripheral signals have a direct connection to their dedicated IO_MUX pins. However, the signals can also be routed to any other available pins using the less direct GPIO matrix. If at least one signal is routed through the GPIO matrix, then all signals will be routed through it. Most of the chip's peripheral signals have a direct connection to their dedicated IO_MUX pins. However, the signals can also be routed to any other available pins using the less direct GPIO matrix. If at least one signal is routed through the GPIO matrix, then all signals will be routed through it.
@@ -772,8 +772,6 @@ Please note that the ISR is disabled during flash operation by default. To keep
- 8.89 - 8.89
.. only:: esp32
.. _spi_known_issues: .. _spi_known_issues:
Known Issues Known Issues
@@ -802,6 +800,7 @@ Application Example
The code example for using the SPI master half duplex mode to read/write an AT93C46D EEPROM (8-bit mode) can be found in the :example:`peripherals/spi_master/hd_eeprom` directory of ESP-IDF examples. The code example for using the SPI master half duplex mode to read/write an AT93C46D EEPROM (8-bit mode) can be found in the :example:`peripherals/spi_master/hd_eeprom` directory of ESP-IDF examples.
The code example for using the SPI master full duplex mode to drive a SPI_LCD (e.g. ST7789V or ILI9341) can be found in the :example:`peripherals/spi_master/lcd` directory of ESP-IDF examples.
API Reference - SPI Common API Reference - SPI Common
-------------------------- --------------------------

69
docs/zh_CN/api-reference/peripherals/spi_master.rst
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@@ -182,28 +182,28 @@ SPI 总线传输事务由五个阶段构成，详见下表（任意阶段均可
- 1 - 1
- 1 - 1
- 2 - 2
- {SPI_TRANS_MODE_DIO} - SPI_TRANS_MODE_DIO
- {SPICOMMON_BUSFLAG_DUAL} - SPICOMMON_BUSFLAG_DUAL
* - 双线 I/O 模式 * - 双线 I/O 模式
- 1 - 1
- 2 - 2
- 2 - 2
- * {SPI_TRANS_MODE_DIO} - SPI_TRANS_MODE_DIO
* {SPI_TRANS_MULTILINE_ADDR} SPI_TRANS_MULTILINE_ADDR
- - SPICOMMON_BUSFLAG_DUAL
* - 四线输出模式 * - 四线输出模式
- 1 - 1
- 1 - 1
- 4 - 4
- {SPI_TRANS_MODE_QIO} - SPI_TRANS_MODE_QIO
- {SPICOMMON_BUSFLAG_QUAD} - SPICOMMON_BUSFLAG_QUAD
* - 四线 I/O 模式 * - 四线 I/O 模式
- 1 - 1
- 4 - 4
- 4 - 4
- * {SPI_TRANS_MODE_QIO} - SPI_TRANS_MODE_QIO
* {SPI_TRANS_MULTILINE_ADDR} SPI_TRANS_MULTILINE_ADDR
- {SPICOMMON_BUSFLAG_QUAD} - SPICOMMON_BUSFLAG_QUAD
.. only:: SOC_SPI_SUPPORT_OCT .. only:: SOC_SPI_SUPPORT_OCT
@@ -227,42 +227,42 @@ SPI 总线传输事务由五个阶段构成，详见下表（任意阶段均可
- 1 - 1
- 1 - 1
- 2 - 2
- {SPI_TRANS_MODE_DIO} - SPI_TRANS_MODE_DIO
- {SPICOMMON_BUSFLAG_DUAL} - SPICOMMON_BUSFLAG_DUAL
* - 双线 I/O 模式 * - 双线 I/O 模式
- 1 - 1
- 2 - 2
- 2 - 2
- * {SPI_TRANS_MODE_DIO} - SPI_TRANS_MODE_DIO
* {SPI_TRANS_MULTILINE_ADDR} SPI_TRANS_MULTILINE_ADDR
- - SPICOMMON_BUSFLAG_DUAL
* - 四线输出模式 * - 四线输出模式
- 1 - 1
- 1 - 1
- 4 - 4
- {SPI_TRANS_MODE_QIO} - SPI_TRANS_MODE_QIO
- {SPICOMMON_BUSFLAG_QUAD} - SPICOMMON_BUSFLAG_QUAD
* - 四线 I/O 模式 * - 四线 I/O 模式
- 1 - 1
- 4 - 4
- 4 - 4
- * {SPI_TRANS_MODE_QIO} - SPI_TRANS_MODE_QIO
* {SPI_TRANS_MULTILINE_ADDR} SPI_TRANS_MULTILINE_ADDR
- {SPICOMMON_BUSFLAG_QUAD} - SPICOMMON_BUSFLAG_QUAD
* - 八线输出模式 * - 八线输出模式
- 1 - 1
- 1 - 1
- 8 - 8
- {SPI_TRANS_MODE_OCT} - SPI_TRANS_MODE_OCT
- {SPICOMMON_BUSFLAG_OCTAL} - SPICOMMON_BUSFLAG_OCTAL
* - OPI 模式 * - OPI 模式
- 8 - 8
- 8 - 8
- 8 - 8
- * {SPI_TRANS_MODE_OCT} - SPI_TRANS_MODE_OCT
* {SPI_TRANS_MULTILINE_ADDR} SPI_TRANS_MULTILINE_ADDR
* {SPI_TRANS_MULTILINE_CMD} SPI_TRANS_MULTILINE_CMD
- {SPICOMMON_BUSFLAG_OCTAL} - SPICOMMON_BUSFLAG_OCTAL
命令阶段和地址阶段 命令阶段和地址阶段
^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^
@@ -292,7 +292,7 @@ SPI 总线传输事务由五个阶段构成，详见下表（任意阶段均可
当启用 DMA 时，不支持同时具有读取阶段和写入阶段的半双工传输事务。有关细节和解决方法，请参阅 :ref:`spi_known_issues`。 当启用 DMA 时，不支持同时具有读取阶段和写入阶段的半双工传输事务。有关细节和解决方法，请参阅 :ref:`spi_known_issues`。
.. only:: esp32s3 or esp32c3 or esp32c2 or esp32c6 or esp32h2 .. only:: not SOC_SPI_HD_BOTH_INOUT_SUPPORTED
.. note:: .. note::
@@ -473,12 +473,12 @@ GPIO 矩阵与 IO_MUX 管脚
.. only:: not esp32 .. only:: not esp32
{IDF_TARGET_SPI2_IOMUX_PIN_CS:default="N/A", esp32s2="10", esp32s3="10", esp32c2="10", esp32c3="10", esp32c6="16", esp32h2="1"} {IDF_TARGET_SPI2_IOMUX_PIN_CS:default="N/A", esp32s2="10", esp32s3="10", esp32c2="10", esp32c3="10", esp32c6="16", esp32h2="1", esp32p4="7"}
{IDF_TARGET_SPI2_IOMUX_PIN_CLK:default="N/A", esp32s2="12", esp32s3="12", esp32c2="6", esp32c3="6", esp32c6="6", esp32h2="4"} {IDF_TARGET_SPI2_IOMUX_PIN_CLK:default="N/A", esp32s2="12", esp32s3="12", esp32c2="6", esp32c3="6", esp32c6="6", esp32h2="4", esp32p4="9"}
{IDF_TARGET_SPI2_IOMUX_PIN_MOSI:default="N/A", esp32s2="11" esp32s3="11", esp32c2="7" esp32c3="7", esp32c6="7", esp32h2="5"} {IDF_TARGET_SPI2_IOMUX_PIN_MOSI:default="N/A", esp32s2="11" esp32s3="11", esp32c2="7" esp32c3="7", esp32c6="7", esp32h2="5", esp32p4="8"}
{IDF_TARGET_SPI2_IOMUX_PIN_MISO:default="N/A", esp32s2="13" esp32s3="13", esp32c2="2" esp32c3="2", esp32c6="2", esp32h2="0"} {IDF_TARGET_SPI2_IOMUX_PIN_MISO:default="N/A", esp32s2="13" esp32s3="13", esp32c2="2" esp32c3="2", esp32c6="2", esp32h2="0", esp32p4="10"}
{IDF_TARGET_SPI2_IOMUX_PIN_HD:default="N/A", esp32s2="9" esp32s3="9", esp32c2="4" esp32c3="4", esp32c6="4", esp32h2="3"} {IDF_TARGET_SPI2_IOMUX_PIN_HD:default="N/A", esp32s2="9" esp32s3="9", esp32c2="4" esp32c3="4", esp32c6="4", esp32h2="3", esp32p4="6"}
{IDF_TARGET_SPI2_IOMUX_PIN_WP:default="N/A", esp32s2="14" esp32s3="14", esp32c2="5" esp32c3="5", esp32c6="5", esp32h2="2"} {IDF_TARGET_SPI2_IOMUX_PIN_WP:default="N/A", esp32s2="14" esp32s3="14", esp32c2="5" esp32c3="5", esp32c6="5", esp32h2="2", esp32p4="11"}
芯片的大多数外围信号都与之专用的 IO_MUX 管脚连接，但这些信号也可以通过较不直接的 GPIO 矩阵路由到任何其他可用的管脚。只要有一个信号是通过 GPIO 矩阵路由的，那么所有的信号都将通过它路由。 芯片的大多数外围信号都与之专用的 IO_MUX 管脚连接，但这些信号也可以通过较不直接的 GPIO 矩阵路由到任何其他可用的管脚。只要有一个信号是通过 GPIO 矩阵路由的，那么所有的信号都将通过它路由。
@@ -772,8 +772,6 @@ GPSPI 外设的时钟源可以通过设置 :cpp:member:`spi_device_handle_t::cfg
- 8.89 - 8.89
.. only:: esp32
.. _spi_known_issues: .. _spi_known_issues:
已知问题 已知问题
@@ -802,6 +800,7 @@ GPSPI 外设的时钟源可以通过设置 :cpp:member:`spi_device_handle_t::cfg
查看使用 SPI 主机驱动程序在半双工模式下读取/写入 AT93C46D EEPROM（8 位模式）的示例代码，请前往 ESP-IDF 示例的 :example:`peripherals/spi_master/hd_eeprom` 目录。 查看使用 SPI 主机驱动程序在半双工模式下读取/写入 AT93C46D EEPROM（8 位模式）的示例代码，请前往 ESP-IDF 示例的 :example:`peripherals/spi_master/hd_eeprom` 目录。
查看使用 SPI 主机驱动程序在全双工模式下驱动 LCD 屏幕（如 ST7789V 或 ILI9341）的示例代码，请前往 ESP-IDF 示例的 :example:`peripherals/spi_master/lcd` 目录。
API 参考 - SPI Common API 参考 - SPI Common
-------------------------- --------------------------