forked from espressif/esp-idf
refactor(esp_mm): reformat code with astyle_py 2
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@@ -35,7 +35,6 @@ extern "C" {
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* - A Slot is the vaddr range between 2 blocks.
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*/
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/**
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* MMAP flags
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*/
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@@ -53,7 +53,6 @@ void cache_register_writeback(cache_driver_t *func);
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*/
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void cache_sync(void);
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#ifdef __cplusplus
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}
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#endif
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@@ -58,7 +58,6 @@ esp_err_t esp_cache_aligned_malloc(size_t size, uint32_t flags, void **out_ptr,
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*/
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esp_err_t esp_cache_aligned_calloc(size_t n, size_t size, uint32_t flags, void **out_ptr, size_t *actual_size);
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#ifdef __cplusplus
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}
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#endif
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@@ -14,7 +14,6 @@
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extern "C" {
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#endif
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/**
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* Memory Mapping Private APIs for MMU supported memory
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*/
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@@ -52,7 +51,6 @@ esp_err_t esp_mmu_map_reserve_block_with_caps(size_t size, mmu_mem_caps_t caps,
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*/
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esp_err_t esp_mmu_map_dump_mapped_blocks_private(void);
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#ifdef __cplusplus
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}
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#endif
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@@ -14,7 +14,6 @@
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extern "C" {
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#endif
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/**
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* Set addr space dirty
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*
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@@ -61,6 +61,5 @@ void app_main(void)
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printf("| |___/\\__/ / | | | | || | | | | | | |___/\\__/ / | |\r\n");
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printf("\\____/\\____/\\_| \\_| |_/\\_| |_/ \\_/ \\____/\\____/ \\_/\r\n");
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unity_run_menu();
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}
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@@ -30,7 +30,6 @@ const static char *TAG = "CACHE_TEST";
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#define TEST_NUM 10
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#define TEST_BUF {0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, 0x9}
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#define TEST_OFFSET 0x100000
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#if CONFIG_IDF_TARGET_ESP32S2
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#define TEST_SYNC_START (SOC_DPORT_CACHE_ADDRESS_LOW + TEST_OFFSET)
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@@ -41,13 +40,11 @@ const static char *TAG = "CACHE_TEST";
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#endif
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#define TEST_SYNC_SIZE 0x8000
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#define RECORD_TIME_PREPARE() uint32_t __t1, __t2
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#define RECORD_TIME_START() do {__t1 = esp_cpu_get_cycle_count();} while(0)
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#define RECORD_TIME_END(p_time) do{__t2 = esp_cpu_get_cycle_count(); p_time = (__t2 - __t1);} while(0)
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#define GET_US_BY_CCOUNT(t) ((double)(t)/CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ)
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static void s_test_with_msync_cb(void *arg)
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{
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(void)arg;
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@@ -156,7 +153,6 @@ TEST_CASE("test cache msync work with Flash operation when XIP from PSRAM", "[ca
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}
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#endif //#if CONFIG_SPIRAM_FETCH_INSTRUCTIONS && CONFIG_SPIRAM_RODATA
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#if CONFIG_SPIRAM
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/*---------------------------------------------------------------
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Test esp_cache_msync with PSRAM stack
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@@ -56,7 +56,6 @@ typedef struct test_block_info_ {
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static LIST_HEAD(test_block_list_head_, test_block_info_) test_block_head;
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static void s_fill_random_data(uint8_t *buffer, size_t size, int random_seed)
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{
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srand(random_seed);
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@@ -102,7 +101,6 @@ TEST_CASE("test all readable vaddr can map to flash", "[mmu]")
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ESP_LOGV(TAG, "rand seed: %d, write flash addr: %p...", test_seed, (void *)part->address);
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TEST_ESP_OK(esp_flash_write(part->flash_chip, sector_buf, part->address, sizeof(sector_buf)));
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esp_err_t ret = ESP_FAIL;
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int count = 0;
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LIST_INIT(&test_block_head);
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@@ -144,7 +142,6 @@ TEST_CASE("test all readable vaddr can map to flash", "[mmu]")
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free(sector_buf);
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}
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TEST_CASE("test all executable vaddr can map to flash", "[mmu]")
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{
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//Get the partition used for SPI1 erase operation
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@@ -173,8 +170,7 @@ TEST_CASE("test all executable vaddr can map to flash", "[mmu]")
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TEST_ASSERT(paddr == part->address + i);
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ESP_LOGV(TAG, "paddr: %p, on %s", (void *)paddr, (mem_target) == MMU_TARGET_FLASH0 ? "Flash" : "PSRAM");
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}
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}
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else if (ret == ESP_ERR_NOT_FOUND) {
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} else if (ret == ESP_ERR_NOT_FOUND) {
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free(block_info);
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break;
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} else {
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