From fcc9293f6618bfe4678012cedc44e3e303ba6e25 Mon Sep 17 00:00:00 2001 From: laokaiyao Date: Mon, 25 Dec 2023 15:32:55 +0800 Subject: [PATCH] change(esp32c5): update soc files for esp32c5 beta3 --- .../test_apps/.build-test-rules.yml | 4 + .../deprecated/driver/adc_types_legacy.h | 2 +- components/hal/esp32c5/clk_tree_hal.c | 78 + components/hal/esp32c5/efuse_hal.c | 112 + components/hal/esp32c5/include/hal/cache_ll.h | 6 +- .../hal/esp32c5/include/hal/clk_gate_ll.h | 72 + .../hal/esp32c5/include/hal/clk_tree_ll.h | 743 ++++ components/hal/esp32c5/include/hal/gpio_ll.h | 726 ++++ .../hal/esp32c5/include/hal/gpspi_flash_ll.h | 455 +++ components/hal/esp32c5/include/hal/lpwdt_ll.h | 57 +- components/hal/esp32c5/include/hal/mmu_ll.h | 348 +- .../hal/esp32c5/include/hal/modem_lpcon_ll.h | 293 ++ .../hal/esp32c5/include/hal/modem_syscon_ll.h | 630 ++++ components/hal/esp32c5/include/hal/mwdt_ll.h | 48 +- components/hal/esp32c5/include/hal/pmu_hal.h | 45 + components/hal/esp32c5/include/hal/pmu_ll.h | 676 ++++ .../hal/esp32c5/include/hal/regi2c_ctrl_ll.h | 66 + .../hal/esp32c5/include/hal/rtc_io_ll.h | 456 +++ .../include/hal/spi_flash_encrypted_ll.h | 175 + .../hal/esp32c5/include/hal/spi_flash_ll.h | 102 + components/hal/esp32c5/include/hal/spi_ll.h | 1404 ++++++++ .../hal/esp32c5/include/hal/spimem_flash_ll.h | 656 ++++ .../hal/esp32c5/include/hal/systimer_ll.h | 205 ++ components/hal/esp32c5/include/hal/timer_ll.h | 80 + components/hal/esp32c5/include/hal/uart_ll.h | 939 +++-- components/hal/esp32c5/modem_clock_hal.c | 267 ++ components/hal/esp32c5/pmu_hal.c | 70 + components/hal/include/hal/rtc_hal.h | 4 +- components/hal/include/hal/sha_types.h | 2 + components/hal/include/hal/spi_slave_hal.h | 2 + .../esp32c5/include/modem/modem_lpcon_reg.h | 359 ++ .../include/modem/modem_lpcon_struct.h | 247 ++ .../esp32c5/include/modem/modem_syscon_reg.h | 517 +++ .../include/modem/modem_syscon_struct.h | 164 + .../soc/esp32c5/include/modem/reg_base.h | 9 + .../esp32c5/include/soc/Kconfig.soc_caps.in | 264 ++ .../soc/esp32c5/include/soc/adc_channel.h | 28 + .../soc/esp32c5/include/soc/clk_tree_defs.h | 25 +- .../soc/esp32c5/include/soc/ext_mem_defs.h | 152 + .../soc/esp32c5/include/soc/gdma_channel.h | 32 + .../soc/esp32c5/include/soc/gdma_struct.h | 1210 +------ components/soc/esp32c5/include/soc/gpio_num.h | 56 + .../soc/esp32c5/include/soc/gpio_sig_map.h | 1 + .../soc/esp32c5/include/soc/gpio_struct.h | 2314 +------------ .../soc/esp32c5/include/soc/huk_struct.h | 10 +- .../soc/esp32c5/include/soc/hwcrypto_reg.h | 12 + .../include/soc/interrupt_matrix_struct.h | 2 +- .../soc/esp32c5/include/soc/interrupts.h | 117 +- .../soc/esp32c5/include/soc/io_mux_reg.h | 269 +- .../soc/esp32c5/include/soc/keymng_struct.h | 12 +- .../soc/esp32c5/include/soc/lp_uart_struct.h | 3 +- .../soc/esp32c5/include/soc/lp_wdt_struct.h | 9 +- components/soc/esp32c5/include/soc/pcr_reg.h | 89 + .../soc/esp32c5/include/soc/pmu_icg_mapping.h | 68 + .../soc/esp32c5/include/soc/pmu_struct.h | 2957 +++------------- components/soc/esp32c5/include/soc/reg_base.h | 4 +- .../soc/esp32c5/include/soc/regi2c_bbpll.h | 86 + .../soc/esp32c5/include/soc/regi2c_defs.h | 30 + .../soc/esp32c5/include/soc/regi2c_dig_reg.h | 64 + .../soc/esp32c5/include/soc/reset_reasons.h | 39 +- components/soc/esp32c5/include/soc/rtc.h | 524 +++ .../soc/esp32c5/include/soc/sha_struct.h | 6 +- components/soc/esp32c5/include/soc/soc.h | 4 +- components/soc/esp32c5/include/soc/soc_caps.h | 235 +- .../soc/esp32c5/include/soc/soc_etm_struct.h | 12 +- .../soc/esp32c5/include/soc/spi1_mem_struct.h | 2 - .../soc/esp32c5/include/soc/spi_mem_reg.h | 146 +- .../soc/esp32c5/include/soc/spi_mem_struct.h | 3068 ++++++----------- .../soc/esp32c5/include/soc/system_reg.h | 12 + .../soc/esp32c5/include/soc/systimer_struct.h | 606 +--- .../esp32c5/include/soc/timer_group_struct.h | 22 +- .../soc/esp32c5/include/soc/uart_channel.h | 20 + .../soc/esp32c5/include/soc/uart_pins.h | 48 + .../soc/esp32c5/include/soc/uart_struct.h | 30 +- components/soc/esp32c5/include/soc/wdev_reg.h | 13 + components/soc/esp32c5/interrupts.c | 97 + .../soc/esp32c5/ld/esp32c5.peripherals.ld | 2 + 77 files changed, 13318 insertions(+), 9401 deletions(-) create mode 100644 components/hal/esp32c5/clk_tree_hal.c create mode 100644 components/hal/esp32c5/efuse_hal.c create mode 100644 components/hal/esp32c5/include/hal/clk_gate_ll.h create mode 100644 components/hal/esp32c5/include/hal/clk_tree_ll.h create mode 100644 components/hal/esp32c5/include/hal/gpio_ll.h create mode 100644 components/hal/esp32c5/include/hal/gpspi_flash_ll.h create mode 100644 components/hal/esp32c5/include/hal/modem_lpcon_ll.h create mode 100644 components/hal/esp32c5/include/hal/modem_syscon_ll.h create mode 100644 components/hal/esp32c5/include/hal/pmu_hal.h create mode 100644 components/hal/esp32c5/include/hal/pmu_ll.h create mode 100644 components/hal/esp32c5/include/hal/regi2c_ctrl_ll.h create mode 100644 components/hal/esp32c5/include/hal/rtc_io_ll.h create mode 100644 components/hal/esp32c5/include/hal/spi_flash_encrypted_ll.h create mode 100644 components/hal/esp32c5/include/hal/spi_flash_ll.h create mode 100644 components/hal/esp32c5/include/hal/spi_ll.h create mode 100644 components/hal/esp32c5/include/hal/spimem_flash_ll.h create mode 100644 components/hal/esp32c5/include/hal/systimer_ll.h create mode 100644 components/hal/esp32c5/include/hal/timer_ll.h create mode 100644 components/hal/esp32c5/modem_clock_hal.c create mode 100644 components/hal/esp32c5/pmu_hal.c create mode 100644 components/soc/esp32c5/include/modem/modem_lpcon_reg.h create mode 100644 components/soc/esp32c5/include/modem/modem_lpcon_struct.h create mode 100644 components/soc/esp32c5/include/modem/modem_syscon_reg.h create mode 100644 components/soc/esp32c5/include/modem/modem_syscon_struct.h create mode 100644 components/soc/esp32c5/include/modem/reg_base.h create mode 100644 components/soc/esp32c5/include/soc/adc_channel.h create mode 100644 components/soc/esp32c5/include/soc/ext_mem_defs.h create mode 100644 components/soc/esp32c5/include/soc/gdma_channel.h create mode 100644 components/soc/esp32c5/include/soc/gpio_num.h create mode 100644 components/soc/esp32c5/include/soc/hwcrypto_reg.h create mode 100644 components/soc/esp32c5/include/soc/pmu_icg_mapping.h create mode 100644 components/soc/esp32c5/include/soc/regi2c_bbpll.h create mode 100644 components/soc/esp32c5/include/soc/regi2c_defs.h create mode 100644 components/soc/esp32c5/include/soc/regi2c_dig_reg.h create mode 100644 components/soc/esp32c5/include/soc/rtc.h create mode 100644 components/soc/esp32c5/include/soc/system_reg.h create mode 100644 components/soc/esp32c5/include/soc/uart_channel.h create mode 100644 components/soc/esp32c5/include/soc/uart_pins.h create mode 100644 components/soc/esp32c5/include/soc/wdev_reg.h diff --git a/components/bootloader_support/test_apps/.build-test-rules.yml b/components/bootloader_support/test_apps/.build-test-rules.yml index 1dbe91f913..c4bd999324 100644 --- a/components/bootloader_support/test_apps/.build-test-rules.yml +++ b/components/bootloader_support/test_apps/.build-test-rules.yml @@ -4,3 +4,7 @@ components/bootloader_support/test_apps/rtc_custom_section: enable: - if: SOC_RTC_MEM_SUPPORTED == 1 reason: this feature is supported on chips that have RTC memory + disable: + - if: IDF_TARGET == "esp32c5" + temporary: true + reason: not supported yet diff --git a/components/driver/deprecated/driver/adc_types_legacy.h b/components/driver/deprecated/driver/adc_types_legacy.h index e8cecf04bd..06642a99cc 100644 --- a/components/driver/deprecated/driver/adc_types_legacy.h +++ b/components/driver/deprecated/driver/adc_types_legacy.h @@ -70,7 +70,7 @@ typedef enum { ADC1_CHANNEL_4, /*!< ADC1 channel 4 is GPIO4 */ ADC1_CHANNEL_MAX, } adc1_channel_t; -#elif CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4 +#elif CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32C5 typedef enum { ADC1_CHANNEL_0 = 0, /*!< ADC1 channel 0 is GPIO0 */ ADC1_CHANNEL_1, /*!< ADC1 channel 1 is GPIO1 */ diff --git a/components/hal/esp32c5/clk_tree_hal.c b/components/hal/esp32c5/clk_tree_hal.c new file mode 100644 index 0000000000..0624828a85 --- /dev/null +++ b/components/hal/esp32c5/clk_tree_hal.c @@ -0,0 +1,78 @@ +/* + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "hal/clk_tree_hal.h" +#include "hal/clk_tree_ll.h" +#include "soc/rtc.h" +#include "hal/assert.h" +#include "hal/log.h" + +static const char *CLK_HAL_TAG = "clk_hal"; + +uint32_t clk_hal_soc_root_get_freq_mhz(soc_cpu_clk_src_t cpu_clk_src) +{ + switch (cpu_clk_src) { + case SOC_CPU_CLK_SRC_XTAL: + return clk_hal_xtal_get_freq_mhz(); + case SOC_CPU_CLK_SRC_PLL_F160: + return CLK_LL_PLL_160M_FREQ_MHZ; + case SOC_CPU_CLK_SRC_PLL_F240: + return CLK_LL_PLL_240M_FREQ_MHZ; + case SOC_CPU_CLK_SRC_RC_FAST: + return SOC_CLK_RC_FAST_FREQ_APPROX / MHZ; + default: + // Unknown CPU_CLK mux input + HAL_ASSERT(false); + return 0; + } +} + +uint32_t clk_hal_cpu_get_freq_hz(void) +{ + soc_cpu_clk_src_t source = clk_ll_cpu_get_src(); + uint32_t divider = clk_ll_cpu_get_divider(); + return clk_hal_soc_root_get_freq_mhz(source) * MHZ / divider; +} + +uint32_t clk_hal_ahb_get_freq_hz(void) +{ + soc_cpu_clk_src_t source = clk_ll_cpu_get_src(); + uint32_t divider = clk_ll_ahb_get_divider(); + return clk_hal_soc_root_get_freq_mhz(source) * MHZ / divider; +} + +uint32_t clk_hal_apb_get_freq_hz(void) +{ + return clk_hal_ahb_get_freq_hz() / clk_ll_apb_get_divider(); +} + +uint32_t clk_hal_lp_slow_get_freq_hz(void) +{ + switch (clk_ll_rtc_slow_get_src()) { + // case SOC_RTC_SLOW_CLK_SRC_RC_SLOW: + // return SOC_CLK_RC_SLOW_FREQ_APPROX; + case SOC_RTC_SLOW_CLK_SRC_XTAL32K: + return SOC_CLK_XTAL32K_FREQ_APPROX; + case SOC_RTC_SLOW_CLK_SRC_OSC_SLOW: + return SOC_CLK_OSC_SLOW_FREQ_APPROX; + case SOC_RTC_SLOW_CLK_SRC_RC32K: + return SOC_CLK_RC32K_FREQ_APPROX; + default: + // Unknown RTC_SLOW_CLK mux input + HAL_ASSERT(false); + return 0; + } +} + +uint32_t clk_hal_xtal_get_freq_mhz(void) +{ + uint32_t freq = clk_ll_xtal_load_freq_mhz(); + if (freq == 0) { + HAL_LOGW(CLK_HAL_TAG, "invalid RTC_XTAL_FREQ_REG value, assume 40MHz"); + return (uint32_t)RTC_XTAL_FREQ_40M; + } + return freq; +} diff --git a/components/hal/esp32c5/efuse_hal.c b/components/hal/esp32c5/efuse_hal.c new file mode 100644 index 0000000000..86f7dd4a83 --- /dev/null +++ b/components/hal/esp32c5/efuse_hal.c @@ -0,0 +1,112 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include "sdkconfig.h" +#include "soc/soc_caps.h" +#include "hal/assert.h" +#include "hal/efuse_hal.h" +#include "hal/efuse_ll.h" +#include "esp_attr.h" + +#define ESP_EFUSE_BLOCK_ERROR_BITS(error_reg, block) ((error_reg) & (0x08 << (4 * (block)))) +#define ESP_EFUSE_BLOCK_ERROR_NUM_BITS(error_reg, block) ((error_reg) & (0x07 << (4 * (block)))) + +IRAM_ATTR uint32_t efuse_hal_get_major_chip_version(void) +{ +#ifdef CONFIG_ESP_REV_NEW_CHIP_TEST + return CONFIG_ESP_REV_MIN_FULL / 100; +#else + return efuse_ll_get_chip_wafer_version_major(); +#endif +} + +IRAM_ATTR uint32_t efuse_hal_get_minor_chip_version(void) +{ +#ifdef CONFIG_ESP_REV_NEW_CHIP_TEST + return CONFIG_ESP_REV_MIN_FULL % 100; +#else + return efuse_ll_get_chip_wafer_version_minor(); +#endif +} + +/******************* eFuse control functions *************************/ + +void efuse_hal_set_timing(uint32_t apb_freq_hz) +{ + (void) apb_freq_hz; + // TODO: [ESP32C5] IDF-8674 + abort(); + // efuse_ll_set_dac_num(0xFF); + // efuse_ll_set_dac_clk_div(0x28); + // efuse_ll_set_pwr_on_num(0x3000); + // efuse_ll_set_pwr_off_num(0x190); +} + +void efuse_hal_read(void) +{ + // TODO: [ESP32C5] IDF-8674 + abort(); + // efuse_hal_set_timing(0); + + // efuse_ll_set_conf_read_op_code(); + // efuse_ll_set_read_cmd(); + + // while (efuse_ll_get_read_cmd() != 0) { } + // /*Due to a hardware error, we have to read READ_CMD again to make sure the efuse clock is normal*/ + // while (efuse_ll_get_read_cmd() != 0) { } +} + +void efuse_hal_clear_program_registers(void) +{ + // TODO: [ESP32C5] IDF-8674 + abort(); + // ets_efuse_clear_program_registers(); +} + +void efuse_hal_program(uint32_t block) +{ + // TODO: [ESP32C5] IDF-8674 + abort(); + // efuse_hal_set_timing(0); + + // efuse_ll_set_conf_write_op_code(); + // efuse_ll_set_pgm_cmd(block); + + // while (efuse_ll_get_pgm_cmd() != 0) { } + + // efuse_hal_clear_program_registers(); + // efuse_hal_read(); +} + +void efuse_hal_rs_calculate(const void *data, void *rs_values) +{ + // TODO: [ESP32C5] IDF-8674 + abort(); + // ets_efuse_rs_calculate(data, rs_values); +} + +/******************* eFuse control functions *************************/ + +bool efuse_hal_is_coding_error_in_block(unsigned block) +{ + // TODO: [ESP32C5] IDF-8674 + abort(); + // if (block == 0) { + // for (unsigned i = 0; i < 5; i++) { + // if (REG_READ(EFUSE_RD_REPEAT_ERR0_REG + i * 4)) { + // return true; + // } + // } + // } else if (block <= 10) { + // // EFUSE_RD_RS_ERR0_REG: (hi) BLOCK8, BLOCK7, BLOCK6, BLOCK5, BLOCK4, BLOCK3, BLOCK2, BLOCK1 (low) + // // EFUSE_RD_RS_ERR1_REG: BLOCK10, BLOCK9 + // block--; + // uint32_t error_reg = REG_READ(EFUSE_RD_RS_ERR0_REG + (block / 8) * 4); + // return ESP_EFUSE_BLOCK_ERROR_BITS(error_reg, block % 8) != 0; + // } + // return false; +} diff --git a/components/hal/esp32c5/include/hal/cache_ll.h b/components/hal/esp32c5/include/hal/cache_ll.h index 2f460651ad..33fce6ff2a 100644 --- a/components/hal/esp32c5/include/hal/cache_ll.h +++ b/components/hal/esp32c5/include/hal/cache_ll.h @@ -10,7 +10,7 @@ #include // TODO: [ESP32C5] IDF-8646 (inherit from C6) -// #include "soc/extmem_reg.h" +#include "soc/cache_reg.h" // #include "soc/ext_mem_defs.h" #include "hal/cache_types.h" #include "hal/assert.h" @@ -318,11 +318,9 @@ static inline void cache_ll_l1_clear_access_error_intr(uint32_t cache_id, uint32 static inline uint32_t cache_ll_l1_get_access_error_intr_status(uint32_t cache_id, uint32_t mask) { // TODO: [ESP32C5] IDF-8646 (inherit from C6) - // return GET_PERI_REG_MASK(EXTMEM_L1_CACHE_ACS_FAIL_INT_ST_REG, mask); - return (uint32_t)0; + return GET_PERI_REG_MASK(CACHE_L1_CACHE_ACS_FAIL_INT_ST_REG, mask); } #ifdef __cplusplus - return (uint32_t)0; } #endif diff --git a/components/hal/esp32c5/include/hal/clk_gate_ll.h b/components/hal/esp32c5/include/hal/clk_gate_ll.h new file mode 100644 index 0000000000..be5d93824e --- /dev/null +++ b/components/hal/esp32c5/include/hal/clk_gate_ll.h @@ -0,0 +1,72 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include +#include "hal/assert.h" +#include "soc/periph_defs.h" +#include "soc/pcr_reg.h" +#include "soc/soc.h" +#include "soc/soc_caps.h" +#include "esp_attr.h" + +#ifdef __cplusplus +extern "C" { +#endif + +static inline uint32_t periph_ll_get_clk_en_mask(periph_module_t periph) +{ + // Only add peripherals that haven't implemented clock enable by their own ll function + return 0; +} + +static inline uint32_t periph_ll_get_rst_en_mask(periph_module_t periph, bool enable) +{ + // Only add peripherals that haven't implemented reset by their own ll function + return 0; +} + +static inline uint32_t periph_ll_get_clk_en_reg(periph_module_t periph) +{ + // Only add peripherals that haven't implemented clock enable by their own ll function + return 0; +} + +static inline uint32_t periph_ll_get_rst_en_reg(periph_module_t periph) +{ + // Only add peripherals that haven't implemented reset by their own ll function + return 0; +} + +static inline void periph_ll_enable_clk_clear_rst(periph_module_t periph) +{ + SET_PERI_REG_MASK(periph_ll_get_clk_en_reg(periph), periph_ll_get_clk_en_mask(periph)); + CLEAR_PERI_REG_MASK(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, true)); +} + +static inline void periph_ll_disable_clk_set_rst(periph_module_t periph) +{ + CLEAR_PERI_REG_MASK(periph_ll_get_clk_en_reg(periph), periph_ll_get_clk_en_mask(periph)); + SET_PERI_REG_MASK(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false)); +} + +static inline void periph_ll_reset(periph_module_t periph) +{ + SET_PERI_REG_MASK(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false)); + CLEAR_PERI_REG_MASK(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false)); +} + +static inline bool IRAM_ATTR periph_ll_periph_enabled(periph_module_t periph) +{ + return REG_GET_BIT(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false)) == 0 && + REG_GET_BIT(periph_ll_get_clk_en_reg(periph), periph_ll_get_clk_en_mask(periph)) != 0; +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32c5/include/hal/clk_tree_ll.h b/components/hal/esp32c5/include/hal/clk_tree_ll.h new file mode 100644 index 0000000000..8ebd608f26 --- /dev/null +++ b/components/hal/esp32c5/include/hal/clk_tree_ll.h @@ -0,0 +1,743 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include "soc/soc.h" +#include "soc/clk_tree_defs.h" +#include "soc/rtc.h" +#include "soc/pcr_struct.h" +#include "soc/lp_clkrst_struct.h" +#include "soc/pmu_reg.h" +#include "soc/pmu_struct.h" +#include "hal/regi2c_ctrl.h" +#include "soc/regi2c_bbpll.h" +#include "hal/assert.h" +#include "hal/log.h" +#include "esp32c5/rom/rtc.h" +#include "hal/misc.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define MHZ (1000000) + +#define CLK_LL_PLL_80M_FREQ_MHZ (80) +#define CLK_LL_PLL_120M_FREQ_MHZ (120) +#define CLK_LL_PLL_160M_FREQ_MHZ (160) +#define CLK_LL_PLL_240M_FREQ_MHZ (240) + +#define CLK_LL_PLL_480M_FREQ_MHZ (480) + +#define CLK_LL_XTAL32K_CONFIG_DEFAULT() { \ + .dac = 3, \ + .dres = 3, \ + .dgm = 3, \ + .dbuf = 1, \ +} + +/* +Set the frequency division factor of ref_tick +The FOSC of rtc calibration uses the 32 frequency division clock for ECO1, +So the frequency division factor of ref_tick must be greater than or equal to 32 +*/ +#define REG_FOSC_TICK_NUM 255 + +/** + * @brief XTAL32K_CLK enable modes + */ +typedef enum { + CLK_LL_XTAL32K_ENABLE_MODE_CRYSTAL, //!< Enable the external 32kHz crystal for XTAL32K_CLK + CLK_LL_XTAL32K_ENABLE_MODE_EXTERNAL, //!< Enable the external clock signal for OSC_SLOW_CLK + CLK_LL_XTAL32K_ENABLE_MODE_BOOTSTRAP, //!< Bootstrap the crystal oscillator for faster XTAL32K_CLK start up */ +} clk_ll_xtal32k_enable_mode_t; + +/** + * @brief XTAL32K_CLK configuration structure + */ +typedef struct { + uint32_t dac : 6; + uint32_t dres : 3; + uint32_t dgm : 3; + uint32_t dbuf: 1; +} clk_ll_xtal32k_config_t; + +/** + * @brief Power up BBPLL circuit + */ +static inline __attribute__((always_inline)) void clk_ll_bbpll_enable(void) +{ + SET_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_HIGH_XPD_BB_I2C | + PMU_TIE_HIGH_XPD_BBPLL | PMU_TIE_HIGH_XPD_BBPLL_I2C); + SET_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_HIGH_GLOBAL_BBPLL_ICG); +} + +/** + * @brief Power down BBPLL circuit + */ +static inline __attribute__((always_inline)) void clk_ll_bbpll_disable(void) +{ + SET_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_LOW_GLOBAL_BBPLL_ICG) ; + SET_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_LOW_XPD_BBPLL | PMU_TIE_LOW_XPD_BBPLL_I2C); +} + +/** + * @brief Release the root clock source locked by PMU + */ +static inline __attribute__((always_inline)) void clk_ll_cpu_clk_src_lock_release(void) +{ + SET_PERI_REG_MASK(PMU_IMM_SLEEP_SYSCLK_REG, PMU_UPDATE_DIG_SYS_CLK_SEL); +} + +/** + * @brief Enable the 32kHz crystal oscillator + * + * @param mode Used to determine the xtal32k configuration parameters + */ +static inline __attribute__((always_inline)) void clk_ll_xtal32k_enable(clk_ll_xtal32k_enable_mode_t mode) +{ + if (mode == CLK_LL_XTAL32K_ENABLE_MODE_EXTERNAL) { + // No need to configure anything for OSC_SLOW_CLK + return; + } + // Configure xtal32k + clk_ll_xtal32k_config_t cfg = CLK_LL_XTAL32K_CONFIG_DEFAULT(); + LP_CLKRST.xtal32k.dac_xtal32k = cfg.dac; + LP_CLKRST.xtal32k.dres_xtal32k = cfg.dres; + LP_CLKRST.xtal32k.dgm_xtal32k = cfg.dgm; + LP_CLKRST.xtal32k.dbuf_xtal32k = cfg.dbuf; + // Enable xtal32k xpd + SET_PERI_REG_MASK(PMU_HP_SLEEP_LP_CK_POWER_REG, PMU_HP_SLEEP_XPD_XTAL32K); +} + +/** + * @brief Disable the 32kHz crystal oscillator + */ +static inline __attribute__((always_inline)) void clk_ll_xtal32k_disable(void) +{ + // Disable xtal32k xpd + CLEAR_PERI_REG_MASK(PMU_HP_SLEEP_LP_CK_POWER_REG, PMU_HP_SLEEP_XPD_XTAL32K); +} + +/** + * @brief Get the state of the 32kHz crystal clock + * + * @return True if the 32kHz XTAL is enabled + */ +static inline __attribute__((always_inline)) bool clk_ll_xtal32k_is_enabled(void) +{ + return REG_GET_FIELD(PMU_HP_SLEEP_LP_CK_POWER_REG, PMU_HP_SLEEP_XPD_XTAL32K) == 1; +} + +/** + * @brief Enable the internal oscillator output for RC32K_CLK + */ +static inline __attribute__((always_inline)) void clk_ll_rc32k_enable(void) +{ + // Enable rc32k xpd status + SET_PERI_REG_MASK(PMU_HP_SLEEP_LP_CK_POWER_REG, PMU_HP_SLEEP_XPD_RC32K); +} + +/** + * @brief Disable the internal oscillator output for RC32K_CLK + */ +static inline __attribute__((always_inline)) void clk_ll_rc32k_disable(void) +{ + // Disable rc32k xpd status + CLEAR_PERI_REG_MASK(PMU_HP_SLEEP_LP_CK_POWER_REG, PMU_HP_SLEEP_XPD_RC32K); +} + +/** + * @brief Get the state of the internal oscillator for RC32K_CLK + * + * @return True if the oscillator is enabled + */ +static inline __attribute__((always_inline)) bool clk_ll_rc32k_is_enabled(void) +{ + return REG_GET_FIELD(PMU_HP_SLEEP_LP_CK_POWER_REG, PMU_HP_SLEEP_XPD_RC32K) == 1; +} + +/** + * @brief Enable the internal oscillator output for RC_FAST_CLK + */ +static inline __attribute__((always_inline)) void clk_ll_rc_fast_enable(void) +{ + SET_PERI_REG_MASK(PMU_HP_SLEEP_LP_CK_POWER_REG, PMU_HP_SLEEP_XPD_FOSC_CLK); +} + +/** + * @brief Disable the internal oscillator output for RC_FAST_CLK + */ +static inline __attribute__((always_inline)) void clk_ll_rc_fast_disable(void) +{ + CLEAR_PERI_REG_MASK(PMU_HP_SLEEP_LP_CK_POWER_REG, PMU_HP_SLEEP_XPD_FOSC_CLK); +} + +/** + * @brief Get the state of the internal oscillator for RC_FAST_CLK + * + * @return True if the oscillator is enabled + */ +static inline __attribute__((always_inline)) bool clk_ll_rc_fast_is_enabled(void) +{ + return REG_GET_FIELD(PMU_HP_SLEEP_LP_CK_POWER_REG, PMU_HP_SLEEP_XPD_FOSC_CLK) == 1; +} + +/** + * @brief Enable the digital RC_FAST_CLK, which is used to support peripherals. + */ +static inline __attribute__((always_inline)) void clk_ll_rc_fast_digi_enable(void) +{ + LP_CLKRST.clk_to_hp.icg_hp_fosc = 1; +} + +/** + * @brief Disable the digital RC_FAST_CLK, which is used to support peripherals. + */ +static inline __attribute__((always_inline)) void clk_ll_rc_fast_digi_disable(void) +{ + LP_CLKRST.clk_to_hp.icg_hp_fosc = 0; +} + +/** + * @brief Get the state of the digital RC_FAST_CLK + * + * @return True if the digital RC_FAST_CLK is enabled + */ +static inline __attribute__((always_inline)) bool clk_ll_rc_fast_digi_is_enabled(void) +{ + return LP_CLKRST.clk_to_hp.icg_hp_fosc; +} + +/** + * @brief Enable the digital XTAL32K_CLK, which is used to support peripherals. + */ +static inline __attribute__((always_inline)) void clk_ll_xtal32k_digi_enable(void) +{ + LP_CLKRST.clk_to_hp.icg_hp_xtal32k = 1; +} + +/** + * @brief Disable the digital XTAL32K_CLK, which is used to support peripherals. + */ +static inline __attribute__((always_inline)) void clk_ll_xtal32k_digi_disable(void) +{ + LP_CLKRST.clk_to_hp.icg_hp_xtal32k = 0; +} + +/** + * @brief Get the state of the digital XTAL32K_CLK + * + * @return True if the digital XTAL32K_CLK is enabled + */ +static inline __attribute__((always_inline)) bool clk_ll_xtal32k_digi_is_enabled(void) +{ + return LP_CLKRST.clk_to_hp.icg_hp_xtal32k; +} + +/** + * @brief Enable the digital RC32K_CLK, which is used to support peripherals. + */ +static inline __attribute__((always_inline)) void clk_ll_rc32k_digi_enable(void) +{ + LP_CLKRST.clk_to_hp.icg_hp_osc32k = 1; +} + +/** + * @brief Disable the digital RC32K_CLK, which is used to support peripherals. + */ +static inline __attribute__((always_inline)) void clk_ll_rc32k_digi_disable(void) +{ + LP_CLKRST.clk_to_hp.icg_hp_osc32k = 0; +} + +/** + * @brief Get the state of the digital RC32K_CLK + * + * @return True if the digital RC32K_CLK is enabled + */ +static inline __attribute__((always_inline)) bool clk_ll_rc32k_digi_is_enabled(void) +{ + return LP_CLKRST.clk_to_hp.icg_hp_osc32k; +} + +/** + * @brief Get PLL_CLK frequency + * + * @return PLL clock frequency, in MHz. Returns 0 if register field value is invalid. + */ +static inline __attribute__((always_inline)) uint32_t clk_ll_bbpll_get_freq_mhz(void) +{ + // The target has a fixed 480MHz SPLL + return CLK_LL_PLL_480M_FREQ_MHZ; +} + +/** + * @brief Set BBPLL frequency from XTAL source (Digital part) + * + * @param pll_freq_mhz PLL frequency, in MHz + */ +static inline __attribute__((always_inline)) void clk_ll_bbpll_set_freq_mhz(uint32_t pll_freq_mhz) +{ + // The target SPLL is fixed to 480MHz + // Do nothing + HAL_ASSERT(pll_freq_mhz == CLK_LL_PLL_480M_FREQ_MHZ); +} + +/** + * @brief Set BBPLL frequency from XTAL source (Analog part) + * + * @param pll_freq_mhz PLL frequency, in MHz + * @param xtal_freq_mhz XTAL frequency, in MHz + */ +static inline __attribute__((always_inline)) void clk_ll_bbpll_set_config(uint32_t pll_freq_mhz, uint32_t xtal_freq_mhz) +{ + HAL_ASSERT(pll_freq_mhz == CLK_LL_PLL_480M_FREQ_MHZ); + uint8_t div_ref; + uint8_t div7_0; + uint8_t dr1; + uint8_t dr3; + uint8_t dchgp; + uint8_t dbias; + + uint8_t href = 3; + uint8_t lref = 1; + /* Configure 480M PLL */ + switch (xtal_freq_mhz) { + case RTC_XTAL_FREQ_40M: + div_ref = 1; + div7_0 = 12; + dr1 = 0; + dr3 = 0; + dchgp = 5; + dbias = 2; + break; + case RTC_XTAL_FREQ_48M: + div_ref = 1; + div7_0 = 10; + dr1 = 1; + dr3 = 1; + dchgp = 5; + dbias = 2; + break; + default: + div_ref = 1; + div7_0 = 12; + dr1 = 0; + dr3 = 0; + dchgp = 5; + dbias = 2; + break; + } + uint8_t i2c_bbpll_lref = (dchgp << I2C_BBPLL_OC_DCHGP_LSB) | (div_ref); + uint8_t i2c_bbpll_div_7_0 = div7_0; + REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_OC_REF_DIV, i2c_bbpll_lref); + REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_OC_DIV_7_0, i2c_bbpll_div_7_0); + REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_DR1, dr1); + REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_DR3, dr3); + REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_DLREF_SEL, lref); + REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_DHREF_SEL, href); + REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_VCO_DBIAS, dbias); +} + +/** + * @brief Select the clock source for CPU_CLK (SOC Clock Root) + * + * @param in_sel One of the clock sources in soc_cpu_clk_src_t + */ +static inline __attribute__((always_inline)) void clk_ll_cpu_set_src(soc_cpu_clk_src_t in_sel) +{ + switch (in_sel) { + case SOC_CPU_CLK_SRC_XTAL: + PCR.sysclk_conf.soc_clk_sel = 0; + break; + case SOC_CPU_CLK_SRC_RC_FAST: + PCR.sysclk_conf.soc_clk_sel = 1; + break; + case SOC_CPU_CLK_SRC_PLL_F160: + PCR.sysclk_conf.soc_clk_sel = 2; + break; + case SOC_CPU_CLK_SRC_PLL_F240: + PCR.sysclk_conf.soc_clk_sel = 3; + break; + default: + // Unsupported SOC_CLK mux input sel + abort(); + } + HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.bus_clk_update, bus_clock_update, 1); +} + +/** + * @brief Get the clock source for CPU_CLK (SOC Clock Root) + * + * @return Currently selected clock source (one of soc_cpu_clk_src_t values) + */ +static inline __attribute__((always_inline)) soc_cpu_clk_src_t clk_ll_cpu_get_src(void) +{ + uint32_t clk_sel = PCR.sysclk_conf.soc_clk_sel; + switch (clk_sel) { + case 0: + return SOC_CPU_CLK_SRC_XTAL; + case 1: + return SOC_CPU_CLK_SRC_RC_FAST; + case 2: + return SOC_CPU_CLK_SRC_PLL_F160; + case 3: + return SOC_CPU_CLK_SRC_PLL_F240; + default: + // Invalid SOC_CLK_SEL value + return SOC_CPU_CLK_SRC_INVALID; + } +} + +/** + * @brief Get AHB_CLK's low-speed divider + * + * @return Divider. Divider = (PCR_LS_DIV_NUM + 1) * (PCR_AHB_LS_DIV_NUM + 1). + */ +static inline __attribute__((always_inline)) uint32_t clk_ll_ahb_get_divider(void) +{ + uint32_t ahb_div = HAL_FORCE_READ_U32_REG_FIELD(PCR.ahb_freq_conf, ahb_div_num); + uint32_t hp_root_ls_div = HAL_FORCE_READ_U32_REG_FIELD(PCR.sysclk_conf, ls_div_num); + return (hp_root_ls_div + 1) * (ahb_div + 1); +} + +/** + * @brief Set CPU_CLK's divider + * + * @param divider Divider. (PCR_CPU_DIV_NUM + 1) = divider. + */ +static inline __attribute__((always_inline)) void clk_ll_cpu_set_divider(uint32_t divider) +{ + // SOC_ROOT_CLK ---(1)---> HP_ROOT_CLK ---(2)---> CPU_CLK + // (2) configurable + // divider option: 1, 2, 4 (PCR_CPU_HS_DIV_NUM=0, 1, 3) + HAL_ASSERT(divider == 1 || divider == 2 || divider == 3 || divider == 4 || divider == 6); + HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.cpu_freq_conf, cpu_div_num, (divider) - 1); + HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.bus_clk_update, bus_clock_update, 1); +} + +/** + * @brief Set AHB_CLK's low-speed divider (valid when SOC_ROOT clock source is XTAL/RC_FAST) + * + * @param divider Divider. (PCR_LS_DIV_NUM + 1) * (PCR_AHB_LS_DIV_NUM + 1) = divider. + */ +static inline __attribute__((always_inline)) void clk_ll_ahb_set_divider(uint32_t divider) +{ + // SOC_ROOT_CLK ---(1)---> HP_ROOT_CLK ---(2)---> AHB_CLK + HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.ahb_freq_conf, ahb_div_num, divider - 1); + HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.bus_clk_update, bus_clock_update, 1); +} + +/** + * @brief Get CPU_CLK's high-speed divider + * + * @return Divider. Divider = (PCR_HS_DIV_NUM + 1) * (PCR_CPU_HS_DIV_NUM + 1). + */ +static inline __attribute__((always_inline)) uint32_t clk_ll_cpu_get_divider(void) +{ + uint32_t cpu_div = HAL_FORCE_READ_U32_REG_FIELD(PCR.cpu_freq_conf, cpu_div_num); + return (cpu_div + 1); +} + +/** + * @brief Set APB_CLK divider. freq of APB_CLK = freq of AHB_CLK / divider + * + * @param divider Divider. PCR_APB_DIV_NUM = divider - 1. + */ +static inline __attribute__((always_inline)) void clk_ll_apb_set_divider(uint32_t divider) +{ + // AHB ------> APB + // Divider option: 1, 2, 4 (PCR_APB_DIV_NUM=0, 1, 3) + HAL_ASSERT(divider == 1 || divider == 2 || divider == 4); + HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.apb_freq_conf, apb_div_num, divider - 1); +} + +/** + * @brief Get APB_CLK divider + * + * @return Divider. Divider = (PCR_APB_DIV_NUM + 1). + */ +static inline __attribute__((always_inline)) uint32_t clk_ll_apb_get_divider(void) +{ + return HAL_FORCE_READ_U32_REG_FIELD(PCR.apb_freq_conf, apb_div_num) + 1; +} + +static inline __attribute__((always_inline)) void clk_ll_mspi_fast_sel_clk(soc_periph_mspi_clk_src_t mspi_clk_src) +{ + switch (mspi_clk_src) { + case MSPI_CLK_SRC_XTAL: + PCR.mspi_clk_conf.mspi_func_clk_sel = 0; + break; + case MSPI_CLK_SRC_RC_FAST: + PCR.mspi_clk_conf.mspi_func_clk_sel = 1; + break; + case SOC_MOD_CLK_PLL_F480M: + PCR.mspi_clk_conf.mspi_func_clk_sel = 2; + break; + default: + abort(); + } +} + +/** + * @brief Set MSPI_FAST_CLK's low-speed divider (valid when SOC_ROOT clock source is XTAL/RC_FAST) + * + * @param divider Divider. + */ +static inline __attribute__((always_inline)) void clk_ll_mspi_fast_set_divider(uint32_t divider) +{ + HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.mspi_clk_conf, mspi_fast_div_num, divider - 1); +} + +/** + * @brief Select the calibration 32kHz clock source for timergroup0 + * + * @param in_sel One of the 32kHz clock sources (RC32K_CLK, XTAL32K_CLK, OSC_SLOW_CLK) + */ +static inline __attribute__((always_inline)) void clk_ll_32k_calibration_set_target(soc_rtc_slow_clk_src_t in_sel) +{ + switch (in_sel) { + case SOC_RTC_SLOW_CLK_SRC_RC32K: + PCR.ctrl_32k_conf.clk_32k_sel = 0; + break; + case SOC_RTC_SLOW_CLK_SRC_XTAL32K: + PCR.ctrl_32k_conf.clk_32k_sel = 1; + break; + case SOC_RTC_SLOW_CLK_SRC_OSC_SLOW: + PCR.ctrl_32k_conf.clk_32k_sel = 2; + break; + default: + // Unsupported 32K_SEL mux input + abort(); + } + HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.bus_clk_update, bus_clock_update, 1); +} + +/** + * @brief Get the calibration 32kHz clock source for timergroup0 + * + * @return soc_rtc_slow_clk_src_t Currently selected calibration 32kHz clock (one of the 32kHz clocks) + */ +static inline __attribute__((always_inline)) soc_rtc_slow_clk_src_t clk_ll_32k_calibration_get_target(void) +{ + uint32_t clk_sel = PCR.ctrl_32k_conf.clk_32k_sel; + switch (clk_sel) { + case 0: + return SOC_RTC_SLOW_CLK_SRC_RC32K; + case 1: + return SOC_RTC_SLOW_CLK_SRC_XTAL32K; + case 2: + return SOC_RTC_SLOW_CLK_SRC_OSC_SLOW; + default: + return SOC_RTC_SLOW_CLK_SRC_INVALID; + } +} + +/** + * @brief Select the clock source for RTC_SLOW_CLK + * + * @param in_sel One of the clock sources in soc_rtc_slow_clk_src_t + */ +static inline __attribute__((always_inline)) void clk_ll_rtc_slow_set_src(soc_rtc_slow_clk_src_t in_sel) +{ + switch (in_sel) { + // case SOC_RTC_SLOW_CLK_SRC_RC_SLOW: + // LP_CLKRST.lp_clk_conf.slow_clk_sel = 0; + // break; + case SOC_RTC_SLOW_CLK_SRC_XTAL32K: + LP_CLKRST.lp_clk_conf.slow_clk_sel = 1; + break; + case SOC_RTC_SLOW_CLK_SRC_RC32K: + LP_CLKRST.lp_clk_conf.slow_clk_sel = 2; + break; + case SOC_RTC_SLOW_CLK_SRC_OSC_SLOW: + LP_CLKRST.lp_clk_conf.slow_clk_sel = 3; + break; + default: + // Unsupported RTC_SLOW_CLK mux input sel + abort(); + } +} + +/** + * @brief Get the clock source for RTC_SLOW_CLK + * + * @return Currently selected clock source (one of soc_rtc_slow_clk_src_t values) + */ +static inline __attribute__((always_inline)) soc_rtc_slow_clk_src_t clk_ll_rtc_slow_get_src(void) +{ + uint32_t clk_sel = LP_CLKRST.lp_clk_conf.slow_clk_sel; + switch (clk_sel) { + // case 0: + // return SOC_RTC_SLOW_CLK_SRC_RC_SLOW; + case 1: + return SOC_RTC_SLOW_CLK_SRC_XTAL32K; + case 2: + return SOC_RTC_SLOW_CLK_SRC_RC32K; + case 3: + return SOC_RTC_SLOW_CLK_SRC_OSC_SLOW; + default: + return SOC_RTC_SLOW_CLK_SRC_INVALID; + } +} + +/** + * @brief Select the clock source for RTC_FAST_CLK + * + * @param in_sel One of the clock sources in soc_rtc_fast_clk_src_t + */ +static inline __attribute__((always_inline)) void clk_ll_rtc_fast_set_src(soc_rtc_fast_clk_src_t in_sel) +{ + switch (in_sel) { + case SOC_RTC_FAST_CLK_SRC_RC_FAST: + LP_CLKRST.lp_clk_conf.fast_clk_sel = 0; + break; + case SOC_RTC_FAST_CLK_SRC_XTAL_D2: + LP_CLKRST.lp_clk_conf.fast_clk_sel = 1; + break; + case SOC_RTC_FAST_CLK_SRC_XTAL_D1: + LP_CLKRST.lp_clk_conf.fast_clk_sel = 2; + break; + default: + // Unsupported RTC_FAST_CLK mux input sel + abort(); + } +} + +/** + * @brief Get the clock source for RTC_FAST_CLK + * + * @return Currently selected clock source (one of soc_rtc_fast_clk_src_t values) + */ +static inline __attribute__((always_inline)) soc_rtc_fast_clk_src_t clk_ll_rtc_fast_get_src(void) +{ + uint32_t clk_sel = LP_CLKRST.lp_clk_conf.fast_clk_sel; + switch (clk_sel) { + case 0: + return SOC_RTC_FAST_CLK_SRC_RC_FAST; + case 1: + return SOC_RTC_FAST_CLK_SRC_XTAL_D2; + default: + return SOC_RTC_FAST_CLK_SRC_XTAL_D1; + } +} + +/** + * @brief Set RC_FAST_CLK divider. The output from the divider is passed into rtc_fast_clk MUX. + * + * @param divider Divider of RC_FAST_CLK. Usually this divider is set to 1 (reg. value is 0) in bootloader stage. + */ +static inline __attribute__((always_inline)) void clk_ll_rc_fast_set_divider(uint32_t divider) +{ + // No divider on the target + HAL_ASSERT(divider == 1); +} + +/** + * @brief Get RC_FAST_CLK divider + * + * @return Divider. Divider = (CK8M_DIV_SEL + 1). + */ +static inline __attribute__((always_inline)) uint32_t clk_ll_rc_fast_get_divider(void) +{ + // No divider on the target, always return divider = 1 + return 1; +} + +/** + * @brief Set RC_SLOW_CLK divider + * + * @param divider Divider of RC_SLOW_CLK. Usually this divider is set to 1 (reg. value is 0) in bootloader stage. + */ +static inline __attribute__((always_inline)) void clk_ll_rc_slow_set_divider(uint32_t divider) +{ + // No divider on the target + HAL_ASSERT(divider == 1); +} + +/************************** LP STORAGE REGISTER STORE/LOAD **************************/ +/** + * @brief Store XTAL_CLK frequency in RTC storage register + * + * Value of RTC_XTAL_FREQ_REG is stored as two copies in lower and upper 16-bit + * halves. These are the routines to work with that representation. + * + * @param xtal_freq_mhz XTAL frequency, in MHz. The frequency must necessarily be even, + * otherwise there will be a conflict with the low bit, which is used to disable logs + * in the ROM code. + */ +static inline __attribute__((always_inline)) void clk_ll_xtal_store_freq_mhz(uint32_t xtal_freq_mhz) +{ + // Read the status of whether disabling logging from ROM code + uint32_t reg = READ_PERI_REG(RTC_XTAL_FREQ_REG) & RTC_DISABLE_ROM_LOG; + // If so, need to write back this setting + if (reg == RTC_DISABLE_ROM_LOG) { + xtal_freq_mhz |= 1; + } + WRITE_PERI_REG(RTC_XTAL_FREQ_REG, (xtal_freq_mhz & UINT16_MAX) | ((xtal_freq_mhz & UINT16_MAX) << 16)); +} + +/** + * @brief Load XTAL_CLK frequency from RTC storage register + * + * Value of RTC_XTAL_FREQ_REG is stored as two copies in lower and upper 16-bit + * halves. These are the routines to work with that representation. + * + * @return XTAL frequency, in MHz. Returns 0 if value in reg is invalid. + */ +static inline __attribute__((always_inline)) uint32_t clk_ll_xtal_load_freq_mhz(void) +{ + // Read from RTC storage register + uint32_t xtal_freq_reg = READ_PERI_REG(RTC_XTAL_FREQ_REG); + if ((xtal_freq_reg & 0xFFFF) == ((xtal_freq_reg >> 16) & 0xFFFF) && + xtal_freq_reg != 0 && xtal_freq_reg != UINT32_MAX) { + return xtal_freq_reg & ~RTC_DISABLE_ROM_LOG & UINT16_MAX; + } + // If the format in reg is invalid + return 0; +} + +/** + * @brief Store RTC_SLOW_CLK calibration value in RTC storage register + * + * Value of RTC_SLOW_CLK_CAL_REG has to be in the same format as returned by rtc_clk_cal (microseconds, + * in Q13.19 fixed-point format). + * + * @param cal_value The calibration value of slow clock period in microseconds, in Q13.19 fixed point format + */ +static inline __attribute__((always_inline)) void clk_ll_rtc_slow_store_cal(uint32_t cal_value) +{ + REG_WRITE(RTC_SLOW_CLK_CAL_REG, cal_value); +} + +/** + * @brief Load the calibration value of RTC_SLOW_CLK frequency from RTC storage register + * + * This value gets updated (i.e. rtc slow clock gets calibrated) every time RTC_SLOW_CLK source switches + * + * @return The calibration value of slow clock period in microseconds, in Q13.19 fixed point format + */ +static inline __attribute__((always_inline)) uint32_t clk_ll_rtc_slow_load_cal(void) +{ + return REG_READ(RTC_SLOW_CLK_CAL_REG); +} + + +/* +Set the frequency division factor of ref_tick +*/ +static inline void clk_ll_rc_fast_tick_conf(void) +{ + PCR.ctrl_tick_conf.fosc_tick_num = REG_FOSC_TICK_NUM; +} + + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32c5/include/hal/gpio_ll.h b/components/hal/esp32c5/include/hal/gpio_ll.h new file mode 100644 index 0000000000..ddd353dc1f --- /dev/null +++ b/components/hal/esp32c5/include/hal/gpio_ll.h @@ -0,0 +1,726 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/******************************************************************************* + * NOTICE + * The hal is not public api, don't use in application code. + * See readme.md in hal/include/hal/readme.md + ******************************************************************************/ + +// The LL layer for ESP32-C5 GPIO register operations + +#pragma once + +#include +#include +#include "soc/soc.h" +#include "soc/gpio_periph.h" +#include "soc/gpio_struct.h" +#include "soc/lp_aon_struct.h" +#include "soc/lp_io_struct.h" +#include "soc/pmu_struct.h" +#include "soc/usb_serial_jtag_reg.h" +#include "soc/pcr_struct.h" +#include "soc/clk_tree_defs.h" +#include "hal/gpio_types.h" +#include "hal/misc.h" +#include "hal/assert.h" + +#ifdef __cplusplus +extern "C" { +#endif + +// Get GPIO hardware instance with giving gpio num +#define GPIO_LL_GET_HW(num) (((num) == 0) ? (&GPIO) : NULL) + +#define GPIO_LL_PRO_CPU_INTR_ENA (BIT(0)) +#define GPIO_LL_PRO_CPU_NMI_INTR_ENA (BIT(1)) + +/** + * @brief Get the configuration for an IO + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + * @param pu Pull-up enabled or not + * @param pd Pull-down enabled or not + * @param ie Input enabled or not + * @param oe Output enabled or not + * @param od Open-drain enabled or not + * @param drv Drive strength value + * @param fun_sel IOMUX function selection value + * @param sig_out Outputting peripheral signal index + * @param slp_sel Pin sleep mode enabled or not + */ +static inline void gpio_ll_get_io_config(gpio_dev_t *hw, uint32_t gpio_num, + bool *pu, bool *pd, bool *ie, bool *oe, bool *od, uint32_t *drv, + uint32_t *fun_sel, uint32_t *sig_out, bool *slp_sel) +{ + // TODO: [ESP32C5] IDF-8717 + uint32_t bit_mask = 1 << gpio_num; + uint32_t iomux_reg_val = REG_READ(GPIO_PIN_MUX_REG[gpio_num]); + *pu = (iomux_reg_val & FUN_PU_M) >> FUN_PU_S; + *pd = (iomux_reg_val & FUN_PD_M) >> FUN_PD_S; + *ie = (iomux_reg_val & FUN_IE_M) >> FUN_IE_S; + *oe = (hw->enable.val & bit_mask) >> gpio_num; + *od = hw->pin[gpio_num].pad_driver; + *drv = (iomux_reg_val & FUN_DRV_M) >> FUN_DRV_S; + *fun_sel = (iomux_reg_val & MCU_SEL_M) >> MCU_SEL_S; + *sig_out = hw->func_out_sel_cfg[gpio_num].out_sel; + *slp_sel = (iomux_reg_val & SLP_SEL_M) >> SLP_SEL_S; +} + +/** + * @brief Enable pull-up on GPIO. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + */ +static inline void gpio_ll_pullup_en(gpio_dev_t *hw, uint32_t gpio_num) +{ + // TODO: [ESP32C5] IDF-8717 + REG_SET_BIT(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_PU); +} + +/** + * @brief Disable pull-up on GPIO. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + */ +__attribute__((always_inline)) +static inline void gpio_ll_pullup_dis(gpio_dev_t *hw, uint32_t gpio_num) +{ + // TODO: [ESP32C5] IDF-8717 + REG_CLR_BIT(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_PU); +} + +/** + * @brief Enable pull-down on GPIO. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + */ +static inline void gpio_ll_pulldown_en(gpio_dev_t *hw, uint32_t gpio_num) +{ + // TODO: [ESP32C5] IDF-8717 + REG_SET_BIT(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_PD); +} + +/** + * @brief Disable pull-down on GPIO. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + */ +__attribute__((always_inline)) +static inline void gpio_ll_pulldown_dis(gpio_dev_t *hw, uint32_t gpio_num) +{ + // TODO: [ESP32C5] IDF-8717 + // The pull-up value of the USB pins are controlled by the pins’ pull-up value together with USB pull-up value + // USB DP pin is default to PU enabled + // Note that esp32C5 has supported USB_EXCHG_PINS feature. If this efuse is burnt, the gpio pin + // which should be checked is USB_INT_PHY0_DM_GPIO_NUM instead. + // TODO: read the specific efuse with efuse_ll.h + if (gpio_num == USB_INT_PHY0_DP_GPIO_NUM) { + SET_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_PAD_PULL_OVERRIDE); + CLEAR_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_DP_PULLUP); + } + REG_CLR_BIT(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_PD); +} + +/** + * @brief GPIO set interrupt trigger type + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number. If you want to set the trigger type of e.g. of GPIO16, gpio_num should be GPIO_NUM_16 (16); + * @param intr_type Interrupt type, select from gpio_int_type_t + */ +static inline void gpio_ll_set_intr_type(gpio_dev_t *hw, uint32_t gpio_num, gpio_int_type_t intr_type) +{ + // TODO: [ESP32C5] IDF-8717 + hw->pin[gpio_num].int_type = intr_type; +} + +/** + * @brief Get GPIO interrupt status + * + * @param hw Peripheral GPIO hardware instance address. + * @param core_id interrupt core id + * @param status interrupt status + */ +__attribute__((always_inline)) +static inline void gpio_ll_get_intr_status(gpio_dev_t *hw, uint32_t core_id, uint32_t *status) +{ + // TODO: [ESP32C5] IDF-8717 + (void)core_id; + *status = hw->pcpu_int.procpu_int; +} + +/** + * @brief Get GPIO interrupt status high + * + * @param hw Peripheral GPIO hardware instance address. + * @param core_id interrupt core id + * @param status interrupt status high + */ +__attribute__((always_inline)) +static inline void gpio_ll_get_intr_status_high(gpio_dev_t *hw, uint32_t core_id, uint32_t *status) +{ + // TODO: [ESP32C5] IDF-8717 + *status = 0; // Less than 32 GPIOs in ESP32-C5 +} + +/** + * @brief Clear GPIO interrupt status + * + * @param hw Peripheral GPIO hardware instance address. + * @param mask interrupt status clear mask + */ +__attribute__((always_inline)) +static inline void gpio_ll_clear_intr_status(gpio_dev_t *hw, uint32_t mask) +{ + // TODO: [ESP32C5] IDF-8717 + hw->status_w1tc.status_w1tc = mask; +} + +/** + * @brief Clear GPIO interrupt status high + * + * @param hw Peripheral GPIO hardware instance address. + * @param mask interrupt status high clear mask + */ +__attribute__((always_inline)) +static inline void gpio_ll_clear_intr_status_high(gpio_dev_t *hw, uint32_t mask) +{ + // TODO: [ESP32C5] IDF-8717 + // Less than 32 GPIOs on ESP32-C5 Do nothing. +} + +/** + * @brief Enable GPIO module interrupt signal + * + * @param hw Peripheral GPIO hardware instance address. + * @param core_id Interrupt enabled CPU to corresponding ID + * @param gpio_num GPIO number. If you want to enable the interrupt of e.g. GPIO16, gpio_num should be GPIO_NUM_16 (16); + */ +__attribute__((always_inline)) +static inline void gpio_ll_intr_enable_on_core(gpio_dev_t *hw, uint32_t core_id, uint32_t gpio_num) +{ + // TODO: [ESP32C5] IDF-8717 + HAL_ASSERT(core_id == 0 && "target SoC only has a single core"); + GPIO.pin[gpio_num].int_ena = GPIO_LL_PRO_CPU_INTR_ENA; //enable pro cpu intr +} + +/** + * @brief Disable GPIO module interrupt signal + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number. If you want to disable the interrupt of e.g. GPIO16, gpio_num should be GPIO_NUM_16 (16); + */ +__attribute__((always_inline)) +static inline void gpio_ll_intr_disable(gpio_dev_t *hw, uint32_t gpio_num) +{ + // TODO: [ESP32C5] IDF-8717 + hw->pin[gpio_num].int_ena = 0; //disable GPIO intr +} + +/** + * @brief Disable input mode on GPIO. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + */ +__attribute__((always_inline)) +static inline void gpio_ll_input_disable(gpio_dev_t *hw, uint32_t gpio_num) +{ + // TODO: [ESP32C5] IDF-8717 + PIN_INPUT_DISABLE(IO_MUX_GPIO0_REG + (gpio_num * 4)); +} + +/** + * @brief Enable input mode on GPIO. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + */ +static inline void gpio_ll_input_enable(gpio_dev_t *hw, uint32_t gpio_num) +{ + // TODO: [ESP32C5] IDF-8717 + PIN_INPUT_ENABLE(IO_MUX_GPIO0_REG + (gpio_num * 4)); +} + +/** + * @brief Enable GPIO pin filter + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number of the pad. + */ +static inline void gpio_ll_pin_filter_enable(gpio_dev_t *hw, uint32_t gpio_num) +{ + // TODO: [ESP32C5] IDF-8717 + PIN_FILTER_EN(IO_MUX_GPIO0_REG + (gpio_num * 4)); +} + +/** + * @brief Disable GPIO pin filter + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number of the pad. + */ +static inline void gpio_ll_pin_filter_disable(gpio_dev_t *hw, uint32_t gpio_num) +{ + // TODO: [ESP32C5] IDF-8717 + PIN_FILTER_DIS(IO_MUX_GPIO0_REG + (gpio_num * 4)); +} + +/** + * @brief Disable output mode on GPIO. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + */ +__attribute__((always_inline)) +static inline void gpio_ll_output_disable(gpio_dev_t *hw, uint32_t gpio_num) +{ + // TODO: [ESP32C5] IDF-8717 + hw->enable_w1tc.enable_w1tc = (0x1 << gpio_num); + // Ensure no other output signal is routed via GPIO matrix to this pin + REG_WRITE(GPIO_FUNC0_OUT_SEL_CFG_REG + (gpio_num * 4), + SIG_GPIO_OUT_IDX); +} + +/** + * @brief Enable output mode on GPIO. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + */ +__attribute__((always_inline)) +static inline void gpio_ll_output_enable(gpio_dev_t *hw, uint32_t gpio_num) +{ + // TODO: [ESP32C5] IDF-8717 + hw->enable_w1ts.enable_w1ts = (0x1 << gpio_num); +} + +/** + * @brief Disable open-drain mode on GPIO. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + */ +static inline void gpio_ll_od_disable(gpio_dev_t *hw, uint32_t gpio_num) +{ + // TODO: [ESP32C5] IDF-8717 + hw->pin[gpio_num].pad_driver = 0; +} + +/** + * @brief Enable open-drain mode on GPIO. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + */ +static inline void gpio_ll_od_enable(gpio_dev_t *hw, uint32_t gpio_num) +{ + // TODO: [ESP32C5] IDF-8717 + hw->pin[gpio_num].pad_driver = 1; +} + +/** + * @brief GPIO set output level + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number. If you want to set the output level of e.g. GPIO16, gpio_num should be GPIO_NUM_16 (16); + * @param level Output level. 0: low ; 1: high + */ +__attribute__((always_inline)) +static inline void gpio_ll_set_level(gpio_dev_t *hw, uint32_t gpio_num, uint32_t level) +{ + // TODO: [ESP32C5] IDF-8717 + if (level) { + hw->out_w1ts.out_w1ts = (1 << gpio_num); + } else { + hw->out_w1tc.out_w1tc = (1 << gpio_num); + } +} + +/** + * @brief GPIO get input level + * + * @warning If the pad is not configured for input (or input and output) the returned value is always 0. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number. If you want to get the logic level of e.g. pin GPIO16, gpio_num should be GPIO_NUM_16 (16); + * + * @return + * - 0 the GPIO input level is 0 + * - 1 the GPIO input level is 1 + */ +__attribute__((always_inline)) +static inline int gpio_ll_get_level(gpio_dev_t *hw, uint32_t gpio_num) +{ + // TODO: [ESP32C5] IDF-8717 + return (hw->in.in_data_next >> gpio_num) & 0x1; + return (int)0; +} + +/** + * @brief Enable GPIO wake-up function. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number. + */ +static inline void gpio_ll_wakeup_enable(gpio_dev_t *hw, uint32_t gpio_num) +{ + // TODO: [ESP32C5] IDF-8717 + hw->pin[gpio_num].wakeup_enable = 0x1; +} + +/** + * @brief Disable GPIO wake-up function. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + */ +static inline void gpio_ll_wakeup_disable(gpio_dev_t *hw, uint32_t gpio_num) +{ + // TODO: [ESP32C5] IDF-8717 + hw->pin[gpio_num].wakeup_enable = 0; +} + +/** + * @brief Set GPIO pad drive capability + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number, only support output GPIOs + * @param strength Drive capability of the pad + */ +static inline void gpio_ll_set_drive_capability(gpio_dev_t *hw, uint32_t gpio_num, gpio_drive_cap_t strength) +{ + // TODO: [ESP32C5] IDF-8717 + SET_PERI_REG_BITS(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_DRV_V, strength, FUN_DRV_S); +} + +/** + * @brief Get GPIO pad drive capability + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number, only support output GPIOs + * @param strength Pointer to accept drive capability of the pad + */ +static inline void gpio_ll_get_drive_capability(gpio_dev_t *hw, uint32_t gpio_num, gpio_drive_cap_t *strength) +{ + // TODO: [ESP32C5] IDF-8717 + *strength = (gpio_drive_cap_t)GET_PERI_REG_BITS2(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_DRV_V, FUN_DRV_S); +} + +/** + * @brief Enable gpio pad hold function. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number, only support output GPIOs + */ +static inline void gpio_ll_hold_en(gpio_dev_t *hw, uint32_t gpio_num) +{ + // TODO: [ESP32C5] IDF-8717 + LP_AON.gpio_hold0.gpio_hold0 |= GPIO_HOLD_MASK[gpio_num]; +} + +/** + * @brief Disable gpio pad hold function. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number, only support output GPIOs + */ +static inline void gpio_ll_hold_dis(gpio_dev_t *hw, uint32_t gpio_num) +{ + // TODO: [ESP32C5] IDF-8717 + LP_AON.gpio_hold0.gpio_hold0 &= ~GPIO_HOLD_MASK[gpio_num]; +} + +/** + * @brief Get digital gpio pad hold status. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number, only support output GPIOs + * + * @note caller must ensure that gpio_num is a digital io pad + * + * @return + * - true digital gpio pad is held + * - false digital gpio pad is unheld + */ +__attribute__((always_inline)) +static inline bool gpio_ll_is_digital_io_hold(gpio_dev_t *hw, uint32_t gpio_num) +{ + // TODO: [ESP32C5] IDF-8717 + return !!(LP_AON.gpio_hold0.gpio_hold0 & BIT(gpio_num)); + return (bool)0; +} + +/** + * @brief Set pad input to a peripheral signal through the IOMUX. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number of the pad. + * @param signal_idx Peripheral signal id to input. One of the ``*_IN_IDX`` signals in ``soc/gpio_sig_map.h``. + */ +__attribute__((always_inline)) +static inline void gpio_ll_iomux_in(gpio_dev_t *hw, uint32_t gpio, uint32_t signal_idx) +{ + // TODO: [ESP32C5] IDF-8717 + hw->func_in_sel_cfg[signal_idx].sig_in_sel = 0; + PIN_INPUT_ENABLE(IO_MUX_GPIO0_REG + (gpio * 4)); +} + +/** + * @brief Select a function for the pin in the IOMUX + * + * @param pin_name Pin name to configure + * @param func Function to assign to the pin + */ +static inline void gpio_ll_iomux_func_sel(uint32_t pin_name, uint32_t func) +{ + // TODO: [ESP32C5] IDF-8717 + // Disable USB Serial JTAG if pins 12 or pins 13 needs to select an IOMUX function + if (pin_name == IO_MUX_GPIO12_REG || pin_name == IO_MUX_GPIO13_REG) { + CLEAR_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_USB_PAD_ENABLE); + } + PIN_FUNC_SELECT(pin_name, func); +} + +/** + * @brief Control the pin in the IOMUX + * + * @param bmap write mask of control value + * @param val Control value + * @param shift write mask shift of control value + */ +static inline __attribute__((always_inline)) void gpio_ll_set_pin_ctrl(uint32_t val, uint32_t bmap, uint32_t shift) +{ + // TODO: [ESP32C5] IDF-8717 + SET_PERI_REG_BITS(PIN_CTRL, bmap, val, shift); +} + +/** + * @brief Select a function for the pin in the IOMUX + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + * @param func Function to assign to the pin + */ +__attribute__((always_inline)) +static inline void gpio_ll_func_sel(gpio_dev_t *hw, uint8_t gpio_num, uint32_t func) +{ + // TODO: [ESP32C5] IDF-8717 + // Disable USB Serial JTAG if pins 12 or pins 13 needs to select an IOMUX function + if (gpio_num == USB_INT_PHY0_DM_GPIO_NUM || gpio_num == USB_INT_PHY0_DP_GPIO_NUM) { + CLEAR_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_USB_PAD_ENABLE); + } + PIN_FUNC_SELECT(IO_MUX_GPIO0_REG + (gpio_num * 4), func); +} + +/** + * @brief Set peripheral output to an GPIO pad through the IOMUX. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num gpio_num GPIO number of the pad. + * @param func The function number of the peripheral pin to output pin. + * One of the ``FUNC_X_*`` of specified pin (X) in ``soc/io_mux_reg.h``. + * @param oen_inv True if the output enable needs to be inverted, otherwise False. + */ +static inline void gpio_ll_iomux_out(gpio_dev_t *hw, uint8_t gpio_num, int func, uint32_t oen_inv) +{ + // TODO: [ESP32C5] IDF-8717 + hw->func_out_sel_cfg[gpio_num].oen_sel = 0; + hw->func_out_sel_cfg[gpio_num].oen_inv_sel = oen_inv; + gpio_ll_func_sel(hw, gpio_num, func); +} + +/** + * @brief Set clock source of IO MUX module + * + * @param src IO MUX clock source (only a subset of soc_module_clk_t values are valid) + */ +static inline void gpio_ll_iomux_set_clk_src(soc_module_clk_t src) +{ + // TODO: [ESP32C5] IDF-8717 + switch (src) { + case SOC_MOD_CLK_XTAL: + PCR.iomux_clk_conf.iomux_func_clk_sel = 3; + break; + case SOC_MOD_CLK_PLL_F80M: + PCR.iomux_clk_conf.iomux_func_clk_sel = 1; + break; + default: + // Unsupported IO_MUX clock source + HAL_ASSERT(false); + } +} + +/** + * @brief Get the GPIO number that is routed to the input peripheral signal through GPIO matrix. + * + * @param hw Peripheral GPIO hardware instance address. + * @param in_sig_idx Peripheral signal index (tagged as input attribute). + * + * @return + * - -1 Signal bypassed GPIO matrix + * - Others GPIO number + */ +static inline int gpio_ll_get_in_signal_connected_io(gpio_dev_t *hw, uint32_t in_sig_idx) +{ + // TODO: [ESP32C5] IDF-8717 + gpio_func_in_sel_cfg_reg_t reg; + reg.val = hw->func_in_sel_cfg[in_sig_idx].val; + return (reg.sig_in_sel ? reg.in_sel : -1); + return (int)0; +} + +/** + * @brief Force hold digital io pad. + * @note GPIO force hold, whether the chip in sleep mode or wakeup mode. + */ +static inline void gpio_ll_force_hold_all(void) +{ + // WT flag, it gets self-cleared after the configuration is done + PMU.imm.pad_hold_all.tie_high_hp_pad_hold_all = 1; +} + +/** + * @brief Force unhold digital io pad. + * @note GPIO force unhold, whether the chip in sleep mode or wakeup mode. + */ +static inline void gpio_ll_force_unhold_all(void) +{ + // WT flag, it gets self-cleared after the configuration is done + PMU.imm.pad_hold_all.tie_low_hp_pad_hold_all = 1; +} + +/** + * @brief Enable GPIO pin to use sleep mode pin functions during light sleep. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + */ +static inline void gpio_ll_sleep_sel_en(gpio_dev_t *hw, uint32_t gpio_num) +{ + // TODO: [ESP32C5] IDF-8717 + PIN_SLP_SEL_ENABLE(IO_MUX_GPIO0_REG + (gpio_num * 4)); +} + +/** + * @brief Disable GPIO pin to use sleep mode pin functions during light sleep. + * Pin functions remains the same in both normal execution and in light-sleep mode. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + */ +static inline void gpio_ll_sleep_sel_dis(gpio_dev_t *hw, uint32_t gpio_num) +{ + // TODO: [ESP32C5] IDF-8717 + PIN_SLP_SEL_DISABLE(IO_MUX_GPIO0_REG + (gpio_num * 4)); +} + +/** + * @brief Disable GPIO pull-up in sleep mode. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + */ +static inline void gpio_ll_sleep_pullup_dis(gpio_dev_t *hw, uint32_t gpio_num) +{ + // TODO: [ESP32C5] IDF-8717 + PIN_SLP_PULLUP_DISABLE(IO_MUX_GPIO0_REG + (gpio_num * 4)); +} + +/** + * @brief Enable GPIO pull-up in sleep mode. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + */ +static inline void gpio_ll_sleep_pullup_en(gpio_dev_t *hw, uint32_t gpio_num) +{ + // TODO: [ESP32C5] IDF-8717 + PIN_SLP_PULLUP_ENABLE(IO_MUX_GPIO0_REG + (gpio_num * 4)); +} + +/** + * @brief Enable GPIO pull-down in sleep mode. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + */ +static inline void gpio_ll_sleep_pulldown_en(gpio_dev_t *hw, uint32_t gpio_num) +{ + // TODO: [ESP32C5] IDF-8717 + PIN_SLP_PULLDOWN_ENABLE(IO_MUX_GPIO0_REG + (gpio_num * 4)); +} + +/** + * @brief Disable GPIO pull-down in sleep mode. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + */ +static inline void gpio_ll_sleep_pulldown_dis(gpio_dev_t *hw, uint32_t gpio_num) +{ + // TODO: [ESP32C5] IDF-8717 + PIN_SLP_PULLDOWN_DISABLE(IO_MUX_GPIO0_REG + (gpio_num * 4)); +} + +/** + * @brief Disable GPIO input in sleep mode. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + */ +static inline void gpio_ll_sleep_input_disable(gpio_dev_t *hw, uint32_t gpio_num) +{ + // TODO: [ESP32C5] IDF-8717 + PIN_SLP_INPUT_DISABLE(IO_MUX_GPIO0_REG + (gpio_num * 4)); +} + +/** + * @brief Enable GPIO input in sleep mode. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + */ +static inline void gpio_ll_sleep_input_enable(gpio_dev_t *hw, uint32_t gpio_num) +{ + // TODO: [ESP32C5] IDF-8717 + PIN_SLP_INPUT_ENABLE(IO_MUX_GPIO0_REG + (gpio_num * 4)); +} + +/** + * @brief Disable GPIO output in sleep mode. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + */ +static inline void gpio_ll_sleep_output_disable(gpio_dev_t *hw, uint32_t gpio_num) +{ + // TODO: [ESP32C5] IDF-8717 + PIN_SLP_OUTPUT_DISABLE(IO_MUX_GPIO0_REG + (gpio_num * 4)); +} + +/** + * @brief Enable GPIO output in sleep mode. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + */ +static inline void gpio_ll_sleep_output_enable(gpio_dev_t *hw, uint32_t gpio_num) +{ + // TODO: [ESP32C5] IDF-8717 + PIN_SLP_OUTPUT_ENABLE(IO_MUX_GPIO0_REG + (gpio_num * 4)); +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32c5/include/hal/gpspi_flash_ll.h b/components/hal/esp32c5/include/hal/gpspi_flash_ll.h new file mode 100644 index 0000000000..9bf5f63a10 --- /dev/null +++ b/components/hal/esp32c5/include/hal/gpspi_flash_ll.h @@ -0,0 +1,455 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/******************************************************************************* + * NOTICE + * The ll is not public api, don't use in application code. + * See readme.md in soc/include/hal/readme.md + ******************************************************************************/ + +// The Lowlevel layer for SPI Flash + +#pragma once + +#include +#include "soc/spi_periph.h" +#include "soc/spi_struct.h" +#include "hal/spi_types.h" +#include "hal/spi_flash_types.h" +#include // For MIN/MAX +#include +#include +#include "hal/misc.h" + +#ifdef __cplusplus +extern "C" { +#endif + +//NOTE: These macros are changed on c3 for build. MODIFY these when bringup flash. +#define gpspi_flash_ll_get_hw(host_id) ( ((host_id)==SPI2_HOST) ? &GPSPI2 : ({abort();(spi_dev_t*)0;}) ) +#define gpspi_flash_ll_hw_get_id(dev) ( ((dev) == (void*)&GPSPI2) ? SPI2_HOST : -1 ) + +typedef typeof(GPSPI2.clock.val) gpspi_flash_ll_clock_reg_t; +#define GPSPI_FLASH_LL_PERIPHERAL_FREQUENCY_MHZ (80) + +/*------------------------------------------------------------------------------ + * Control + *----------------------------------------------------------------------------*/ +/** + * Reset peripheral registers before configuration and starting control + * + * @param dev Beginning address of the peripheral registers. + */ +static inline void gpspi_flash_ll_reset(spi_dev_t *dev) +{ + // TODO: [ESP32C5] IDF-8698, IDF-8699 + // dev->user.val = 0; + // dev->ctrl.val = 0; + // // dev->clk_gate.clk_en = 1; + // dev->clk_gate.mst_clk_active = 1; + // dev->clk_gate.mst_clk_sel = 1; + // // dev->dma_conf.val = 0; + // dev->dma_conf.slv_tx_seg_trans_clr_en = 1; + // dev->dma_conf.slv_rx_seg_trans_clr_en = 1; + // dev->dma_conf.dma_slv_seg_trans_en = 0; + abort(); +} + +/** + * Check whether the previous operation is done. + * + * @param dev Beginning address of the peripheral registers. + * + * @return true if last command is done, otherwise false. + */ +static inline bool gpspi_flash_ll_cmd_is_done(const spi_dev_t *dev) +{ + // TODO: [ESP32C5] IDF-8698, IDF-8699 + // return (dev->cmd.usr == 0); + abort(); + return (bool)0; +} + +/** + * Get the read data from the buffer after ``gpspi_flash_ll_read`` is done. + * + * @param dev Beginning address of the peripheral registers. + * @param buffer Buffer to hold the output data + * @param read_len Length to get out of the buffer + */ +static inline void gpspi_flash_ll_get_buffer_data(spi_dev_t *dev, void *buffer, uint32_t read_len) +{ + // TODO: [ESP32C5] IDF-8698, IDF-8699 + // if (((intptr_t)buffer % 4 == 0) && (read_len % 4 == 0)) { + // // If everything is word-aligned, do a faster memcpy + // memcpy(buffer, (void *)dev->data_buf, read_len); + // } else { + // // Otherwise, slow(er) path copies word by word + // int copy_len = read_len; + // for (int i = 0; i < (read_len + 3) / 4; i++) { + // int word_len = MIN(sizeof(uint32_t), copy_len); + // uint32_t word = dev->data_buf[i].buf; + // memcpy(buffer, &word, word_len); + // buffer = (void *)((intptr_t)buffer + word_len); + // copy_len -= word_len; + // } + // } + abort(); +} + +/** + * Write a word to the data buffer. + * + * @param dev Beginning address of the peripheral registers. + * @param word Data to write at address 0. + */ +static inline void gpspi_flash_ll_write_word(spi_dev_t *dev, uint32_t word) +{ + // TODO: [ESP32C5] IDF-8698, IDF-8699 + // dev->data_buf[0].buf = word; + abort(); +} + +/** + * Set the data to be written in the data buffer. + * + * @param dev Beginning address of the peripheral registers. + * @param buffer Buffer holding the data + * @param length Length of data in bytes. + */ +static inline void gpspi_flash_ll_set_buffer_data(spi_dev_t *dev, const void *buffer, uint32_t length) +{ + // TODO: [ESP32C5] IDF-8698, IDF-8699 + // // Load data registers, word at a time + // int num_words = (length + 3) / 4; + // for (int i = 0; i < num_words; i++) { + // uint32_t word = 0; + // uint32_t word_len = MIN(length, sizeof(word)); + // memcpy(&word, buffer, word_len); + // dev->data_buf[i].buf = word; + // length -= word_len; + // buffer = (void *)((intptr_t)buffer + word_len); + // } + abort(); +} + +/** + * Trigger a user defined transaction. All phases, including command, address, dummy, and the data phases, + * should be configured before this is called. + * + * @param dev Beginning address of the peripheral registers. + * @param pe_ops Is page program/erase operation or not. (not used in gpspi) + */ +static inline void gpspi_flash_ll_user_start(spi_dev_t *dev, bool pe_ops) +{ + // TODO: [ESP32C5] IDF-8698, IDF-8699 + // dev->cmd.update = 1; + // while (dev->cmd.update); + // dev->cmd.usr = 1; + abort(); +} + +/** + * In user mode, it is set to indicate that program/erase operation will be triggered. + * + * @param dev Beginning address of the peripheral registers. + */ +static inline void gpspi_flash_ll_set_pe_bit(spi_dev_t *dev) +{ + // TODO: [ESP32C5] IDF-8698, IDF-8699 + // // Not supported on GPSPI + abort(); +} + +/** + * Set HD pin high when flash work at spi mode. + * + * @param dev Beginning address of the peripheral registers. + */ +static inline void gpspi_flash_ll_set_hold_pol(spi_dev_t *dev, uint32_t pol_val) +{ + // TODO: [ESP32C5] IDF-8698, IDF-8699 + // dev->ctrl.hold_pol = pol_val; + abort(); +} + +/** + * Check whether the host is idle to perform new commands. + * + * @param dev Beginning address of the peripheral registers. + * + * @return true if the host is idle, otherwise false + */ +static inline bool gpspi_flash_ll_host_idle(const spi_dev_t *dev) +{ + // TODO: [ESP32C5] IDF-8698, IDF-8699 + // return dev->cmd.usr == 0; + abort(); + return (bool)0; +} + +/** + * Set phases for user-defined transaction to read + * + * @param dev Beginning address of the peripheral registers. + */ +static inline void gpspi_flash_ll_read_phase(spi_dev_t *dev) +{ + // TODO: [ESP32C5] IDF-8698, IDF-8699 + // typeof (dev->user) user = { + // .usr_mosi = 0, + // .usr_miso = 1, + // .usr_addr = 1, + // .usr_command = 1, + // }; + // dev->user.val = user.val; + abort(); +} +/*------------------------------------------------------------------------------ + * Configs + *----------------------------------------------------------------------------*/ +/** + * Select which pin to use for the flash + * + * @param dev Beginning address of the peripheral registers. + * @param pin Pin ID to use, 0-2. Set to other values to disable all the CS pins. + */ +static inline void gpspi_flash_ll_set_cs_pin(spi_dev_t *dev, int pin) +{ + // TODO: [ESP32C5] IDF-8698, IDF-8699 + // dev->misc.cs0_dis = (pin == 0) ? 0 : 1; + // dev->misc.cs1_dis = (pin == 1) ? 0 : 1; + abort(); +} + +/** + * Set the read io mode. + * + * @param dev Beginning address of the peripheral registers. + * @param read_mode I/O mode to use in the following transactions. + */ +static inline void gpspi_flash_ll_set_read_mode(spi_dev_t *dev, esp_flash_io_mode_t read_mode) +{ + // TODO: [ESP32C5] IDF-8698, IDF-8699 + // typeof (dev->ctrl) ctrl; + // ctrl.val = dev->ctrl.val; + // typeof (dev->user) user; + // user.val = dev->user.val; + // // ctrl.val &= ~(SPI_FCMD_QUAD_M | SPI_FADDR_QUAD_M | SPI_FREAD_QUAD_M | SPI_FCMD_DUAL_M | SPI_FADDR_DUAL_M | SPI_FREAD_DUAL_M); + // user.val &= ~(SPI_FWRITE_QUAD_M | SPI_FWRITE_DUAL_M); + // // switch (read_mode) { + // case SPI_FLASH_FASTRD: + // //the default option + // case SPI_FLASH_SLOWRD: + // break; + // case SPI_FLASH_QIO: + // ctrl.fread_quad = 1; + // ctrl.faddr_quad = 1; + // user.fwrite_quad = 1; + // break; + // case SPI_FLASH_QOUT: + // ctrl.fread_quad = 1; + // user.fwrite_quad = 1; + // break; + // case SPI_FLASH_DIO: + // ctrl.fread_dual = 1; + // ctrl.faddr_dual = 1; + // user.fwrite_dual = 1; + // break; + // case SPI_FLASH_DOUT: + // ctrl.fread_dual = 1; + // user.fwrite_dual = 1; + // break; + // default: + // abort(); + // } + // // dev->ctrl.val = ctrl.val; + // dev->user.val = user.val; + abort(); +} + +/** + * Set clock frequency to work at. + * + * @param dev Beginning address of the peripheral registers. + * @param clock_val pointer to the clock value to set + */ +static inline void gpspi_flash_ll_set_clock(spi_dev_t *dev, gpspi_flash_ll_clock_reg_t *clock_val) +{ + // TODO: [ESP32C5] IDF-8698, IDF-8699 + // dev->clock.val = *clock_val; + abort(); +} + +/** + * Set the input length, in bits. + * + * @param dev Beginning address of the peripheral registers. + * @param bitlen Length of input, in bits. + */ +static inline void gpspi_flash_ll_set_miso_bitlen(spi_dev_t *dev, uint32_t bitlen) +{ + // TODO: [ESP32C5] IDF-8698, IDF-8699 + // dev->user.usr_miso = bitlen > 0; + // if (bitlen) { + // dev->ms_dlen.ms_data_bitlen = bitlen - 1; + // } + abort(); +} + +/** + * Set the output length, in bits (not including command, address and dummy + * phases) + * + * @param dev Beginning address of the peripheral registers. + * @param bitlen Length of output, in bits. + */ +static inline void gpspi_flash_ll_set_mosi_bitlen(spi_dev_t *dev, uint32_t bitlen) +{ + // TODO: [ESP32C5] IDF-8698, IDF-8699 + // dev->user.usr_mosi = bitlen > 0; + // if (bitlen) { + // dev->ms_dlen.ms_data_bitlen = bitlen - 1; + // } + abort(); +} + +/** + * Set the command. + * + * @param dev Beginning address of the peripheral registers. + * @param command Command to send + * @param bitlen Length of the command + */ +static inline void gpspi_flash_ll_set_command(spi_dev_t *dev, uint8_t command, uint32_t bitlen) +{ + // TODO: [ESP32C5] IDF-8698, IDF-8699 + // dev->user.usr_command = 1; + // typeof(dev->user2) user2 = { + // .usr_command_value = command, + // .usr_command_bitlen = (bitlen - 1), + // }; + // dev->user2.val = user2.val; + abort(); +} + +/** + * Get the address length that is set in register, in bits. + * + * @param dev Beginning address of the peripheral registers. + * + */ +static inline int gpspi_flash_ll_get_addr_bitlen(spi_dev_t *dev) +{ + // TODO: [ESP32C5] IDF-8698, IDF-8699 + // return dev->user.usr_addr ? dev->user1.usr_addr_bitlen + 1 : 0; + abort(); + return (int)0; +} + +/** + * Set the address length to send, in bits. Should be called before commands that requires the address e.g. erase sector, read, write... + * + * @param dev Beginning address of the peripheral registers. + * @param bitlen Length of the address, in bits + */ +static inline void gpspi_flash_ll_set_addr_bitlen(spi_dev_t *dev, uint32_t bitlen) +{ + // TODO: [ESP32C5] IDF-8698, IDF-8699 + // dev->user1.usr_addr_bitlen = (bitlen - 1); + // dev->user.usr_addr = bitlen ? 1 : 0; + abort(); +} + +/** + * Set the address to send in user mode. Should be called before commands that requires the address e.g. erase sector, read, write... + * + * @param dev Beginning address of the peripheral registers. + * @param addr Address to send + */ +static inline void gpspi_flash_ll_set_usr_address(spi_dev_t *dev, uint32_t addr, uint32_t bitlen) +{ + // TODO: [ESP32C5] IDF-8698, IDF-8699 + // // The blank region should be all ones + // uint32_t padding_ones = (bitlen == 32? 0 : UINT32_MAX >> bitlen); + // dev->addr.val = (addr << (32 - bitlen)) | padding_ones; + abort(); +} + +/** + * Set the address to send. Should be called before commands that requires the address e.g. erase sector, read, write... + * + * @param dev Beginning address of the peripheral registers. + * @param addr Address to send + */ +static inline void gpspi_flash_ll_set_address(spi_dev_t *dev, uint32_t addr) +{ + // TODO: [ESP32C5] IDF-8698, IDF-8699 + // dev->addr.val = addr; + abort(); +} + +/** + * Set the length of dummy cycles. + * + * @param dev Beginning address of the peripheral registers. + * @param dummy_n Cycles of dummy phases + */ +static inline void gpspi_flash_ll_set_dummy(spi_dev_t *dev, uint32_t dummy_n) +{ + // TODO: [ESP32C5] IDF-8698, IDF-8699 + // dev->user.usr_dummy = dummy_n ? 1 : 0; + // HAL_FORCE_MODIFY_U32_REG_FIELD(dev->user1, usr_dummy_cyclelen, dummy_n - 1); + abort(); +} + +/** + * Set extra hold time of CS after the clocks. + * + * @param dev Beginning address of the peripheral registers. + * @param hold_n Cycles of clocks before CS is inactive + */ +static inline void gpspi_flash_ll_set_hold(spi_dev_t *dev, uint32_t hold_n) +{ + // TODO: [ESP32C5] IDF-8698, IDF-8699 + // dev->user1.cs_hold_time = hold_n - 1; + // dev->user.cs_hold = (hold_n > 0? 1: 0); + abort(); +} + +static inline void gpspi_flash_ll_set_cs_setup(spi_dev_t *dev, uint32_t cs_setup_time) +{ + // TODO: [ESP32C5] IDF-8698, IDF-8699 + // dev->user.cs_setup = (cs_setup_time > 0 ? 1 : 0); + // dev->user1.cs_setup_time = cs_setup_time - 1; + abort(); +} + +/** + * Calculate spi_flash clock frequency division parameters for register. + * + * @param clkdiv frequency division factor + * + * @return Register setting for the given clock division factor. + */ +static inline uint32_t gpspi_flash_ll_calculate_clock_reg(uint8_t clkdiv) +{ + // TODO: [ESP32C5] IDF-8698, IDF-8699 + // uint32_t div_parameter; + // // See comments of `clock` in `spi_struct.h` + // if (clkdiv == 1) { + // div_parameter = (1 << 31); + // } else { + // div_parameter = ((clkdiv - 1) | (((clkdiv/2 - 1) & 0xff) << 6 ) | (((clkdiv - 1) & 0xff) << 12)); + // } + // return div_parameter; + abort(); + return (uint32_t)0; +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32c5/include/hal/lpwdt_ll.h b/components/hal/esp32c5/include/hal/lpwdt_ll.h index 7bd643be2d..c2c5008bae 100644 --- a/components/hal/esp32c5/include/hal/lpwdt_ll.h +++ b/components/hal/esp32c5/include/hal/lpwdt_ll.h @@ -68,8 +68,9 @@ ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_3_2us == LP_WDT_RESET_LENGTH_3200_NS, "Ad */ FORCE_INLINE_ATTR void lpwdt_ll_enable(lp_wdt_dev_t *hw) { - // TODO: [ESP32C5] IDF-8635 (inherit from C6) + // TODO: [ESP32C5] IDF-8635 // hw->config0.wdt_en = 1; + abort(); } /** @@ -82,8 +83,9 @@ FORCE_INLINE_ATTR void lpwdt_ll_enable(lp_wdt_dev_t *hw) */ FORCE_INLINE_ATTR void lpwdt_ll_disable(lp_wdt_dev_t *hw) { - // TODO: [ESP32C5] IDF-8635 (inherit from C6) + // TODO: [ESP32C5] IDF-8635 // hw->config0.wdt_en = 0; + abort(); } /** @@ -94,8 +96,9 @@ FORCE_INLINE_ATTR void lpwdt_ll_disable(lp_wdt_dev_t *hw) */ FORCE_INLINE_ATTR bool lpwdt_ll_check_if_enabled(lp_wdt_dev_t *hw) { - // TODO: [ESP32C5] IDF-8635 (inherit from C6) + // TODO: [ESP32C5] IDF-8635 // return (hw->config0.wdt_en) ? true : false; + abort(); return (bool)0; } @@ -119,7 +122,7 @@ FORCE_INLINE_ATTR bool lpwdt_ll_check_if_enabled(lp_wdt_dev_t *hw) */ FORCE_INLINE_ATTR void lpwdt_ll_config_stage(lp_wdt_dev_t *hw, wdt_stage_t stage, uint32_t timeout_ticks, wdt_stage_action_t behavior) { - // TODO: [ESP32C5] IDF-8635 (inherit from C6) + // TODO: [ESP32C5] IDF-8635 // switch (stage) { // case WDT_STAGE0: // hw->config0.wdt_stg0 = behavior; @@ -141,6 +144,7 @@ FORCE_INLINE_ATTR void lpwdt_ll_config_stage(lp_wdt_dev_t *hw, wdt_stage_t stage // default: // abort(); // } + abort(); } /** @@ -151,7 +155,7 @@ FORCE_INLINE_ATTR void lpwdt_ll_config_stage(lp_wdt_dev_t *hw, wdt_stage_t stage */ FORCE_INLINE_ATTR void lpwdt_ll_disable_stage(lp_wdt_dev_t *hw, wdt_stage_t stage) { - // TODO: [ESP32C5] IDF-8635 (inherit from C6) + // TODO: [ESP32C5] IDF-8635 // switch (stage) { // case WDT_STAGE0: // hw->config0.wdt_stg0 = WDT_STAGE_ACTION_OFF; @@ -168,6 +172,7 @@ FORCE_INLINE_ATTR void lpwdt_ll_disable_stage(lp_wdt_dev_t *hw, wdt_stage_t stag // default: // abort(); // } + abort(); } /** @@ -178,8 +183,9 @@ FORCE_INLINE_ATTR void lpwdt_ll_disable_stage(lp_wdt_dev_t *hw, wdt_stage_t stag */ FORCE_INLINE_ATTR void lpwdt_ll_set_cpu_reset_length(lp_wdt_dev_t *hw, wdt_reset_sig_length_t length) { - // TODO: [ESP32C5] IDF-8635 (inherit from C6) + // TODO: [ESP32C5] IDF-8635 // hw->config0.wdt_cpu_reset_length = length; + abort(); } /** @@ -190,8 +196,9 @@ FORCE_INLINE_ATTR void lpwdt_ll_set_cpu_reset_length(lp_wdt_dev_t *hw, wdt_reset */ FORCE_INLINE_ATTR void lpwdt_ll_set_sys_reset_length(lp_wdt_dev_t *hw, wdt_reset_sig_length_t length) { - // TODO: [ESP32C5] IDF-8635 (inherit from C6) + // TODO: [ESP32C5] IDF-8635 // hw->config0.wdt_sys_reset_length = length; + abort(); } /** @@ -206,8 +213,9 @@ FORCE_INLINE_ATTR void lpwdt_ll_set_sys_reset_length(lp_wdt_dev_t *hw, wdt_reset */ FORCE_INLINE_ATTR void lpwdt_ll_set_flashboot_en(lp_wdt_dev_t *hw, bool enable) { - // TODO: [ESP32C5] IDF-8635 (inherit from C6) + // TODO: [ESP32C5] IDF-8635 // hw->config0.wdt_flashboot_mod_en = (enable) ? 1 : 0; + abort(); } /** @@ -218,8 +226,9 @@ FORCE_INLINE_ATTR void lpwdt_ll_set_flashboot_en(lp_wdt_dev_t *hw, bool enable) */ FORCE_INLINE_ATTR void lpwdt_ll_set_procpu_reset_en(lp_wdt_dev_t *hw, bool enable) { - // TODO: [ESP32C5] IDF-8635 (inherit from C6) + // TODO: [ESP32C5] IDF-8635 // hw->config0.wdt_procpu_reset_en = (enable) ? 1 : 0; + abort(); } /** @@ -230,8 +239,9 @@ FORCE_INLINE_ATTR void lpwdt_ll_set_procpu_reset_en(lp_wdt_dev_t *hw, bool enabl */ FORCE_INLINE_ATTR void lpwdt_ll_set_appcpu_reset_en(lp_wdt_dev_t *hw, bool enable) { - // TODO: [ESP32C5] IDF-8635 (inherit from C6) + // TODO: [ESP32C5] IDF-8635 // hw->config0.wdt_appcpu_reset_en = (enable) ? 1 : 0; + abort(); } /** @@ -242,8 +252,9 @@ FORCE_INLINE_ATTR void lpwdt_ll_set_appcpu_reset_en(lp_wdt_dev_t *hw, bool enabl */ FORCE_INLINE_ATTR void lpwdt_ll_set_pause_in_sleep_en(lp_wdt_dev_t *hw, bool enable) { - // TODO: [ESP32C5] IDF-8635 (inherit from C6) + // TODO: [ESP32C5] IDF-8635 // hw->config0.wdt_pause_in_slp = (enable) ? 1 : 0; + abort(); } /** @@ -257,8 +268,9 @@ FORCE_INLINE_ATTR void lpwdt_ll_set_pause_in_sleep_en(lp_wdt_dev_t *hw, bool ena */ FORCE_INLINE_ATTR void lpwdt_ll_set_chip_reset_en(lp_wdt_dev_t *hw, bool enable) { - // TODO: [ESP32C5] IDF-8635 (inherit from C6) + // TODO: [ESP32C5] IDF-8635 // hw->config0.wdt_chip_reset_en = (enable) ? 1 : 0; + abort(); } /** @@ -269,8 +281,9 @@ FORCE_INLINE_ATTR void lpwdt_ll_set_chip_reset_en(lp_wdt_dev_t *hw, bool enable) */ FORCE_INLINE_ATTR void lpwdt_ll_set_chip_reset_width(lp_wdt_dev_t *hw, uint32_t width) { - // TODO: [ESP32C5] IDF-8635 (inherit from C6) + // TODO: [ESP32C5] IDF-8635 // HAL_FORCE_MODIFY_U32_REG_FIELD(hw->config0, wdt_chip_reset_width, width); + abort(); } /** @@ -282,8 +295,9 @@ FORCE_INLINE_ATTR void lpwdt_ll_set_chip_reset_width(lp_wdt_dev_t *hw, uint32_t */ FORCE_INLINE_ATTR void lpwdt_ll_feed(lp_wdt_dev_t *hw) { - // TODO: [ESP32C5] IDF-8635 (inherit from C6) + // TODO: [ESP32C5] IDF-8635 // hw->feed.rtc_wdt_feed = 1; + abort(); } /** @@ -293,8 +307,9 @@ FORCE_INLINE_ATTR void lpwdt_ll_feed(lp_wdt_dev_t *hw) */ FORCE_INLINE_ATTR void lpwdt_ll_write_protect_enable(lp_wdt_dev_t *hw) { - // TODO: [ESP32C5] IDF-8635 (inherit from C6) + // TODO: [ESP32C5] IDF-8635 // hw->wprotect.val = 0; + abort(); } /** @@ -304,8 +319,9 @@ FORCE_INLINE_ATTR void lpwdt_ll_write_protect_enable(lp_wdt_dev_t *hw) */ FORCE_INLINE_ATTR void lpwdt_ll_write_protect_disable(lp_wdt_dev_t *hw) { - // TODO: [ESP32C5] IDF-8635 (inherit from C6) + // TODO: [ESP32C5] IDF-8635 // hw->wprotect.val = LP_WDT_WKEY_VALUE; + abort(); } /** @@ -316,8 +332,9 @@ FORCE_INLINE_ATTR void lpwdt_ll_write_protect_disable(lp_wdt_dev_t *hw) */ FORCE_INLINE_ATTR void lpwdt_ll_set_intr_enable(lp_wdt_dev_t *hw, bool enable) { - // TODO: [ESP32C5] IDF-8635 (inherit from C6) + // TODO: [ESP32C5] IDF-8635 // hw->int_ena.lp_wdt_int_ena = (enable) ? 1 : 0; + abort(); } /** @@ -328,8 +345,9 @@ FORCE_INLINE_ATTR void lpwdt_ll_set_intr_enable(lp_wdt_dev_t *hw, bool enable) */ FORCE_INLINE_ATTR bool lpwdt_ll_check_intr_status(lp_wdt_dev_t *hw) { - // TODO: [ESP32C5] IDF-8635 (inherit from C6) + // TODO: [ESP32C5] IDF-8635 // return (hw->int_st.lp_wdt_int_st) ? true : false; + abort(); return (bool)0; } @@ -340,8 +358,9 @@ FORCE_INLINE_ATTR bool lpwdt_ll_check_intr_status(lp_wdt_dev_t *hw) */ FORCE_INLINE_ATTR void lpwdt_ll_clear_intr_status(lp_wdt_dev_t *hw) { - // TODO: [ESP32C5] IDF-8635 (inherit from C6) + // TODO: [ESP32C5] IDF-8635 // hw->int_clr.lp_wdt_int_clr = 1; + abort(); } #ifdef __cplusplus diff --git a/components/hal/esp32c5/include/hal/mmu_ll.h b/components/hal/esp32c5/include/hal/mmu_ll.h index c63225b0d5..9d5129d5ec 100644 --- a/components/hal/esp32c5/include/hal/mmu_ll.h +++ b/components/hal/esp32c5/include/hal/mmu_ll.h @@ -9,7 +9,7 @@ #pragma once #include "soc/spi_mem_reg.h" -// #include "soc/ext_mem_defs.h" +#include "soc/ext_mem_defs.h" #include "hal/assert.h" #include "hal/mmu_types.h" #include "hal/efuse_ll.h" @@ -29,8 +29,7 @@ extern "C" { static inline uint32_t mmu_ll_vaddr_to_laddr(uint32_t vaddr) { // TODO: [ESP32C5] IDF-8658 (inherit from C6) - // return vaddr & SOC_MMU_LINEAR_ADDR_MASK; - return (uint32_t)0; + return vaddr & SOC_MMU_LINEAR_ADDR_MASK; } /** @@ -45,21 +44,19 @@ static inline uint32_t mmu_ll_vaddr_to_laddr(uint32_t vaddr) static inline uint32_t mmu_ll_laddr_to_vaddr(uint32_t laddr, mmu_vaddr_t vaddr_type, mmu_target_t target) { // TODO: [ESP32C5] IDF-8658 (inherit from C6) - // (void)target; - // (void)vaddr_type; - // //On ESP32C5, I/D share the same vaddr range - // return SOC_MMU_IBUS_VADDR_BASE | laddr; - return (uint32_t)0; + (void)target; + (void)vaddr_type; + //On ESP32C5, I/D share the same vaddr range + return SOC_MMU_IBUS_VADDR_BASE | laddr; } __attribute__((always_inline)) static inline bool mmu_ll_cache_encryption_enabled(void) { // TODO: [ESP32C5] IDF-8658 (inherit from C6) - // unsigned cnt = efuse_ll_get_flash_crypt_cnt(); - // // 3 bits wide, any odd number - 1 or 3 - bits set means encryption is on - // cnt = ((cnt >> 2) ^ (cnt >> 1) ^ cnt) & 0x1; - // return (cnt == 1); - return (bool)0; + unsigned cnt = efuse_ll_get_flash_crypt_cnt(); + // 3 bits wide, any odd number - 1 or 3 - bits set means encryption is on + cnt = ((cnt >> 2) ^ (cnt >> 1) ^ cnt) & 0x1; + return (cnt == 1); } /** @@ -73,13 +70,12 @@ __attribute__((always_inline)) static inline mmu_page_size_t mmu_ll_get_page_size(uint32_t mmu_id) { // TODO: [ESP32C5] IDF-8658 (inherit from C6) - // (void)mmu_id; - // uint32_t page_size_code = REG_GET_FIELD(SPI_MEM_MMU_POWER_CTRL_REG(0), SPI_MEM_MMU_PAGE_SIZE); - // return (page_size_code == 0) ? MMU_PAGE_64KB : - // (page_size_code == 1) ? MMU_PAGE_32KB : - // (page_size_code == 2) ? MMU_PAGE_16KB : - // MMU_PAGE_8KB; - return (mmu_page_size_t)0; + (void)mmu_id; + uint32_t page_size_code = REG_GET_FIELD(SPI_MEM_MMU_POWER_CTRL_REG(0), SPI_MMU_PAGE_SIZE); + return (page_size_code == 0) ? MMU_PAGE_64KB : + (page_size_code == 1) ? MMU_PAGE_32KB : + (page_size_code == 2) ? MMU_PAGE_16KB : + MMU_PAGE_8KB; } /** @@ -91,11 +87,11 @@ __attribute__((always_inline)) static inline void mmu_ll_set_page_size(uint32_t mmu_id, uint32_t size) { // TODO: [ESP32C5] IDF-8658 (inherit from C6) - // uint8_t reg_val = (size == MMU_PAGE_64KB) ? 0 : - // (size == MMU_PAGE_32KB) ? 1 : - // (size == MMU_PAGE_16KB) ? 2 : - // (size == MMU_PAGE_8KB) ? 3 : 0; - // REG_SET_FIELD(SPI_MEM_MMU_POWER_CTRL_REG(0), SPI_MEM_MMU_PAGE_SIZE, reg_val); + uint8_t reg_val = (size == MMU_PAGE_64KB) ? 0 : + (size == MMU_PAGE_32KB) ? 1 : + (size == MMU_PAGE_16KB) ? 2 : + (size == MMU_PAGE_8KB) ? 3 : 0; + REG_SET_FIELD(SPI_MEM_MMU_POWER_CTRL_REG(0), SPI_MMU_PAGE_SIZE, reg_val); } /** @@ -113,11 +109,10 @@ __attribute__((always_inline)) static inline bool mmu_ll_check_valid_ext_vaddr_region(uint32_t mmu_id, uint32_t vaddr_start, uint32_t len, mmu_vaddr_t type) { // TODO: [ESP32C5] IDF-8658 (inherit from C6) - // (void)mmu_id; - // (void)type; - // uint32_t vaddr_end = vaddr_start + len - 1; - // return (SOC_ADDRESS_IN_IRAM0_CACHE(vaddr_start) && SOC_ADDRESS_IN_IRAM0_CACHE(vaddr_end)) || (SOC_ADDRESS_IN_DRAM0_CACHE(vaddr_start) && SOC_ADDRESS_IN_DRAM0_CACHE(vaddr_end)); - return (bool)0; + (void)mmu_id; + (void)type; + uint32_t vaddr_end = vaddr_start + len - 1; + return (SOC_ADDRESS_IN_IRAM0_CACHE(vaddr_start) && SOC_ADDRESS_IN_IRAM0_CACHE(vaddr_end)) || (SOC_ADDRESS_IN_DRAM0_CACHE(vaddr_start) && SOC_ADDRESS_IN_DRAM0_CACHE(vaddr_end)); } /** @@ -133,11 +128,10 @@ static inline bool mmu_ll_check_valid_ext_vaddr_region(uint32_t mmu_id, uint32_t static inline bool mmu_ll_check_valid_paddr_region(uint32_t mmu_id, uint32_t paddr_start, uint32_t len) { // TODO: [ESP32C5] IDF-8658 (inherit from C6) - // (void)mmu_id; - // return (paddr_start < (mmu_ll_get_page_size(mmu_id) * SOC_MMU_MAX_PADDR_PAGE_NUM)) && - // (len < (mmu_ll_get_page_size(mmu_id) * SOC_MMU_MAX_PADDR_PAGE_NUM)) && - // ((paddr_start + len - 1) < (mmu_ll_get_page_size(mmu_id) * SOC_MMU_MAX_PADDR_PAGE_NUM)); - return (bool)0; + (void)mmu_id; + return (paddr_start < (mmu_ll_get_page_size(mmu_id) * SOC_MMU_MAX_PADDR_PAGE_NUM)) && + (len < (mmu_ll_get_page_size(mmu_id) * SOC_MMU_MAX_PADDR_PAGE_NUM)) && + ((paddr_start + len - 1) < (mmu_ll_get_page_size(mmu_id) * SOC_MMU_MAX_PADDR_PAGE_NUM)); } /** @@ -153,27 +147,26 @@ __attribute__((always_inline)) static inline uint32_t mmu_ll_get_entry_id(uint32_t mmu_id, uint32_t vaddr) { // TODO: [ESP32C5] IDF-8658 (inherit from C6) - // (void)mmu_id; - // mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id); - // uint32_t shift_code = 0; - // switch (page_size) { - // case MMU_PAGE_64KB: - // shift_code = 16; - // break; - // case MMU_PAGE_32KB: - // shift_code = 15; - // break; - // case MMU_PAGE_16KB: - // shift_code = 14; - // break; - // case MMU_PAGE_8KB: - // shift_code = 13; - // break; - // default: - // HAL_ASSERT(shift_code); - // } - // return ((vaddr & SOC_MMU_VADDR_MASK) >> shift_code); - return (uint32_t)0; + (void)mmu_id; + mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id); + uint32_t shift_code = 0; + switch (page_size) { + case MMU_PAGE_64KB: + shift_code = 16; + break; + case MMU_PAGE_32KB: + shift_code = 15; + break; + case MMU_PAGE_16KB: + shift_code = 14; + break; + case MMU_PAGE_8KB: + shift_code = 13; + break; + default: + HAL_ASSERT(shift_code); + } + return ((vaddr & SOC_MMU_VADDR_MASK) >> shift_code); } /** @@ -190,28 +183,27 @@ __attribute__((always_inline)) static inline uint32_t mmu_ll_format_paddr(uint32_t mmu_id, uint32_t paddr, mmu_target_t target) { // TODO: [ESP32C5] IDF-8658 (inherit from C6) - // (void)mmu_id; - // (void)target; - // mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id); - // uint32_t shift_code = 0; - // switch (page_size) { - // case MMU_PAGE_64KB: - // shift_code = 16; - // break; - // case MMU_PAGE_32KB: - // shift_code = 15; - // break; - // case MMU_PAGE_16KB: - // shift_code = 14; - // break; - // case MMU_PAGE_8KB: - // shift_code = 13; - // break; - // default: - // HAL_ASSERT(shift_code); - // } - // return paddr >> shift_code; - return (uint32_t)0; + (void)mmu_id; + (void)target; + mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id); + uint32_t shift_code = 0; + switch (page_size) { + case MMU_PAGE_64KB: + shift_code = 16; + break; + case MMU_PAGE_32KB: + shift_code = 15; + break; + case MMU_PAGE_16KB: + shift_code = 14; + break; + case MMU_PAGE_8KB: + shift_code = 13; + break; + default: + HAL_ASSERT(shift_code); + } + return paddr >> shift_code; } /** @@ -225,15 +217,16 @@ static inline uint32_t mmu_ll_format_paddr(uint32_t mmu_id, uint32_t paddr, mmu_ __attribute__((always_inline)) static inline void mmu_ll_write_entry(uint32_t mmu_id, uint32_t entry_id, uint32_t mmu_val, mmu_target_t target) { // TODO: [ESP32C5] IDF-8658 (inherit from C6) - // (void)mmu_id; - // (void)target; - // uint32_t mmu_raw_value; - // if (mmu_ll_cache_encryption_enabled()) { - // mmu_val |= SOC_MMU_SENSITIVE; - // } - // // mmu_raw_value = mmu_val | SOC_MMU_VALID; - // REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id); - // REG_WRITE(SPI_MEM_MMU_ITEM_CONTENT_REG(0), mmu_raw_value); + (void)mmu_id; + (void)target; + uint32_t mmu_raw_value; + if (mmu_ll_cache_encryption_enabled()) { + mmu_val |= SOC_MMU_SENSITIVE; + } + + mmu_raw_value = mmu_val | SOC_MMU_VALID; + REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id); + REG_WRITE(SPI_MEM_MMU_ITEM_CONTENT_REG(0), mmu_raw_value); } /** @@ -246,20 +239,19 @@ __attribute__((always_inline)) static inline void mmu_ll_write_entry(uint32_t mm __attribute__((always_inline)) static inline uint32_t mmu_ll_read_entry(uint32_t mmu_id, uint32_t entry_id) { // TODO: [ESP32C5] IDF-8658 (inherit from C6) - // (void)mmu_id; - // uint32_t mmu_raw_value; - // uint32_t ret; - // REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id); - // mmu_raw_value = REG_READ(SPI_MEM_MMU_ITEM_CONTENT_REG(0)); - // if (mmu_ll_cache_encryption_enabled()) { - // mmu_raw_value &= ~SOC_MMU_SENSITIVE; - // } - // if (!(mmu_raw_value & SOC_MMU_VALID)) { - // return 0; - // } - // ret = mmu_raw_value & SOC_MMU_VALID_VAL_MASK; - // return ret; - return (uint32_t)0; + (void)mmu_id; + uint32_t mmu_raw_value; + uint32_t ret; + REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id); + mmu_raw_value = REG_READ(SPI_MEM_MMU_ITEM_CONTENT_REG(0)); + if (mmu_ll_cache_encryption_enabled()) { + mmu_raw_value &= ~SOC_MMU_SENSITIVE; + } + if (!(mmu_raw_value & SOC_MMU_VALID)) { + return 0; + } + ret = mmu_raw_value & SOC_MMU_VALID_VAL_MASK; + return ret; } /** @@ -271,9 +263,9 @@ __attribute__((always_inline)) static inline uint32_t mmu_ll_read_entry(uint32_t __attribute__((always_inline)) static inline void mmu_ll_set_entry_invalid(uint32_t mmu_id, uint32_t entry_id) { // TODO: [ESP32C5] IDF-8658 (inherit from C6) - // (void)mmu_id; - // REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id); - // REG_WRITE(SPI_MEM_MMU_ITEM_CONTENT_REG(0), SOC_MMU_INVALID); + (void)mmu_id; + REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id); + REG_WRITE(SPI_MEM_MMU_ITEM_CONTENT_REG(0), SOC_MMU_INVALID); } /** @@ -285,9 +277,9 @@ __attribute__((always_inline)) static inline void mmu_ll_unmap_all(uint32_t mmu_id) { // TODO: [ESP32C5] IDF-8658 (inherit from C6) - // for (int i = 0; i < SOC_MMU_ENTRY_NUM; i++) { - // mmu_ll_set_entry_invalid(mmu_id, i); - // } + for (int i = 0; i < SOC_MMU_ENTRY_NUM; i++) { + mmu_ll_set_entry_invalid(mmu_id, i); + } } /** @@ -301,11 +293,11 @@ static inline void mmu_ll_unmap_all(uint32_t mmu_id) static inline bool mmu_ll_check_entry_valid(uint32_t mmu_id, uint32_t entry_id) { // TODO: [ESP32C5] IDF-8658 (inherit from C6) - // (void)mmu_id; - // HAL_ASSERT(entry_id < SOC_MMU_ENTRY_NUM); - // // REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id); - // return (REG_READ(SPI_MEM_MMU_ITEM_CONTENT_REG(0)) & SOC_MMU_VALID) ? true : false; - return (bool)0; + (void)mmu_id; + HAL_ASSERT(entry_id < SOC_MMU_ENTRY_NUM); + + REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id); + return (REG_READ(SPI_MEM_MMU_ITEM_CONTENT_REG(0)) & SOC_MMU_VALID) ? true : false; } /** @@ -319,9 +311,8 @@ static inline bool mmu_ll_check_entry_valid(uint32_t mmu_id, uint32_t entry_id) static inline mmu_target_t mmu_ll_get_entry_target(uint32_t mmu_id, uint32_t entry_id) { // TODO: [ESP32C5] IDF-8658 (inherit from C6) - // (void)mmu_id; - // return MMU_TARGET_FLASH0; - return (mmu_target_t)0; + (void)mmu_id; + return MMU_TARGET_FLASH0; } /** @@ -335,29 +326,30 @@ static inline mmu_target_t mmu_ll_get_entry_target(uint32_t mmu_id, uint32_t ent static inline uint32_t mmu_ll_entry_id_to_paddr_base(uint32_t mmu_id, uint32_t entry_id) { // TODO: [ESP32C5] IDF-8658 (inherit from C6) - // (void)mmu_id; - // HAL_ASSERT(entry_id < SOC_MMU_ENTRY_NUM); - // // mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id); - // uint32_t shift_code = 0; - // switch (page_size) { - // case MMU_PAGE_64KB: - // shift_code = 16; - // break; - // case MMU_PAGE_32KB: - // shift_code = 15; - // break; - // case MMU_PAGE_16KB: - // shift_code = 14; - // break; - // case MMU_PAGE_8KB: - // shift_code = 13; - // break; - // default: - // HAL_ASSERT(shift_code); - // } - // // REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id); - // return (REG_READ(SPI_MEM_MMU_ITEM_CONTENT_REG(0)) & SOC_MMU_VALID_VAL_MASK) << shift_code; - return (uint32_t)0; + (void)mmu_id; + HAL_ASSERT(entry_id < SOC_MMU_ENTRY_NUM); + + mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id); + uint32_t shift_code = 0; + switch (page_size) { + case MMU_PAGE_64KB: + shift_code = 16; + break; + case MMU_PAGE_32KB: + shift_code = 15; + break; + case MMU_PAGE_16KB: + shift_code = 14; + break; + case MMU_PAGE_8KB: + shift_code = 13; + break; + default: + HAL_ASSERT(shift_code); + } + + REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id); + return (REG_READ(SPI_MEM_MMU_ITEM_CONTENT_REG(0)) & SOC_MMU_VALID_VAL_MASK) << shift_code; } /** @@ -374,19 +366,19 @@ static inline uint32_t mmu_ll_entry_id_to_paddr_base(uint32_t mmu_id, uint32_t e static inline int mmu_ll_find_entry_id_based_on_map_value(uint32_t mmu_id, uint32_t mmu_val, mmu_target_t target) { // TODO: [ESP32C5] IDF-8658 (inherit from C6) - // (void)mmu_id; - // for (int i = 0; i < SOC_MMU_ENTRY_NUM; i++) { - // if (mmu_ll_check_entry_valid(mmu_id, i)) { - // if (mmu_ll_get_entry_target(mmu_id, i) == target) { - // REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), i); - // if ((REG_READ(SPI_MEM_MMU_ITEM_CONTENT_REG(0)) & SOC_MMU_VALID_VAL_MASK) == mmu_val) { - // return i; - // } - // } - // } - // } - // // return -1; - return (int)0; + (void)mmu_id; + for (int i = 0; i < SOC_MMU_ENTRY_NUM; i++) { + if (mmu_ll_check_entry_valid(mmu_id, i)) { + if (mmu_ll_get_entry_target(mmu_id, i) == target) { + REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), i); + if ((REG_READ(SPI_MEM_MMU_ITEM_CONTENT_REG(0)) & SOC_MMU_VALID_VAL_MASK) == mmu_val) { + return i; + } + } + } + } + + return -1; } /** @@ -399,35 +391,35 @@ static inline int mmu_ll_find_entry_id_based_on_map_value(uint32_t mmu_id, uint3 static inline uint32_t mmu_ll_entry_id_to_vaddr_base(uint32_t mmu_id, uint32_t entry_id, mmu_vaddr_t type) { // TODO: [ESP32C5] IDF-8658 (inherit from C6) - // (void)mmu_id; - // mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id); - // uint32_t shift_code = 0; - // // switch (page_size) { - // case MMU_PAGE_64KB: - // shift_code = 16; - // break; - // case MMU_PAGE_32KB: - // shift_code = 15; - // break; - // case MMU_PAGE_16KB: - // shift_code = 14; - // break; - // case MMU_PAGE_8KB: - // shift_code = 13; - // break; - // default: - // HAL_ASSERT(shift_code); - // } - // uint32_t laddr = entry_id << shift_code; - // // /** - // * For `mmu_ll_laddr_to_vaddr`, target is for compatibility on this chip. - // * Here we just pass MMU_TARGET_FLASH0 to get vaddr - // */ - // return mmu_ll_laddr_to_vaddr(laddr, type, MMU_TARGET_FLASH0); - return (uint32_t)0; + (void)mmu_id; + mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id); + uint32_t shift_code = 0; + + switch (page_size) { + case MMU_PAGE_64KB: + shift_code = 16; + break; + case MMU_PAGE_32KB: + shift_code = 15; + break; + case MMU_PAGE_16KB: + shift_code = 14; + break; + case MMU_PAGE_8KB: + shift_code = 13; + break; + default: + HAL_ASSERT(shift_code); + } + uint32_t laddr = entry_id << shift_code; + + /** + * For `mmu_ll_laddr_to_vaddr`, target is for compatibility on this chip. + * Here we just pass MMU_TARGET_FLASH0 to get vaddr + */ + return mmu_ll_laddr_to_vaddr(laddr, type, MMU_TARGET_FLASH0); } #ifdef __cplusplus - return (uint32_t)0; } #endif diff --git a/components/hal/esp32c5/include/hal/modem_lpcon_ll.h b/components/hal/esp32c5/include/hal/modem_lpcon_ll.h new file mode 100644 index 0000000000..6a28de5f73 --- /dev/null +++ b/components/hal/esp32c5/include/hal/modem_lpcon_ll.h @@ -0,0 +1,293 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +// The LL layer for ESP32-C5 MODEM LPCON register operations + +#pragma once + +#include +#include +#include "soc/soc.h" +#include "hal/assert.h" +#include "modem/modem_lpcon_struct.h" +#include "hal/modem_clock_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_enable_test_clk(modem_lpcon_dev_t *hw, bool en) +{ + hw->test_conf.clk_en = en; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_enable_ble_rtc_timer_slow_osc(modem_lpcon_dev_t *hw, bool en) +{ + hw->lp_timer_conf.clk_lp_timer_sel_osc_slow = en; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_enable_ble_rtc_timer_fast_osc(modem_lpcon_dev_t *hw, bool en) +{ + hw->lp_timer_conf.clk_lp_timer_sel_osc_fast = en; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_enable_ble_rtc_timer_main_xtal(modem_lpcon_dev_t *hw, bool en) +{ + hw->lp_timer_conf.clk_lp_timer_sel_xtal = en; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_enable_ble_rtc_timer_32k_xtal(modem_lpcon_dev_t *hw, bool en) +{ + hw->lp_timer_conf.clk_lp_timer_sel_xtal32k = en; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_set_ble_rtc_timer_divisor_value(modem_lpcon_dev_t *hw, uint32_t value) +{ + hw->lp_timer_conf.clk_lp_timer_div_num = value; +} + +__attribute__((always_inline)) +static inline uint32_t modem_lpcon_ll_get_ble_rtc_timer_divisor_value(modem_lpcon_dev_t *hw) +{ + return hw->lp_timer_conf.clk_lp_timer_div_num; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_enable_coex_lpclk_slow_osc(modem_lpcon_dev_t *hw, bool en) +{ + hw->coex_lp_clk_conf.clk_coex_lp_sel_osc_slow = en; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_enable_coex_lpclk_fast_osc(modem_lpcon_dev_t *hw, bool en) +{ + hw->coex_lp_clk_conf.clk_coex_lp_sel_osc_fast = en; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_enable_coex_lpclk_main_xtal(modem_lpcon_dev_t *hw, bool en) +{ + hw->coex_lp_clk_conf.clk_coex_lp_sel_xtal = en; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_enable_coex_lpclk_32k_xtal(modem_lpcon_dev_t *hw, bool en) +{ + hw->coex_lp_clk_conf.clk_coex_lp_sel_xtal32k = en; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_set_coex_lpclk_divisor_value(modem_lpcon_dev_t *hw, uint32_t value) +{ + hw->coex_lp_clk_conf.clk_coex_lp_div_num = value; +} + +__attribute__((always_inline)) +static inline uint32_t modem_lpcon_ll_get_coex_lpclk_divisor_value(modem_lpcon_dev_t *hw) +{ + return hw->coex_lp_clk_conf.clk_coex_lp_div_num; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_enable_wifi_lpclk_slow_osc(modem_lpcon_dev_t *hw, bool en) +{ + hw->wifi_lp_clk_conf.clk_wifipwr_lp_sel_osc_slow = en; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_enable_wifi_lpclk_fast_osc(modem_lpcon_dev_t *hw, bool en) +{ + hw->wifi_lp_clk_conf.clk_wifipwr_lp_sel_osc_fast = en; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_enable_wifi_lpclk_main_xtal(modem_lpcon_dev_t *hw, bool en) +{ + hw->wifi_lp_clk_conf.clk_wifipwr_lp_sel_xtal = en; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_enable_wifi_lpclk_32k_xtal(modem_lpcon_dev_t *hw, bool en) +{ + hw->wifi_lp_clk_conf.clk_wifipwr_lp_sel_xtal32k = en; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_set_wifi_lpclk_divisor_value(modem_lpcon_dev_t *hw, uint32_t value) +{ + hw->wifi_lp_clk_conf.clk_wifipwr_lp_div_num = value; +} + +__attribute__((always_inline)) +static inline uint32_t modem_lpcon_ll_get_wifi_lpclk_divisor_value(modem_lpcon_dev_t *hw) +{ + return hw->wifi_lp_clk_conf.clk_wifipwr_lp_div_num; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_enable_i2c_master_160m_clock(modem_lpcon_dev_t *hw, bool en) +{ + hw->i2c_mst_clk_conf.clk_i2c_mst_sel_160m = en; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_select_modem_32k_clock_source(modem_lpcon_dev_t *hw, uint32_t src) +{ + hw->modem_32k_clk_conf.clk_modem_32k_sel = src; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_enable_wifipwr_clock(modem_lpcon_dev_t *hw, bool en) +{ + hw->clk_conf.clk_wifipwr_en = en; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_enable_coex_clock(modem_lpcon_dev_t *hw, bool en) +{ + hw->clk_conf.clk_coex_en = en; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_enable_i2c_master_clock(modem_lpcon_dev_t *hw, bool en) +{ + hw->clk_conf.clk_i2c_mst_en = en; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_enable_ble_rtc_timer_clock(modem_lpcon_dev_t *hw, bool en) +{ + hw->clk_conf.clk_lp_timer_en = en; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_enable_wifipwr_force_clock(modem_lpcon_dev_t *hw, bool en) +{ + hw->clk_conf_force_on.clk_wifipwr_fo = en; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_enable_coex_force_clock(modem_lpcon_dev_t *hw, bool en) +{ + hw->clk_conf_force_on.clk_coex_fo = en; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_enable_i2c_master_force_clock(modem_lpcon_dev_t *hw, bool en) +{ + hw->clk_conf_force_on.clk_i2c_mst_fo = en; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_enable_ble_rtc_timer_force_clock(modem_lpcon_dev_t *hw, bool en) +{ + hw->clk_conf_force_on.clk_lp_timer_fo = en; +} + +__attribute__((always_inline)) +static inline uint32_t modem_lpcon_ll_get_wifipwr_icg_bitmap(modem_lpcon_dev_t *hw) +{ + return hw->clk_conf_power_st.clk_wifipwr_st_map; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_set_wifipwr_icg_bitmap(modem_lpcon_dev_t *hw, uint32_t bitmap) +{ + hw->clk_conf_power_st.clk_wifipwr_st_map = bitmap; +} + +__attribute__((always_inline)) +static inline uint32_t modem_lpcon_ll_get_coex_icg_bitmap(modem_lpcon_dev_t *hw) +{ + return hw->clk_conf_power_st.clk_coex_st_map; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_set_coex_icg_bitmap(modem_lpcon_dev_t *hw, uint32_t bitmap) +{ + hw->clk_conf_power_st.clk_coex_st_map = bitmap; +} + +__attribute__((always_inline)) +static inline uint32_t modem_lpcon_ll_get_i2c_master_icg_bitmap(modem_lpcon_dev_t *hw) +{ + return hw->clk_conf_power_st.clk_i2c_mst_st_map; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_set_i2c_master_icg_bitmap(modem_lpcon_dev_t *hw, uint32_t bitmap) +{ + hw->clk_conf_power_st.clk_i2c_mst_st_map = bitmap; +} + +__attribute__((always_inline)) +static inline uint32_t modem_lpcon_ll_get_lp_apb_icg_bitmap(modem_lpcon_dev_t *hw) +{ + return hw->clk_conf_power_st.clk_lp_apb_st_map; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_set_lp_apb_icg_bitmap(modem_lpcon_dev_t *hw, uint32_t bitmap) +{ + hw->clk_conf_power_st.clk_lp_apb_st_map = bitmap; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_reset_wifipwr(modem_lpcon_dev_t *hw) +{ + hw->rst_conf.rst_wifipwr = 1; + hw->rst_conf.rst_wifipwr = 0; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_reset_coex(modem_lpcon_dev_t *hw) +{ + hw->rst_conf.rst_coex = 1; + hw->rst_conf.rst_coex = 0; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_reset_i2c_master(modem_lpcon_dev_t *hw) +{ + hw->rst_conf.rst_i2c_mst = 1; + hw->rst_conf.rst_i2c_mst = 0; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_reset_ble_rtc_timer(modem_lpcon_dev_t *hw) +{ + hw->rst_conf.rst_lp_timer = 1; + hw->rst_conf.rst_lp_timer = 0; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_reset_all(modem_lpcon_dev_t *hw) +{ + hw->rst_conf.val = 0xf; + hw->rst_conf.val = 0; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_set_pwr_tick_target(modem_lpcon_dev_t *hw, uint32_t val) +{ + hw->tick_conf.modem_pwr_tick_target = val; +} + +__attribute__((always_inline)) +static inline uint32_t modem_lpcon_ll_get_date(modem_lpcon_dev_t *hw) +{ + return hw->date.val; +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32c5/include/hal/modem_syscon_ll.h b/components/hal/esp32c5/include/hal/modem_syscon_ll.h new file mode 100644 index 0000000000..5dae940aea --- /dev/null +++ b/components/hal/esp32c5/include/hal/modem_syscon_ll.h @@ -0,0 +1,630 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +// The LL layer for ESP32-C5 MODEM SYSCON register operations + +#pragma once + +#include +#include +#include "soc/soc.h" +#include "hal/assert.h" +#include "modem/modem_syscon_struct.h" +#include "hal/modem_clock_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_test_clk(modem_syscon_dev_t *hw, bool en) +{ + hw->test_conf.clk_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_data_dump_mux_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf.clk_data_dump_mux = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_etm_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf.clk_etm_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_ieee802154_apb_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf.clk_zb_apb_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_ieee802154_mac_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf.clk_zbmac_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_modem_sec_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf.clk_modem_sec_en = en; + hw->clk_conf.clk_modem_sec_ecb_en = en; + hw->clk_conf.clk_modem_sec_ccm_en = en; + hw->clk_conf.clk_modem_sec_bah_en = en; + hw->clk_conf.clk_modem_sec_apb_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_ble_timer_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf.clk_ble_timer_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_data_dump_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf.clk_data_dump_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_etm_force_clock(modem_syscon_dev_t *hw) +{ + hw->clk_conf_force_on.clk_etm_fo = 1; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_ieee802154_apb_clock_force(modem_syscon_dev_t *hw) +{ + hw->clk_conf_force_on.clk_zbmac_apb_fo = 1; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_ieee802154_mac_clock_force(modem_syscon_dev_t *hw) +{ + hw->clk_conf_force_on.clk_zbmac_fo = 1; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_modem_sec_force_clock(modem_syscon_dev_t *hw) +{ + hw->clk_conf_force_on.clk_modem_sec_fo = 1; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_ble_timer_force_clock(modem_syscon_dev_t *hw) +{ + hw->clk_conf_force_on.clk_ble_timer_fo = 1; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_data_dump_force_clock(modem_syscon_dev_t *hw) +{ + hw->clk_conf_force_on.clk_data_dump_fo = 1; +} + +__attribute__((always_inline)) +static inline uint32_t modem_syscon_ll_get_ieee802154_icg_bitmap(modem_syscon_dev_t *hw) +{ + return hw->clk_conf_power_st.clk_zb_st_map; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_set_ieee802154_icg_bitmap(modem_syscon_dev_t *hw, uint32_t bitmap) +{ + hw->clk_conf_power_st.clk_zb_st_map = bitmap; +} + +__attribute__((always_inline)) +static inline uint32_t modem_syscon_ll_get_fe_icg_bitmap(modem_syscon_dev_t *hw) +{ + return hw->clk_conf_power_st.clk_fe_st_map; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_set_fe_icg_bitmap(modem_syscon_dev_t *hw, uint32_t bitmap) +{ + hw->clk_conf_power_st.clk_fe_st_map = bitmap; +} + +__attribute__((always_inline)) +static inline uint32_t modem_syscon_ll_get_bt_icg_bitmap(modem_syscon_dev_t *hw) +{ + return hw->clk_conf_power_st.clk_bt_st_map; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_set_bt_icg_bitmap(modem_syscon_dev_t *hw, uint32_t bitmap) +{ + hw->clk_conf_power_st.clk_bt_st_map = bitmap; +} + +__attribute__((always_inline)) +static inline uint32_t modem_syscon_ll_get_wifi_icg_bitmap(modem_syscon_dev_t *hw) +{ + return hw->clk_conf_power_st.clk_wifi_st_map; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_set_wifi_icg_bitmap(modem_syscon_dev_t *hw, uint32_t bitmap) +{ + hw->clk_conf_power_st.clk_wifi_st_map = bitmap; +} + +__attribute__((always_inline)) +static inline uint32_t modem_syscon_ll_get_modem_periph_icg_bitmap(modem_syscon_dev_t *hw) +{ + return hw->clk_conf_power_st.clk_modem_peri_st_map; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_set_modem_periph_icg_bitmap(modem_syscon_dev_t *hw, uint32_t bitmap) +{ + hw->clk_conf_power_st.clk_modem_peri_st_map = bitmap; +} + +__attribute__((always_inline)) +static inline uint32_t modem_syscon_ll_get_modem_apb_icg_bitmap(modem_syscon_dev_t *hw) +{ + return hw->clk_conf_power_st.clk_modem_apb_st_map; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_set_modem_apb_icg_bitmap(modem_syscon_dev_t *hw, uint32_t bitmap) +{ + hw->clk_conf_power_st.clk_modem_apb_st_map = bitmap; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_reset_wifibb(modem_syscon_dev_t *hw) +{ + hw->modem_rst_conf.rst_wifibb = 1; + hw->modem_rst_conf.rst_wifibb = 0; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_reset_wifimac(modem_syscon_dev_t *hw) +{ + hw->modem_rst_conf.rst_wifimac = 1; + hw->modem_rst_conf.rst_wifimac = 0; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_reset_fe(modem_syscon_dev_t *hw) +{ + hw->modem_rst_conf.rst_fe = 1; + hw->modem_rst_conf.rst_fe = 0; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_reset_btmac_apb(modem_syscon_dev_t *hw) +{ + hw->modem_rst_conf.rst_btmac_apb = 1; + hw->modem_rst_conf.rst_btmac_apb = 0; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_reset_btmac(modem_syscon_dev_t *hw) +{ + hw->modem_rst_conf.rst_btmac = 1; + hw->modem_rst_conf.rst_btmac = 0; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_reset_btbb_apb(modem_syscon_dev_t *hw) +{ + hw->modem_rst_conf.rst_btbb_apb = 1; + hw->modem_rst_conf.rst_btbb_apb = 0; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_reset_btbb(modem_syscon_dev_t *hw) +{ + hw->modem_rst_conf.rst_btbb = 1; + hw->modem_rst_conf.rst_btbb = 0; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_reset_etm(modem_syscon_dev_t *hw) +{ + hw->modem_rst_conf.rst_etm = 1; + hw->modem_rst_conf.rst_etm = 0; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_reset_zbmac(modem_syscon_dev_t *hw) +{ + hw->modem_rst_conf.rst_zbmac = 1; + hw->modem_rst_conf.rst_zbmac = 0; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_reset_modem_sec(modem_syscon_dev_t *hw) +{ + hw->modem_rst_conf.rst_modem_ecb = 1; + hw->modem_rst_conf.rst_modem_ccm = 1; + hw->modem_rst_conf.rst_modem_bah = 1; + hw->modem_rst_conf.rst_modem_sec = 1; + hw->modem_rst_conf.rst_modem_ecb = 0; + hw->modem_rst_conf.rst_modem_ccm = 0; + hw->modem_rst_conf.rst_modem_bah = 0; + hw->modem_rst_conf.rst_modem_sec = 0; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_reset_ble_timer(modem_syscon_dev_t *hw) +{ + hw->modem_rst_conf.rst_ble_timer = 1; + hw->modem_rst_conf.rst_ble_timer = 0; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_reset_data_dump(modem_syscon_dev_t *hw) +{ + hw->modem_rst_conf.rst_data_dump = 1; + hw->modem_rst_conf.rst_data_dump = 0; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_reset_all(modem_syscon_dev_t *hw) +{ + hw->modem_rst_conf.val = 0xffffffff; + hw->modem_rst_conf.val = 0; +} + + +__attribute__((always_inline)) +static inline void modem_syscon_ll_clk_conf1_configure(modem_syscon_dev_t *hw, bool en, uint32_t mask) +{ + if(en){ + hw->clk_conf1.val = hw->clk_conf1.val | mask; + } else { + hw->clk_conf1.val = hw->clk_conf1.val & ~mask; + } +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_clk_wifibb_configure(modem_syscon_dev_t *hw, bool en) +{ + /* Configure + clk_wifibb_22m / clk_wifibb_40m / clk_wifibb_44m / clk_wifibb_80m + clk_wifibb_40x / clk_wifibb_80x / clk_wifibb_40x1 / clk_wifibb_80x1 + clk_wifibb_160x1 + */ + modem_syscon_ll_clk_conf1_configure(hw, en, 0x1ff); +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_wifibb_22m_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1.clk_wifibb_22m_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_wifibb_40m_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1.clk_wifibb_40m_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_wifibb_44m_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1.clk_wifibb_44m_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_wifibb_80m_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1.clk_wifibb_80m_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_wifibb_40x_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1.clk_wifibb_40x_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_wifibb_80x_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1.clk_wifibb_80x_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_wifibb_40x1_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1.clk_wifibb_40x1_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_wifibb_80x1_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1.clk_wifibb_80x1_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_wifibb_160x1_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1.clk_wifibb_160x1_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_wifibb_480m_clock(modem_syscon_dev_t *hw, bool en) +{ + HAL_ASSERT(0 && "not implemented yet"); + // hw->clk_conf1.clk_wifibb_480m_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_wifi_mac_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1.clk_wifimac_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_wifi_apb_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1.clk_wifi_apb_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_fe_20m_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1.clk_fe_20m_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_fe_40m_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1.clk_fe_40m_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_fe_80m_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1.clk_fe_80m_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_fe_160m_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1.clk_fe_160m_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_fe_cal_160m_clock(modem_syscon_dev_t *hw, bool en) +{ + HAL_ASSERT(0 && "not implemented yet"); + // hw->clk_conf1.clk_fe_cal_160m_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_fe_apb_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1.clk_fe_apb_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_bt_apb_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1.clk_bt_apb_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_bt_mac_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1.clk_btmac_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_bt_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1.clk_btbb_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_fe_480m_clock(modem_syscon_dev_t *hw, bool en) +{ + HAL_ASSERT(0 && "not implemented yet"); + // hw->clk_conf1.clk_fe_480m_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_fe_anamode_40m_clock(modem_syscon_dev_t *hw, bool en) +{ + HAL_ASSERT(0 && "not implemented yet"); + // hw->clk_conf1.clk_fe_anamode_40m_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_fe_anamode_80m_clock(modem_syscon_dev_t *hw, bool en) +{ + HAL_ASSERT(0 && "not implemented yet"); + // hw->clk_conf1.clk_fe_anamode_80m_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_fe_anamode_160m_clock(modem_syscon_dev_t *hw, bool en) +{ + HAL_ASSERT(0 && "not implemented yet"); + // hw->clk_conf1.clk_fe_anamode_160m_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_wifibb_22m_force_clock(modem_syscon_dev_t *hw, bool en) +{ + HAL_ASSERT(0 && "not implemented yet"); + // hw->clk_conf1_force_on.clk_wifibb_22m_fo = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_wifibb_40m_force_clock(modem_syscon_dev_t *hw, bool en) +{ + HAL_ASSERT(0 && "not implemented yet"); + // hw->clk_conf1_force_on.clk_wifibb_40m_fo = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_wifibb_44m_force_clock(modem_syscon_dev_t *hw, bool en) +{ + HAL_ASSERT(0 && "not implemented yet"); + // hw->clk_conf1_force_on.clk_wifibb_44m_fo = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_wifibb_80m_force_clock(modem_syscon_dev_t *hw, bool en) +{ + HAL_ASSERT(0 && "not implemented yet"); + // hw->clk_conf1_force_on.clk_wifibb_80m_fo = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_wifibb_40x_force_clock(modem_syscon_dev_t *hw, bool en) +{ + HAL_ASSERT(0 && "not implemented yet"); + // hw->clk_conf1_force_on.clk_wifibb_40x_fo = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_wifibb_80x_force_clock(modem_syscon_dev_t *hw, bool en) +{ + HAL_ASSERT(0 && "not implemented yet"); + // hw->clk_conf1_force_on.clk_wifibb_80x_fo = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_wifibb_40x1_force_clock(modem_syscon_dev_t *hw, bool en) +{ + HAL_ASSERT(0 && "not implemented yet"); + // hw->clk_conf1_force_on.clk_wifibb_40x1_fo = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_wifibb_80x1_force_clock(modem_syscon_dev_t *hw, bool en) +{ + HAL_ASSERT(0 && "not implemented yet"); + // hw->clk_conf1_force_on.clk_wifibb_80x1_fo = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_wifibb_160x1_force_clock(modem_syscon_dev_t *hw, bool en) +{ + HAL_ASSERT(0 && "not implemented yet"); + // hw->clk_conf1_force_on.clk_wifibb_160x1_fo = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_wifibb_480m_force_clock(modem_syscon_dev_t *hw, bool en) +{ + HAL_ASSERT(0 && "not implemented yet"); +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_wifi_mac_force_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf_force_on.clk_wifimac_fo = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_wifi_apb_force_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf_force_on.clk_wifi_apb_fo = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_fe_20m_force_clock(modem_syscon_dev_t *hw, bool en) +{ + HAL_ASSERT(0 && "not implemented yet"); + // hw->clk_conf1_force_on.clk_fe_20m_fo = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_fe_40m_force_clock(modem_syscon_dev_t *hw, bool en) +{ + HAL_ASSERT(0 && "not implemented yet"); + // hw->clk_conf1_force_on.clk_fe_40m_fo = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_fe_80m_force_clock(modem_syscon_dev_t *hw, bool en) +{ + HAL_ASSERT(0 && "not implemented yet"); + // hw->clk_conf1_force_on.clk_fe_80m_fo = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_fe_160m_force_clock(modem_syscon_dev_t *hw, bool en) +{ + HAL_ASSERT(0 && "not implemented yet"); + // hw->clk_conf1_force_on.clk_fe_160m_fo = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_fe_cal_160m_force_clock(modem_syscon_dev_t *hw, bool en) +{ + HAL_ASSERT(0 && "not implemented yet"); + // hw->clk_conf1_force_on.clk_fe_cal_160m_fo = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_fe_apb_force_clock(modem_syscon_dev_t *hw, bool en) +{ + HAL_ASSERT(0 && "not implemented yet"); + // hw->clk_conf1_force_on.clk_fe_apb_fo = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_bt_apb_force_clock(modem_syscon_dev_t *hw, bool en) +{ + HAL_ASSERT(0 && "not implemented yet"); + // hw->clk_conf1_force_on.clk_bt_apb_fo = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_bt_force_clock(modem_syscon_dev_t *hw, bool en) +{ + HAL_ASSERT(0 && "not implemented yet"); + // hw->clk_conf1_force_on.clk_bt_fo = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_fe_480m_force_clock(modem_syscon_dev_t *hw, bool en) +{ + HAL_ASSERT(0 && "not implemented yet"); + // hw->clk_conf1_force_on.clk_fe_480m_fo = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_fe_anamode_40m_force_clock(modem_syscon_dev_t *hw, bool en) +{ + HAL_ASSERT(0 && "not implemented yet"); + // hw->clk_conf1_force_on.clk_fe_anamode_40m_fo = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_fe_anamode_80m_force_clock(modem_syscon_dev_t *hw, bool en) +{ + HAL_ASSERT(0 && "not implemented yet"); + // hw->clk_conf1_force_on.clk_fe_anamode_80m_fo = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_fe_anamode_160m_force_clock(modem_syscon_dev_t *hw, bool en) +{ + HAL_ASSERT(0 && "not implemented yet"); + // hw->clk_conf1_force_on.clk_fe_anamode_160m_fo = en; +} + +__attribute__((always_inline)) +static inline uint32_t modem_syscon_ll_get_date(modem_syscon_dev_t *hw) +{ + return hw->date.val; +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32c5/include/hal/mwdt_ll.h b/components/hal/esp32c5/include/hal/mwdt_ll.h index 48e6af7d27..ab70f2cffd 100644 --- a/components/hal/esp32c5/include/hal/mwdt_ll.h +++ b/components/hal/esp32c5/include/hal/mwdt_ll.h @@ -67,8 +67,9 @@ ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_3_2us == TIMG_WDT_RESET_LENGTH_3200_NS, " */ FORCE_INLINE_ATTR void mwdt_ll_enable(timg_dev_t *hw) { - // TODO: [ESP32C5] IDF-8650 (inherit from C6) + // TODO: [ESP32C5] IDF-8650 // hw->wdtconfig0.wdt_en = 1; + abort(); } /** @@ -81,8 +82,9 @@ FORCE_INLINE_ATTR void mwdt_ll_enable(timg_dev_t *hw) */ FORCE_INLINE_ATTR void mwdt_ll_disable(timg_dev_t *hw) { - // TODO: [ESP32C5] IDF-8650 (inherit from C6) + // TODO: [ESP32C5] IDF-8650 // hw->wdtconfig0.wdt_en = 0; + abort(); } /** @@ -93,8 +95,9 @@ FORCE_INLINE_ATTR void mwdt_ll_disable(timg_dev_t *hw) */ FORCE_INLINE_ATTR bool mwdt_ll_check_if_enabled(timg_dev_t *hw) { - // TODO: [ESP32C5] IDF-8650 (inherit from C6) + // TODO: [ESP32C5] IDF-8650 // return (hw->wdtconfig0.wdt_en) ? true : false; + abort(); return (bool)0; } @@ -108,7 +111,7 @@ FORCE_INLINE_ATTR bool mwdt_ll_check_if_enabled(timg_dev_t *hw) */ FORCE_INLINE_ATTR void mwdt_ll_config_stage(timg_dev_t *hw, wdt_stage_t stage, uint32_t timeout, wdt_stage_action_t behavior) { - // TODO: [ESP32C5] IDF-8650 (inherit from C6) + // TODO: [ESP32C5] IDF-8650 // switch (stage) { // case WDT_STAGE0: // hw->wdtconfig0.wdt_stg0 = behavior; @@ -132,6 +135,7 @@ FORCE_INLINE_ATTR void mwdt_ll_config_stage(timg_dev_t *hw, wdt_stage_t stage, u // } // //Config registers are updated asynchronously // hw->wdtconfig0.wdt_conf_update_en = 1; + abort(); } /** @@ -142,7 +146,7 @@ FORCE_INLINE_ATTR void mwdt_ll_config_stage(timg_dev_t *hw, wdt_stage_t stage, u */ FORCE_INLINE_ATTR void mwdt_ll_disable_stage(timg_dev_t *hw, uint32_t stage) { - // TODO: [ESP32C5] IDF-8650 (inherit from C6) + // TODO: [ESP32C5] IDF-8650 // switch (stage) { // case WDT_STAGE0: // hw->wdtconfig0.wdt_stg0 = WDT_STAGE_ACTION_OFF; @@ -162,6 +166,7 @@ FORCE_INLINE_ATTR void mwdt_ll_disable_stage(timg_dev_t *hw, uint32_t stage) // } // //Config registers are updated asynchronously // hw->wdtconfig0.wdt_conf_update_en = 1; + abort(); } /** @@ -172,10 +177,11 @@ FORCE_INLINE_ATTR void mwdt_ll_disable_stage(timg_dev_t *hw, uint32_t stage) */ FORCE_INLINE_ATTR void mwdt_ll_set_cpu_reset_length(timg_dev_t *hw, wdt_reset_sig_length_t length) { - // TODO: [ESP32C5] IDF-8650 (inherit from C6) + // TODO: [ESP32C5] IDF-8650 // hw->wdtconfig0.wdt_cpu_reset_length = length; // //Config registers are updated asynchronously // hw->wdtconfig0.wdt_conf_update_en = 1; + abort(); } /** @@ -186,10 +192,11 @@ FORCE_INLINE_ATTR void mwdt_ll_set_cpu_reset_length(timg_dev_t *hw, wdt_reset_si */ FORCE_INLINE_ATTR void mwdt_ll_set_sys_reset_length(timg_dev_t *hw, wdt_reset_sig_length_t length) { - // TODO: [ESP32C5] IDF-8650 (inherit from C6) + // TODO: [ESP32C5] IDF-8650 // hw->wdtconfig0.wdt_sys_reset_length = length; // //Config registers are updated asynchronously // hw->wdtconfig0.wdt_conf_update_en = 1; + abort(); } /** @@ -204,10 +211,11 @@ FORCE_INLINE_ATTR void mwdt_ll_set_sys_reset_length(timg_dev_t *hw, wdt_reset_si */ FORCE_INLINE_ATTR void mwdt_ll_set_flashboot_en(timg_dev_t *hw, bool enable) { - // TODO: [ESP32C5] IDF-8650 (inherit from C6) + // TODO: [ESP32C5] IDF-8650 // hw->wdtconfig0.wdt_flashboot_mod_en = (enable) ? 1 : 0; // //Config registers are updated asynchronously // hw->wdtconfig0.wdt_conf_update_en = 1; + abort(); } /** @@ -218,12 +226,13 @@ FORCE_INLINE_ATTR void mwdt_ll_set_flashboot_en(timg_dev_t *hw, bool enable) */ FORCE_INLINE_ATTR void mwdt_ll_set_prescaler(timg_dev_t *hw, uint32_t prescaler) { - // TODO: [ESP32C5] IDF-8650 (inherit from C6) + // TODO: [ESP32C5] IDF-8650 // // In case the compiler optimise a 32bit instruction (e.g. s32i) into 8/16bit instruction (e.g. s8i, which is not allowed to access a register) // // We take care of the "read-modify-write" procedure by ourselves. // HAL_FORCE_MODIFY_U32_REG_FIELD(hw->wdtconfig1, wdt_clk_prescale, prescaler); // //Config registers are updated asynchronously // hw->wdtconfig0.wdt_conf_update_en = 1; + abort(); } /** @@ -235,8 +244,9 @@ FORCE_INLINE_ATTR void mwdt_ll_set_prescaler(timg_dev_t *hw, uint32_t prescaler) */ FORCE_INLINE_ATTR void mwdt_ll_feed(timg_dev_t *hw) { - // TODO: [ESP32C5] IDF-8650 (inherit from C6) + // TODO: [ESP32C5] IDF-8650 // hw->wdtfeed.wdt_feed = 1; + abort(); } /** @@ -248,8 +258,9 @@ FORCE_INLINE_ATTR void mwdt_ll_feed(timg_dev_t *hw) */ FORCE_INLINE_ATTR void mwdt_ll_write_protect_enable(timg_dev_t *hw) { - // TODO: [ESP32C5] IDF-8650 (inherit from C6) + // TODO: [ESP32C5] IDF-8650 // hw->wdtwprotect.wdt_wkey = 0; + abort(); } /** @@ -259,8 +270,9 @@ FORCE_INLINE_ATTR void mwdt_ll_write_protect_enable(timg_dev_t *hw) */ FORCE_INLINE_ATTR void mwdt_ll_write_protect_disable(timg_dev_t *hw) { - // TODO: [ESP32C5] IDF-8650 (inherit from C6) + // TODO: [ESP32C5] IDF-8650 // hw->wdtwprotect.wdt_wkey = TIMG_WDT_WKEY_VALUE; + abort(); } /** @@ -270,8 +282,9 @@ FORCE_INLINE_ATTR void mwdt_ll_write_protect_disable(timg_dev_t *hw) */ FORCE_INLINE_ATTR void mwdt_ll_clear_intr_status(timg_dev_t *hw) { - // TODO: [ESP32C5] IDF-8650 (inherit from C6) + // TODO: [ESP32C5] IDF-8650 // hw->int_clr_timers.wdt_int_clr = 1; + abort(); } /** @@ -282,8 +295,9 @@ FORCE_INLINE_ATTR void mwdt_ll_clear_intr_status(timg_dev_t *hw) */ FORCE_INLINE_ATTR void mwdt_ll_set_intr_enable(timg_dev_t *hw, bool enable) { - // TODO: [ESP32C5] IDF-8650 (inherit from C6) + // TODO: [ESP32C5] IDF-8650 // hw->int_ena_timers.wdt_int_ena = (enable) ? 1 : 0; + abort(); } /** @@ -294,7 +308,7 @@ FORCE_INLINE_ATTR void mwdt_ll_set_intr_enable(timg_dev_t *hw, bool enable) */ FORCE_INLINE_ATTR void mwdt_ll_set_clock_source(timg_dev_t *hw, mwdt_clock_source_t clk_src) { - // TODO: [ESP32C5] IDF-8650 (inherit from C6) + // TODO: [ESP32C5] IDF-8650 // uint8_t clk_id = 0; // switch (clk_src) { // case MWDT_CLK_SRC_XTAL: @@ -315,6 +329,7 @@ FORCE_INLINE_ATTR void mwdt_ll_set_clock_source(timg_dev_t *hw, mwdt_clock_sourc // } else { // PCR.timergroup1_wdt_clk_conf.tg1_wdt_clk_sel = clk_id; // } + abort(); } /** @@ -326,12 +341,13 @@ FORCE_INLINE_ATTR void mwdt_ll_set_clock_source(timg_dev_t *hw, mwdt_clock_sourc __attribute__((always_inline)) static inline void mwdt_ll_enable_clock(timg_dev_t *hw, bool en) { - // TODO: [ESP32C5] IDF-8650 (inherit from C6) + // TODO: [ESP32C5] IDF-8650 // if (hw == &TIMERG0) { // PCR.timergroup0_wdt_clk_conf.tg0_wdt_clk_en = en; // } else { // PCR.timergroup1_wdt_clk_conf.tg1_wdt_clk_en = en; // } + abort(); } diff --git a/components/hal/esp32c5/include/hal/pmu_hal.h b/components/hal/esp32c5/include/hal/pmu_hal.h new file mode 100644 index 0000000000..f4ca27e9e8 --- /dev/null +++ b/components/hal/esp32c5/include/hal/pmu_hal.h @@ -0,0 +1,45 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +// The HAL layer for PMU + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include "soc/soc_caps.h" +#include "hal/pmu_ll.h" +#include "hal/pmu_types.h" + +typedef struct { + pmu_dev_t *dev; +} pmu_hal_context_t; + +void pmu_hal_hp_set_digital_power_up_wait_cycle(pmu_hal_context_t *hal, uint32_t power_supply_wait_cycle, uint32_t power_up_wait_cycle); + +uint32_t pmu_hal_hp_get_digital_power_up_wait_cycle(pmu_hal_context_t *hal); + +void pmu_hal_lp_set_digital_power_up_wait_cycle(pmu_hal_context_t *hal, uint32_t power_supply_wait_cycle, uint32_t power_up_wait_cycle); + +uint32_t pmu_hal_lp_get_digital_power_up_wait_cycle(pmu_hal_context_t *hal); + +void pmu_hal_hp_set_sleep_active_backup_enable(pmu_hal_context_t *hal); + +void pmu_hal_hp_set_sleep_active_backup_disable(pmu_hal_context_t *hal); + +void pmu_hal_hp_set_sleep_modem_backup_enable(pmu_hal_context_t *hal); + +void pmu_hal_hp_set_sleep_modem_backup_disable(pmu_hal_context_t *hal); + +void pmu_hal_hp_set_modem_active_backup_enable(pmu_hal_context_t *hal); + +void pmu_hal_hp_set_modem_active_backup_disable(pmu_hal_context_t *hal); + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32c5/include/hal/pmu_ll.h b/components/hal/esp32c5/include/hal/pmu_ll.h new file mode 100644 index 0000000000..15f39d10e4 --- /dev/null +++ b/components/hal/esp32c5/include/hal/pmu_ll.h @@ -0,0 +1,676 @@ +/* + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +// The LL layer for ESP32-C6 PMU register operations + +#pragma once + +#include +#include +#include "soc/soc.h" +#include "esp_attr.h" +#include "hal/assert.h" +#include "soc/pmu_struct.h" +#include "hal/pmu_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Set the power domain that needs to be powered down in the digital power + * + * @param hw Beginning address of the peripheral registers. + * @param mode The pmu mode + * @param flag Digital power domain flag + * + * @return None + */ +FORCE_INLINE_ATTR void pmu_ll_hp_set_dig_power(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t flag) +{ + hw->hp_sys[mode].dig_power.val = flag; +} + +FORCE_INLINE_ATTR void pmu_ll_hp_set_icg_func(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t icg_func) +{ + hw->hp_sys[mode].icg_func = icg_func; +} + +FORCE_INLINE_ATTR void pmu_ll_hp_set_icg_apb(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t bitmap) +{ + hw->hp_sys[mode].icg_apb = bitmap; +} + +FORCE_INLINE_ATTR void pmu_ll_hp_set_icg_modem(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t code) +{ + hw->hp_sys[mode].icg_modem.code = code; +} + +FORCE_INLINE_ATTR void pmu_ll_hp_set_uart_wakeup_enable(pmu_dev_t *hw, pmu_hp_mode_t mode, bool wakeup_en) +{ + hw->hp_sys[mode].syscntl.uart_wakeup_en = wakeup_en; +} + +FORCE_INLINE_ATTR void pmu_ll_hp_set_hold_all_lp_pad(pmu_dev_t *hw, pmu_hp_mode_t mode, bool hold_all) +{ + hw->hp_sys[mode].syscntl.lp_pad_hold_all = hold_all; +} + +FORCE_INLINE_ATTR void pmu_ll_hp_set_hold_all_hp_pad(pmu_dev_t *hw, pmu_hp_mode_t mode, bool hold_all) +{ + hw->hp_sys[mode].syscntl.hp_pad_hold_all = hold_all; +} + +FORCE_INLINE_ATTR void pmu_ll_hp_set_dig_pad_slp_sel(pmu_dev_t *hw, pmu_hp_mode_t mode, bool slp_sel) +{ + hw->hp_sys[mode].syscntl.dig_pad_slp_sel = slp_sel; +} + +FORCE_INLINE_ATTR void pmu_ll_hp_set_pause_watchdog(pmu_dev_t *hw, pmu_hp_mode_t mode, bool pause_wdt) +{ + hw->hp_sys[mode].syscntl.dig_pause_wdt = pause_wdt; +} + +FORCE_INLINE_ATTR void pmu_ll_hp_set_cpu_stall(pmu_dev_t *hw, pmu_hp_mode_t mode, bool cpu_stall) +{ + hw->hp_sys[mode].syscntl.dig_cpu_stall = cpu_stall; +} + +/** + * @brief Set the power domain that needs to be powered down in the clock power + * + * @param hw Beginning address of the peripheral registers. + * @param mode The pmu mode + * @param flag Clock power domain flag + * + * @return None + */ +FORCE_INLINE_ATTR void pmu_ll_hp_set_clk_power(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t xpd_flag) +{ + hw->hp_sys[mode].clk_power.val = xpd_flag; +} + +FORCE_INLINE_ATTR void pmu_ll_hp_set_xtal_xpd(pmu_dev_t *hw, pmu_hp_mode_t mode, bool xpd_xtal) +{ + hw->hp_sys[mode].xtal.xpd_xtal = xpd_xtal; +} + +FORCE_INLINE_ATTR void pmu_ll_hp_set_bias_xpd(pmu_dev_t *hw, pmu_hp_mode_t mode, bool xpd_bias) +{ + hw->hp_sys[mode].bias.xpd_bias = xpd_bias; +} + +FORCE_INLINE_ATTR void pmu_ll_hp_set_dbg_atten(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t value) +{ + hw->hp_sys[mode].bias.dbg_atten = value; +} + +FORCE_INLINE_ATTR void pmu_ll_hp_set_current_power_off(pmu_dev_t *hw, pmu_hp_mode_t mode, bool off) +{ + hw->hp_sys[mode].bias.pd_cur = off; +} + +FORCE_INLINE_ATTR void pmu_ll_hp_set_bias_sleep_enable(pmu_dev_t *hw, pmu_hp_mode_t mode, bool en) +{ + hw->hp_sys[mode].bias.bias_sleep = en; +} + +FORCE_INLINE_ATTR void pmu_ll_hp_set_retention_param(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t param) +{ + hw->hp_sys[mode].backup.val = param; +} + +FORCE_INLINE_ATTR void pmu_ll_hp_set_sleep_to_active_backup_enable(pmu_dev_t *hw) +{ + hw->hp_sys[PMU_MODE_HP_ACTIVE].backup.hp_sleep2active_backup_en = 1; +} + +FORCE_INLINE_ATTR void pmu_ll_hp_set_sleep_to_active_backup_disable(pmu_dev_t *hw) +{ + hw->hp_sys[PMU_MODE_HP_ACTIVE].backup.hp_sleep2active_backup_en = 0; +} + +FORCE_INLINE_ATTR void pmu_ll_hp_set_modem_to_active_backup_enable(pmu_dev_t *hw) +{ + hw->hp_sys[PMU_MODE_HP_ACTIVE].backup.hp_modem2active_backup_en = 1; +} + +FORCE_INLINE_ATTR void pmu_ll_hp_set_modem_to_active_backup_disable(pmu_dev_t *hw) +{ + hw->hp_sys[PMU_MODE_HP_ACTIVE].backup.hp_modem2active_backup_en = 0; +} + +FORCE_INLINE_ATTR void pmu_ll_hp_set_sleep_to_modem_backup_enable(pmu_dev_t *hw) +{ + hw->hp_sys[PMU_MODE_HP_MODEM].backup.hp_sleep2modem_backup_en = 1; +} + +FORCE_INLINE_ATTR void pmu_ll_hp_set_sleep_to_modem_backup_disable(pmu_dev_t *hw) +{ + hw->hp_sys[PMU_MODE_HP_MODEM].backup.hp_sleep2modem_backup_en = 0; +} + +FORCE_INLINE_ATTR void pmu_ll_hp_set_active_to_sleep_backup_enable(pmu_dev_t *hw) +{ + hw->hp_sys[PMU_MODE_HP_SLEEP].backup.hp_active2sleep_backup_en = 1; +} + +FORCE_INLINE_ATTR void pmu_ll_hp_set_active_to_sleep_backup_disable(pmu_dev_t *hw) +{ + hw->hp_sys[PMU_MODE_HP_SLEEP].backup.hp_active2sleep_backup_en = 0; +} + +FORCE_INLINE_ATTR void pmu_ll_hp_set_modem_to_sleep_backup_enable(pmu_dev_t *hw) +{ + hw->hp_sys[PMU_MODE_HP_SLEEP].backup.hp_modem2sleep_backup_en = 1; +} + +FORCE_INLINE_ATTR void pmu_ll_hp_set_modem_to_sleep_backup_disable(pmu_dev_t *hw) +{ + hw->hp_sys[PMU_MODE_HP_SLEEP].backup.hp_modem2sleep_backup_en = 0; +} + +FORCE_INLINE_ATTR void pmu_ll_hp_set_backup_icg_func(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t icg_func) +{ + hw->hp_sys[mode].backup_clk = icg_func; +} + +FORCE_INLINE_ATTR void pmu_ll_hp_set_sysclk_nodiv(pmu_dev_t *hw, pmu_hp_mode_t mode, bool sysclk_nodiv) +{ + hw->hp_sys[mode].sysclk.dig_sysclk_nodiv = sysclk_nodiv; +} + +FORCE_INLINE_ATTR void pmu_ll_hp_set_icg_sysclk_enable(pmu_dev_t *hw, pmu_hp_mode_t mode, bool icg_sysclk_en) +{ + hw->hp_sys[mode].sysclk.icg_sysclk_en = icg_sysclk_en; +} + +FORCE_INLINE_ATTR void pmu_ll_hp_set_sysclk_slp_sel(pmu_dev_t *hw, pmu_hp_mode_t mode, bool slp_sel) +{ + hw->hp_sys[mode].sysclk.sysclk_slp_sel = slp_sel; +} + +FORCE_INLINE_ATTR void pmu_ll_hp_set_icg_sysclk_slp_sel(pmu_dev_t *hw, pmu_hp_mode_t mode, bool slp_sel) +{ + hw->hp_sys[mode].sysclk.icg_slp_sel = slp_sel; +} + +FORCE_INLINE_ATTR void pmu_ll_hp_set_dig_sysclk(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t sysclk_sel) +{ + hw->hp_sys[mode].sysclk.dig_sysclk_sel = sysclk_sel; +} + +FORCE_INLINE_ATTR void pmu_ll_hp_set_regulator_sleep_logic_xpd(pmu_dev_t *hw, pmu_hp_mode_t mode, bool slp_xpd) +{ + hw->hp_sys[mode].regulator0.slp_logic_xpd = slp_xpd; +} + +FORCE_INLINE_ATTR void pmu_ll_hp_set_regulator_sleep_memory_xpd(pmu_dev_t *hw, pmu_hp_mode_t mode, bool slp_xpd) +{ + hw->hp_sys[mode].regulator0.slp_mem_xpd = slp_xpd; +} + +FORCE_INLINE_ATTR void pmu_ll_hp_set_regulator_xpd(pmu_dev_t *hw, pmu_hp_mode_t mode, bool xpd) +{ + hw->hp_sys[mode].regulator0.xpd = xpd; +} + +FORCE_INLINE_ATTR void pmu_ll_hp_set_regulator_sleep_logic_dbias(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t slp_dbias) +{ + hw->hp_sys[mode].regulator0.slp_logic_dbias = slp_dbias; +} + +FORCE_INLINE_ATTR void pmu_ll_hp_set_regulator_sleep_memory_dbias(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t slp_dbias) +{ + hw->hp_sys[mode].regulator0.slp_mem_dbias = slp_dbias; +} + +FORCE_INLINE_ATTR void pmu_ll_hp_set_regulator_dbias(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t dbias) +{ + hw->hp_sys[mode].regulator0.dbias = dbias; +} + +FORCE_INLINE_ATTR void pmu_ll_hp_set_regulator_driver_bar(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t drv_b) +{ + hw->hp_sys[mode].regulator1.drv_b = drv_b; +} + + +FORCE_INLINE_ATTR void pmu_ll_lp_set_regulator_slp_xpd(pmu_dev_t *hw, pmu_lp_mode_t mode, bool slp_xpd) +{ + hw->lp_sys[mode].regulator0.slp_xpd = slp_xpd; +} + +FORCE_INLINE_ATTR void pmu_ll_lp_set_regulator_xpd(pmu_dev_t *hw, pmu_lp_mode_t mode, bool xpd) +{ + hw->lp_sys[mode].regulator0.xpd = xpd; +} + +FORCE_INLINE_ATTR void pmu_ll_lp_set_regulator_sleep_dbias(pmu_dev_t *hw, pmu_lp_mode_t mode, uint32_t slp_dbias) +{ + hw->lp_sys[mode].regulator0.slp_dbias = slp_dbias; +} + +FORCE_INLINE_ATTR void pmu_ll_lp_set_regulator_dbias(pmu_dev_t *hw, pmu_lp_mode_t mode, uint32_t dbias) +{ + hw->lp_sys[mode].regulator0.dbias = dbias; +} + +FORCE_INLINE_ATTR void pmu_ll_lp_set_regulator_driver_bar(pmu_dev_t *hw, pmu_lp_mode_t mode, uint32_t drv_b) +{ + hw->lp_sys[mode].regulator1.drv_b = drv_b; +} + +FORCE_INLINE_ATTR void pmu_ll_lp_set_xtal_xpd(pmu_dev_t *hw, pmu_lp_mode_t mode, bool xpd_xtal) +{ + HAL_ASSERT(mode == PMU_MODE_LP_SLEEP); + hw->lp_sys[mode].xtal.xpd_xtal = xpd_xtal; +} + + +FORCE_INLINE_ATTR void pmu_ll_lp_set_dig_power(pmu_dev_t *hw, pmu_lp_mode_t mode, uint32_t flag) +{ + hw->lp_sys[mode].dig_power.val = flag; +} + +FORCE_INLINE_ATTR void pmu_ll_lp_set_clk_power(pmu_dev_t *hw, pmu_lp_mode_t mode, uint32_t xpd_flag) +{ + hw->lp_sys[mode].clk_power.val = xpd_flag; +} + +FORCE_INLINE_ATTR uint32_t pmu_ll_lp_get_clk_power(pmu_dev_t *hw, pmu_lp_mode_t mode) +{ + return hw->lp_sys[mode].clk_power.val; +} + +FORCE_INLINE_ATTR void pmu_ll_lp_set_bias_xpd(pmu_dev_t *hw, pmu_lp_mode_t mode, bool xpd_bias) +{ + HAL_ASSERT(mode == PMU_MODE_LP_SLEEP); + hw->lp_sys[mode].bias.xpd_bias = xpd_bias; +} + +FORCE_INLINE_ATTR void pmu_ll_lp_set_dbg_atten(pmu_dev_t *hw, pmu_lp_mode_t mode, uint32_t value) +{ + HAL_ASSERT(mode == PMU_MODE_LP_SLEEP); + hw->lp_sys[mode].bias.dbg_atten = value; +} + +FORCE_INLINE_ATTR void pmu_ll_lp_set_current_power_off(pmu_dev_t *hw, pmu_lp_mode_t mode, bool off) +{ + HAL_ASSERT(mode == PMU_MODE_LP_SLEEP); + hw->lp_sys[mode].bias.pd_cur = off; +} + +FORCE_INLINE_ATTR void pmu_ll_lp_set_bias_sleep_enable(pmu_dev_t *hw, pmu_lp_mode_t mode, bool en) +{ + HAL_ASSERT(mode == PMU_MODE_LP_SLEEP); + hw->lp_sys[mode].bias.bias_sleep = en; +} + + +/****/ +FORCE_INLINE_ATTR void pmu_ll_imm_set_clk_power(pmu_dev_t *hw, uint32_t flag) +{ + hw->imm.clk_power.val = flag; +} + +FORCE_INLINE_ATTR void pmu_ll_imm_set_icg_slp_sel(pmu_dev_t *hw, bool slp_sel) +{ + if (slp_sel) { + hw->imm.sleep_sysclk.tie_high_icg_slp_sel = 1; + } else { + hw->imm.sleep_sysclk.tie_low_icg_slp_sel = 1; + } +} + +FORCE_INLINE_ATTR void pmu_ll_imm_update_dig_sysclk_sel(pmu_dev_t *hw, bool update) +{ + hw->imm.sleep_sysclk.update_dig_sysclk_sel = update; +} + +FORCE_INLINE_ATTR void pmu_ll_imm_update_dig_icg_switch(pmu_dev_t *hw, bool update) +{ + hw->imm.sleep_sysclk.update_dig_icg_switch = update; +} + +FORCE_INLINE_ATTR void pmu_ll_imm_update_dig_icg_func(pmu_dev_t *hw, bool icg_func_update) +{ + hw->imm.hp_func_icg.update_dig_icg_func_en = icg_func_update; +} + +FORCE_INLINE_ATTR void pmu_ll_imm_update_dig_icg_apb(pmu_dev_t *hw, bool icg_apb_update) +{ + hw->imm.hp_apb_icg.update_dig_icg_apb_en = icg_apb_update; +} + +FORCE_INLINE_ATTR void pmu_ll_imm_update_dig_icg_modem_code(pmu_dev_t *hw, bool icg_modem_update) +{ + hw->imm.modem_icg.update_dig_icg_modem_en = icg_modem_update; +} + +FORCE_INLINE_ATTR void pmu_ll_imm_set_lp_rootclk_sel(pmu_dev_t *hw, bool rootclk_sel) +{ + if (rootclk_sel) { + hw->imm.lp_icg.tie_high_lp_rootclk_sel = 1; + } else { + hw->imm.lp_icg.tie_low_lp_rootclk_sel = 1; + } +} + +FORCE_INLINE_ATTR void pmu_ll_imm_set_hp_pad_hold_all(pmu_dev_t *hw, bool hold_all) +{ + if (hold_all) { + hw->imm.pad_hold_all.tie_high_hp_pad_hold_all = 1; + } else { + hw->imm.pad_hold_all.tie_low_hp_pad_hold_all = 1; + } +} + +FORCE_INLINE_ATTR void pmu_ll_imm_set_lp_pad_hold_all(pmu_dev_t *hw, bool hold_all) +{ + if (hold_all) { + hw->imm.pad_hold_all.tie_high_lp_pad_hold_all = 1; + } else { + hw->imm.pad_hold_all.tie_low_lp_pad_hold_all = 1; + } +} + +/*** */ +FORCE_INLINE_ATTR void pmu_ll_hp_set_power_force_reset(pmu_dev_t *hw, pmu_hp_power_domain_t domain, bool rst) +{ + hw->power.hp_pd[domain].force_reset = rst; +} + +FORCE_INLINE_ATTR void pmu_ll_hp_set_power_force_isolate(pmu_dev_t *hw, pmu_hp_power_domain_t domain, bool iso) +{ + hw->power.hp_pd[domain].force_iso = iso; +} + +FORCE_INLINE_ATTR void pmu_ll_hp_set_power_force_power_up(pmu_dev_t *hw, pmu_hp_power_domain_t domain, bool fpu) +{ + hw->power.hp_pd[domain].force_pu = fpu; +} + +FORCE_INLINE_ATTR void pmu_ll_hp_set_power_force_no_reset(pmu_dev_t *hw, pmu_hp_power_domain_t domain, bool no_rst) +{ + hw->power.hp_pd[domain].force_no_reset = no_rst; +} + +FORCE_INLINE_ATTR void pmu_ll_hp_set_power_force_no_isolate(pmu_dev_t *hw, pmu_hp_power_domain_t domain, bool no_iso) +{ + hw->power.hp_pd[domain].force_no_iso = no_iso; +} + +FORCE_INLINE_ATTR void pmu_ll_hp_set_power_force_power_down(pmu_dev_t *hw, pmu_hp_power_domain_t domain, bool fpd) +{ + hw->power.hp_pd[domain].force_pd = fpd; +} + +FORCE_INLINE_ATTR void pmu_ll_lp_set_power_force_reset(pmu_dev_t *hw, bool rst) +{ + hw->power.lp_peri.force_reset = rst; +} + +FORCE_INLINE_ATTR void pmu_ll_lp_set_power_force_isolate(pmu_dev_t *hw, bool iso) +{ + hw->power.lp_peri.force_iso = iso; +} + +FORCE_INLINE_ATTR void pmu_ll_lp_set_power_force_power_up(pmu_dev_t *hw, bool fpu) +{ + hw->power.lp_peri.force_pu = fpu; +} + +FORCE_INLINE_ATTR void pmu_ll_lp_set_power_force_no_reset(pmu_dev_t *hw, bool no_rst) +{ + hw->power.lp_peri.force_no_reset = no_rst; +} + +FORCE_INLINE_ATTR void pmu_ll_lp_set_power_force_no_isolate(pmu_dev_t *hw, bool no_iso) +{ + hw->power.lp_peri.force_no_iso = no_iso; +} + +FORCE_INLINE_ATTR void pmu_ll_lp_set_power_force_power_down(pmu_dev_t *hw, bool fpd) +{ + hw->power.lp_peri.force_pd = fpd; +} + +FORCE_INLINE_ATTR void pmu_ll_hp_set_memory_isolate(pmu_dev_t *hw, uint32_t iso) +{ + hw->power.mem_cntl.force_hp_mem_iso = iso; +} + +FORCE_INLINE_ATTR void pmu_ll_hp_set_memory_power_down(pmu_dev_t *hw, uint32_t fpd) +{ + hw->power.mem_cntl.force_hp_mem_pd = fpd; +} + +FORCE_INLINE_ATTR void pmu_ll_hp_set_memory_no_isolate(pmu_dev_t *hw, uint32_t no_iso) +{ + hw->power.mem_cntl.force_hp_mem_no_iso = no_iso; +} + +FORCE_INLINE_ATTR void pmu_ll_hp_set_memory_power_up(pmu_dev_t *hw, uint32_t fpu) +{ + hw->power.mem_cntl.force_hp_mem_pu = fpu; +} + +/*** */ +FORCE_INLINE_ATTR void pmu_ll_hp_set_sleep_enable(pmu_dev_t *hw) +{ + hw->wakeup.cntl0.sleep_req = 1; +} + +FORCE_INLINE_ATTR void pmu_ll_hp_set_reject_enable(pmu_dev_t *hw, uint32_t reject) +{ + hw->wakeup.cntl1.sleep_reject_ena = reject; + hw->wakeup.cntl1.slp_reject_en = 1; +} + +FORCE_INLINE_ATTR void pmu_ll_hp_set_reject_disable(pmu_dev_t *hw) +{ + hw->wakeup.cntl1.slp_reject_en = 0; +} + +FORCE_INLINE_ATTR void pmu_ll_hp_set_wakeup_enable(pmu_dev_t *hw, uint32_t wakeup) +{ + hw->wakeup.cntl2 = wakeup; +} + +FORCE_INLINE_ATTR void pmu_ll_hp_set_sleep_protect_mode(pmu_dev_t *hw, int mode) +{ + hw->wakeup.cntl3.sleep_prt_sel = mode; +} + +FORCE_INLINE_ATTR void pmu_ll_hp_set_min_sleep_cycle(pmu_dev_t *hw, uint32_t slow_clk_cycle) +{ + hw->wakeup.cntl3.hp_min_slp_val = slow_clk_cycle; +} + +FORCE_INLINE_ATTR void pmu_ll_hp_clear_reject_cause(pmu_dev_t *hw) +{ + hw->wakeup.cntl4.slp_reject_cause_clr = 1; +} + +FORCE_INLINE_ATTR bool pmu_ll_hp_is_sleep_wakeup(pmu_dev_t *hw) +{ + return (hw->hp_ext.int_raw.wakeup == 1); +} + +FORCE_INLINE_ATTR bool pmu_ll_hp_is_sleep_reject(pmu_dev_t *hw) +{ + return (hw->hp_ext.int_raw.reject == 1); +} + +FORCE_INLINE_ATTR void pmu_ll_hp_clear_sw_intr_status(pmu_dev_t *hw) +{ + hw->hp_ext.int_clr.sw = 1; +} + +FORCE_INLINE_ATTR void pmu_ll_hp_clear_wakeup_intr_status(pmu_dev_t *hw) +{ + hw->hp_ext.int_clr.wakeup = 1; +} + +FORCE_INLINE_ATTR void pmu_ll_hp_clear_reject_intr_status(pmu_dev_t *hw) +{ + hw->hp_ext.int_clr.reject = 1; +} + +FORCE_INLINE_ATTR uint32_t pmu_ll_hp_get_wakeup_cause(pmu_dev_t *hw) +{ + return hw->wakeup.status0; +} + +FORCE_INLINE_ATTR uint32_t pmu_ll_hp_get_reject_cause(pmu_dev_t *hw) +{ + return hw->wakeup.status1; +} + +FORCE_INLINE_ATTR void pmu_ll_lp_set_min_sleep_cycle(pmu_dev_t *hw, uint32_t slow_clk_cycle) +{ + hw->wakeup.cntl3.lp_min_slp_val = slow_clk_cycle; +} + +FORCE_INLINE_ATTR void pmu_ll_hp_set_modify_icg_cntl_wait_cycle(pmu_dev_t *hw, uint32_t cycle) +{ + hw->hp_ext.clk_cntl.modify_icg_cntl_wait = cycle; +} + +FORCE_INLINE_ATTR uint32_t pmu_ll_hp_get_modify_icg_cntl_wait_cycle(pmu_dev_t *hw) +{ + return hw->hp_ext.clk_cntl.modify_icg_cntl_wait; +} + +FORCE_INLINE_ATTR void pmu_ll_hp_set_switch_icg_cntl_wait_cycle(pmu_dev_t *hw, uint32_t cycle) +{ + hw->hp_ext.clk_cntl.switch_icg_cntl_wait = cycle; +} + +FORCE_INLINE_ATTR uint32_t pmu_ll_hp_get_switch_icg_cntl_wait_cycle(pmu_dev_t *hw) +{ + return hw->hp_ext.clk_cntl.switch_icg_cntl_wait; +} + +FORCE_INLINE_ATTR void pmu_ll_hp_set_digital_power_down_wait_cycle(pmu_dev_t *hw, uint32_t cycle) +{ + hw->power.wait_timer0.powerdown_timer = cycle; +} + +FORCE_INLINE_ATTR uint32_t pmu_ll_hp_get_digital_power_down_wait_cycle(pmu_dev_t *hw) +{ + return hw->power.wait_timer0.powerdown_timer; +} + +FORCE_INLINE_ATTR void pmu_ll_lp_set_digital_power_down_wait_cycle(pmu_dev_t *hw, uint32_t cycle) +{ + hw->power.wait_timer1.powerdown_timer = cycle; +} + +FORCE_INLINE_ATTR uint32_t pmu_ll_lp_get_digital_power_down_wait_cycle(pmu_dev_t *hw) +{ + return hw->power.wait_timer1.powerdown_timer; +} + +FORCE_INLINE_ATTR void pmu_ll_lp_set_analog_wait_target_cycle(pmu_dev_t *hw, uint32_t slow_clk_cycle) +{ + hw->wakeup.cntl5.lp_ana_wait_target = slow_clk_cycle; +} + +FORCE_INLINE_ATTR uint32_t pmu_ll_lp_get_analog_wait_target_cycle(pmu_dev_t *hw) +{ + return hw->wakeup.cntl5.lp_ana_wait_target; +} + +FORCE_INLINE_ATTR void pmu_ll_set_modem_wait_target_cycle(pmu_dev_t *hw, uint32_t cycle) +{ + hw->wakeup.cntl5.modem_wait_target = cycle; +} + +FORCE_INLINE_ATTR uint32_t pmu_ll_get_modem_wait_target_cycle(pmu_dev_t *hw) +{ + return hw->wakeup.cntl5.modem_wait_target; +} + +FORCE_INLINE_ATTR void pmu_ll_set_xtal_stable_wait_cycle(pmu_dev_t *hw, uint32_t cycle) +{ + hw->power.clk_wait.wait_xtal_stable = cycle; +} + +FORCE_INLINE_ATTR uint32_t pmu_ll_get_xtal_stable_wait_cycle(pmu_dev_t *hw) +{ + return hw->power.clk_wait.wait_xtal_stable; +} + +FORCE_INLINE_ATTR void pmu_ll_set_pll_stable_wait_cycle(pmu_dev_t *hw, uint32_t cycle) +{ + hw->power.clk_wait.wait_pll_stable = cycle; +} + +FORCE_INLINE_ATTR uint32_t pmu_ll_get_pll_stable_wait_cycle(pmu_dev_t *hw) +{ + return hw->power.clk_wait.wait_pll_stable; +} + +FORCE_INLINE_ATTR void pmu_ll_lp_set_digital_power_supply_wait_cycle(pmu_dev_t *hw, uint32_t cycle) +{ + hw->power.wait_timer1.wait_timer = cycle; +} + +FORCE_INLINE_ATTR uint32_t pmu_ll_lp_get_digital_power_supply_wait_cycle(pmu_dev_t *hw) +{ + return hw->power.wait_timer1.wait_timer; +} + +FORCE_INLINE_ATTR void pmu_ll_lp_set_digital_power_up_wait_cycle(pmu_dev_t *hw, uint32_t cycle) +{ + hw->power.wait_timer1.powerup_timer = cycle; +} + +FORCE_INLINE_ATTR uint32_t pmu_ll_lp_get_digital_power_up_wait_cycle(pmu_dev_t *hw) +{ + return hw->power.wait_timer1.powerup_timer; +} + +FORCE_INLINE_ATTR void pmu_ll_hp_set_analog_wait_target_cycle(pmu_dev_t *hw, uint32_t cycle) +{ + hw->wakeup.cntl7.ana_wait_target = cycle; +} + +FORCE_INLINE_ATTR uint32_t pmu_ll_hp_get_analog_wait_target_cycle(pmu_dev_t *hw) +{ + return hw->wakeup.cntl7.ana_wait_target; +} + +FORCE_INLINE_ATTR void pmu_ll_hp_set_digital_power_supply_wait_cycle(pmu_dev_t *hw, uint32_t cycle) +{ + hw->power.wait_timer0.wait_timer = cycle; +} + +FORCE_INLINE_ATTR uint32_t pmu_ll_hp_get_digital_power_supply_wait_cycle(pmu_dev_t *hw) +{ + return hw->power.wait_timer0.wait_timer; +} + +FORCE_INLINE_ATTR void pmu_ll_hp_set_digital_power_up_wait_cycle(pmu_dev_t *hw, uint32_t cycle) +{ + hw->power.wait_timer0.powerup_timer = cycle; +} + +FORCE_INLINE_ATTR uint32_t pmu_ll_hp_get_digital_power_up_wait_cycle(pmu_dev_t *hw) +{ + return hw->power.wait_timer0.powerup_timer; +} + +FORCE_INLINE_ATTR uint32_t pmu_ll_get_sysclk_sleep_select_state(pmu_dev_t *hw) +{ + return hw->clk_state0.sysclk_slp_sel; +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32c5/include/hal/regi2c_ctrl_ll.h b/components/hal/esp32c5/include/hal/regi2c_ctrl_ll.h new file mode 100644 index 0000000000..597cbdf368 --- /dev/null +++ b/components/hal/esp32c5/include/hal/regi2c_ctrl_ll.h @@ -0,0 +1,66 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include +#include "soc/soc.h" +#include "soc/regi2c_defs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Start BBPLL self-calibration + */ +static inline __attribute__((always_inline)) void regi2c_ctrl_ll_bbpll_calibration_start(void) +{ + REG_CLR_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH); + REG_SET_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW); +} + +/** + * @brief Stop BBPLL self-calibration + */ +static inline __attribute__((always_inline)) void regi2c_ctrl_ll_bbpll_calibration_stop(void) +{ + REG_CLR_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW); + REG_SET_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH); +} + +/** + * @brief Check whether BBPLL calibration is done + * + * @return True if calibration is done; otherwise false + */ +static inline __attribute__((always_inline)) bool regi2c_ctrl_ll_bbpll_calibration_is_done(void) +{ + return REG_GET_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_CAL_DONE); +} + +/** + * @brief Enable the I2C internal bus to do I2C read/write operation to the SAR_ADC register + */ +static inline void regi2c_ctrl_ll_i2c_saradc_enable(void) +{ + CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, ANA_I2C_SAR_FORCE_PD); + SET_PERI_REG_MASK(ANA_CONFIG2_REG, ANA_I2C_SAR_FORCE_PU); +} + +/** + * @brief Disable the I2C internal bus to do I2C read/write operation to the SAR_ADC register + */ +static inline void regi2c_ctrl_ll_i2c_saradc_disable(void) +{ + CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, ANA_I2C_SAR_FORCE_PU); + SET_PERI_REG_MASK(ANA_CONFIG2_REG, ANA_I2C_SAR_FORCE_PD); +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32c5/include/hal/rtc_io_ll.h b/components/hal/esp32c5/include/hal/rtc_io_ll.h new file mode 100644 index 0000000000..a987c8d90f --- /dev/null +++ b/components/hal/esp32c5/include/hal/rtc_io_ll.h @@ -0,0 +1,456 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/******************************************************************************* + * NOTICE + * The ll is not public api, don't use in application code. + * See readme.md in hal/include/hal/readme.md + ******************************************************************************/ + +#pragma once + +#include +#include +#include "soc/soc_caps.h" +#include "soc/pcr_struct.h" +#include "soc/lp_io_struct.h" +#include "soc/lp_aon_struct.h" +#include "soc/pmu_struct.h" +#include "hal/misc.h" +#include "hal/assert.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define RTCIO_LL_PIN_FUNC 0 + +typedef enum { + RTCIO_LL_FUNC_RTC = 0x0, /*!< The pin controlled by RTC module. */ + RTCIO_LL_FUNC_DIGITAL = 0x1, /*!< The pin controlled by DIGITAL module. */ +} rtcio_ll_func_t; + +typedef enum { + RTCIO_LL_WAKEUP_DISABLE = 0, /*!< Disable GPIO interrupt */ + RTCIO_LL_WAKEUP_LOW_LEVEL = 0x4, /*!< GPIO interrupt type : input low level trigger */ + RTCIO_LL_WAKEUP_HIGH_LEVEL = 0x5, /*!< GPIO interrupt type : input high level trigger */ +} rtcio_ll_wake_type_t; + +typedef enum { + RTCIO_LL_OUTPUT_NORMAL = 0, /*!< RTCIO output mode is normal. */ + RTCIO_LL_OUTPUT_OD = 0x1, /*!< RTCIO output mode is open-drain. */ +} rtcio_ll_out_mode_t; + +/** + * @brief Select a RTC IOMUX function for the RTC IO + * + * @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio). + * @param func Function to assign to the pin + */ +static inline void rtcio_ll_iomux_func_sel(int rtcio_num, int func) +{ + // TODO: [ESP32C5] IDF-8719 + // LP_IO.gpio[rtcio_num].mcu_sel = func; + abort(); +} + +/** + * @brief Select the rtcio function. + * + * @note The RTC function must be selected before the pad analog function is enabled. + * @note The clock gating 'PCR.iomux_conf.iomux_clk_en' is the gate of both 'lp_io' and 'etm_gpio' + * And it's default to be turned on, so we don't need to operate this clock gate here additionally + * + * @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio). + * @param func Select pin function. + */ +static inline void rtcio_ll_function_select(int rtcio_num, rtcio_ll_func_t func) +{ + // TODO: [ESP32C5] IDF-8719 + // if (func == RTCIO_LL_FUNC_RTC) { + // // 0: GPIO connected to digital GPIO module. 1: GPIO connected to analog RTC module. + // uint32_t sel_mask = HAL_FORCE_READ_U32_REG_FIELD(LP_AON.gpio_mux, gpio_mux_sel); + // sel_mask |= BIT(rtcio_num); + // HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.gpio_mux, gpio_mux_sel, sel_mask); + // //0:RTC FUNCTION 1,2,3:Reserved + // rtcio_ll_iomux_func_sel(rtcio_num, RTCIO_LL_PIN_FUNC); + // } else if (func == RTCIO_LL_FUNC_DIGITAL) { + // // Clear the bit to use digital GPIO module + // uint32_t sel_mask = HAL_FORCE_READ_U32_REG_FIELD(LP_AON.gpio_mux, gpio_mux_sel); + // sel_mask &= ~BIT(rtcio_num); + // HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.gpio_mux, gpio_mux_sel, sel_mask); + // } + abort(); +} + +/** + * Enable rtcio output. + * + * @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio). + */ +static inline void rtcio_ll_output_enable(int rtcio_num) +{ + // TODO: [ESP32C5] IDF-8719 + // HAL_FORCE_MODIFY_U32_REG_FIELD(LP_IO.out_enable_w1ts, enable_w1ts, BIT(rtcio_num)); + abort(); +} + +/** + * Disable rtcio output. + * + * @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio). + */ +static inline void rtcio_ll_output_disable(int rtcio_num) +{ + // TODO: [ESP32C5] IDF-8719 + // HAL_FORCE_MODIFY_U32_REG_FIELD(LP_IO.out_enable_w1tc, enable_w1tc, BIT(rtcio_num)); + abort(); +} + +/** + * Set RTCIO output level. + * + * @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio). + * @param level 0: output low; ~0: output high. + */ +static inline void rtcio_ll_set_level(int rtcio_num, uint32_t level) +{ + // TODO: [ESP32C5] IDF-8719 + // if (level) { + // HAL_FORCE_MODIFY_U32_REG_FIELD(LP_IO.out_data_w1ts, out_data_w1ts, BIT(rtcio_num)); + // } else { + // HAL_FORCE_MODIFY_U32_REG_FIELD(LP_IO.out_data_w1tc, out_data_w1tc, BIT(rtcio_num)); + // } + abort(); +} + +/** + * Enable rtcio input. + * + * @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio). + */ +static inline void rtcio_ll_input_enable(int rtcio_num) +{ + // TODO: [ESP32C5] IDF-8719 + // LP_IO.gpio[rtcio_num].fun_ie = 1; + abort(); +} + +/** + * Disable rtcio input. + * + * @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio). + */ +static inline void rtcio_ll_input_disable(int rtcio_num) +{ + // TODO: [ESP32C5] IDF-8719 + // LP_IO.gpio[rtcio_num].fun_ie = 0; + abort(); +} + +/** + * Get RTCIO input level. + * + * @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio). + * @return 0: input low; ~0: input high. + */ +static inline uint32_t rtcio_ll_get_level(int rtcio_num) +{ + // TODO: [ESP32C5] IDF-8719 + // return (uint32_t)(HAL_FORCE_READ_U32_REG_FIELD(LP_IO.in, in_data_next) >> rtcio_num) & 0x1; + abort(); + return (uint32_t)0; +} + +/** + * @brief Set RTC GPIO pad drive capability + * + * @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio). + * @param strength Drive capability of the pad. Range: 0 ~ 3. + */ +static inline void rtcio_ll_set_drive_capability(int rtcio_num, uint32_t strength) +{ + // TODO: [ESP32C5] IDF-8719 + // LP_IO.gpio[rtcio_num].fun_drv = strength; + abort(); +} + +/** + * @brief Get RTC GPIO pad drive capability. + * + * @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio). + * @return Drive capability of the pad. Range: 0 ~ 3. + */ +static inline uint32_t rtcio_ll_get_drive_capability(int rtcio_num) +{ + // TODO: [ESP32C5] IDF-8719 + // return LP_IO.gpio[rtcio_num].fun_drv; + abort(); + return (uint32_t)0; +} + +/** + * @brief Set RTC GPIO pad output mode. + * + * @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio). + * @return mode Output mode. + */ +static inline void rtcio_ll_output_mode_set(int rtcio_num, rtcio_ll_out_mode_t mode) +{ + // TODO: [ESP32C5] IDF-8719 + // LP_IO.pin[rtcio_num].pad_driver = mode; + abort(); +} + +/** + * RTC GPIO pullup enable. + * + * @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio). + */ +static inline void rtcio_ll_pullup_enable(int rtcio_num) +{ + // TODO: [ESP32C5] IDF-8719 + // /* Enable internal weak pull-up */ + // LP_IO.gpio[rtcio_num].fun_wpu = 1; + abort(); +} + +/** + * RTC GPIO pullup disable. + * + * @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio). + */ +static inline void rtcio_ll_pullup_disable(int rtcio_num) +{ + // TODO: [ESP32C5] IDF-8719 + // /* Disable internal weak pull-up */ + // LP_IO.gpio[rtcio_num].fun_wpu = 0; + abort(); +} + +/** + * RTC GPIO pulldown enable. + * + * @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio). + */ +static inline void rtcio_ll_pulldown_enable(int rtcio_num) +{ + // TODO: [ESP32C5] IDF-8719 + // /* Enable internal weak pull-down */ + // LP_IO.gpio[rtcio_num].fun_wpd = 1; + abort(); +} + +/** + * RTC GPIO pulldown disable. + * + * @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio). + */ +static inline void rtcio_ll_pulldown_disable(int rtcio_num) +{ + // TODO: [ESP32C5] IDF-8719 + // /* Enable internal weak pull-down */ + // LP_IO.gpio[rtcio_num].fun_wpd = 0; + abort(); +} + +/** + * Enable force hold function for an RTC IO pad. + * + * Enabling HOLD function will cause the pad to lock current status, such as, + * input/output enable, input/output value, function, drive strength values. + * This function is useful when going into light or deep sleep mode to prevent + * the pin configuration from changing. + * + * @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio). + */ +static inline void rtcio_ll_force_hold_enable(int rtcio_num) +{ + // TODO: [ESP32C5] IDF-8719 + // LP_AON.gpio_hold0.gpio_hold0 |= BIT(rtcio_num); + abort(); +} + +/** + * Disable hold function on an RTC IO pad + * + * @note If disable the pad hold, the status of pad maybe changed in sleep mode. + * @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio). + */ +static inline void rtcio_ll_force_hold_disable(int rtcio_num) +{ + // TODO: [ESP32C5] IDF-8719 + // LP_AON.gpio_hold0.gpio_hold0 &= ~BIT(rtcio_num); + abort(); +} + +/** + * Enable force hold function for all RTC IO pads + * + * Enabling HOLD function will cause the pad to lock current status, such as, + * input/output enable, input/output value, function, drive strength values. + * This function is useful when going into light or deep sleep mode to prevent + * the pin configuration from changing. + */ +static inline void rtcio_ll_force_hold_all(void) +{ + // TODO: [ESP32C5] IDF-8719 + // PMU.imm.pad_hold_all.tie_high_lp_pad_hold_all = 1; + abort(); +} + +/** + * Disable hold function fon all RTC IO pads + * + * @note If disable the pad hold, the status of pad maybe changed in sleep mode. + */ +static inline void rtcio_ll_force_unhold_all(void) +{ + // TODO: [ESP32C5] IDF-8719 + // PMU.imm.pad_hold_all.tie_low_lp_pad_hold_all = 1; + abort(); +} + +/** + * Enable wakeup function and set wakeup type from light sleep or deep sleep for rtcio. + * + * @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio). + * @param type Wakeup on high level or low level. + */ +static inline void rtcio_ll_wakeup_enable(int rtcio_num, rtcio_ll_wake_type_t type) +{ + // TODO: [ESP32C5] IDF-8719 + // LP_IO.pin[rtcio_num].wakeup_enable = 0x1; + // LP_IO.pin[rtcio_num].int_type = type; + abort(); +} + +/** + * Disable wakeup function from light sleep or deep sleep for rtcio. + * + * @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio). + */ +static inline void rtcio_ll_wakeup_disable(int rtcio_num) +{ + // TODO: [ESP32C5] IDF-8719 + // LP_IO.pin[rtcio_num].wakeup_enable = 0; + // LP_IO.pin[rtcio_num].int_type = RTCIO_LL_WAKEUP_DISABLE; + abort(); +} + +/** + * Enable rtc io output in deep sleep. + * + * @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio). + */ +static inline void rtcio_ll_enable_output_in_sleep(int rtcio_num) +{ + // TODO: [ESP32C5] IDF-8719 + // LP_IO.gpio[rtcio_num].mcu_oe = 1; + abort(); +} + +/** + * Disable rtc io output in deep sleep. + * + * @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio). + */ +static inline void rtcio_ll_disable_output_in_sleep(int rtcio_num) +{ + // TODO: [ESP32C5] IDF-8719 + // LP_IO.gpio[rtcio_num].mcu_oe = 0; + abort(); +} + +/** + * Enable rtc io input in deep sleep. + * + * @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio). + */ +static inline void rtcio_ll_enable_input_in_sleep(int rtcio_num) +{ + // TODO: [ESP32C5] IDF-8719 + // LP_IO.gpio[rtcio_num].mcu_ie = 1; + abort(); +} + +/** + * Disable rtc io input in deep sleep. + * + * @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio). + */ +static inline void rtcio_ll_disable_input_in_sleep(int rtcio_num) +{ + // TODO: [ESP32C5] IDF-8719 + // LP_IO.gpio[rtcio_num].mcu_ie = 0; + abort(); +} + +/** + * Enable rtc io keep another setting in deep sleep. + * + * @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio). + */ +static inline void rtcio_ll_enable_sleep_setting(int rtcio_num) +{ + // TODO: [ESP32C5] IDF-8719 + // LP_IO.gpio[rtcio_num].slp_sel = 1; + abort(); +} + +/** + * Disable rtc io keep another setting in deep sleep. (Default) + * + * @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio). + */ +static inline void rtcio_ll_disable_sleep_setting(int rtcio_num) +{ + // TODO: [ESP32C5] IDF-8719 + // LP_IO.gpio[rtcio_num].slp_sel = 0; + abort(); +} + +/** + * @brief Get the status of whether an IO is used for sleep wake-up. + * + * @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio). + * @return True if the pin is enabled to wake up from deep-sleep + */ +static inline bool rtcio_ll_wakeup_is_enabled(int rtcio_num) +{ + // TODO: [ESP32C5] IDF-8719 + // HAL_ASSERT(rtcio_num >= 0 && rtcio_num < SOC_RTCIO_PIN_COUNT && "io does not support deep sleep wake-up function"); + // return LP_IO.pin[rtcio_num].wakeup_enable; + abort(); + return (bool)0; +} + +/** + * @brief Get the rtc io interrupt status + * + * @return bit 0~7 corresponding to 0 ~ SOC_RTCIO_PIN_COUNT. + */ +static inline uint32_t rtcio_ll_get_interrupt_status(void) +{ + // TODO: [ESP32C5] IDF-8719 + // return (uint32_t)HAL_FORCE_READ_U32_REG_FIELD(LP_IO.status, status_interrupt); + abort(); + return (uint32_t)0; +} + +/** + * @brief Clear all LP IO pads status + */ +static inline void rtcio_ll_clear_interrupt_status(void) +{ + // TODO: [ESP32C5] IDF-8719 + // HAL_FORCE_MODIFY_U32_REG_FIELD(LP_IO.status_w1tc, status_w1tc, 0xff); + abort(); +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32c5/include/hal/spi_flash_encrypted_ll.h b/components/hal/esp32c5/include/hal/spi_flash_encrypted_ll.h new file mode 100644 index 0000000000..30d0174744 --- /dev/null +++ b/components/hal/esp32c5/include/hal/spi_flash_encrypted_ll.h @@ -0,0 +1,175 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/******************************************************************************* + * NOTICE + * The ll is not public api, don't use in application code. + * See readme.md in hal/include/hal/readme.md + ******************************************************************************/ + +// The Lowlevel layer for SPI Flash Encryption. + +#include +#include +#include "soc/hp_system_reg.h" +// #include "soc/xts_aes_reg.h" +#include "soc/soc.h" +#include "soc/soc_caps.h" +#include "hal/assert.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/// Choose type of chip you want to encrypt manually +typedef enum +{ + // TODO: [ESP32C5] IDF-8622, IDF-8649 + FLASH_ENCRYPTION_MANU = 0, ///!< Manually encrypt the flash chip. + PSRAM_ENCRYPTION_MANU = 1 ///!< Manually encrypt the psram chip. +} flash_encrypt_ll_type_t; + +/** + * Enable the flash encryption function under spi boot mode and download boot mode. + */ +static inline void spi_flash_encrypt_ll_enable(void) +{ + // TODO: [ESP32C5] IDF-8622, IDF-8649 + // REG_SET_BIT(HP_SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG, + // HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT | + // HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT); + abort(); +} + +/* + * Disable the flash encryption mode. + */ +static inline void spi_flash_encrypt_ll_disable(void) +{ + // TODO: [ESP32C5] IDF-8622, IDF-8649 + // REG_CLR_BIT(HP_SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG, + // HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT); + abort(); +} + +/** + * Choose type of chip you want to encrypt manully + * + * @param type The type of chip to be encrypted + * + * @note The hardware currently support flash encryption. + */ +static inline void spi_flash_encrypt_ll_type(flash_encrypt_ll_type_t type) +{ + // TODO: [ESP32C5] IDF-8622, IDF-8649 + // // Our hardware only support flash encryption + // HAL_ASSERT(type == FLASH_ENCRYPTION_MANU); + // REG_SET_FIELD(XTS_AES_DESTINATION_REG(0), XTS_AES_DESTINATION, type); + abort(); +} + +/** + * Configure the data size of a single encryption. + * + * @param block_size Size of the desired block. + */ +static inline void spi_flash_encrypt_ll_buffer_length(uint32_t size) +{ + // TODO: [ESP32C5] IDF-8622, IDF-8649 + // // Desired block should not be larger than the block size. + // REG_SET_FIELD(XTS_AES_LINESIZE_REG(0), XTS_AES_LINESIZE, size >> 5); + abort(); +} + +/** + * Save 32-bit piece of plaintext. + * + * @param address the address of written flash partition. + * @param buffer Buffer to store the input data. + * @param size Buffer size. + * + */ +static inline void spi_flash_encrypt_ll_plaintext_save(uint32_t address, const uint32_t* buffer, uint32_t size) +{ + // TODO: [ESP32C5] IDF-8622, IDF-8649 + // uint32_t plaintext_offs = (address % SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX); + // HAL_ASSERT(plaintext_offs + size <= SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX); + // memcpy((void *)(XTS_AES_PLAIN_MEM(0) + plaintext_offs), buffer, size); + abort(); +} + +/** + * Copy the flash address to XTS_AES physical address + * + * @param flash_addr flash address to write. + */ +static inline void spi_flash_encrypt_ll_address_save(uint32_t flash_addr) +{ + // TODO: [ESP32C5] IDF-8622, IDF-8649 + // REG_SET_FIELD(XTS_AES_PHYSICAL_ADDRESS_REG(0), XTS_AES_PHYSICAL_ADDRESS, flash_addr); + abort(); +} + +/** + * Start flash encryption + */ +static inline void spi_flash_encrypt_ll_calculate_start(void) +{ + // TODO: [ESP32C5] IDF-8622, IDF-8649 + // REG_SET_FIELD(XTS_AES_TRIGGER_REG(0), XTS_AES_TRIGGER, 1); + abort(); +} + +/** + * Wait for flash encryption termination + */ +static inline void spi_flash_encrypt_ll_calculate_wait_idle(void) +{ + // TODO: [ESP32C5] IDF-8622, IDF-8649 + // while(REG_GET_FIELD(XTS_AES_STATE_REG(0), XTS_AES_STATE) == 0x1) { + // } + abort(); +} + +/** + * Finish the flash encryption and make encrypted result accessible to SPI. + */ +static inline void spi_flash_encrypt_ll_done(void) +{ + // TODO: [ESP32C5] IDF-8622, IDF-8649 + // REG_SET_BIT(XTS_AES_RELEASE_REG(0), XTS_AES_RELEASE); + // while(REG_GET_FIELD(XTS_AES_STATE_REG(0), XTS_AES_STATE) != 0x3) { + // } + abort(); +} + +/** + * Set to destroy encrypted result + */ +static inline void spi_flash_encrypt_ll_destroy(void) +{ + // TODO: [ESP32C5] IDF-8622, IDF-8649 + // REG_SET_BIT(XTS_AES_DESTROY_REG(0), XTS_AES_DESTROY); + abort(); +} + +/** + * Check if is qualified to encrypt the buffer + * + * @param address the address of written flash partition. + * @param length Buffer size. + */ +static inline bool spi_flash_encrypt_ll_check(uint32_t address, uint32_t length) +{ + // TODO: [ESP32C5] IDF-8622, IDF-8649 + // return ((address % length) == 0) ? true : false; + abort(); + return (bool)0; +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32c5/include/hal/spi_flash_ll.h b/components/hal/esp32c5/include/hal/spi_flash_ll.h new file mode 100644 index 0000000000..b8dde2bf34 --- /dev/null +++ b/components/hal/esp32c5/include/hal/spi_flash_ll.h @@ -0,0 +1,102 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/******************************************************************************* + * NOTICE + * The ll is not public api, don't use in application code. + * See readme.md in soc/include/hal/readme.md + ******************************************************************************/ + +// The Lowlevel layer for SPI Flash + +#pragma once + +#include "gpspi_flash_ll.h" +#include "spimem_flash_ll.h" + +#ifdef __cplusplus +extern "C" { +#endif + +// TODO: [ESP32C5] IDF-8715 + +#define spi_flash_ll_calculate_clock_reg(host_id, clock_div) (((host_id)<=SPI1_HOST) ? spimem_flash_ll_calculate_clock_reg(clock_div) \ + : gpspi_flash_ll_calculate_clock_reg(clock_div)) + +#define spi_flash_ll_get_source_clock_freq_mhz(host_id) (((host_id)<=SPI1_HOST) ? spimem_flash_ll_get_source_freq_mhz() : GPSPI_FLASH_LL_PERIPHERAL_FREQUENCY_MHZ) + +#define spi_flash_ll_get_hw(host_id) (((host_id)<=SPI1_HOST ? (spi_dev_t*) spimem_flash_ll_get_hw(host_id) \ + : gpspi_flash_ll_get_hw(host_id))) + +#define spi_flash_ll_hw_get_id(dev) ({int dev_id = spimem_flash_ll_hw_get_id(dev); \ + if (dev_id < 0) {\ + dev_id = gpspi_flash_ll_hw_get_id(dev);\ + }\ + dev_id; \ + }) +// Since ESP32-C5, WB_mode is available, we extend 8 bits to occupy `Continuous Read Mode` bits. +#define SPI_FLASH_LL_CONTINUOUS_MODE_BIT_NUMS (8) + +typedef union { + gpspi_flash_ll_clock_reg_t gpspi; + spimem_flash_ll_clock_reg_t spimem; +} spi_flash_ll_clock_reg_t; + +#ifdef GPSPI_BUILD +#define spi_flash_ll_reset(dev) gpspi_flash_ll_reset((spi_dev_t*)dev) +#define spi_flash_ll_cmd_is_done(dev) gpspi_flash_ll_cmd_is_done((spi_dev_t*)dev) +#define spi_flash_ll_get_buffer_data(dev, buffer, read_len) gpspi_flash_ll_get_buffer_data((spi_dev_t*)dev, buffer, read_len) +#define spi_flash_ll_set_buffer_data(dev, buffer, len) gpspi_flash_ll_set_buffer_data((spi_dev_t*)dev, buffer, len) +#define spi_flash_ll_user_start(dev, pe_ops) gpspi_flash_ll_user_start((spi_dev_t*)dev, pe_ops) +#define spi_flash_ll_host_idle(dev) gpspi_flash_ll_host_idle((spi_dev_t*)dev) +#define spi_flash_ll_read_phase(dev) gpspi_flash_ll_read_phase((spi_dev_t*)dev) +#define spi_flash_ll_set_cs_pin(dev, pin) gpspi_flash_ll_set_cs_pin((spi_dev_t*)dev, pin) +#define spi_flash_ll_set_read_mode(dev, read_mode) gpspi_flash_ll_set_read_mode((spi_dev_t*)dev, read_mode) +#define spi_flash_ll_set_clock(dev, clk) gpspi_flash_ll_set_clock((spi_dev_t*)dev, (gpspi_flash_ll_clock_reg_t*)clk) +#define spi_flash_ll_set_miso_bitlen(dev, bitlen) gpspi_flash_ll_set_miso_bitlen((spi_dev_t*)dev, bitlen) +#define spi_flash_ll_set_mosi_bitlen(dev, bitlen) gpspi_flash_ll_set_mosi_bitlen((spi_dev_t*)dev, bitlen) +#define spi_flash_ll_set_command(dev, cmd, bitlen) gpspi_flash_ll_set_command((spi_dev_t*)dev, cmd, bitlen) +#define spi_flash_ll_set_addr_bitlen(dev, bitlen) gpspi_flash_ll_set_addr_bitlen((spi_dev_t*)dev, bitlen) +#define spi_flash_ll_get_addr_bitlen(dev) gpspi_flash_ll_get_addr_bitlen((spi_dev_t*)dev) +#define spi_flash_ll_set_address(dev, addr) gpspi_flash_ll_set_address((spi_dev_t*)dev, addr) +#define spi_flash_ll_set_usr_address(dev, addr, bitlen) gpspi_flash_ll_set_usr_address((spi_dev_t*)dev, addr, bitlen) +#define spi_flash_ll_set_dummy(dev, dummy) gpspi_flash_ll_set_dummy((spi_dev_t*)dev, dummy) +#define spi_flash_ll_set_hold(dev, hold_n) gpspi_flash_ll_set_hold((spi_dev_t*)dev, hold_n) +#define spi_flash_ll_set_cs_setup(dev, cs_setup_time) gpspi_flash_ll_set_cs_setup((spi_dev_t*)dev, cs_setup_time) +#define spi_flash_ll_set_extra_address(dev, extra_addr) { /* Not supported on gpspi on ESP32-C*/ } +#else +#define spi_flash_ll_reset(dev) spimem_flash_ll_reset((spi_mem_dev_t*)dev) +#define spi_flash_ll_cmd_is_done(dev) spimem_flash_ll_cmd_is_done((spi_mem_dev_t*)dev) +#define spi_flash_ll_erase_chip(dev) spimem_flash_ll_erase_chip((spi_mem_dev_t*)dev) +#define spi_flash_ll_erase_sector(dev) spimem_flash_ll_erase_sector((spi_mem_dev_t*)dev) +#define spi_flash_ll_erase_block(dev) spimem_flash_ll_erase_block((spi_mem_dev_t*)dev) +#define spi_flash_ll_set_write_protect(dev, wp) spimem_flash_ll_set_write_protect((spi_mem_dev_t*)dev, wp) +#define spi_flash_ll_get_buffer_data(dev, buffer, read_len) spimem_flash_ll_get_buffer_data((spi_mem_dev_t*)dev, buffer, read_len) +#define spi_flash_ll_set_buffer_data(dev, buffer, len) spimem_flash_ll_set_buffer_data((spi_mem_dev_t*)dev, buffer, len) +#define spi_flash_ll_program_page(dev, buffer, len) spimem_flash_ll_program_page((spi_mem_dev_t*)dev, buffer, len) +#define spi_flash_ll_user_start(dev, pe_ops) spimem_flash_ll_user_start((spi_mem_dev_t*)dev, pe_ops) +#define spi_flash_ll_host_idle(dev) spimem_flash_ll_host_idle((spi_mem_dev_t*)dev) +#define spi_flash_ll_read_phase(dev) spimem_flash_ll_read_phase((spi_mem_dev_t*)dev) +#define spi_flash_ll_set_cs_pin(dev, pin) spimem_flash_ll_set_cs_pin((spi_mem_dev_t*)dev, pin) +#define spi_flash_ll_set_read_mode(dev, read_mode) spimem_flash_ll_set_read_mode((spi_mem_dev_t*)dev, read_mode) +#define spi_flash_ll_set_clock(dev, clk) spimem_flash_ll_set_clock((spi_mem_dev_t*)dev, (spimem_flash_ll_clock_reg_t*)clk) +#define spi_flash_ll_set_miso_bitlen(dev, bitlen) spimem_flash_ll_set_miso_bitlen((spi_mem_dev_t*)dev, bitlen) +#define spi_flash_ll_set_mosi_bitlen(dev, bitlen) spimem_flash_ll_set_mosi_bitlen((spi_mem_dev_t*)dev, bitlen) +#define spi_flash_ll_set_command(dev, cmd, bitlen) spimem_flash_ll_set_command((spi_mem_dev_t*)dev, cmd, bitlen) +#define spi_flash_ll_set_addr_bitlen(dev, bitlen) spimem_flash_ll_set_addr_bitlen((spi_mem_dev_t*)dev, bitlen) +#define spi_flash_ll_get_addr_bitlen(dev) spimem_flash_ll_get_addr_bitlen((spi_mem_dev_t*) dev) +#define spi_flash_ll_set_address(dev, addr) spimem_flash_ll_set_address((spi_mem_dev_t*)dev, addr) +#define spi_flash_ll_set_usr_address(dev, addr, bitlen) spimem_flash_ll_set_usr_address((spi_mem_dev_t*)dev, addr, bitlen) +#define spi_flash_ll_set_dummy(dev, dummy) spimem_flash_ll_set_dummy((spi_mem_dev_t*)dev, dummy) +#define spi_flash_ll_set_hold(dev, hold_n) spimem_flash_ll_set_hold((spi_mem_dev_t*)dev, hold_n) +#define spi_flash_ll_set_cs_setup(dev, cs_setup_time) spimem_flash_ll_set_cs_setup((spi_mem_dev_t*)dev, cs_setup_time) +#define spi_flash_ll_set_extra_address(dev, extra_addr) spimem_flash_ll_set_extra_address((spi_mem_dev_t*)dev, extra_addr) + +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32c5/include/hal/spi_ll.h b/components/hal/esp32c5/include/hal/spi_ll.h new file mode 100644 index 0000000000..bb04567705 --- /dev/null +++ b/components/hal/esp32c5/include/hal/spi_ll.h @@ -0,0 +1,1404 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/******************************************************************************* + * NOTICE + * The hal is not public api, don't use in application code. + * See readme.md in soc/include/hal/readme.md + ******************************************************************************/ + +// The LL layer for SPI register operations + +#pragma once + +#include //for abs() +#include +#include "esp_attr.h" +#include "esp_types.h" +#include "soc/spi_periph.h" +#include "soc/spi_struct.h" +#include "soc/lldesc.h" +#include "hal/assert.h" +#include "hal/misc.h" +#include "hal/spi_types.h" +#include "soc/pcr_struct.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/// Interrupt not used. Don't use in app. +#define SPI_LL_UNUSED_INT_MASK (SPI_TRANS_DONE_INT_ENA | SPI_SLV_WR_DMA_DONE_INT_ENA | SPI_SLV_RD_DMA_DONE_INT_ENA | SPI_SLV_WR_BUF_DONE_INT_ENA | SPI_SLV_RD_BUF_DONE_INT_ENA) +/// These 2 masks together will set SPI transaction to one line mode +#define SPI_LL_ONE_LINE_CTRL_MASK (SPI_FREAD_QUAD | SPI_FREAD_DUAL | SPI_FCMD_QUAD | SPI_FCMD_DUAL | SPI_FADDR_QUAD | SPI_FADDR_DUAL) +#define SPI_LL_ONE_LINE_USER_MASK (SPI_FWRITE_QUAD | SPI_FWRITE_DUAL) +/// Swap the bit order to its correct place to send +#define HAL_SPI_SWAP_DATA_TX(data, len) HAL_SWAP32((uint32_t)(data) << (32 - len)) +#define SPI_LL_GET_HW(ID) (((ID)==1) ? &GPSPI2 : NULL) + +#define SPI_LL_DMA_MAX_BIT_LEN (1 << 18) //reg len: 18 bits +#define SPI_LL_CPU_MAX_BIT_LEN (16 * 32) //Fifo len: 16 words +#define SPI_LL_MOSI_FREE_LEVEL 1 //Default level after bus initialized + +/** + * The data structure holding calculated clock configuration. Since the + * calculation needs long time, it should be calculated during initialization and + * stored somewhere to be quickly used. + */ +typedef uint32_t spi_ll_clock_val_t; +typedef spi_dev_t spi_dma_dev_t; + +// Type definition of all supported interrupts +typedef enum { + SPI_LL_INTR_TRANS_DONE = BIT(0), ///< A transaction has done + SPI_LL_INTR_RDBUF = BIT(6), ///< Has received RDBUF command. Only available in slave HD. + SPI_LL_INTR_WRBUF = BIT(7), ///< Has received WRBUF command. Only available in slave HD. + SPI_LL_INTR_RDDMA = BIT(8), ///< Has received RDDMA command. Only available in slave HD. + SPI_LL_INTR_WRDMA = BIT(9), ///< Has received WRDMA command. Only available in slave HD. + SPI_LL_INTR_CMD7 = BIT(10), ///< Has received CMD7 command. Only available in slave HD. + SPI_LL_INTR_CMD8 = BIT(11), ///< Has received CMD8 command. Only available in slave HD. + SPI_LL_INTR_CMD9 = BIT(12), ///< Has received CMD9 command. Only available in slave HD. + SPI_LL_INTR_CMDA = BIT(13), ///< Has received CMDA command. Only available in slave HD. + SPI_LL_INTR_SEG_DONE = BIT(14), +} spi_ll_intr_t; + +// Flags for conditions under which the transaction length should be recorded +typedef enum { + SPI_LL_TRANS_LEN_COND_WRBUF = BIT(0), ///< WRBUF length will be recorded + SPI_LL_TRANS_LEN_COND_RDBUF = BIT(1), ///< RDBUF length will be recorded + SPI_LL_TRANS_LEN_COND_WRDMA = BIT(2), ///< WRDMA length will be recorded + SPI_LL_TRANS_LEN_COND_RDDMA = BIT(3), ///< RDDMA length will be recorded +} spi_ll_trans_len_cond_t; + +// SPI base command +typedef enum { + /* Slave HD Only */ + SPI_LL_BASE_CMD_HD_WRBUF = 0x01, + SPI_LL_BASE_CMD_HD_RDBUF = 0x02, + SPI_LL_BASE_CMD_HD_WRDMA = 0x03, + SPI_LL_BASE_CMD_HD_RDDMA = 0x04, + SPI_LL_BASE_CMD_HD_SEG_END = 0x05, + SPI_LL_BASE_CMD_HD_EN_QPI = 0x06, + SPI_LL_BASE_CMD_HD_WR_END = 0x07, + SPI_LL_BASE_CMD_HD_INT0 = 0x08, + SPI_LL_BASE_CMD_HD_INT1 = 0x09, + SPI_LL_BASE_CMD_HD_INT2 = 0x0A, +} spi_ll_base_command_t; + +/*------------------------------------------------------------------------------ + * Control + *----------------------------------------------------------------------------*/ +/** + * Enable peripheral register clock + * + * @param host_id Peripheral index number, see `spi_host_device_t` + * @param enable Enable/Disable + */ +static inline void spi_ll_enable_bus_clock(spi_host_device_t host_id, bool enable) +{ + // TODO: [ESP32C5] IDF-8698, IDF-8699 + // switch (host_id) + // { + // case SPI1_HOST: + // PCR.mspi_conf.mspi_clk_en = enable; + // break; + // case SPI2_HOST: + // PCR.spi2_conf.spi2_clk_en = enable; + // break; + // default: HAL_ASSERT(false); + // } + abort(); +} + +/** + * Reset whole peripheral register to init value defined by HW design + * + * @param host_id Peripheral index number, see `spi_host_device_t` + */ +static inline void spi_ll_reset_register(spi_host_device_t host_id) +{ + // TODO: [ESP32C5] IDF-8698, IDF-8699 + // switch (host_id) + // { + // case SPI1_HOST: + // PCR.mspi_conf.mspi_rst_en = 1; + // PCR.mspi_conf.mspi_rst_en = 0; + // break; + // case SPI2_HOST: + // PCR.spi2_conf.spi2_rst_en = 1; + // PCR.spi2_conf.spi2_rst_en = 0; + // break; + // default: HAL_ASSERT(false); + // } + abort(); +} + +/** + * Enable functional output clock within peripheral + * + * @param host_id Peripheral index number, see `spi_host_device_t` + * @param enable Enable/Disable + */ +static inline void spi_ll_enable_clock(spi_host_device_t host_id, bool enable) +{ + // TODO: [ESP32C5] IDF-8698, IDF-8699 + // (void) host_id; + // PCR.spi2_clkm_conf.spi2_clkm_en = enable; + abort(); +} + +/** + * Select SPI peripheral clock source (master). + * + * @param hw Beginning address of the peripheral registers. + * @param clk_source clock source to select, see valid sources in type `spi_clock_source_t` + */ +__attribute__((always_inline)) +static inline void spi_ll_set_clk_source(spi_dev_t *hw, spi_clock_source_t clk_source) +{ + // TODO: [ESP32C5] IDF-8698, IDF-8699 + // switch (clk_source) + // { + // case SPI_CLK_SRC_RC_FAST: + // PCR.spi2_clkm_conf.spi2_clkm_sel = 2; + // break; + // case SPI_CLK_SRC_XTAL: + // PCR.spi2_clkm_conf.spi2_clkm_sel = 0; + // break; + // default: + // PCR.spi2_clkm_conf.spi2_clkm_sel = 1; + // break; + // } + abort(); +} + +/** + * Initialize SPI peripheral (master). + * + * @param hw Beginning address of the peripheral registers. + */ +static inline void spi_ll_master_init(spi_dev_t *hw) +{ + // TODO: [ESP32C5] IDF-8698, IDF-8699 + // //Reset timing + // hw->user1.cs_setup_time = 0; + // hw->user1.cs_hold_time = 0; + // // //use all 64 bytes of the buffer + // hw->user.usr_miso_highpart = 0; + // hw->user.usr_mosi_highpart = 0; + // // //Disable unneeded ints + // hw->slave.val = 0; + // hw->user.val = 0; + // // PCR.spi2_clkm_conf.spi2_clkm_sel = 1; + // // hw->dma_conf.val = 0; + // hw->dma_conf.slv_tx_seg_trans_clr_en = 1; + // hw->dma_conf.slv_rx_seg_trans_clr_en = 1; + // hw->dma_conf.dma_slv_seg_trans_en = 0; + abort(); +} + +/** + * Initialize SPI peripheral (slave). + * + * @param hw Beginning address of the peripheral registers. + */ +static inline void spi_ll_slave_init(spi_dev_t *hw) +{ + // TODO: [ESP32C5] IDF-8698, IDF-8699 + // //Configure slave + // hw->clock.val = 0; + // hw->user.val = 0; + // hw->ctrl.val = 0; + // hw->user.doutdin = 1; //we only support full duplex + // hw->user.sio = 0; + // hw->slave.slave_mode = 1; + // hw->slave.soft_reset = 1; + // hw->slave.soft_reset = 0; + // //use all 64 bytes of the buffer + // hw->user.usr_miso_highpart = 0; + // hw->user.usr_mosi_highpart = 0; + // // // Configure DMA In-Link to not be terminated when transaction bit counter exceeds + // hw->dma_conf.rx_eof_en = 0; + // hw->dma_conf.dma_slv_seg_trans_en = 0; + // // //Disable unneeded ints + // hw->dma_int_ena.val &= ~SPI_LL_UNUSED_INT_MASK; + abort(); +} + +/** + * Initialize SPI peripheral (slave half duplex mode) + * + * @param hw Beginning address of the peripheral registers. + */ +static inline void spi_ll_slave_hd_init(spi_dev_t *hw) +{ + // TODO: [ESP32C5] IDF-8698, IDF-8699 + // hw->clock.val = 0; + // hw->user.val = 0; + // hw->ctrl.val = 0; + // hw->user.doutdin = 0; + // hw->user.sio = 0; + // // hw->slave.soft_reset = 1; + // hw->slave.soft_reset = 0; + // hw->slave.slave_mode = 1; + abort(); +} + +/** + * Determine and unify the default level of mosi line when bus free + * + * @param hw Beginning address of the peripheral registers. + */ +static inline void spi_ll_set_mosi_free_level(spi_dev_t *hw, bool level) +{ + // TODO: [ESP32C5] IDF-8698, IDF-8699 + // hw->ctrl.d_pol = level; //set default level for MOSI only on IDLE state + abort(); +} + +/** + * Apply the register configurations and wait until it's done + * + * @param hw Beginning address of the peripheral registers. + */ +static inline void spi_ll_apply_config(spi_dev_t *hw) +{ + // TODO: [ESP32C5] IDF-8698, IDF-8699 + // hw->cmd.update = 1; + // while (hw->cmd.update); //waiting config applied + abort(); +} + +/** + * Check whether user-defined transaction is done. + * + * @param hw Beginning address of the peripheral registers. + * + * @return True if transaction is done, otherwise false. + */ +static inline bool spi_ll_usr_is_done(spi_dev_t *hw) +{ + // TODO: [ESP32C5] IDF-8698, IDF-8699 + // return hw->dma_int_raw.trans_done; + abort(); + return (bool)0; +} + +/** + * Trigger start of user-defined transaction. + * + * @param hw Beginning address of the peripheral registers. + */ +static inline void spi_ll_user_start(spi_dev_t *hw) +{ + // TODO: [ESP32C5] IDF-8698, IDF-8699 + // hw->cmd.usr = 1; + abort(); +} + +/** + * Get current running command bit-mask. (Preview) + * + * @param hw Beginning address of the peripheral registers. + * + * @return Bitmask of running command, see ``SPI_CMD_REG``. 0 if no in-flight command. + */ +static inline uint32_t spi_ll_get_running_cmd(spi_dev_t *hw) +{ + // TODO: [ESP32C5] IDF-8698, IDF-8699 + // return hw->cmd.val; + abort(); + return (uint32_t)0; +} + +/** + * Reset the slave peripheral before next transaction. + * + * @param hw Beginning address of the peripheral registers. + */ +static inline void spi_ll_slave_reset(spi_dev_t *hw) +{ + // TODO: [ESP32C5] IDF-8698, IDF-8699 + // hw->slave.soft_reset = 1; + // hw->slave.soft_reset = 0; + abort(); +} + +/** + * Reset SPI CPU TX FIFO + * + * On ESP32C3, this function is not seperated + * + * @param hw Beginning address of the peripheral registers. + */ +static inline void spi_ll_cpu_tx_fifo_reset(spi_dev_t *hw) +{ + // TODO: [ESP32C5] IDF-8698, IDF-8699 + // hw->dma_conf.buf_afifo_rst = 1; + // hw->dma_conf.buf_afifo_rst = 0; + abort(); +} + +/** + * Reset SPI CPU RX FIFO + * + * On ESP32C3, this function is not seperated + * + * @param hw Beginning address of the peripheral registers. + */ +static inline void spi_ll_cpu_rx_fifo_reset(spi_dev_t *hw) +{ + // TODO: [ESP32C5] IDF-8698, IDF-8699 + // hw->dma_conf.rx_afifo_rst = 1; + // hw->dma_conf.rx_afifo_rst = 0; + abort(); +} + +/** + * Reset SPI DMA TX FIFO + * + * @param hw Beginning address of the peripheral registers. + */ +static inline void spi_ll_dma_tx_fifo_reset(spi_dev_t *hw) +{ + // TODO: [ESP32C5] IDF-8698, IDF-8699 + // hw->dma_conf.dma_afifo_rst = 1; + // hw->dma_conf.dma_afifo_rst = 0; + abort(); +} + +/** + * Reset SPI DMA RX FIFO + * + * @param hw Beginning address of the peripheral registers. + */ +static inline void spi_ll_dma_rx_fifo_reset(spi_dev_t *hw) +{ + // TODO: [ESP32C5] IDF-8698, IDF-8699 + // hw->dma_conf.rx_afifo_rst = 1; + // hw->dma_conf.rx_afifo_rst = 0; + abort(); +} + +/** + * Clear in fifo full error + * + * @param hw Beginning address of the peripheral registers. + */ +static inline void spi_ll_infifo_full_clr(spi_dev_t *hw) +{ + // TODO: [ESP32C5] IDF-8698, IDF-8699 + // hw->dma_int_clr.dma_infifo_full_err = 1; + abort(); +} + +/** + * Clear out fifo empty error + * + * @param hw Beginning address of the peripheral registers. + */ +static inline void spi_ll_outfifo_empty_clr(spi_dev_t *hw) +{ + // TODO: [ESP32C5] IDF-8698, IDF-8699 + // hw->dma_int_clr.dma_outfifo_empty_err = 1; + abort(); +} + +/*------------------------------------------------------------------------------ + * DMA + *----------------------------------------------------------------------------*/ +/** + * Enable/Disable RX DMA (Peripherals->DMA->RAM) + * + * @param hw Beginning address of the peripheral registers. + * @param enable 1: enable; 2: disable + */ +static inline void spi_ll_dma_rx_enable(spi_dev_t *hw, bool enable) +{ + // TODO: [ESP32C5] IDF-8698, IDF-8699 + // hw->dma_conf.dma_rx_ena = enable; + abort(); +} + +/** + * Enable/Disable TX DMA (RAM->DMA->Peripherals) + * + * @param hw Beginning address of the peripheral registers. + * @param enable 1: enable; 2: disable + */ +static inline void spi_ll_dma_tx_enable(spi_dev_t *hw, bool enable) +{ + // TODO: [ESP32C5] IDF-8698, IDF-8699 + // hw->dma_conf.dma_tx_ena = enable; + abort(); +} + +/** + * Configuration of RX DMA EOF interrupt generation way + * + * @param hw Beginning address of the peripheral registers. + * @param enable 1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition. 0: spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or spi_dma_seg_trans_done in seg-trans. + */ +static inline void spi_ll_dma_set_rx_eof_generation(spi_dev_t *hw, bool enable) +{ + // TODO: [ESP32C5] IDF-8698, IDF-8699 + // hw->dma_conf.rx_eof_en = enable; + abort(); +} + +/*------------------------------------------------------------------------------ + * Buffer + *----------------------------------------------------------------------------*/ +/** + * Write to SPI hardware data buffer. + * + * @param hw Beginning address of the peripheral registers. + * @param buffer_to_send Address of the data to be written to the hardware data buffer. + * @param bitlen Length to write, in bits. + */ +static inline void spi_ll_write_buffer(spi_dev_t *hw, const uint8_t *buffer_to_send, size_t bitlen) +{ + // TODO: [ESP32C5] IDF-8698, IDF-8699 + // for (int x = 0; x < bitlen; x += 32) { + // //Use memcpy to get around alignment issues for txdata + // uint32_t word; + // memcpy(&word, &buffer_to_send[x / 8], 4); + // hw->data_buf[(x / 32)].buf = word; + // } + abort(); +} + +/** + * Write to SPI hardware data buffer by buffer ID (address) + * + * @param hw Beginning address of the peripheral registers + * @param byte_id Start ID (address) of the hardware buffer to be written + * @param data Address of the data to be written to the hardware data buffer. + * @param len Length to write, in bytes. + */ +static inline void spi_ll_write_buffer_byte(spi_dev_t *hw, int byte_id, uint8_t *data, int len) +{ + // TODO: [ESP32C5] IDF-8698, IDF-8699 + // HAL_ASSERT(byte_id + len <= 64); + // HAL_ASSERT(len > 0); + // HAL_ASSERT(byte_id >= 0); + // // while (len > 0) { + // uint32_t word; + // int offset = byte_id % 4; + // int copy_len = 4 - offset; + // if (copy_len > len) { + // copy_len = len; + // } + // // //read-modify-write + // if (copy_len != 4) { + // word = hw->data_buf[byte_id / 4].buf; //read + // } + // memcpy(((uint8_t *)&word) + offset, data, copy_len); //modify + // hw->data_buf[byte_id / 4].buf = word; //write + // // data += copy_len; + // byte_id += copy_len; + // len -= copy_len; + // } + abort(); +} + +/** + * Read from SPI hardware data buffer. + * + * @param hw Beginning address of the peripheral registers. + * @param buffer_to_rcv Address of a buffer to read data from hardware data buffer + * @param bitlen Length to read, in bits. + */ +static inline void spi_ll_read_buffer(spi_dev_t *hw, uint8_t *buffer_to_rcv, size_t bitlen) +{ + // TODO: [ESP32C5] IDF-8698, IDF-8699 + // for (int x = 0; x < bitlen; x += 32) { + // //Do a memcpy to get around possible alignment issues in rx_buffer + // uint32_t word = hw->data_buf[x / 32].buf; + // int len = bitlen - x; + // if (len > 32) { + // len = 32; + // } + // memcpy(&buffer_to_rcv[x / 8], &word, (len + 7) / 8); + // } + abort(); +} + +/** + * Read from SPI hardware data buffer by buffer ID (address) + * + * @param hw Beginning address of the peripheral registers + * @param byte_id Start ID (address) of the hardware buffer to be read + * @param data Address of a buffer to read data from hardware data buffer + * @param len Length to read, in bytes. + */ +static inline void spi_ll_read_buffer_byte(spi_dev_t *hw, int byte_id, uint8_t *out_data, int len) +{ + // TODO: [ESP32C5] IDF-8698, IDF-8699 + // while (len > 0) { + // uint32_t word = hw->data_buf[byte_id / 4].buf; + // int offset = byte_id % 4; + // int copy_len = 4 - offset; + // if (copy_len > len) { + // copy_len = len; + // } + // // memcpy(out_data, ((uint8_t *)&word) + offset, copy_len); + // byte_id += copy_len; + // out_data += copy_len; + // len -= copy_len; + // } + abort(); +} + +/*------------------------------------------------------------------------------ + * Configs: mode + *----------------------------------------------------------------------------*/ +/** + * Enable/disable the postive-cs feature. + * + * @param hw Beginning address of the peripheral registers. + * @param cs One of the CS (0-2) to enable/disable the feature. + * @param pos_cs True to enable the feature, otherwise disable (default). + */ +static inline void spi_ll_master_set_pos_cs(spi_dev_t *hw, int cs, uint32_t pos_cs) +{ + // TODO: [ESP32C5] IDF-8698, IDF-8699 + // if (pos_cs) { + // hw->misc.master_cs_pol |= (1 << cs); + // } else { + // hw->misc.master_cs_pol &= ~(1 << cs); + // } + abort(); +} + +/** + * Enable/disable the LSBFIRST feature for TX data. + * + * @param hw Beginning address of the peripheral registers. + * @param lsbfirst True if LSB of TX data to be sent first, otherwise MSB is sent first (default). + */ +static inline void spi_ll_set_tx_lsbfirst(spi_dev_t *hw, bool lsbfirst) +{ + // TODO: [ESP32C5] IDF-8698, IDF-8699 + // hw->ctrl.wr_bit_order = lsbfirst; + abort(); +} + +/** + * Enable/disable the LSBFIRST feature for RX data. + * + * @param hw Beginning address of the peripheral registers. + * @param lsbfirst True if first bit received as LSB, otherwise as MSB (default). + */ +static inline void spi_ll_set_rx_lsbfirst(spi_dev_t *hw, bool lsbfirst) +{ + // TODO: [ESP32C5] IDF-8698, IDF-8699 + // hw->ctrl.rd_bit_order = lsbfirst; + abort(); +} + +/** + * Set SPI mode for the peripheral as master. + * + * @param hw Beginning address of the peripheral registers. + * @param mode SPI mode to work at, 0-3. + */ +static inline void spi_ll_master_set_mode(spi_dev_t *hw, uint8_t mode) +{ + // TODO: [ESP32C5] IDF-8698, IDF-8699 + // //Configure polarity + // if (mode == 0) { + // hw->misc.ck_idle_edge = 0; + // hw->user.ck_out_edge = 0; + // } else if (mode == 1) { + // hw->misc.ck_idle_edge = 0; + // hw->user.ck_out_edge = 1; + // } else if (mode == 2) { + // hw->misc.ck_idle_edge = 1; + // hw->user.ck_out_edge = 1; + // } else if (mode == 3) { + // hw->misc.ck_idle_edge = 1; + // hw->user.ck_out_edge = 0; + // } + abort(); +} + +/** + * Set SPI mode for the peripheral as slave. + * + * @param hw Beginning address of the peripheral registers. + * @param mode SPI mode to work at, 0-3. + */ +static inline void spi_ll_slave_set_mode(spi_dev_t *hw, const int mode, bool dma_used) +{ + // TODO: [ESP32C5] IDF-8698, IDF-8699 + // if (mode == 0) { + // hw->misc.ck_idle_edge = 0; + // hw->user.rsck_i_edge = 0; + // hw->user.tsck_i_edge = 0; + // hw->slave.clk_mode_13 = 0; + // } else if (mode == 1) { + // hw->misc.ck_idle_edge = 0; + // hw->user.rsck_i_edge = 1; + // hw->user.tsck_i_edge = 1; + // hw->slave.clk_mode_13 = 1; + // } else if (mode == 2) { + // hw->misc.ck_idle_edge = 1; + // hw->user.rsck_i_edge = 1; + // hw->user.tsck_i_edge = 1; + // hw->slave.clk_mode_13 = 0; + // } else if (mode == 3) { + // hw->misc.ck_idle_edge = 1; + // hw->user.rsck_i_edge = 0; + // hw->user.tsck_i_edge = 0; + // hw->slave.clk_mode_13 = 1; + // } + // hw->slave.rsck_data_out = 0; + abort(); +} + +/** + * Set SPI to work in full duplex or half duplex mode. + * + * @param hw Beginning address of the peripheral registers. + * @param half_duplex True to work in half duplex mode, otherwise in full duplex mode. + */ +static inline void spi_ll_set_half_duplex(spi_dev_t *hw, bool half_duplex) +{ + // TODO: [ESP32C5] IDF-8698, IDF-8699 + // hw->user.doutdin = !half_duplex; + abort(); +} + +/** + * Set SPI to work in SIO mode or not. + * + * SIO is a mode which MOSI and MISO share a line. The device MUST work in half-duplexmode. + * + * @param hw Beginning address of the peripheral registers. + * @param sio_mode True to work in SIO mode, otherwise false. + */ +static inline void spi_ll_set_sio_mode(spi_dev_t *hw, int sio_mode) +{ + // TODO: [ESP32C5] IDF-8698, IDF-8699 + // hw->user.sio = sio_mode; + abort(); +} + +/** + * Configure the SPI transaction line mode for the master to use. + * + * @param hw Beginning address of the peripheral registers. + * @param line_mode SPI transaction line mode to use, see ``spi_line_mode_t``. + */ +static inline void spi_ll_master_set_line_mode(spi_dev_t *hw, spi_line_mode_t line_mode) +{ + // TODO: [ESP32C5] IDF-8698, IDF-8699 + // hw->ctrl.val &= ~SPI_LL_ONE_LINE_CTRL_MASK; + // hw->user.val &= ~SPI_LL_ONE_LINE_USER_MASK; + // hw->ctrl.fcmd_dual = (line_mode.cmd_lines == 2); + // hw->ctrl.fcmd_quad = (line_mode.cmd_lines == 4); + // hw->ctrl.faddr_dual = (line_mode.addr_lines == 2); + // hw->ctrl.faddr_quad = (line_mode.addr_lines == 4); + // hw->ctrl.fread_dual = (line_mode.data_lines == 2); + // hw->user.fwrite_dual = (line_mode.data_lines == 2); + // hw->ctrl.fread_quad = (line_mode.data_lines == 4); + // hw->user.fwrite_quad = (line_mode.data_lines == 4); + abort(); +} + +/** + * Set the SPI slave to work in segment transaction mode + * + * @param hw Beginning address of the peripheral registers. + * @param seg_trans True to work in seg mode, otherwise false. + */ +static inline void spi_ll_slave_set_seg_mode(spi_dev_t *hw, bool seg_trans) +{ + // TODO: [ESP32C5] IDF-8698, IDF-8699 + // hw->dma_conf.dma_slv_seg_trans_en = seg_trans; + abort(); +} + +/** + * Select one of the CS to use in current transaction. + * + * @param hw Beginning address of the peripheral registers. + * @param cs_id The cs to use, 0-2, otherwise none of them is used. + */ +static inline void spi_ll_master_select_cs(spi_dev_t *hw, int cs_id) +{ + // TODO: [ESP32C5] IDF-8698, IDF-8699 + // hw->misc.cs0_dis = (cs_id == 0) ? 0 : 1; + // hw->misc.cs1_dis = (cs_id == 1) ? 0 : 1; + // hw->misc.cs2_dis = (cs_id == 2) ? 0 : 1; + // hw->misc.cs3_dis = (cs_id == 3) ? 0 : 1; + // hw->misc.cs4_dis = (cs_id == 4) ? 0 : 1; + // hw->misc.cs5_dis = (cs_id == 5) ? 0 : 1; + abort(); +} + +/** + * Keep Chip Select activated after the current transaction. + * + * @param hw Beginning address of the peripheral registers. + * @param keep_active if 0 don't keep CS activated, else keep CS activated + */ +static inline void spi_ll_master_keep_cs(spi_dev_t *hw, int keep_active) +{ + // TODO: [ESP32C5] IDF-8698, IDF-8699 + // hw->misc.cs_keep_active = (keep_active != 0) ? 1 : 0; + abort(); +} + +/*------------------------------------------------------------------------------ + * Configs: parameters + *----------------------------------------------------------------------------*/ +/** + * Set the clock for master by stored value. + * + * @param hw Beginning address of the peripheral registers. + * @param val Stored clock configuration calculated before (by ``spi_ll_cal_clock``). + */ +static inline void spi_ll_master_set_clock_by_reg(spi_dev_t *hw, const spi_ll_clock_val_t *val) +{ + // TODO: [ESP32C5] IDF-8698, IDF-8699 + // hw->clock.val = *(uint32_t *)val; + abort(); +} + +/** + * Get the frequency of given dividers. Don't use in app. + * + * @param fapb APB clock of the system. + * @param pre Pre devider. + * @param n Main divider. + * + * @return Frequency of given dividers. + */ +static inline int spi_ll_freq_for_pre_n(int fapb, int pre, int n) +{ + // TODO: [ESP32C5] IDF-8698, IDF-8699 + // return (fapb / (pre * n)); + abort(); + return (int)0; +} + +/** + * Calculate the nearest frequency avaliable for master. + * + * @param fapb APB clock of the system. + * @param hz Frequncy desired. + * @param duty_cycle Duty cycle desired. + * @param out_reg Output address to store the calculated clock configurations for the return frequency. + * + * @return Actual (nearest) frequency. + */ +static inline int spi_ll_master_cal_clock(int fapb, int hz, int duty_cycle, spi_ll_clock_val_t *out_reg) +{ + // TODO: [ESP32C5] IDF-8698, IDF-8699 + // typeof(GPSPI2.clock) reg; + // int eff_clk; + // // //In hw, n, h and l are 1-64, pre is 1-8K. Value written to register is one lower than used value. + // if (hz > ((fapb / 4) * 3)) { + // //Using Fapb directly will give us the best result here. + // reg.clkcnt_l = 0; + // reg.clkcnt_h = 0; + // reg.clkcnt_n = 0; + // reg.clkdiv_pre = 0; + // reg.clk_equ_sysclk = 1; + // eff_clk = fapb; + // } else { + // //For best duty cycle resolution, we want n to be as close to 32 as possible, but + // //we also need a pre/n combo that gets us as close as possible to the intended freq. + // //To do this, we bruteforce n and calculate the best pre to go along with that. + // //If there's a choice between pre/n combos that give the same result, use the one + // //with the higher n. + // int pre, n, h, l; + // int bestn = -1; + // int bestpre = -1; + // int besterr = 0; + // int errval; + // for (n = 2; n <= 64; n++) { //Start at 2: we need to be able to set h/l so we have at least one high and one low pulse. + // //Effectively, this does pre=round((fapb/n)/hz). + // pre = ((fapb / n) + (hz / 2)) / hz; + // if (pre <= 0) { + // pre = 1; + // } + // if (pre > 16) { + // pre = 16; + // } + // errval = abs(spi_ll_freq_for_pre_n(fapb, pre, n) - hz); + // if (bestn == -1 || errval <= besterr) { + // besterr = errval; + // bestn = n; + // bestpre = pre; + // } + // } + // // n = bestn; + // pre = bestpre; + // l = n; + // //This effectively does round((duty_cycle*n)/256) + // h = (duty_cycle * n + 127) / 256; + // if (h <= 0) { + // h = 1; + // } + // // reg.clk_equ_sysclk = 0; + // reg.clkcnt_n = n - 1; + // reg.clkdiv_pre = pre - 1; + // reg.clkcnt_h = h - 1; + // reg.clkcnt_l = l - 1; + // eff_clk = spi_ll_freq_for_pre_n(fapb, pre, n); + // } + // if (out_reg != NULL) { + // *(uint32_t *)out_reg = reg.val; + // } + // return eff_clk; + abort(); + return (int)0; +} + +/** + * Calculate and set clock for SPI master according to desired parameters. + * + * This takes long, suggest to calculate the configuration during + * initialization by ``spi_ll_master_cal_clock`` and store the result, then + * configure the clock by stored value when used by + * ``spi_ll_msater_set_clock_by_reg``. + * + * @param hw Beginning address of the peripheral registers. + * @param fapb APB clock of the system. + * @param hz Frequncy desired. + * @param duty_cycle Duty cycle desired. + * + * @return Actual frequency that is used. + */ +static inline int spi_ll_master_set_clock(spi_dev_t *hw, int fapb, int hz, int duty_cycle) +{ + // TODO: [ESP32C5] IDF-8698, IDF-8699 + // spi_ll_clock_val_t reg_val; + // int freq = spi_ll_master_cal_clock(fapb, hz, duty_cycle, ®_val); + // spi_ll_master_set_clock_by_reg(hw, ®_val); + // return freq; + abort(); + return (int)0; +} + +/** + * Set the mosi delay after the output edge to the signal. (Preview) + * + * The delay mode/num is a Espressif conception, may change in the new chips. + * + * @param hw Beginning address of the peripheral registers. + * @param delay_mode Delay mode, see TRM. + * @param delay_num APB clocks to delay. + */ +static inline void spi_ll_set_mosi_delay(spi_dev_t *hw, int delay_mode, int delay_num) +{ + // TODO: [ESP32C5] IDF-8698, IDF-8699 + abort(); +} + +/** + * Set the miso delay applied to the input signal before the internal peripheral. (Preview) + * + * The delay mode/num is a Espressif conception, may change in the new chips. + * + * @param hw Beginning address of the peripheral registers. + * @param delay_mode Delay mode, see TRM. + * @param delay_num APB clocks to delay. + */ +static inline void spi_ll_set_miso_delay(spi_dev_t *hw, int delay_mode, int delay_num) +{ + // TODO: [ESP32C5] IDF-8698, IDF-8699 + abort(); +} + +/** + * Set the delay of SPI clocks before the CS inactive edge after the last SPI clock. + * + * @param hw Beginning address of the peripheral registers. + * @param hold Delay of SPI clocks after the last clock, 0 to disable the hold phase. + */ +static inline void spi_ll_master_set_cs_hold(spi_dev_t *hw, int hold) +{ + // TODO: [ESP32C5] IDF-8698, IDF-8699 + // hw->user1.cs_hold_time = hold; + // hw->user.cs_hold = hold ? 1 : 0; + abort(); +} + +/** + * Set the delay of SPI clocks before the first SPI clock after the CS active edge. + * + * Note ESP32 doesn't support to use this feature when command/address phases + * are used in full duplex mode. + * + * @param hw Beginning address of the peripheral registers. + * @param setup Delay of SPI clocks after the CS active edge, 0 to disable the setup phase. + */ +static inline void spi_ll_master_set_cs_setup(spi_dev_t *hw, uint8_t setup) +{ + // TODO: [ESP32C5] IDF-8698, IDF-8699 + // hw->user1.cs_setup_time = setup - 1; + // hw->user.cs_setup = setup ? 1 : 0; + abort(); +} + +/*------------------------------------------------------------------------------ + * Configs: data + *----------------------------------------------------------------------------*/ +/** + * Set the output length (master). + * This should be called before master setting MISO(input) length + * + * @param hw Beginning address of the peripheral registers. + * @param bitlen output length, in bits. + */ +static inline void spi_ll_set_mosi_bitlen(spi_dev_t *hw, size_t bitlen) +{ + // TODO: [ESP32C5] IDF-8698, IDF-8699 + // if (bitlen > 0) { + // hw->ms_dlen.ms_data_bitlen = bitlen - 1; + // } + abort(); +} + +/** + * Set the input length (master). + * + * @param hw Beginning address of the peripheral registers. + * @param bitlen input length, in bits. + */ +static inline void spi_ll_set_miso_bitlen(spi_dev_t *hw, size_t bitlen) +{ + // TODO: [ESP32C5] IDF-8698, IDF-8699 + // if (bitlen > 0) { + // hw->ms_dlen.ms_data_bitlen = bitlen - 1; + // } + abort(); +} + +/** + * Set the maximum input length (slave). + * + * @param hw Beginning address of the peripheral registers. + * @param bitlen Input length, in bits. + */ +static inline void spi_ll_slave_set_rx_bitlen(spi_dev_t *hw, size_t bitlen) +{ + // TODO: [ESP32C5] IDF-8698, IDF-8699 + // //This is not used in esp32c3 + abort(); +} + +/** + * Set the maximum output length (slave). + * + * @param hw Beginning address of the peripheral registers. + * @param bitlen Output length, in bits. + */ +static inline void spi_ll_slave_set_tx_bitlen(spi_dev_t *hw, size_t bitlen) +{ + // TODO: [ESP32C5] IDF-8698, IDF-8699 + // //This is not used in esp32c3 + abort(); +} + +/** + * Set the length of command phase. + * + * When in 4-bit mode, the SPI cycles of the phase will be shorter. E.g. 16-bit + * command phases takes 4 cycles in 4-bit mode. + * + * @param hw Beginning address of the peripheral registers. + * @param bitlen Length of command phase, in bits. 0 to disable the command phase. + */ +static inline void spi_ll_set_command_bitlen(spi_dev_t *hw, int bitlen) +{ + // TODO: [ESP32C5] IDF-8698, IDF-8699 + // hw->user2.usr_command_bitlen = bitlen - 1; + // hw->user.usr_command = bitlen ? 1 : 0; + abort(); +} + +/** + * Set the length of address phase. + * + * When in 4-bit mode, the SPI cycles of the phase will be shorter. E.g. 16-bit + * address phases takes 4 cycles in 4-bit mode. + * + * @param hw Beginning address of the peripheral registers. + * @param bitlen Length of address phase, in bits. 0 to disable the address phase. + */ +static inline void spi_ll_set_addr_bitlen(spi_dev_t *hw, int bitlen) +{ + // TODO: [ESP32C5] IDF-8698, IDF-8699 + // hw->user1.usr_addr_bitlen = bitlen - 1; + // hw->user.usr_addr = bitlen ? 1 : 0; + abort(); +} + +/** + * Set the address value in an intuitive way. + * + * The length and lsbfirst is required to shift and swap the address to the right place. + * + * @param hw Beginning address of the peripheral registers. + * @param address Address to set + * @param addrlen Length of the address phase + * @param lsbfirst Whether the LSB first feature is enabled. + */ +static inline void spi_ll_set_address(spi_dev_t *hw, uint64_t addr, int addrlen, uint32_t lsbfirst) +{ + // TODO: [ESP32C5] IDF-8698, IDF-8699 + // if (lsbfirst) { + // /* The output address start from the LSB of the highest byte, i.e. + // * addr[24] -> addr[31] + // * ... + // * addr[0] -> addr[7] + // * So swap the byte order to let the LSB sent first. + // */ + // addr = HAL_SWAP32(addr); + // //otherwise only addr register is sent + // hw->addr.val = addr; + // } else { + // // shift the address to MSB of addr register. + // // output address will be sent from MSB to LSB of addr register + // hw->addr.val = addr << (32 - addrlen); + // } + abort(); +} + +/** + * Set the command value in an intuitive way. + * + * The length and lsbfirst is required to shift and swap the command to the right place. + * + * @param hw Beginning command of the peripheral registers. + * @param command Command to set + * @param addrlen Length of the command phase + * @param lsbfirst Whether the LSB first feature is enabled. + */ +static inline void spi_ll_set_command(spi_dev_t *hw, uint16_t cmd, int cmdlen, bool lsbfirst) +{ + // TODO: [ESP32C5] IDF-8698, IDF-8699 + // if (lsbfirst) { + // // The output command start from bit0 to bit 15, kept as is. + // HAL_FORCE_MODIFY_U32_REG_FIELD(hw->user2, usr_command_value, cmd); + // } else { + // /* Output command will be sent from bit 7 to 0 of command_value, and + // * then bit 15 to 8 of the same register field. Shift and swap to send + // * more straightly. + // */ + // HAL_FORCE_MODIFY_U32_REG_FIELD(hw->user2, usr_command_value, HAL_SPI_SWAP_DATA_TX(cmd, cmdlen)); + // } + abort(); +} + +/** + * Set dummy clocks to output before RX phase (master), or clocks to skip + * before the data phase and after the address phase (slave). + * + * Note this phase is also used to compensate RX timing in half duplex mode. + * + * @param hw Beginning address of the peripheral registers. + * @param dummy_n Dummy cycles used. 0 to disable the dummy phase. + */ +static inline void spi_ll_set_dummy(spi_dev_t *hw, int dummy_n) +{ + // TODO: [ESP32C5] IDF-8698, IDF-8699 + // hw->user.usr_dummy = dummy_n ? 1 : 0; + // HAL_FORCE_MODIFY_U32_REG_FIELD(hw->user1, usr_dummy_cyclelen, dummy_n - 1); + abort(); +} + +/** + * Enable/disable the RX data phase. + * + * @param hw Beginning address of the peripheral registers. + * @param enable True if RX phase exist, otherwise false. + */ +static inline void spi_ll_enable_miso(spi_dev_t *hw, int enable) +{ + // TODO: [ESP32C5] IDF-8698, IDF-8699 + // hw->user.usr_miso = enable; + abort(); +} + +/** + * Enable/disable the TX data phase. + * + * @param hw Beginning address of the peripheral registers. + * @param enable True if TX phase exist, otherwise false. + */ +static inline void spi_ll_enable_mosi(spi_dev_t *hw, int enable) +{ + // TODO: [ESP32C5] IDF-8698, IDF-8699 + // hw->user.usr_mosi = enable; + abort(); +} + +/** + * Get the received bit length of the slave. + * + * @param hw Beginning address of the peripheral registers. + * + * @return Received bits of the slave. + */ +static inline uint32_t spi_ll_slave_get_rcv_bitlen(spi_dev_t *hw) +{ + // TODO: [ESP32C5] IDF-8698, IDF-8699 + // return hw->slave1.slv_data_bitlen; + abort(); + return (uint32_t)0; +} + +/*------------------------------------------------------------------------------ + * Interrupts + *----------------------------------------------------------------------------*/ +//helper macros to generate code for each interrupts +#define FOR_EACH_ITEM(op, list) do { list(op) } while(0) +#define INTR_LIST(item) \ + item(SPI_LL_INTR_TRANS_DONE, dma_int_ena.trans_done, dma_int_raw.trans_done, dma_int_clr.trans_done, dma_int_set.trans_done_int_set) \ + item(SPI_LL_INTR_RDBUF, dma_int_ena.slv_rd_buf_done, dma_int_raw.slv_rd_buf_done, dma_int_clr.slv_rd_buf_done, dma_int_set.slv_rd_buf_done_int_set) \ + item(SPI_LL_INTR_WRBUF, dma_int_ena.slv_wr_buf_done, dma_int_raw.slv_wr_buf_done, dma_int_clr.slv_wr_buf_done, dma_int_set.slv_wr_buf_done_int_set) \ + item(SPI_LL_INTR_RDDMA, dma_int_ena.slv_rd_dma_done, dma_int_raw.slv_rd_dma_done, dma_int_clr.slv_rd_dma_done, dma_int_set.slv_rd_dma_done_int_set) \ + item(SPI_LL_INTR_WRDMA, dma_int_ena.slv_wr_dma_done, dma_int_raw.slv_wr_dma_done, dma_int_clr.slv_wr_dma_done, dma_int_set.slv_wr_dma_done_int_set) \ + item(SPI_LL_INTR_SEG_DONE, dma_int_ena.dma_seg_trans_done, dma_int_raw.dma_seg_trans_done, dma_int_clr.dma_seg_trans_done, dma_int_set.dma_seg_trans_done_int_set) \ + item(SPI_LL_INTR_CMD7, dma_int_ena.slv_cmd7, dma_int_raw.slv_cmd7, dma_int_clr.slv_cmd7, dma_int_set.slv_cmd7_int_set) \ + item(SPI_LL_INTR_CMD8, dma_int_ena.slv_cmd8, dma_int_raw.slv_cmd8, dma_int_clr.slv_cmd8, dma_int_set.slv_cmd8_int_set) \ + item(SPI_LL_INTR_CMD9, dma_int_ena.slv_cmd9, dma_int_raw.slv_cmd9, dma_int_clr.slv_cmd9, dma_int_set.slv_cmd9_int_set) \ + item(SPI_LL_INTR_CMDA, dma_int_ena.slv_cmda, dma_int_raw.slv_cmda, dma_int_clr.slv_cmda, dma_int_set.slv_cmda_int_set) + + +static inline void spi_ll_enable_intr(spi_dev_t *hw, spi_ll_intr_t intr_mask) +{ + // TODO: [ESP32C5] IDF-8698, IDF-8699 + // ine ENA_INTR(intr_bit, en_reg, ...) if (intr_mask & (intr_bit)) hw->en_reg = 1; + // FOR_EACH_ITEM(ENA_INTR, INTR_LIST); + // ef ENA_INTR + abort(); +} + +static inline void spi_ll_disable_intr(spi_dev_t *hw, spi_ll_intr_t intr_mask) +{ + // TODO: [ESP32C5] IDF-8698, IDF-8699 + // ine DIS_INTR(intr_bit, en_reg, ...) if (intr_mask & (intr_bit)) hw->en_reg = 0; + // FOR_EACH_ITEM(DIS_INTR, INTR_LIST); + // ef DIS_INTR + abort(); +} + +static inline void spi_ll_set_intr(spi_dev_t *hw, spi_ll_intr_t intr_mask) +{ + // TODO: [ESP32C5] IDF-8698, IDF-8699 + // ine SET_INTR(intr_bit, _, __, ___, set_reg) if (intr_mask & (intr_bit)) hw->set_reg = 1; + // FOR_EACH_ITEM(SET_INTR, INTR_LIST); + // ef SET_INTR + abort(); +} + +static inline void spi_ll_clear_intr(spi_dev_t *hw, spi_ll_intr_t intr_mask) +{ + // TODO: [ESP32C5] IDF-8698, IDF-8699 + // ine CLR_INTR(intr_bit, _, __, clr_reg, ...) if (intr_mask & (intr_bit)) hw->clr_reg = 1; + // FOR_EACH_ITEM(CLR_INTR, INTR_LIST); + // ef CLR_INTR + abort(); +} + +static inline bool spi_ll_get_intr(spi_dev_t *hw, spi_ll_intr_t intr_mask) +{ + // TODO: [ESP32C5] IDF-8698, IDF-8699 + // ine GET_INTR(intr_bit, _, st_reg, ...) if (intr_mask & (intr_bit) && hw->st_reg) return true; + // FOR_EACH_ITEM(GET_INTR, INTR_LIST); + // return false; + // ef GET_INTR + abort(); + return (bool)0; +} + +#undef FOR_EACH_ITEM +#undef INTR_LIST + +/** + * Disable the trans_done interrupt. + * + * @param hw Beginning address of the peripheral registers. + */ +static inline void spi_ll_disable_int(spi_dev_t *hw) +{ + // TODO: [ESP32C5] IDF-8698, IDF-8699 + // hw->dma_int_ena.trans_done = 0; + abort(); +} + +/** + * Clear the trans_done interrupt. + * + * @param hw Beginning address of the peripheral registers. + */ +static inline void spi_ll_clear_int_stat(spi_dev_t *hw) +{ + // TODO: [ESP32C5] IDF-8698, IDF-8699 + // hw->dma_int_clr.trans_done = 1; + abort(); +} + +/** + * Set the trans_done interrupt. + * + * @param hw Beginning address of the peripheral registers. + */ +static inline void spi_ll_set_int_stat(spi_dev_t *hw) +{ + // TODO: [ESP32C5] IDF-8698, IDF-8699 + // hw->dma_int_set.trans_done_int_set = 1; + abort(); +} + +/** + * Enable the trans_done interrupt. + * + * @param hw Beginning address of the peripheral registers. + */ +static inline void spi_ll_enable_int(spi_dev_t *hw) +{ + // TODO: [ESP32C5] IDF-8698, IDF-8699 + // hw->dma_int_ena.trans_done = 1; + abort(); +} + +/*------------------------------------------------------------------------------ + * Slave HD + *----------------------------------------------------------------------------*/ +static inline void spi_ll_slave_hd_set_len_cond(spi_dev_t *hw, spi_ll_trans_len_cond_t cond_mask) +{ + // TODO: [ESP32C5] IDF-8698, IDF-8699 + // hw->slave.slv_rdbuf_bitlen_en = (cond_mask & SPI_LL_TRANS_LEN_COND_RDBUF) ? 1 : 0; + // hw->slave.slv_wrbuf_bitlen_en = (cond_mask & SPI_LL_TRANS_LEN_COND_WRBUF) ? 1 : 0; + // hw->slave.slv_rddma_bitlen_en = (cond_mask & SPI_LL_TRANS_LEN_COND_RDDMA) ? 1 : 0; + // hw->slave.slv_wrdma_bitlen_en = (cond_mask & SPI_LL_TRANS_LEN_COND_WRDMA) ? 1 : 0; + abort(); +} + +static inline int spi_ll_slave_get_rx_byte_len(spi_dev_t *hw) +{ + // TODO: [ESP32C5] IDF-8698, IDF-8699 + // return hw->slave1.slv_data_bitlen / 8; + abort(); + return (int)0; +} + +static inline uint32_t spi_ll_slave_hd_get_last_addr(spi_dev_t *hw) +{ + // TODO: [ESP32C5] IDF-8698, IDF-8699 + // return hw->slave1.slv_last_addr; + abort(); + return (uint32_t)0; +} + +#undef SPI_LL_RST_MASK +#undef SPI_LL_UNUSED_INT_MASK + +/** + * Get the base spi command + * + * @param cmd_t Command value + */ +static inline uint8_t spi_ll_get_slave_hd_base_command(spi_command_t cmd_t) +{ + // TODO: [ESP32C5] IDF-8698, IDF-8699 + // uint8_t cmd_base = 0x00; + // switch (cmd_t) + // { + // case SPI_CMD_HD_WRBUF: + // cmd_base = SPI_LL_BASE_CMD_HD_WRBUF; + // break; + // case SPI_CMD_HD_RDBUF: + // cmd_base = SPI_LL_BASE_CMD_HD_RDBUF; + // break; + // case SPI_CMD_HD_WRDMA: + // cmd_base = SPI_LL_BASE_CMD_HD_WRDMA; + // break; + // case SPI_CMD_HD_RDDMA: + // cmd_base = SPI_LL_BASE_CMD_HD_RDDMA; + // break; + // case SPI_CMD_HD_SEG_END: + // cmd_base = SPI_LL_BASE_CMD_HD_SEG_END; + // break; + // case SPI_CMD_HD_EN_QPI: + // cmd_base = SPI_LL_BASE_CMD_HD_EN_QPI; + // break; + // case SPI_CMD_HD_WR_END: + // cmd_base = SPI_LL_BASE_CMD_HD_WR_END; + // break; + // case SPI_CMD_HD_INT0: + // cmd_base = SPI_LL_BASE_CMD_HD_INT0; + // break; + // case SPI_CMD_HD_INT1: + // cmd_base = SPI_LL_BASE_CMD_HD_INT1; + // break; + // case SPI_CMD_HD_INT2: + // cmd_base = SPI_LL_BASE_CMD_HD_INT2; + // break; + // default: + // HAL_ASSERT(cmd_base); + // } + // return cmd_base; + abort(); + return (uint8_t)0; +} + +/** + * Get the spi communication command + * + * @param cmd_t Base command value + * @param line_mode Line mode of SPI transaction phases: CMD, ADDR, DOUT/DIN. + */ +static inline uint16_t spi_ll_get_slave_hd_command(spi_command_t cmd_t, spi_line_mode_t line_mode) +{ + // TODO: [ESP32C5] IDF-8698, IDF-8699 + // uint8_t cmd_base = spi_ll_get_slave_hd_base_command(cmd_t); + // uint8_t cmd_mod = 0x00; //CMD:1-bit, ADDR:1-bit, DATA:1-bit + // // if (line_mode.data_lines == 2) { + // if (line_mode.addr_lines == 2) { + // cmd_mod = 0x50; //CMD:1-bit, ADDR:2-bit, DATA:2-bit + // } else { + // cmd_mod = 0x10; //CMD:1-bit, ADDR:1-bit, DATA:2-bit + // } + // } else if (line_mode.data_lines == 4) { + // if (line_mode.addr_lines == 4) { + // cmd_mod = 0xA0; //CMD:1-bit, ADDR:4-bit, DATA:4-bit + // } else { + // cmd_mod = 0x20; //CMD:1-bit, ADDR:1-bit, DATA:4-bit + // } + // } + // if (cmd_base == SPI_LL_BASE_CMD_HD_SEG_END || cmd_base == SPI_LL_BASE_CMD_HD_EN_QPI) { + // cmd_mod = 0x00; + // } + // // return cmd_base | cmd_mod; + abort(); + return (uint16_t)0; +} + +/** + * Get the dummy bits + * + * @param line_mode Line mode of SPI transaction phases: CMD, ADDR, DOUT/DIN. + */ +static inline int spi_ll_get_slave_hd_dummy_bits(spi_line_mode_t line_mode) +{ + // TODO: [ESP32C5] IDF-8698, IDF-8699 + // return 8; + abort(); + return (int)0; +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32c5/include/hal/spimem_flash_ll.h b/components/hal/esp32c5/include/hal/spimem_flash_ll.h new file mode 100644 index 0000000000..f1195261a7 --- /dev/null +++ b/components/hal/esp32c5/include/hal/spimem_flash_ll.h @@ -0,0 +1,656 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/******************************************************************************* + * NOTICE + * The ll is not public api, don't use in application code. + * See readme.md in soc/include/hal/readme.md + ******************************************************************************/ + +// The Lowlevel layer for SPI Flash + +#pragma once + +#include +#include // For MIN/MAX +#include +#include + +#include "soc/spi_periph.h" +#include "soc/spi_mem_struct.h" +#include "soc/spi_mem_reg.h" +#include "hal/assert.h" +#include "hal/misc.h" +#include "hal/spi_types.h" +#include "hal/spi_flash_types.h" +#include "soc/pcr_struct.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define spimem_flash_ll_get_hw(host_id) (((host_id)==SPI1_HOST ? &SPIMEM1 : NULL )) +#define spimem_flash_ll_hw_get_id(dev) ((dev) == (void*)&SPIMEM1? SPI1_HOST: -1) + +#define SPIMEM_FLASH_LL_SPI0_MAX_LOCK_VAL_MSPI_TICKS (0x1f) + +typedef typeof(SPIMEM1.clock.val) spimem_flash_ll_clock_reg_t; + +/*------------------------------------------------------------------------------ + * Control + *----------------------------------------------------------------------------*/ +/** + * Reset peripheral registers before configuration and starting control + * + * @param dev Beginning address of the peripheral registers. + */ +static inline void spimem_flash_ll_reset(spi_mem_dev_t *dev) +{ + dev->user.val = 0; + dev->ctrl.val = 0; +} + +/** + * Check whether the previous operation is done. + * + * @param dev Beginning address of the peripheral registers. + * + * @return true if last command is done, otherwise false. + */ +static inline bool spimem_flash_ll_cmd_is_done(const spi_mem_dev_t *dev) +{ + return (dev->cmd.val == 0); +} + +/** + * Erase the flash chip. + * + * @param dev Beginning address of the peripheral registers. + */ +static inline void spimem_flash_ll_erase_chip(spi_mem_dev_t *dev) +{ + dev->cmd.flash_ce = 1; +} + +/** + * Erase the sector, the address should be set by spimem_flash_ll_set_address. + * + * @param dev Beginning address of the peripheral registers. + */ +static inline void spimem_flash_ll_erase_sector(spi_mem_dev_t *dev) +{ + dev->ctrl.val = 0; + dev->cmd.flash_se = 1; +} + +/** + * Erase the block, the address should be set by spimem_flash_ll_set_address. + * + * @param dev Beginning address of the peripheral registers. + */ +static inline void spimem_flash_ll_erase_block(spi_mem_dev_t *dev) +{ + dev->cmd.flash_be = 1; +} + +/** + * Suspend erase/program operation. + * + * @param dev Beginning address of the peripheral registers. + */ +static inline void spimem_flash_ll_suspend(spi_mem_dev_t *dev) +{ + dev->flash_sus_ctrl.flash_pes = 1; +} + +/** + * Resume suspended erase/program operation. + * + * @param dev Beginning address of the peripheral registers. + */ +static inline void spimem_flash_ll_resume(spi_mem_dev_t *dev) +{ + dev->flash_sus_ctrl.flash_per = 1; +} + +/** + * Initialize auto suspend mode, and esp32c3 doesn't support disable auto-suspend. + * + * @param dev Beginning address of the peripheral registers. + * @param auto_sus Enable/disable Flash Auto-Suspend. + */ +static inline void spimem_flash_ll_auto_suspend_init(spi_mem_dev_t *dev, bool auto_sus) +{ + dev->flash_sus_ctrl.flash_pes_en = auto_sus; +} + +/** + * Initialize auto resume mode + * + * @param dev Beginning address of the peripheral registers. + * @param auto_res Enable/Disable Flash Auto-Resume. + * + */ +static inline void spimem_flash_ll_auto_resume_init(spi_mem_dev_t *dev, bool auto_res) +{ + dev->flash_sus_ctrl.pes_per_en = auto_res; +} + +/** + * Setup the flash suspend command, may vary from chips to chips. + * + * @param dev Beginning address of the peripheral registers. + * @param sus_cmd Flash suspend command. + * + */ +static inline void spimem_flash_ll_suspend_cmd_setup(spi_mem_dev_t *dev, uint32_t sus_cmd) +{ + HAL_FORCE_MODIFY_U32_REG_FIELD(dev->flash_sus_cmd, flash_pes_command, sus_cmd); +} + +/** + * Setup the flash resume command, may vary from chips to chips. + * + * @param dev Beginning address of the peripheral registers. + * @param res_cmd Flash resume command. + * + */ +static inline void spimem_flash_ll_resume_cmd_setup(spi_mem_dev_t *dev, uint32_t res_cmd) +{ + HAL_FORCE_MODIFY_U32_REG_FIELD(dev->sus_status, flash_per_command, res_cmd); +} + +/** + * Setup the flash read suspend status command, may vary from chips to chips. + * + * @param dev Beginning address of the peripheral registers. + * @param pesr_cmd Flash read suspend status command. + * + */ +static inline void spimem_flash_ll_rd_sus_cmd_setup(spi_mem_dev_t *dev, uint32_t pesr_cmd) +{ + HAL_FORCE_MODIFY_U32_REG_FIELD(dev->flash_sus_cmd, wait_pesr_command, pesr_cmd); +} + +/** + * Setup to check SUS/SUS1/SUS2 to ensure the suspend status of flashs. + * + * @param dev Beginning address of the peripheral registers. + * @param sus_check_sus_en 1: enable, 0: disable. + * + */ +static inline void spimem_flash_ll_sus_check_sus_setup(spi_mem_dev_t *dev, bool sus_check_sus_en) +{ + dev->flash_sus_ctrl.sus_timeout_cnt = 5; + dev->flash_sus_ctrl.pes_end_en = sus_check_sus_en; +} + +/** + * Setup to check SUS/SUS1/SUS2 to ensure the resume status of flashs. + * + * @param dev Beginning address of the peripheral registers. + * @param sus_check_sus_en 1: enable, 0: disable. + * + */ +static inline void spimem_flash_ll_res_check_sus_setup(spi_mem_dev_t *dev, bool res_check_sus_en) +{ + dev->flash_sus_ctrl.sus_timeout_cnt = 5; + dev->flash_sus_ctrl.per_end_en = res_check_sus_en; +} + +/** + * Set 8 bit command to read suspend status + * + * @param dev Beginning address of the peripheral registers. + */ +static inline void spimem_flash_ll_set_read_sus_status(spi_mem_dev_t *dev, uint32_t sus_conf) +{ + dev->flash_sus_ctrl.frd_sus_2b = 0; + HAL_FORCE_MODIFY_U32_REG_FIELD(dev->flash_sus_ctrl, pesr_end_msk, sus_conf); +} + +/** + * Configure the delay after Suspend/Resume + * + * @param dev Beginning address of the peripheral registers. + * @param dly_val delay time + */ +static inline void spimem_flash_ll_set_sus_delay(spi_mem_dev_t *dev, uint32_t dly_val) +{ + dev->ctrl1.cs_hold_dly_res = dly_val; + dev->sus_status.flash_per_dly_128 = 1; + dev->sus_status.flash_pes_dly_128 = 1; +} + +/** + * Configure the cs hold delay time(used to set the minimum CS high time tSHSL) + * + * @param dev Beginning address of the peripheral registers. + * @param cs_hold_delay cs hold delay time + */ +static inline void spimem_flash_set_cs_hold_delay(spi_mem_dev_t *dev, uint32_t cs_hold_delay) +{ + SPIMEM0.ctrl2.cs_hold_delay = cs_hold_delay; +} + +/** + * Initialize auto wait idle mode + * + * @param dev Beginning address of the peripheral registers. + * @param auto_waiti Enable/disable auto wait-idle function + */ +static inline void spimem_flash_ll_auto_wait_idle_init(spi_mem_dev_t *dev, bool auto_waiti) +{ + HAL_FORCE_MODIFY_U32_REG_FIELD(dev->flash_waiti_ctrl, waiti_cmd, 0x05); + dev->flash_sus_ctrl.flash_per_wait_en = auto_waiti; + dev->flash_sus_ctrl.flash_pes_wait_en = auto_waiti; +} + +/** + * This function is used to set dummy phase when auto suspend is enabled. + * + * @note This function is only used when timing tuning is enabled. + * + * @param dev Beginning address of the peripheral registers. + * @param extra_dummy extra dummy length. Get from timing tuning. + */ +static inline void spimem_flash_ll_set_wait_idle_dummy_phase(spi_mem_dev_t *dev, uint32_t extra_dummy) +{ + // Not supported on this chip. +} + +/** + * Return the suspend status of erase or program operations. + * + * @param dev Beginning address of the peripheral registers. + * + * @return true if suspended, otherwise false. + */ +static inline bool spimem_flash_ll_sus_status(spi_mem_dev_t *dev) +{ + return dev->sus_status.flash_sus; +} + +/** + * @brief Set lock for SPI0 so that spi0 can request new cache request after a cache transfer. + * + * @param dev Beginning address of the peripheral registers. + * @param lock_time Lock delay time + */ +static inline void spimem_flash_ll_sus_set_spi0_lock_trans(spi_mem_dev_t *dev, uint32_t lock_time) +{ + dev->sus_status.spi0_lock_en = 1; + SPIMEM0.fsm.lock_delay_time = lock_time; +} + +/** + * @brief Get tsus unit values in SPI_CLK cycles + * + * @param dev Beginning address of the peripheral registers. + * @return uint32_t tsus unit values + */ +static inline uint32_t spimem_flash_ll_get_tsus_unit_in_cycles(spi_mem_dev_t *dev) +{ + uint32_t tsus_unit = 0; + if (dev->sus_status.flash_pes_dly_128 == 1) { + tsus_unit = 128; + } else { + tsus_unit = 4; + } + return tsus_unit; +} + +/** + * Enable/disable write protection for the flash chip. + * + * @param dev Beginning address of the peripheral registers. + * @param wp true to enable the protection, false to disable (write enable). + */ +static inline void spimem_flash_ll_set_write_protect(spi_mem_dev_t *dev, bool wp) +{ + if (wp) { + dev->cmd.flash_wrdi = 1; + } else { + dev->cmd.flash_wren = 1; + } +} + +/** + * Get the read data from the buffer after ``spimem_flash_ll_read`` is done. + * + * @param dev Beginning address of the peripheral registers. + * @param buffer Buffer to hold the output data + * @param read_len Length to get out of the buffer + */ +static inline void spimem_flash_ll_get_buffer_data(spi_mem_dev_t *dev, void *buffer, uint32_t read_len) +{ + if (((intptr_t)buffer % 4 == 0) && (read_len % 4 == 0)) { + // If everything is word-aligned, do a faster memcpy + memcpy(buffer, (void *)dev->data_buf, read_len); + } else { + // Otherwise, slow(er) path copies word by word + int copy_len = read_len; + for (int i = 0; i < (read_len + 3) / 4; i++) { + int word_len = MIN(sizeof(uint32_t), copy_len); + uint32_t word = dev->data_buf[i]; + memcpy(buffer, &word, word_len); + buffer = (void *)((intptr_t)buffer + word_len); + copy_len -= word_len; + } + } +} + +/** + * Set the data to be written in the data buffer. + * + * @param dev Beginning address of the peripheral registers. + * @param buffer Buffer holding the data + * @param length Length of data in bytes. + */ +static inline void spimem_flash_ll_set_buffer_data(spi_mem_dev_t *dev, const void *buffer, uint32_t length) +{ + // Load data registers, word at a time + int num_words = (length + 3) / 4; + for (int i = 0; i < num_words; i++) { + uint32_t word = 0; + uint32_t word_len = MIN(length, sizeof(word)); + memcpy(&word, buffer, word_len); + dev->data_buf[i] = word; + length -= word_len; + buffer = (void *)((intptr_t)buffer + word_len); + } +} + + +/** + * Program a page of the flash chip. Call ``spimem_flash_ll_set_address`` before + * this to set the address to program. + * + * @param dev Beginning address of the peripheral registers. + * @param buffer Buffer holding the data to program + * @param length Length to program. + */ +static inline void spimem_flash_ll_program_page(spi_mem_dev_t *dev, const void *buffer, uint32_t length) +{ + dev->user.usr_dummy = 0; + spimem_flash_ll_set_buffer_data(dev, buffer, length); + dev->cmd.flash_pp = 1; +} + +/** + * Trigger a user defined transaction. All phases, including command, address, dummy, and the data phases, + * should be configured before this is called. + * + * @param dev Beginning address of the peripheral registers. + * @param pe_ops Is page program/erase operation or not. + */ +static inline void spimem_flash_ll_user_start(spi_mem_dev_t *dev, bool pe_ops) +{ + uint32_t usr_pe = (pe_ops ? 0x60000 : 0x40000); + dev->cmd.val |= usr_pe; +} + +/** + * Check whether the host is idle to perform new commands. + * + * @param dev Beginning address of the peripheral registers. + * + * @return true if the host is idle, otherwise false + */ +static inline bool spimem_flash_ll_host_idle(const spi_mem_dev_t *dev) +{ + return dev->cmd.mst_st == 0; +} + +/** + * Set phases for user-defined transaction to read + * + * @param dev Beginning address of the peripheral registers. + */ +static inline void spimem_flash_ll_read_phase(spi_mem_dev_t *dev) +{ + typeof (dev->user) user = { + .usr_mosi = 0, + .usr_miso = 1, + .usr_addr = 1, + .usr_command = 1, + }; + dev->user.val = user.val; +} +/*------------------------------------------------------------------------------ + * Configs + *----------------------------------------------------------------------------*/ +/** + * Select which pin to use for the flash + * + * @param dev Beginning address of the peripheral registers. + * @param pin Pin ID to use, 0-2. Set to other values to disable all the CS pins. + */ +static inline void spimem_flash_ll_set_cs_pin(spi_mem_dev_t *dev, int pin) +{ + dev->misc.cs0_dis = (pin == 0) ? 0 : 1; + dev->misc.cs1_dis = (pin == 1) ? 0 : 1; +} + +/** + * Set the read io mode. + * + * @param dev Beginning address of the peripheral registers. + * @param read_mode I/O mode to use in the following transactions. + */ +static inline void spimem_flash_ll_set_read_mode(spi_mem_dev_t *dev, esp_flash_io_mode_t read_mode) +{ + typeof (dev->ctrl) ctrl; + ctrl.val = dev->ctrl.val; + + ctrl.val &= ~(SPI_MEM_FREAD_QIO_M | SPI_MEM_FREAD_QUAD_M | SPI_MEM_FREAD_DIO_M | SPI_MEM_FREAD_DUAL_M); + ctrl.val |= SPI_MEM_FASTRD_MODE_M; + switch (read_mode) { + case SPI_FLASH_FASTRD: + //the default option + break; + case SPI_FLASH_QIO: + ctrl.fread_qio = 1; + break; + case SPI_FLASH_QOUT: + ctrl.fread_quad = 1; + break; + case SPI_FLASH_DIO: + ctrl.fread_dio = 1; + break; + case SPI_FLASH_DOUT: + ctrl.fread_dual = 1; + break; + case SPI_FLASH_SLOWRD: + ctrl.fastrd_mode = 0; + break; + default: + abort(); + } + dev->ctrl.val = ctrl.val; +} + +/** + * Set clock frequency to work at. + * + * @param dev Beginning address of the peripheral registers. + * @param clock_val pointer to the clock value to set + */ +static inline void spimem_flash_ll_set_clock(spi_mem_dev_t *dev, spimem_flash_ll_clock_reg_t *clock_val) +{ + dev->clock.val = *clock_val; +} + +/** + * Set the input length, in bits. + * + * @param dev Beginning address of the peripheral registers. + * @param bitlen Length of input, in bits. + */ +static inline void spimem_flash_ll_set_miso_bitlen(spi_mem_dev_t *dev, uint32_t bitlen) +{ + dev->user.usr_miso = bitlen > 0; + dev->miso_dlen.usr_miso_bit_len = bitlen ? (bitlen - 1) : 0; +} + +/** + * Set the output length, in bits (not including command, address and dummy + * phases) + * + * @param dev Beginning address of the peripheral registers. + * @param bitlen Length of output, in bits. + */ +static inline void spimem_flash_ll_set_mosi_bitlen(spi_mem_dev_t *dev, uint32_t bitlen) +{ + dev->user.usr_mosi = bitlen > 0; + dev->mosi_dlen.usr_mosi_bit_len = bitlen ? (bitlen - 1) : 0; +} + +/** + * Set the command. + * + * @param dev Beginning address of the peripheral registers. + * @param command Command to send + * @param bitlen Length of the command + */ +static inline void spimem_flash_ll_set_command(spi_mem_dev_t *dev, uint32_t command, uint32_t bitlen) +{ + dev->user.usr_command = 1; + typeof(dev->user2) user2 = { + .usr_command_value = command, + .usr_command_bitlen = (bitlen - 1), + }; + dev->user2.val = user2.val; +} + +/** + * Get the address length that is set in register, in bits. + * + * @param dev Beginning address of the peripheral registers. + * + */ +static inline int spimem_flash_ll_get_addr_bitlen(spi_mem_dev_t *dev) +{ + return dev->user.usr_addr ? dev->user1.usr_addr_bitlen + 1 : 0; +} + +/** + * Set the address length to send, in bits. Should be called before commands that requires the address e.g. erase sector, read, write... + * + * @param dev Beginning address of the peripheral registers. + * @param bitlen Length of the address, in bits + */ +static inline void spimem_flash_ll_set_addr_bitlen(spi_mem_dev_t *dev, uint32_t bitlen) +{ + dev->user1.usr_addr_bitlen = (bitlen - 1); + dev->user.usr_addr = bitlen ? 1 : 0; +} + +/** + * Set extra address for bits M0-M7 in DIO/QIO mode. + * + * @param dev Beginning address of the peripheral registers. + * @param extra_addr extra address(M0-M7) to send. + */ +static inline void spimem_flash_ll_set_extra_address(spi_mem_dev_t *dev, uint32_t extra_addr) +{ + dev->cache_fctrl.usr_addr_4byte = 0; + dev->rd_status.wb_mode = extra_addr; +} + +/** + * Set the address to send. Should be called before commands that requires the address e.g. erase sector, read, write... + * + * @param dev Beginning address of the peripheral registers. + * @param addr Address to send + */ +static inline void spimem_flash_ll_set_address(spi_mem_dev_t *dev, uint32_t addr) +{ + dev->addr = addr; +} + +/** + * Set the address to send in user mode. Should be called before commands that requires the address e.g. erase sector, read, write... + * + * @param dev Beginning address of the peripheral registers. + * @param addr Address to send + */ +static inline void spimem_flash_ll_set_usr_address(spi_mem_dev_t *dev, uint32_t addr, uint32_t bitlen) +{ + (void)bitlen; + spimem_flash_ll_set_address(dev, addr); +} + +/** + * Set the length of dummy cycles. + * + * @param dev Beginning address of the peripheral registers. + * @param dummy_n Cycles of dummy phases + */ +static inline void spimem_flash_ll_set_dummy(spi_mem_dev_t *dev, uint32_t dummy_n) +{ + dev->user.usr_dummy = dummy_n ? 1 : 0; + dev->user1.usr_dummy_cyclelen = dummy_n - 1; +} + +/** + * Set CS hold time. + * + * @param dev Beginning address of the peripheral registers. + * @param hold_n CS hold time config used by the host. + */ +static inline void spimem_flash_ll_set_hold(spi_mem_dev_t *dev, uint32_t hold_n) +{ + dev->ctrl2.cs_hold_time = hold_n - 1; + dev->user.cs_hold = (hold_n > 0? 1: 0); +} + +static inline void spimem_flash_ll_set_cs_setup(spi_mem_dev_t *dev, uint32_t cs_setup_time) +{ + dev->user.cs_setup = (cs_setup_time > 0 ? 1 : 0); + dev->ctrl2.cs_setup_time = cs_setup_time - 1; +} + +/** + * Get the spi flash source clock frequency. Used for calculating + * the divider parameters. + * + * @param None + * + * @return the frequency of spi flash clock source.(MHz) + */ +static inline uint8_t spimem_flash_ll_get_source_freq_mhz(void) +{ + // TODO: [ESP32C5] IDF-8649 + // MAY CAN IMPROVE (ONLY rc_fast case is incorrect)! + // TODO: Default is PLL480M, this is hard-coded. + // In the future, we can get the CPU clock source by calling interface. + // HAL_ASSERT(HAL_FORCE_READ_U32_REG_FIELD(PCR.mspi_clk_conf, mspi_func_clk_sel) == 2); + return 40; // Use Xtal clock source +} + +/** + * Calculate spi_flash clock frequency division parameters for register. + * + * @param clkdiv frequency division factor + * + * @return Register setting for the given clock division factor. + */ +static inline uint32_t spimem_flash_ll_calculate_clock_reg(uint8_t clkdiv) +{ + uint32_t div_parameter; + // See comments of `clock` in `spi_mem_struct.h` + if (clkdiv == 1) { + div_parameter = (1 << 31); + } else { + div_parameter = ((clkdiv - 1) | (((clkdiv - 1) / 2 & 0xff) << 8 ) | (((clkdiv - 1) & 0xff) << 16)); + } + return div_parameter; +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32c5/include/hal/systimer_ll.h b/components/hal/esp32c5/include/hal/systimer_ll.h new file mode 100644 index 0000000000..ec53aebd6a --- /dev/null +++ b/components/hal/esp32c5/include/hal/systimer_ll.h @@ -0,0 +1,205 @@ +/* + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include +#include "soc/systimer_struct.h" +#include "soc/clk_tree_defs.h" +#include "soc/pcr_struct.h" +#include "hal/assert.h" + +#ifdef __cplusplus +extern "C" { +#endif + +// TODO: [ESP32C5] IDF-8707 + +// All these functions get invoked either from ISR or HAL that linked to IRAM. +// Always inline these functions even no gcc optimization is applied. + +/******************* Clock *************************/ + +__attribute__((always_inline)) static inline void systimer_ll_enable_clock(systimer_dev_t *dev, bool en) +{ + dev->conf.clk_en = en; +} + +// Set clock source: XTAL(default) or RC_FAST +static inline void systimer_ll_set_clock_source(soc_periph_systimer_clk_src_t clk_src) +{ + PCR.systimer_func_clk_conf.systimer_func_clk_sel = (clk_src == SYSTIMER_CLK_SRC_RC_FAST) ? 1 : 0; +} + +static inline soc_periph_systimer_clk_src_t systimer_ll_get_clock_source(void) +{ + return (PCR.systimer_func_clk_conf.systimer_func_clk_sel == 1) ? SYSTIMER_CLK_SRC_RC_FAST : SYSTIMER_CLK_SRC_XTAL; +} + +/** + * @brief Enable the bus clock for systimer module + * + * @param enable true to enable, false to disable + */ +static inline void systimer_ll_enable_bus_clock(bool enable) +{ + PCR.systimer_conf.systimer_clk_en = enable; +} + +/// use a macro to wrap the function, force the caller to use it in a critical section +/// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance +#define systimer_ll_enable_bus_clock(...) (void)__DECLARE_RCC_RC_ATOMIC_ENV; systimer_ll_enable_bus_clock(__VA_ARGS__) + +/** + * @brief Reset the systimer module + * + * @param group_id Group ID + */ +static inline void systimer_ll_reset_register(void) +{ + PCR.systimer_conf.systimer_rst_en = 1; + PCR.systimer_conf.systimer_rst_en = 0; +} + +/// use a macro to wrap the function, force the caller to use it in a critical section +/// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance +#define systimer_ll_reset_register(...) (void)__DECLARE_RCC_RC_ATOMIC_ENV; systimer_ll_reset_register(__VA_ARGS__) + +/********************** ETM *****************************/ + +__attribute__((always_inline)) static inline void systimer_ll_enable_etm(systimer_dev_t *dev, bool en) +{ + dev->conf.etm_en = en; +} + +/******************* Counter *************************/ + +__attribute__((always_inline)) static inline void systimer_ll_enable_counter(systimer_dev_t *dev, uint32_t counter_id, bool en) +{ + if (en) { + dev->conf.val |= 1 << (30 - counter_id); + } else { + dev->conf.val &= ~(1 << (30 - counter_id)); + } +} + +__attribute__((always_inline)) static inline void systimer_ll_counter_can_stall_by_cpu(systimer_dev_t *dev, uint32_t counter_id, uint32_t cpu_id, bool can) +{ + if (can) { + dev->conf.val |= 1 << ((28 - counter_id * 2) - cpu_id); + } else { + dev->conf.val &= ~(1 << ((28 - counter_id * 2) - cpu_id)); + } +} + +__attribute__((always_inline)) static inline void systimer_ll_counter_snapshot(systimer_dev_t *dev, uint32_t counter_id) +{ + dev->unit_op[counter_id].timer_unit_update = 1; +} + +__attribute__((always_inline)) static inline bool systimer_ll_is_counter_value_valid(systimer_dev_t *dev, uint32_t counter_id) +{ + return dev->unit_op[counter_id].timer_unit_value_valid; +} + +__attribute__((always_inline)) static inline void systimer_ll_set_counter_value(systimer_dev_t *dev, uint32_t counter_id, uint64_t value) +{ + dev->unit_load_val[counter_id].hi.timer_unit_load_hi = value >> 32; + dev->unit_load_val[counter_id].lo.timer_unit_load_lo = value & 0xFFFFFFFF; +} + +__attribute__((always_inline)) static inline uint32_t systimer_ll_get_counter_value_low(systimer_dev_t *dev, uint32_t counter_id) +{ + return dev->unit_val[counter_id].lo.timer_unit_value_lo; +} + +__attribute__((always_inline)) static inline uint32_t systimer_ll_get_counter_value_high(systimer_dev_t *dev, uint32_t counter_id) +{ + return dev->unit_val[counter_id].hi.timer_unit_value_hi; +} + +__attribute__((always_inline)) static inline void systimer_ll_apply_counter_value(systimer_dev_t *dev, uint32_t counter_id) +{ + dev->unit_load[counter_id].val = 0x01; +} + +/******************* Alarm *************************/ + +__attribute__((always_inline)) static inline void systimer_ll_set_alarm_target(systimer_dev_t *dev, uint32_t alarm_id, uint64_t value) +{ + dev->target_val[alarm_id].hi.timer_target_hi = value >> 32; + dev->target_val[alarm_id].lo.timer_target_lo = value & 0xFFFFFFFF; +} + +__attribute__((always_inline)) static inline uint64_t systimer_ll_get_alarm_target(systimer_dev_t *dev, uint32_t alarm_id) +{ + return ((uint64_t)(dev->target_val[alarm_id].hi.timer_target_hi) << 32) | dev->target_val[alarm_id].lo.timer_target_lo; +} + +__attribute__((always_inline)) static inline void systimer_ll_connect_alarm_counter(systimer_dev_t *dev, uint32_t alarm_id, uint32_t counter_id) +{ + dev->target_conf[alarm_id].target_timer_unit_sel = counter_id; +} + +__attribute__((always_inline)) static inline void systimer_ll_enable_alarm_oneshot(systimer_dev_t *dev, uint32_t alarm_id) +{ + dev->target_conf[alarm_id].target_period_mode = 0; +} + +__attribute__((always_inline)) static inline void systimer_ll_enable_alarm_period(systimer_dev_t *dev, uint32_t alarm_id) +{ + dev->target_conf[alarm_id].target_period_mode = 1; +} + +__attribute__((always_inline)) static inline void systimer_ll_set_alarm_period(systimer_dev_t *dev, uint32_t alarm_id, uint32_t period) +{ + HAL_ASSERT(period < (1 << 26)); + dev->target_conf[alarm_id].target_period = period; +} + +__attribute__((always_inline)) static inline uint32_t systimer_ll_get_alarm_period(systimer_dev_t *dev, uint32_t alarm_id) +{ + return dev->target_conf[alarm_id].target_period; +} + +__attribute__((always_inline)) static inline void systimer_ll_apply_alarm_value(systimer_dev_t *dev, uint32_t alarm_id) +{ + dev->comp_load[alarm_id].val = 0x01; +} + +__attribute__((always_inline)) static inline void systimer_ll_enable_alarm(systimer_dev_t *dev, uint32_t alarm_id, bool en) +{ + if (en) { + dev->conf.val |= 1 << (24 - alarm_id); + } else { + dev->conf.val &= ~(1 << (24 - alarm_id)); + } +} + +/******************* Interrupt *************************/ + +__attribute__((always_inline)) static inline void systimer_ll_enable_alarm_int(systimer_dev_t *dev, uint32_t alarm_id, bool en) +{ + if (en) { + dev->int_ena.val |= 1 << alarm_id; + } else { + dev->int_ena.val &= ~(1 << alarm_id); + } +} + +__attribute__((always_inline)) static inline bool systimer_ll_is_alarm_int_fired(systimer_dev_t *dev, uint32_t alarm_id) +{ + return dev->int_st.val & (1 << alarm_id); +} + +__attribute__((always_inline)) static inline void systimer_ll_clear_alarm_int(systimer_dev_t *dev, uint32_t alarm_id) +{ + dev->int_clr.val |= 1 << alarm_id; +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32c5/include/hal/timer_ll.h b/components/hal/esp32c5/include/hal/timer_ll.h new file mode 100644 index 0000000000..b25e146246 --- /dev/null +++ b/components/hal/esp32c5/include/hal/timer_ll.h @@ -0,0 +1,80 @@ +/* + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +// Note that most of the register operations in this layer are non-atomic operations. + +#pragma once + +#include +#include "hal/assert.h" +#include "hal/misc.h" +#include "hal/timer_types.h" +#include "soc/timer_group_struct.h" +#include "soc/pcr_struct.h" +// TODO: [ESP32C5] IDF-8693 +// #include "soc/soc_etm_source.h" + +#ifdef __cplusplus +extern "C" { +#endif + +// Get timer group register base address with giving group number +#define TIMER_LL_GET_HW(group_id) ((group_id == 0) ? (&TIMERG0) : (&TIMERG1)) +#define TIMER_LL_EVENT_ALARM(timer_id) (1 << (timer_id)) + +// TODO: [ESP32C5] IDF-8693 + +/** + * @brief Enable the bus clock for timer group module + * + * @param group_id Group ID + * @param enable true to enable, false to disable + */ +static inline void timer_ll_enable_bus_clock(int group_id, bool enable) +{ + // TODO: [ESP32C5] IDF-8705 + // if (group_id == 0) { + // PCR.timergroup0_conf.tg0_clk_en = enable; + // } else { + // PCR.timergroup1_conf.tg1_clk_en = enable; + // } +} + +/// use a macro to wrap the function, force the caller to use it in a critical section +/// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance +#define timer_ll_enable_bus_clock(...) (void)__DECLARE_RCC_RC_ATOMIC_ENV; timer_ll_enable_bus_clock(__VA_ARGS__) + +/** + * @brief Reset the timer group module + * + * @note After reset the register, the "flash boot protection" will be enabled again. + * FLash boot protection is not used anymore after system boot up. + * This function will disable it by default in order to prevent the system from being reset unexpectedly. + * + * @param group_id Group ID + */ +static inline void timer_ll_reset_register(int group_id) +{ + // TODO: [ESP32C5] IDF-8705 + // if (group_id == 0) { + // PCR.timergroup0_conf.tg0_rst_en = 1; + // PCR.timergroup0_conf.tg0_rst_en = 0; + // TIMERG0.wdtconfig0.wdt_flashboot_mod_en = 0; + // } else { + // PCR.timergroup1_conf.tg1_rst_en = 1; + // PCR.timergroup1_conf.tg1_rst_en = 0; + // TIMERG1.wdtconfig0.wdt_flashboot_mod_en = 0; + // } +} + +/// use a macro to wrap the function, force the caller to use it in a critical section +/// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance +#define timer_ll_reset_register(...) (void)__DECLARE_RCC_RC_ATOMIC_ENV; timer_ll_reset_register(__VA_ARGS__) + + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32c5/include/hal/uart_ll.h b/components/hal/esp32c5/include/hal/uart_ll.h index ab304bc657..6112005b97 100644 --- a/components/hal/esp32c5/include/hal/uart_ll.h +++ b/components/hal/esp32c5/include/hal/uart_ll.h @@ -85,6 +85,8 @@ typedef enum { UART_INTR_WAKEUP = (0x1 << 19), } uart_intr_t; +// TODO: [ESP32C5] IDF-8722, IDF-8633 + /** * @brief Sync the update to UART core clock domain * @@ -94,9 +96,8 @@ typedef enum { */ FORCE_INLINE_ATTR void uart_ll_update(uart_dev_t *hw) { - // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) - // hw->reg_update.reg_update = 1; - // while (hw->reg_update.reg_update); + hw->reg_update.reg_update = 1; + while (hw->reg_update.reg_update); } /****************************************** LP_UART Specific ********************************************/ @@ -108,17 +109,16 @@ FORCE_INLINE_ATTR void uart_ll_update(uart_dev_t *hw) */ FORCE_INLINE_ATTR void lp_uart_ll_get_sclk(uart_dev_t *hw, soc_module_clk_t *source_clk) { - // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) - // (void)hw; - // switch (LP_CLKRST.lpperi.lp_uart_clk_sel) { - // default: - // case 0: - // *source_clk = (soc_module_clk_t)LP_UART_SCLK_LP_FAST; - // break; - // case 1: - // *source_clk = (soc_module_clk_t)LP_UART_SCLK_XTAL_D2; - // break; - // } + (void)hw; + switch (LP_CLKRST.lpperi.lp_uart_clk_sel) { + default: + case 0: + *source_clk = (soc_module_clk_t)LP_UART_SCLK_LP_FAST; + break; + case 1: + *source_clk = (soc_module_clk_t)LP_UART_SCLK_XTAL_D2; + break; + } } /** @@ -129,19 +129,18 @@ FORCE_INLINE_ATTR void lp_uart_ll_get_sclk(uart_dev_t *hw, soc_module_clk_t *sou */ static inline void lp_uart_ll_set_source_clk(uart_dev_t *hw, soc_periph_lp_uart_clk_src_t src_clk) { - // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) - // (void)hw; - // switch (src_clk) { - // case LP_UART_SCLK_LP_FAST: - // LP_CLKRST.lpperi.lp_uart_clk_sel = 0; - // break; - // case LP_UART_SCLK_XTAL_D2: - // LP_CLKRST.lpperi.lp_uart_clk_sel = 1; - // break; - // default: - // // Invalid LP_UART clock source - // HAL_ASSERT(false); - // } + (void)hw; + switch (src_clk) { + case LP_UART_SCLK_LP_FAST: + LP_CLKRST.lpperi.lp_uart_clk_sel = 0; + break; + case LP_UART_SCLK_XTAL_D2: + LP_CLKRST.lpperi.lp_uart_clk_sel = 1; + break; + default: + // Invalid LP_UART clock source + HAL_ASSERT(false); + } } /// LP_CLKRST.lpperi is a shared register, so this function must be used in an atomic way @@ -158,18 +157,19 @@ static inline void lp_uart_ll_set_source_clk(uart_dev_t *hw, soc_periph_lp_uart_ */ FORCE_INLINE_ATTR void lp_uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint32_t sclk_freq) { - // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) - // ine DIV_UP(a, b) (((a) + (b) - 1) / (b)) - // const uint32_t max_div = BIT(12) - 1; // UART divider integer part only has 12 bits - // uint32_t sclk_div = DIV_UP(sclk_freq, (uint64_t)max_div * baud); - // // if (sclk_div == 0) abort(); - // // uint32_t clk_div = ((sclk_freq) << 4) / (baud * sclk_div); - // // The baud rate configuration register is divided into - // // an integer part and a fractional part. - // hw->clkdiv_sync.clkdiv_int = clk_div >> 4; - // hw->clkdiv_sync.clkdiv_frag = clk_div & 0xf; - // HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clk_conf, sclk_div_num, sclk_div - 1); - // uart_ll_update(hw); +#define DIV_UP(a, b) (((a) + (b) - 1) / (b)) + const uint32_t max_div = BIT(12) - 1; // UART divider integer part only has 12 bits + uint32_t sclk_div = DIV_UP(sclk_freq, (uint64_t)max_div * baud); + + if (sclk_div == 0) abort(); + + uint32_t clk_div = ((sclk_freq) << 4) / (baud * sclk_div); + // The baud rate configuration register is divided into + // an integer part and a fractional part. + hw->clkdiv_sync.clkdiv_int = clk_div >> 4; + hw->clkdiv_sync.clkdiv_frag = clk_div & 0xf; + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clk_conf, sclk_div_num, sclk_div - 1); + uart_ll_update(hw); } /** @@ -180,9 +180,8 @@ FORCE_INLINE_ATTR void lp_uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, ui */ static inline void lp_uart_ll_enable_bus_clock(int hw_id, bool enable) { - // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) - // (void)hw_id; - // LPPERI.clk_en.lp_uart_ck_en = enable; + (void)hw_id; + LPPERI.clk_en.lp_uart_ck_en = enable; } /// LPPERI.clk_en is a shared register, so this function must be used in an atomic way @@ -195,10 +194,9 @@ static inline void lp_uart_ll_enable_bus_clock(int hw_id, bool enable) */ static inline void lp_uart_ll_reset_register(int hw_id) { - // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) - // (void)hw_id; - // LPPERI.reset_en.lp_uart_reset_en = 1; - // LPPERI.reset_en.lp_uart_reset_en = 0; + (void)hw_id; + LPPERI.reset_en.lp_uart_reset_en = 1; + LPPERI.reset_en.lp_uart_reset_en = 0; } /// LPPERI.reset_en is a shared register, so this function must be used in an atomic way @@ -215,17 +213,15 @@ static inline void lp_uart_ll_reset_register(int hw_id) */ FORCE_INLINE_ATTR bool uart_ll_is_enabled(uint32_t uart_num) { - // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) - // HAL_ASSERT(uart_num < SOC_UART_HP_NUM); - // uint32_t uart_clk_config_reg = ((uart_num == 0) ? PCR_UART0_CONF_REG : - // (uart_num == 1) ? PCR_UART1_CONF_REG : 0); - // uint32_t uart_rst_bit = ((uart_num == 0) ? PCR_UART0_RST_EN : - // (uart_num == 1) ? PCR_UART1_RST_EN : 0); - // uint32_t uart_en_bit = ((uart_num == 0) ? PCR_UART0_CLK_EN : - // (uart_num == 1) ? PCR_UART1_CLK_EN : 0); - // return REG_GET_BIT(uart_clk_config_reg, uart_rst_bit) == 0 && - // REG_GET_BIT(uart_clk_config_reg, uart_en_bit) != 0; - return (bool)0; + HAL_ASSERT(uart_num < SOC_UART_HP_NUM); + uint32_t uart_clk_config_reg = ((uart_num == 0) ? PCR_UART0_CONF_REG : + (uart_num == 1) ? PCR_UART1_CONF_REG : 0); + uint32_t uart_rst_bit = ((uart_num == 0) ? PCR_UART0_RST_EN : + (uart_num == 1) ? PCR_UART1_RST_EN : 0); + uint32_t uart_en_bit = ((uart_num == 0) ? PCR_UART0_CLK_EN : + (uart_num == 1) ? PCR_UART1_CLK_EN : 0); + return REG_GET_BIT(uart_clk_config_reg, uart_rst_bit) == 0 && + REG_GET_BIT(uart_clk_config_reg, uart_en_bit) != 0; } /** @@ -235,19 +231,18 @@ FORCE_INLINE_ATTR bool uart_ll_is_enabled(uint32_t uart_num) */ static inline void uart_ll_enable_bus_clock(uart_port_t uart_num, bool enable) { - // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) - // switch (uart_num) { - // case 0: - // PCR.uart0_conf.uart0_clk_en = enable; - // break; - // case 1: - // PCR.uart1_conf.uart1_clk_en = enable; - // break; - // default: - // // LP_UART - // abort(); - // break; - // } + switch (uart_num) { + case 0: + PCR.uart0_conf.uart0_clk_en = enable; + break; + case 1: + PCR.uart1_conf.uart1_clk_en = enable; + break; + default: + // LP_UART + abort(); + break; + } } /** @@ -256,21 +251,39 @@ static inline void uart_ll_enable_bus_clock(uart_port_t uart_num, bool enable) */ static inline void uart_ll_reset_register(uart_port_t uart_num) { - // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) - // switch (uart_num) { - // case 0: - // PCR.uart0_conf.uart0_rst_en = 1; - // PCR.uart0_conf.uart0_rst_en = 0; - // break; - // case 1: - // PCR.uart1_conf.uart1_rst_en = 1; - // PCR.uart1_conf.uart1_rst_en = 0; - // break; - // default: - // // LP_UART - // abort(); - // break; - // } + switch (uart_num) { + case 0: + PCR.uart0_conf.uart0_rst_en = 1; + PCR.uart0_conf.uart0_rst_en = 0; + break; + case 1: + PCR.uart1_conf.uart1_rst_en = 1; + PCR.uart1_conf.uart1_rst_en = 0; + break; + default: + // LP_UART + abort(); + break; + } +} + +/** + * @brief Configure the UART core reset. + * + * @param hw Beginning address of the peripheral registers. + * @param core_rst_en True to enable the core reset, otherwise set it false. + * + * @return None. + */ +FORCE_INLINE_ATTR void uart_ll_set_reset_core(uart_dev_t *hw, bool core_rst_en) +{ + if ((hw) != &LP_UART) { + UART_LL_PCR_REG_SET(hw, conf, rst_en, core_rst_en); + } else { + // LP_UART reset shares the same register with other LP peripherals + // Needs to be protected with a lock, therefore, it has its unique LL function, and must be called from lp_periph_ctrl.c + abort(); + } } /** @@ -282,14 +295,13 @@ static inline void uart_ll_reset_register(uart_port_t uart_num) */ FORCE_INLINE_ATTR void uart_ll_sclk_enable(uart_dev_t *hw) { - // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) - // if ((hw) != &LP_UART) { - // UART_LL_PCR_REG_SET(hw, sclk_conf, sclk_en, 1); - // } else { - // // LP_UART clk_en shares the same register with other LP peripherals - // // Needs to be protected with a lock, therefore, it has its unique LL function - // abort(); - // } + if ((hw) != &LP_UART) { + UART_LL_PCR_REG_SET(hw, sclk_conf, sclk_en, 1); + } else { + // LP_UART clk_en shares the same register with other LP peripherals + // Needs to be protected with a lock, therefore, it has its unique LL function, and must be called from lp_periph_ctrl.c + abort(); + } } /** @@ -301,14 +313,13 @@ FORCE_INLINE_ATTR void uart_ll_sclk_enable(uart_dev_t *hw) */ FORCE_INLINE_ATTR void uart_ll_sclk_disable(uart_dev_t *hw) { - // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) - // if ((hw) != &LP_UART) { - // UART_LL_PCR_REG_SET(hw, sclk_conf, sclk_en, 0); - // } else { - // // LP_UART clk_en shares the same register with other LP peripherals - // // Needs to be protected with a lock, therefore, it has its unique LL function - // abort(); - // } + if ((hw) != &LP_UART) { + UART_LL_PCR_REG_SET(hw, sclk_conf, sclk_en, 0); + } else { + // LP_UART clk_en shares the same register with other LP peripherals + // Needs to be protected with a lock, therefore, it has its unique LL function, and must be called from lp_periph_ctrl.c + abort(); + } } /** @@ -322,29 +333,28 @@ FORCE_INLINE_ATTR void uart_ll_sclk_disable(uart_dev_t *hw) */ FORCE_INLINE_ATTR void uart_ll_set_sclk(uart_dev_t *hw, soc_module_clk_t source_clk) { - // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) - // if ((hw) != &LP_UART) { - // uint32_t sel_value = 0; - // switch (source_clk) { - // case UART_SCLK_PLL_F80M: - // sel_value = 1; - // break; - // case UART_SCLK_RTC: - // sel_value = 2; - // break; - // case UART_SCLK_XTAL: - // sel_value = 3; - // break; - // default: - // // Invalid HP_UART clock source - // abort(); - // } - // UART_LL_PCR_REG_SET(hw, sclk_conf, sclk_sel, sel_value); - // } else { - // // LP_UART clk_sel shares the same register with other LP peripherals - // // Needs to be protected with a lock, therefore, it has its unique LL function - // abort(); - // } + if ((hw) != &LP_UART) { + uint32_t sel_value = 0; + switch (source_clk) { + case UART_SCLK_PLL_F80M: + sel_value = 2; + break; + case UART_SCLK_RTC: + sel_value = 1; + break; + case UART_SCLK_XTAL: + sel_value = 0; + break; + default: + // Invalid HP_UART clock source + abort(); + } + UART_LL_PCR_REG_SET(hw, sclk_conf, sclk_sel, sel_value); + } else { + // LP_UART clk_sel shares the same register with other LP peripherals + // Needs to be protected with a lock, therefore, it has its unique LL function, and must be called from lp_periph_ctrl.c + abort(); + } } /** @@ -357,23 +367,22 @@ FORCE_INLINE_ATTR void uart_ll_set_sclk(uart_dev_t *hw, soc_module_clk_t source_ */ FORCE_INLINE_ATTR void uart_ll_get_sclk(uart_dev_t *hw, soc_module_clk_t *source_clk) { - // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) - // if ((hw) != &LP_UART) { - // switch (UART_LL_PCR_REG_GET(hw, sclk_conf, sclk_sel)) { - // default: - // case 1: - // *source_clk = (soc_module_clk_t)UART_SCLK_PLL_F80M; - // break; - // case 2: - // *source_clk = (soc_module_clk_t)UART_SCLK_RTC; - // break; - // case 3: - // *source_clk = (soc_module_clk_t)UART_SCLK_XTAL; - // break; - // } - // } else { - // lp_uart_ll_get_sclk(hw, source_clk); - // } + if ((hw) != &LP_UART) { + switch (UART_LL_PCR_REG_GET(hw, sclk_conf, sclk_sel)) { + default: + case 1: + *source_clk = (soc_module_clk_t)UART_SCLK_PLL_F80M; + break; + case 2: + *source_clk = (soc_module_clk_t)UART_SCLK_RTC; + break; + case 3: + *source_clk = (soc_module_clk_t)UART_SCLK_XTAL; + break; + } + } else { + lp_uart_ll_get_sclk(hw, source_clk); + } } /** @@ -387,23 +396,24 @@ FORCE_INLINE_ATTR void uart_ll_get_sclk(uart_dev_t *hw, soc_module_clk_t *source */ FORCE_INLINE_ATTR void uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint32_t sclk_freq) { - // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) - // ine DIV_UP(a, b) (((a) + (b) - 1) / (b)) - // const uint32_t max_div = BIT(12) - 1; // UART divider integer part only has 12 bits - // uint32_t sclk_div = DIV_UP(sclk_freq, (uint64_t)max_div * baud); - // // if (sclk_div == 0) abort(); - // // uint32_t clk_div = ((sclk_freq) << 4) / (baud * sclk_div); - // // The baud rate configuration register is divided into - // // an integer part and a fractional part. - // hw->clkdiv_sync.clkdiv_int = clk_div >> 4; - // hw->clkdiv_sync.clkdiv_frag = clk_div & 0xf; - // if ((hw) == &LP_UART) { - // abort(); - // } else { - // UART_LL_PCR_REG_U32_SET(hw, sclk_conf, sclk_div_num, sclk_div - 1); - // } - // ef DIV_UP - // uart_ll_update(hw); +#define DIV_UP(a, b) (((a) + (b) - 1) / (b)) + const uint32_t max_div = BIT(12) - 1; // UART divider integer part only has 12 bits + uint32_t sclk_div = DIV_UP(sclk_freq, (uint64_t)max_div * baud); + + if (sclk_div == 0) abort(); + + uint32_t clk_div = ((sclk_freq) << 4) / (baud * sclk_div); + // The baud rate configuration register is divided into + // an integer part and a fractional part. + hw->clkdiv_sync.clkdiv_int = clk_div >> 4; + hw->clkdiv_sync.clkdiv_frag = clk_div & 0xf; + if ((hw) == &LP_UART) { + abort(); + } else { + UART_LL_PCR_REG_U32_SET(hw, sclk_conf, sclk_div_num, sclk_div - 1); + } +#undef DIV_UP + uart_ll_update(hw); } /** @@ -416,17 +426,15 @@ FORCE_INLINE_ATTR void uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint3 */ FORCE_INLINE_ATTR uint32_t uart_ll_get_baudrate(uart_dev_t *hw, uint32_t sclk_freq) { - // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) - // typeof(hw->clkdiv_sync) div_reg; - // div_reg.val = hw->clkdiv_sync.val; - // int sclk_div; - // if ((hw) == &LP_UART) { - // sclk_div = HAL_FORCE_READ_U32_REG_FIELD(hw->clk_conf, sclk_div_num) + 1; - // } else { - // sclk_div = UART_LL_PCR_REG_U32_GET(hw, sclk_conf, sclk_div_num) + 1; - // } - // return ((sclk_freq << 4)) / (((div_reg.clkdiv_int << 4) | div_reg.clkdiv_frag) * sclk_div); - return (uint32_t)0; + typeof(hw->clkdiv_sync) div_reg; + div_reg.val = hw->clkdiv_sync.val; + int sclk_div; + if ((hw) == &LP_UART) { + sclk_div = HAL_FORCE_READ_U32_REG_FIELD(hw->clk_conf, sclk_div_num) + 1; + } else { + sclk_div = UART_LL_PCR_REG_U32_GET(hw, sclk_conf, sclk_div_num) + 1; + } + return ((sclk_freq << 4)) / (((div_reg.clkdiv_int << 4) | div_reg.clkdiv_frag) * sclk_div); } /** @@ -439,8 +447,7 @@ FORCE_INLINE_ATTR uint32_t uart_ll_get_baudrate(uart_dev_t *hw, uint32_t sclk_fr */ FORCE_INLINE_ATTR void uart_ll_ena_intr_mask(uart_dev_t *hw, uint32_t mask) { - // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) - // hw->int_ena.val = hw->int_ena.val | mask; + hw->int_ena.val = hw->int_ena.val | mask; } /** @@ -453,8 +460,7 @@ FORCE_INLINE_ATTR void uart_ll_ena_intr_mask(uart_dev_t *hw, uint32_t mask) */ FORCE_INLINE_ATTR void uart_ll_disable_intr_mask(uart_dev_t *hw, uint32_t mask) { - // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) - // hw->int_ena.val = hw->int_ena.val & (~mask); + hw->int_ena.val = hw->int_ena.val & (~mask); } /** @@ -466,9 +472,7 @@ FORCE_INLINE_ATTR void uart_ll_disable_intr_mask(uart_dev_t *hw, uint32_t mask) */ FORCE_INLINE_ATTR uint32_t uart_ll_get_intraw_mask(uart_dev_t *hw) { - // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) - // return hw->int_raw.val; - return (uint32_t)0; + return hw->int_raw.val; } /** @@ -480,9 +484,7 @@ FORCE_INLINE_ATTR uint32_t uart_ll_get_intraw_mask(uart_dev_t *hw) */ FORCE_INLINE_ATTR uint32_t uart_ll_get_intsts_mask(uart_dev_t *hw) { - // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) - // return hw->int_st.val; - return (uint32_t)0; + return hw->int_st.val; } /** @@ -495,8 +497,7 @@ FORCE_INLINE_ATTR uint32_t uart_ll_get_intsts_mask(uart_dev_t *hw) */ FORCE_INLINE_ATTR void uart_ll_clr_intsts_mask(uart_dev_t *hw, uint32_t mask) { - // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) - // hw->int_clr.val = mask; + hw->int_clr.val = mask; } /** @@ -508,9 +509,7 @@ FORCE_INLINE_ATTR void uart_ll_clr_intsts_mask(uart_dev_t *hw, uint32_t mask) */ FORCE_INLINE_ATTR uint32_t uart_ll_get_intr_ena_status(uart_dev_t *hw) { - // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) - // return hw->int_ena.val; - return (uint32_t)0; + return hw->int_ena.val; } /** @@ -524,10 +523,9 @@ FORCE_INLINE_ATTR uint32_t uart_ll_get_intr_ena_status(uart_dev_t *hw) */ FORCE_INLINE_ATTR void uart_ll_read_rxfifo(uart_dev_t *hw, uint8_t *buf, uint32_t rd_len) { - // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) - // for (int i = 0; i < (int)rd_len; i++) { - // buf[i] = hw->fifo.rxfifo_rd_byte; - // } + for (int i = 0; i < (int)rd_len; i++) { + buf[i] = hw->fifo.rxfifo_rd_byte; + } } /** @@ -541,10 +539,9 @@ FORCE_INLINE_ATTR void uart_ll_read_rxfifo(uart_dev_t *hw, uint8_t *buf, uint32_ */ FORCE_INLINE_ATTR void uart_ll_write_txfifo(uart_dev_t *hw, const uint8_t *buf, uint32_t wr_len) { - // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) - // for (int i = 0; i < (int)wr_len; i++) { - // hw->fifo.rxfifo_rd_byte = buf[i]; - // } + for (int i = 0; i < (int)wr_len; i++) { + hw->fifo.rxfifo_rd_byte = buf[i]; + } } /** @@ -556,11 +553,10 @@ FORCE_INLINE_ATTR void uart_ll_write_txfifo(uart_dev_t *hw, const uint8_t *buf, */ FORCE_INLINE_ATTR void uart_ll_rxfifo_rst(uart_dev_t *hw) { - // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) - // hw->conf0_sync.rxfifo_rst = 1; - // uart_ll_update(hw); - // hw->conf0_sync.rxfifo_rst = 0; - // uart_ll_update(hw); + hw->conf0_sync.rxfifo_rst = 1; + uart_ll_update(hw); + hw->conf0_sync.rxfifo_rst = 0; + uart_ll_update(hw); } /** @@ -572,11 +568,10 @@ FORCE_INLINE_ATTR void uart_ll_rxfifo_rst(uart_dev_t *hw) */ FORCE_INLINE_ATTR void uart_ll_txfifo_rst(uart_dev_t *hw) { - // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) - // hw->conf0_sync.txfifo_rst = 1; - // uart_ll_update(hw); - // hw->conf0_sync.txfifo_rst = 0; - // uart_ll_update(hw); + hw->conf0_sync.txfifo_rst = 1; + uart_ll_update(hw); + hw->conf0_sync.txfifo_rst = 0; + uart_ll_update(hw); } /** @@ -588,9 +583,7 @@ FORCE_INLINE_ATTR void uart_ll_txfifo_rst(uart_dev_t *hw) */ FORCE_INLINE_ATTR uint32_t uart_ll_get_rxfifo_len(uart_dev_t *hw) { - // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) - // return (hw->status.rxfifo_cnt) >> UART_LL_REG_FIELD_BIT_SHIFT(hw); - return (uint32_t)0; + return (hw->status.rxfifo_cnt) >> UART_LL_REG_FIELD_BIT_SHIFT(hw); } /** @@ -602,11 +595,9 @@ FORCE_INLINE_ATTR uint32_t uart_ll_get_rxfifo_len(uart_dev_t *hw) */ FORCE_INLINE_ATTR uint32_t uart_ll_get_txfifo_len(uart_dev_t *hw) { - // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) - // uint32_t total_fifo_len = ((hw) == &LP_UART) ? LP_UART_LL_FIFO_DEF_LEN : UART_LL_FIFO_DEF_LEN; - // uint32_t txfifo_len = (hw->status.txfifo_cnt) >> UART_LL_REG_FIELD_BIT_SHIFT(hw); - // return (total_fifo_len - txfifo_len); - return (uint32_t)0; + uint32_t total_fifo_len = ((hw) == &LP_UART) ? LP_UART_LL_FIFO_DEF_LEN : UART_LL_FIFO_DEF_LEN; + uint32_t txfifo_len = (hw->status.txfifo_cnt) >> UART_LL_REG_FIELD_BIT_SHIFT(hw); + return (total_fifo_len - txfifo_len); } /** @@ -619,9 +610,8 @@ FORCE_INLINE_ATTR uint32_t uart_ll_get_txfifo_len(uart_dev_t *hw) */ FORCE_INLINE_ATTR void uart_ll_set_stop_bits(uart_dev_t *hw, uart_stop_bits_t stop_bit) { - // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) - // hw->conf0_sync.stop_bit_num = stop_bit; - // uart_ll_update(hw); + hw->conf0_sync.stop_bit_num = stop_bit; + uart_ll_update(hw); } /** @@ -634,8 +624,7 @@ FORCE_INLINE_ATTR void uart_ll_set_stop_bits(uart_dev_t *hw, uart_stop_bits_t st */ FORCE_INLINE_ATTR void uart_ll_get_stop_bits(uart_dev_t *hw, uart_stop_bits_t *stop_bit) { - // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) - // *stop_bit = (uart_stop_bits_t)hw->conf0_sync.stop_bit_num; + *stop_bit = (uart_stop_bits_t)hw->conf0_sync.stop_bit_num; } /** @@ -648,12 +637,11 @@ FORCE_INLINE_ATTR void uart_ll_get_stop_bits(uart_dev_t *hw, uart_stop_bits_t *s */ FORCE_INLINE_ATTR void uart_ll_set_parity(uart_dev_t *hw, uart_parity_t parity_mode) { - // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) - // if (parity_mode != UART_PARITY_DISABLE) { - // hw->conf0_sync.parity = parity_mode & 0x1; - // } - // hw->conf0_sync.parity_en = (parity_mode >> 1) & 0x1; - // uart_ll_update(hw); + if (parity_mode != UART_PARITY_DISABLE) { + hw->conf0_sync.parity = parity_mode & 0x1; + } + hw->conf0_sync.parity_en = (parity_mode >> 1) & 0x1; + uart_ll_update(hw); } /** @@ -666,12 +654,11 @@ FORCE_INLINE_ATTR void uart_ll_set_parity(uart_dev_t *hw, uart_parity_t parity_m */ FORCE_INLINE_ATTR void uart_ll_get_parity(uart_dev_t *hw, uart_parity_t *parity_mode) { - // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) - // if (hw->conf0_sync.parity_en) { - // *parity_mode = (uart_parity_t)(0x2 | hw->conf0_sync.parity); - // } else { - // *parity_mode = UART_PARITY_DISABLE; - // } + if (hw->conf0_sync.parity_en) { + *parity_mode = (uart_parity_t)(0x2 | hw->conf0_sync.parity); + } else { + *parity_mode = UART_PARITY_DISABLE; + } } /** @@ -685,8 +672,7 @@ FORCE_INLINE_ATTR void uart_ll_get_parity(uart_dev_t *hw, uart_parity_t *parity_ */ FORCE_INLINE_ATTR void uart_ll_set_rxfifo_full_thr(uart_dev_t *hw, uint16_t full_thrhd) { - // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) - // hw->conf1.rxfifo_full_thrhd = full_thrhd << UART_LL_REG_FIELD_BIT_SHIFT(hw); + hw->conf1.rxfifo_full_thrhd = full_thrhd << UART_LL_REG_FIELD_BIT_SHIFT(hw); } /** @@ -700,8 +686,7 @@ FORCE_INLINE_ATTR void uart_ll_set_rxfifo_full_thr(uart_dev_t *hw, uint16_t full */ FORCE_INLINE_ATTR void uart_ll_set_txfifo_empty_thr(uart_dev_t *hw, uint16_t empty_thrhd) { - // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) - // hw->conf1.txfifo_empty_thrhd = empty_thrhd << UART_LL_REG_FIELD_BIT_SHIFT(hw); + hw->conf1.txfifo_empty_thrhd = empty_thrhd << UART_LL_REG_FIELD_BIT_SHIFT(hw); } /** @@ -715,9 +700,8 @@ FORCE_INLINE_ATTR void uart_ll_set_txfifo_empty_thr(uart_dev_t *hw, uint16_t emp */ FORCE_INLINE_ATTR void uart_ll_set_rx_idle_thr(uart_dev_t *hw, uint32_t rx_idle_thr) { - // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) - // hw->idle_conf_sync.rx_idle_thrhd = rx_idle_thr; - // uart_ll_update(hw); + hw->idle_conf_sync.rx_idle_thrhd = rx_idle_thr; + uart_ll_update(hw); } /** @@ -730,9 +714,8 @@ FORCE_INLINE_ATTR void uart_ll_set_rx_idle_thr(uart_dev_t *hw, uint32_t rx_idle_ */ FORCE_INLINE_ATTR void uart_ll_set_tx_idle_num(uart_dev_t *hw, uint32_t idle_num) { - // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) - // hw->idle_conf_sync.tx_idle_num = idle_num; - // uart_ll_update(hw); + hw->idle_conf_sync.tx_idle_num = idle_num; + uart_ll_update(hw); } /** @@ -745,14 +728,13 @@ FORCE_INLINE_ATTR void uart_ll_set_tx_idle_num(uart_dev_t *hw, uint32_t idle_num */ FORCE_INLINE_ATTR void uart_ll_tx_break(uart_dev_t *hw, uint32_t break_num) { - // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) - // if (break_num > 0) { - // HAL_FORCE_MODIFY_U32_REG_FIELD(hw->txbrk_conf_sync, tx_brk_num, break_num); - // hw->conf0_sync.txd_brk = 1; - // } else { - // hw->conf0_sync.txd_brk = 0; - // } - // uart_ll_update(hw); + if (break_num > 0) { + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->txbrk_conf_sync, tx_brk_num, break_num); + hw->conf0_sync.txd_brk = 1; + } else { + hw->conf0_sync.txd_brk = 0; + } + uart_ll_update(hw); } /** @@ -766,20 +748,19 @@ FORCE_INLINE_ATTR void uart_ll_tx_break(uart_dev_t *hw, uint32_t break_num) */ FORCE_INLINE_ATTR void uart_ll_set_hw_flow_ctrl(uart_dev_t *hw, uart_hw_flowcontrol_t flow_ctrl, uint32_t rx_thrs) { - // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) - // //only when UART_HW_FLOWCTRL_RTS is set , will the rx_thresh value be set. - // if (flow_ctrl & UART_HW_FLOWCTRL_RTS) { - // hw->hwfc_conf_sync.rx_flow_thrhd = rx_thrs << UART_LL_REG_FIELD_BIT_SHIFT(hw); - // hw->hwfc_conf_sync.rx_flow_en = 1; - // } else { - // hw->hwfc_conf_sync.rx_flow_en = 0; - // } - // if (flow_ctrl & UART_HW_FLOWCTRL_CTS) { - // hw->conf0_sync.tx_flow_en = 1; - // } else { - // hw->conf0_sync.tx_flow_en = 0; - // } - // uart_ll_update(hw); + //only when UART_HW_FLOWCTRL_RTS is set , will the rx_thresh value be set. + if (flow_ctrl & UART_HW_FLOWCTRL_RTS) { + hw->hwfc_conf_sync.rx_flow_thrhd = rx_thrs << UART_LL_REG_FIELD_BIT_SHIFT(hw); + hw->hwfc_conf_sync.rx_flow_en = 1; + } else { + hw->hwfc_conf_sync.rx_flow_en = 0; + } + if (flow_ctrl & UART_HW_FLOWCTRL_CTS) { + hw->conf0_sync.tx_flow_en = 1; + } else { + hw->conf0_sync.tx_flow_en = 0; + } + uart_ll_update(hw); } /** @@ -792,14 +773,13 @@ FORCE_INLINE_ATTR void uart_ll_set_hw_flow_ctrl(uart_dev_t *hw, uart_hw_flowcont */ FORCE_INLINE_ATTR void uart_ll_get_hw_flow_ctrl(uart_dev_t *hw, uart_hw_flowcontrol_t *flow_ctrl) { - // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) - // *flow_ctrl = UART_HW_FLOWCTRL_DISABLE; - // if (hw->hwfc_conf_sync.rx_flow_en) { - // *flow_ctrl = (uart_hw_flowcontrol_t)((unsigned int)(*flow_ctrl) | (unsigned int)UART_HW_FLOWCTRL_RTS); - // } - // if (hw->conf0_sync.tx_flow_en) { - // *flow_ctrl = (uart_hw_flowcontrol_t)((unsigned int)(*flow_ctrl) | (unsigned int)UART_HW_FLOWCTRL_CTS); - // } + *flow_ctrl = UART_HW_FLOWCTRL_DISABLE; + if (hw->hwfc_conf_sync.rx_flow_en) { + *flow_ctrl = (uart_hw_flowcontrol_t)((unsigned int)(*flow_ctrl) | (unsigned int)UART_HW_FLOWCTRL_RTS); + } + if (hw->conf0_sync.tx_flow_en) { + *flow_ctrl = (uart_hw_flowcontrol_t)((unsigned int)(*flow_ctrl) | (unsigned int)UART_HW_FLOWCTRL_CTS); + } } /** @@ -813,19 +793,18 @@ FORCE_INLINE_ATTR void uart_ll_get_hw_flow_ctrl(uart_dev_t *hw, uart_hw_flowcont */ FORCE_INLINE_ATTR void uart_ll_set_sw_flow_ctrl(uart_dev_t *hw, uart_sw_flowctrl_t *flow_ctrl, bool sw_flow_ctrl_en) { - // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) - // if (sw_flow_ctrl_en) { - // hw->swfc_conf0_sync.xonoff_del = 1; - // hw->swfc_conf0_sync.sw_flow_con_en = 1; - // hw->swfc_conf1.xon_threshold = (flow_ctrl->xon_thrd) << UART_LL_REG_FIELD_BIT_SHIFT(hw); - // hw->swfc_conf1.xoff_threshold = (flow_ctrl->xoff_thrd) << UART_LL_REG_FIELD_BIT_SHIFT(hw); - // HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf0_sync, xon_char, flow_ctrl->xon_char); - // HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf0_sync, xoff_char, flow_ctrl->xoff_char); - // } else { - // hw->swfc_conf0_sync.sw_flow_con_en = 0; - // hw->swfc_conf0_sync.xonoff_del = 0; - // } - // uart_ll_update(hw); + if (sw_flow_ctrl_en) { + hw->swfc_conf0_sync.xonoff_del = 1; + hw->swfc_conf0_sync.sw_flow_con_en = 1; + hw->swfc_conf1.xon_threshold = (flow_ctrl->xon_thrd) << UART_LL_REG_FIELD_BIT_SHIFT(hw); + hw->swfc_conf1.xoff_threshold = (flow_ctrl->xoff_thrd) << UART_LL_REG_FIELD_BIT_SHIFT(hw); + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf0_sync, xon_char, flow_ctrl->xon_char); + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf0_sync, xoff_char, flow_ctrl->xoff_char); + } else { + hw->swfc_conf0_sync.sw_flow_con_en = 0; + hw->swfc_conf0_sync.xonoff_del = 0; + } + uart_ll_update(hw); } /** @@ -843,13 +822,12 @@ FORCE_INLINE_ATTR void uart_ll_set_sw_flow_ctrl(uart_dev_t *hw, uart_sw_flowctrl */ FORCE_INLINE_ATTR void uart_ll_set_at_cmd_char(uart_dev_t *hw, uart_at_cmd_t *cmd_char) { - // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) - // HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_char_sync, data, cmd_char->cmd_char); - // HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_char_sync, char_num, cmd_char->char_num); - // HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_postcnt_sync, post_idle_num, cmd_char->post_idle); - // HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_precnt_sync, pre_idle_num, cmd_char->pre_idle); - // HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_gaptout_sync, rx_gap_tout, cmd_char->gap_tout); - // uart_ll_update(hw); + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_char_sync, at_cmd_char, cmd_char->cmd_char); + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_char_sync, char_num, cmd_char->char_num); + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_postcnt_sync, post_idle_num, cmd_char->post_idle); + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_precnt_sync, pre_idle_num, cmd_char->pre_idle); + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_gaptout_sync, rx_gap_tout, cmd_char->gap_tout); + uart_ll_update(hw); } /** @@ -862,9 +840,8 @@ FORCE_INLINE_ATTR void uart_ll_set_at_cmd_char(uart_dev_t *hw, uart_at_cmd_t *cm */ FORCE_INLINE_ATTR void uart_ll_set_data_bit_num(uart_dev_t *hw, uart_word_length_t data_bit) { - // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) - // hw->conf0_sync.bit_num = data_bit; - // uart_ll_update(hw); + hw->conf0_sync.bit_num = data_bit; + uart_ll_update(hw); } /** @@ -877,9 +854,8 @@ FORCE_INLINE_ATTR void uart_ll_set_data_bit_num(uart_dev_t *hw, uart_word_length */ FORCE_INLINE_ATTR void uart_ll_set_rts_active_level(uart_dev_t *hw, int level) { - // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) - // hw->conf0_sync.sw_rts = level & 0x1; - // uart_ll_update(hw); + hw->conf0_sync.sw_rts = level & 0x1; + uart_ll_update(hw); } /** @@ -892,8 +868,7 @@ FORCE_INLINE_ATTR void uart_ll_set_rts_active_level(uart_dev_t *hw, int level) */ FORCE_INLINE_ATTR void uart_ll_set_dtr_active_level(uart_dev_t *hw, int level) { - // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) - // hw->conf1.sw_dtr = level & 0x1; + hw->conf1.sw_dtr = level & 0x1; } /** @@ -907,8 +882,7 @@ FORCE_INLINE_ATTR void uart_ll_set_dtr_active_level(uart_dev_t *hw, int level) */ FORCE_INLINE_ATTR void uart_ll_set_wakeup_thrd(uart_dev_t *hw, uint32_t wakeup_thrd) { - // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) - // hw->sleep_conf2.active_threshold = wakeup_thrd - UART_LL_MIN_WAKEUP_THRESH; + hw->sleep_conf2.active_threshold = wakeup_thrd - UART_LL_MIN_WAKEUP_THRESH; } /** @@ -920,15 +894,15 @@ FORCE_INLINE_ATTR void uart_ll_set_wakeup_thrd(uart_dev_t *hw, uint32_t wakeup_t */ FORCE_INLINE_ATTR void uart_ll_set_mode_normal(uart_dev_t *hw) { - // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) - // // This function is only for HP_UART use - // // LP_UART can only work in normal mode - // // lp_uart_dev_t has no following fields (reserved), but no harm since we map the LP_UART instance to the uart_dev_t struct - // // hw->rs485_conf_sync.rs485_en = 0; - // hw->rs485_conf_sync.rs485tx_rx_en = 0; - // hw->rs485_conf_sync.rs485rxby_tx_en = 0; - // hw->conf0_sync.irda_en = 0; - // uart_ll_update(hw); + // This function is only for HP_UART use + // LP_UART can only work in normal mode + // lp_uart_dev_t has no following fields (reserved), but no harm since we map the LP_UART instance to the uart_dev_t struct + + hw->rs485_conf_sync.rs485_en = 0; + hw->rs485_conf_sync.rs485tx_rx_en = 0; + hw->rs485_conf_sync.rs485rxby_tx_en = 0; + hw->conf0_sync.irda_en = 0; + uart_ll_update(hw); } /** @@ -940,19 +914,19 @@ FORCE_INLINE_ATTR void uart_ll_set_mode_normal(uart_dev_t *hw) */ FORCE_INLINE_ATTR void uart_ll_set_mode_rs485_app_ctrl(uart_dev_t *hw) { - // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) - // // This function is only for HP_UART use - // // LP_UART can only work in normal mode - // // lp_uart_dev_t has no following fields (reserved), but no harm since we map the LP_UART instance to the uart_dev_t struct - // // // Application software control, remove echo - // hw->rs485_conf_sync.rs485rxby_tx_en = 1; - // hw->conf0_sync.irda_en = 0; - // hw->conf0_sync.sw_rts = 0; - // hw->conf0_sync.irda_en = 0; - // hw->rs485_conf_sync.dl0_en = 1; - // hw->rs485_conf_sync.dl1_en = 1; - // hw->rs485_conf_sync.rs485_en = 1; - // uart_ll_update(hw); + // This function is only for HP_UART use + // LP_UART can only work in normal mode + // lp_uart_dev_t has no following fields (reserved), but no harm since we map the LP_UART instance to the uart_dev_t struct + + // Application software control, remove echo + hw->rs485_conf_sync.rs485rxby_tx_en = 1; + hw->conf0_sync.irda_en = 0; + hw->conf0_sync.sw_rts = 0; + hw->conf0_sync.irda_en = 0; + hw->rs485_conf_sync.dl0_en = 1; + hw->rs485_conf_sync.dl1_en = 1; + hw->rs485_conf_sync.rs485_en = 1; + uart_ll_update(hw); } /** @@ -964,22 +938,22 @@ FORCE_INLINE_ATTR void uart_ll_set_mode_rs485_app_ctrl(uart_dev_t *hw) */ FORCE_INLINE_ATTR void uart_ll_set_mode_rs485_half_duplex(uart_dev_t *hw) { - // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) - // // This function is only for HP_UART use - // // LP_UART can only work in normal mode - // // lp_uart_dev_t has no following fields (reserved), but no harm since we map the LP_UART instance to the uart_dev_t struct - // // // Enable receiver, sw_rts = 1 generates low level on RTS pin - // hw->conf0_sync.sw_rts = 1; - // // Half duplex mode - // hw->rs485_conf_sync.rs485tx_rx_en = 0; - // // Setting this bit will allow data to be transmitted while receiving data(full-duplex mode). - // // But note that this full-duplex mode has no conflict detection function - // hw->rs485_conf_sync.rs485rxby_tx_en = 0; - // hw->conf0_sync.irda_en = 0; - // hw->rs485_conf_sync.dl0_en = 1; - // hw->rs485_conf_sync.dl1_en = 1; - // hw->rs485_conf_sync.rs485_en = 1; - // uart_ll_update(hw); + // This function is only for HP_UART use + // LP_UART can only work in normal mode + // lp_uart_dev_t has no following fields (reserved), but no harm since we map the LP_UART instance to the uart_dev_t struct + + // Enable receiver, sw_rts = 1 generates low level on RTS pin + hw->conf0_sync.sw_rts = 1; + // Half duplex mode + hw->rs485_conf_sync.rs485tx_rx_en = 0; + // Setting this bit will allow data to be transmitted while receiving data(full-duplex mode). + // But note that this full-duplex mode has no conflict detection function + hw->rs485_conf_sync.rs485rxby_tx_en = 0; + hw->conf0_sync.irda_en = 0; + hw->rs485_conf_sync.dl0_en = 1; + hw->rs485_conf_sync.dl1_en = 1; + hw->rs485_conf_sync.rs485_en = 1; + uart_ll_update(hw); } /** @@ -991,20 +965,20 @@ FORCE_INLINE_ATTR void uart_ll_set_mode_rs485_half_duplex(uart_dev_t *hw) */ FORCE_INLINE_ATTR void uart_ll_set_mode_collision_detect(uart_dev_t *hw) { - // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) - // // This function is only for HP_UART use - // // LP_UART can only work in normal mode - // // lp_uart_dev_t has no following fields (reserved), but no harm since we map the LP_UART instance to the uart_dev_t struct - // // hw->conf0_sync.irda_en = 0; - // // Enable full-duplex mode - // hw->rs485_conf_sync.rs485tx_rx_en = 1; - // // Transmitter should send data when the receiver is busy, - // hw->rs485_conf_sync.rs485rxby_tx_en = 1; - // hw->rs485_conf_sync.dl0_en = 1; - // hw->rs485_conf_sync.dl1_en = 1; - // hw->conf0_sync.sw_rts = 0; - // hw->rs485_conf_sync.rs485_en = 1; - // uart_ll_update(hw); + // This function is only for HP_UART use + // LP_UART can only work in normal mode + // lp_uart_dev_t has no following fields (reserved), but no harm since we map the LP_UART instance to the uart_dev_t struct + + hw->conf0_sync.irda_en = 0; + // Enable full-duplex mode + hw->rs485_conf_sync.rs485tx_rx_en = 1; + // Transmitter should send data when the receiver is busy, + hw->rs485_conf_sync.rs485rxby_tx_en = 1; + hw->rs485_conf_sync.dl0_en = 1; + hw->rs485_conf_sync.dl1_en = 1; + hw->conf0_sync.sw_rts = 0; + hw->rs485_conf_sync.rs485_en = 1; + uart_ll_update(hw); } /** @@ -1016,16 +990,16 @@ FORCE_INLINE_ATTR void uart_ll_set_mode_collision_detect(uart_dev_t *hw) */ FORCE_INLINE_ATTR void uart_ll_set_mode_irda(uart_dev_t *hw) { - // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) - // // This function is only for HP_UART use - // // LP_UART can only work in normal mode - // // lp_uart_dev_t has no following fields (reserved), but no harm since we map the LP_UART instance to the uart_dev_t struct - // // hw->rs485_conf_sync.rs485_en = 0; - // hw->rs485_conf_sync.rs485tx_rx_en = 0; - // hw->rs485_conf_sync.rs485rxby_tx_en = 0; - // hw->conf0_sync.sw_rts = 0; - // hw->conf0_sync.irda_en = 1; - // uart_ll_update(hw); + // This function is only for HP_UART use + // LP_UART can only work in normal mode + // lp_uart_dev_t has no following fields (reserved), but no harm since we map the LP_UART instance to the uart_dev_t struct + + hw->rs485_conf_sync.rs485_en = 0; + hw->rs485_conf_sync.rs485tx_rx_en = 0; + hw->rs485_conf_sync.rs485rxby_tx_en = 0; + hw->conf0_sync.sw_rts = 0; + hw->conf0_sync.irda_en = 1; + uart_ll_update(hw); } /** @@ -1038,29 +1012,28 @@ FORCE_INLINE_ATTR void uart_ll_set_mode_irda(uart_dev_t *hw) */ FORCE_INLINE_ATTR void uart_ll_set_mode(uart_dev_t *hw, uart_mode_t mode) { - // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) - // switch (mode) { - // default: - // case UART_MODE_UART: - // uart_ll_set_mode_normal(hw); - // break; - // case UART_MODE_RS485_COLLISION_DETECT: - // // Only HP_UART support this mode - // uart_ll_set_mode_collision_detect(hw); - // break; - // case UART_MODE_RS485_APP_CTRL: - // // Only HP_UART support this mode - // uart_ll_set_mode_rs485_app_ctrl(hw); - // break; - // case UART_MODE_RS485_HALF_DUPLEX: - // // Only HP_UART support this mode - // uart_ll_set_mode_rs485_half_duplex(hw); - // break; - // case UART_MODE_IRDA: - // // Only HP_UART support this mode - // uart_ll_set_mode_irda(hw); - // break; - // } + switch (mode) { + default: + case UART_MODE_UART: + uart_ll_set_mode_normal(hw); + break; + case UART_MODE_RS485_COLLISION_DETECT: + // Only HP_UART support this mode + uart_ll_set_mode_collision_detect(hw); + break; + case UART_MODE_RS485_APP_CTRL: + // Only HP_UART support this mode + uart_ll_set_mode_rs485_app_ctrl(hw); + break; + case UART_MODE_RS485_HALF_DUPLEX: + // Only HP_UART support this mode + uart_ll_set_mode_rs485_half_duplex(hw); + break; + case UART_MODE_IRDA: + // Only HP_UART support this mode + uart_ll_set_mode_irda(hw); + break; + } } /** @@ -1074,9 +1047,8 @@ FORCE_INLINE_ATTR void uart_ll_set_mode(uart_dev_t *hw, uart_mode_t mode) */ FORCE_INLINE_ATTR void uart_ll_get_at_cmd_char(uart_dev_t *hw, uint8_t *cmd_char, uint8_t *char_num) { - // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) - // *cmd_char = HAL_FORCE_READ_U32_REG_FIELD(hw->at_cmd_char_sync, data); - // *char_num = HAL_FORCE_READ_U32_REG_FIELD(hw->at_cmd_char_sync, char_num); + *cmd_char = HAL_FORCE_READ_U32_REG_FIELD(hw->at_cmd_char_sync, at_cmd_char); + *char_num = HAL_FORCE_READ_U32_REG_FIELD(hw->at_cmd_char_sync, char_num); } /** @@ -1088,9 +1060,7 @@ FORCE_INLINE_ATTR void uart_ll_get_at_cmd_char(uart_dev_t *hw, uint8_t *cmd_char */ FORCE_INLINE_ATTR uint32_t uart_ll_get_wakeup_thrd(uart_dev_t *hw) { - // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) - // return hw->sleep_conf2.active_threshold + UART_LL_MIN_WAKEUP_THRESH; - return (uint32_t)0; + return hw->sleep_conf2.active_threshold + UART_LL_MIN_WAKEUP_THRESH; } /** @@ -1103,8 +1073,7 @@ FORCE_INLINE_ATTR uint32_t uart_ll_get_wakeup_thrd(uart_dev_t *hw) */ FORCE_INLINE_ATTR void uart_ll_get_data_bit_num(uart_dev_t *hw, uart_word_length_t *data_bit) { - // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) - // *data_bit = (uart_word_length_t)hw->conf0_sync.bit_num; + *data_bit = (uart_word_length_t)hw->conf0_sync.bit_num; } /** @@ -1116,9 +1085,7 @@ FORCE_INLINE_ATTR void uart_ll_get_data_bit_num(uart_dev_t *hw, uart_word_length */ FORCE_INLINE_ATTR bool uart_ll_is_tx_idle(uart_dev_t *hw) { - // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) - // return ((((hw->status.txfifo_cnt) >> UART_LL_REG_FIELD_BIT_SHIFT(hw)) == 0) && (hw->fsm_status.st_utx_out == 0)); - return (bool)0; + return ((((hw->status.txfifo_cnt) >> UART_LL_REG_FIELD_BIT_SHIFT(hw)) == 0) && (hw->fsm_status.st_utx_out == 0)); } /** @@ -1130,9 +1097,7 @@ FORCE_INLINE_ATTR bool uart_ll_is_tx_idle(uart_dev_t *hw) */ FORCE_INLINE_ATTR bool uart_ll_is_hw_rts_en(uart_dev_t *hw) { - // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) - // return hw->hwfc_conf_sync.rx_flow_en; - return (bool)0; + return hw->hwfc_conf_sync.rx_flow_en; } /** @@ -1144,9 +1109,7 @@ FORCE_INLINE_ATTR bool uart_ll_is_hw_rts_en(uart_dev_t *hw) */ FORCE_INLINE_ATTR bool uart_ll_is_hw_cts_en(uart_dev_t *hw) { - // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) - // return hw->conf0_sync.tx_flow_en; - return (bool)0; + return hw->conf0_sync.tx_flow_en; } /** @@ -1159,20 +1122,18 @@ FORCE_INLINE_ATTR bool uart_ll_is_hw_cts_en(uart_dev_t *hw) */ FORCE_INLINE_ATTR void uart_ll_set_loop_back(uart_dev_t *hw, bool loop_back_en) { - // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) - // hw->conf0_sync.loopback = loop_back_en; - // uart_ll_update(hw); + hw->conf0_sync.loopback = loop_back_en; + uart_ll_update(hw); } FORCE_INLINE_ATTR void uart_ll_xon_force_on(uart_dev_t *hw, bool always_on) { - // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) - // hw->swfc_conf0_sync.force_xon = 1; - // uart_ll_update(hw); - // if (!always_on) { - // hw->swfc_conf0_sync.force_xon = 0; - // uart_ll_update(hw); - // } + hw->swfc_conf0_sync.force_xon = 1; + uart_ll_update(hw); + if (!always_on) { + hw->swfc_conf0_sync.force_xon = 0; + uart_ll_update(hw); + } } /** @@ -1186,24 +1147,25 @@ FORCE_INLINE_ATTR void uart_ll_xon_force_on(uart_dev_t *hw, bool always_on) */ FORCE_INLINE_ATTR void uart_ll_inverse_signal(uart_dev_t *hw, uint32_t inv_mask) { - // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) - // // LP_UART does not support UART_SIGNAL_IRDA_TX_INV and UART_SIGNAL_IRDA_RX_INV - // // lp_uart_dev_t has no these fields (reserved), but no harm since we map the LP_UART instance to the uart_dev_t struct - // // typeof(hw->conf0_sync) conf0_reg; - // conf0_reg.val = hw->conf0_sync.val; - // conf0_reg.irda_tx_inv = (inv_mask & UART_SIGNAL_IRDA_TX_INV) ? 1 : 0; - // conf0_reg.irda_rx_inv = (inv_mask & UART_SIGNAL_IRDA_RX_INV) ? 1 : 0; - // conf0_reg.rxd_inv = (inv_mask & UART_SIGNAL_RXD_INV) ? 1 : 0; - // conf0_reg.txd_inv = (inv_mask & UART_SIGNAL_TXD_INV) ? 1 : 0; - // hw->conf0_sync.val = conf0_reg.val; - // // typeof(hw->conf1) conf1_reg; - // conf1_reg.val = hw->conf1.val; - // conf1_reg.rts_inv = (inv_mask & UART_SIGNAL_RTS_INV) ? 1 : 0; - // conf1_reg.dtr_inv = (inv_mask & UART_SIGNAL_DTR_INV) ? 1 : 0; - // conf1_reg.cts_inv = (inv_mask & UART_SIGNAL_CTS_INV) ? 1 : 0; - // conf1_reg.dsr_inv = (inv_mask & UART_SIGNAL_DSR_INV) ? 1 : 0; - // hw->conf1.val = conf1_reg.val; - // uart_ll_update(hw); + // LP_UART does not support UART_SIGNAL_IRDA_TX_INV and UART_SIGNAL_IRDA_RX_INV + // lp_uart_dev_t has no these fields (reserved), but no harm since we map the LP_UART instance to the uart_dev_t struct + + typeof(hw->conf0_sync) conf0_reg; + conf0_reg.val = hw->conf0_sync.val; + conf0_reg.irda_tx_inv = (inv_mask & UART_SIGNAL_IRDA_TX_INV) ? 1 : 0; + conf0_reg.irda_rx_inv = (inv_mask & UART_SIGNAL_IRDA_RX_INV) ? 1 : 0; + conf0_reg.rxd_inv = (inv_mask & UART_SIGNAL_RXD_INV) ? 1 : 0; + conf0_reg.txd_inv = (inv_mask & UART_SIGNAL_TXD_INV) ? 1 : 0; + hw->conf0_sync.val = conf0_reg.val; + + typeof(hw->conf1) conf1_reg; + conf1_reg.val = hw->conf1.val; + conf1_reg.rts_inv = (inv_mask & UART_SIGNAL_RTS_INV) ? 1 : 0; + conf1_reg.dtr_inv = (inv_mask & UART_SIGNAL_DTR_INV) ? 1 : 0; + conf1_reg.cts_inv = (inv_mask & UART_SIGNAL_CTS_INV) ? 1 : 0; + conf1_reg.dsr_inv = (inv_mask & UART_SIGNAL_DSR_INV) ? 1 : 0; + hw->conf1.val = conf1_reg.val; + uart_ll_update(hw); } /** @@ -1216,15 +1178,14 @@ FORCE_INLINE_ATTR void uart_ll_inverse_signal(uart_dev_t *hw, uint32_t inv_mask) */ FORCE_INLINE_ATTR void uart_ll_set_rx_tout(uart_dev_t *hw, uint16_t tout_thrd) { - // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) - // uint16_t tout_val = tout_thrd; - // if (tout_thrd > 0) { - // hw->tout_conf_sync.rx_tout_thrhd = tout_val; - // hw->tout_conf_sync.rx_tout_en = 1; - // } else { - // hw->tout_conf_sync.rx_tout_en = 0; - // } - // uart_ll_update(hw); + uint16_t tout_val = tout_thrd; + if (tout_thrd > 0) { + hw->tout_conf_sync.rx_tout_thrhd = tout_val; + hw->tout_conf_sync.rx_tout_en = 1; + } else { + hw->tout_conf_sync.rx_tout_en = 0; + } + uart_ll_update(hw); } /** @@ -1236,13 +1197,11 @@ FORCE_INLINE_ATTR void uart_ll_set_rx_tout(uart_dev_t *hw, uint16_t tout_thrd) */ FORCE_INLINE_ATTR uint16_t uart_ll_get_rx_tout_thr(uart_dev_t *hw) { - // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) - // uint16_t tout_thrd = 0; - // if (hw->tout_conf_sync.rx_tout_en > 0) { - // tout_thrd = hw->tout_conf_sync.rx_tout_thrhd; - // } - // return tout_thrd; - return (uint16_t)0; + uint16_t tout_thrd = 0; + if (hw->tout_conf_sync.rx_tout_en > 0) { + tout_thrd = hw->tout_conf_sync.rx_tout_thrhd; + } + return tout_thrd; } /** @@ -1254,9 +1213,7 @@ FORCE_INLINE_ATTR uint16_t uart_ll_get_rx_tout_thr(uart_dev_t *hw) */ FORCE_INLINE_ATTR uint16_t uart_ll_max_tout_thrd(uart_dev_t *hw) { - // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) - // return ((hw) == &LP_UART) ? LP_UART_RX_TOUT_THRHD_V : UART_RX_TOUT_THRHD_V; - return (uint16_t)0; + return ((hw) == &LP_UART) ? LP_UART_RX_TOUT_THRHD_V : UART_RX_TOUT_THRHD_V; } /** @@ -1267,11 +1224,11 @@ FORCE_INLINE_ATTR uint16_t uart_ll_max_tout_thrd(uart_dev_t *hw) */ FORCE_INLINE_ATTR void uart_ll_set_autobaud_en(uart_dev_t *hw, bool enable) { - // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) - // // LP_UART does not support autobaud - // // lp_uart_dev_t has no following fields (reserved), but no harm since we map the LP_UART instance to the uart_dev_t struct - // // hw->conf0_sync.autobaud_en = enable ? 1 : 0; - // uart_ll_update(hw); + // LP_UART does not support autobaud + // lp_uart_dev_t has no following fields (reserved), but no harm since we map the LP_UART instance to the uart_dev_t struct + + hw->conf0_sync.autobaud_en = enable ? 1 : 0; + uart_ll_update(hw); } /** @@ -1281,11 +1238,10 @@ FORCE_INLINE_ATTR void uart_ll_set_autobaud_en(uart_dev_t *hw, bool enable) */ FORCE_INLINE_ATTR uint32_t uart_ll_get_rxd_edge_cnt(uart_dev_t *hw) { - // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) - // // LP_UART does not support this feature - // // lp_uart_dev_t has no following fields (reserved), but no harm since we map the LP_UART instance to the uart_dev_t struct - // // return hw->rxd_cnt.rxd_edge_cnt; - return (uint32_t)0; + // LP_UART does not support this feature + // lp_uart_dev_t has no following fields (reserved), but no harm since we map the LP_UART instance to the uart_dev_t struct + + return hw->rxd_cnt.rxd_edge_cnt; } /** @@ -1295,11 +1251,10 @@ FORCE_INLINE_ATTR uint32_t uart_ll_get_rxd_edge_cnt(uart_dev_t *hw) */ FORCE_INLINE_ATTR uint32_t uart_ll_get_pos_pulse_cnt(uart_dev_t *hw) { - // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) - // // LP_UART does not support this feature - // // lp_uart_dev_t has no following fields (reserved), but no harm since we map the LP_UART instance to the uart_dev_t struct - // // return hw->pospulse.posedge_min_cnt; - return (uint32_t)0; + // LP_UART does not support this feature + // lp_uart_dev_t has no following fields (reserved), but no harm since we map the LP_UART instance to the uart_dev_t struct + + return hw->pospulse.posedge_min_cnt; } /** @@ -1309,11 +1264,10 @@ FORCE_INLINE_ATTR uint32_t uart_ll_get_pos_pulse_cnt(uart_dev_t *hw) */ FORCE_INLINE_ATTR uint32_t uart_ll_get_neg_pulse_cnt(uart_dev_t *hw) { - // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) - // // LP_UART does not support this feature - // // lp_uart_dev_t has no following fields (reserved), but no harm since we map the LP_UART instance to the uart_dev_t struct - // // return hw->negpulse.negedge_min_cnt; - return (uint32_t)0; + // LP_UART does not support this feature + // lp_uart_dev_t has no following fields (reserved), but no harm since we map the LP_UART instance to the uart_dev_t struct + + return hw->negpulse.negedge_min_cnt; } /** @@ -1323,11 +1277,10 @@ FORCE_INLINE_ATTR uint32_t uart_ll_get_neg_pulse_cnt(uart_dev_t *hw) */ FORCE_INLINE_ATTR uint32_t uart_ll_get_high_pulse_cnt(uart_dev_t *hw) { - // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) - // // LP_UART does not support this feature - // // lp_uart_dev_t has no following fields (reserved), but no harm since we map the LP_UART instance to the uart_dev_t struct - // // return hw->highpulse.highpulse_min_cnt; - return (uint32_t)0; + // LP_UART does not support this feature + // lp_uart_dev_t has no following fields (reserved), but no harm since we map the LP_UART instance to the uart_dev_t struct + + return hw->highpulse.highpulse_min_cnt; } /** @@ -1337,11 +1290,10 @@ FORCE_INLINE_ATTR uint32_t uart_ll_get_high_pulse_cnt(uart_dev_t *hw) */ FORCE_INLINE_ATTR uint32_t uart_ll_get_low_pulse_cnt(uart_dev_t *hw) { - // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) - // // LP_UART does not support this feature - // // lp_uart_dev_t has no following fields (reserved), but no harm since we map the LP_UART instance to the uart_dev_t struct - // // return hw->lowpulse.lowpulse_min_cnt; - return (uint32_t)0; + // LP_UART does not support this feature + // lp_uart_dev_t has no following fields (reserved), but no harm since we map the LP_UART instance to the uart_dev_t struct + + return hw->lowpulse.lowpulse_min_cnt; } /** @@ -1353,12 +1305,11 @@ FORCE_INLINE_ATTR uint32_t uart_ll_get_low_pulse_cnt(uart_dev_t *hw) */ FORCE_INLINE_ATTR void uart_ll_force_xoff(uart_port_t uart_num) { - // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) - // uart_dev_t *hw = UART_LL_GET_HW(uart_num); - // hw->swfc_conf0_sync.force_xon = 0; - // hw->swfc_conf0_sync.sw_flow_con_en = 1; - // hw->swfc_conf0_sync.force_xoff = 1; - // uart_ll_update(hw); + uart_dev_t *hw = UART_LL_GET_HW(uart_num); + hw->swfc_conf0_sync.force_xon = 0; + hw->swfc_conf0_sync.sw_flow_con_en = 1; + hw->swfc_conf0_sync.force_xoff = 1; + uart_ll_update(hw); } /** @@ -1370,13 +1321,12 @@ FORCE_INLINE_ATTR void uart_ll_force_xoff(uart_port_t uart_num) */ FORCE_INLINE_ATTR void uart_ll_force_xon(uart_port_t uart_num) { - // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) - // uart_dev_t *hw = UART_LL_GET_HW(uart_num); - // hw->swfc_conf0_sync.force_xoff = 0; - // hw->swfc_conf0_sync.force_xon = 1; - // hw->swfc_conf0_sync.sw_flow_con_en = 0; - // hw->swfc_conf0_sync.force_xon = 0; - // uart_ll_update(hw); + uart_dev_t *hw = UART_LL_GET_HW(uart_num); + hw->swfc_conf0_sync.force_xoff = 0; + hw->swfc_conf0_sync.force_xon = 1; + hw->swfc_conf0_sync.sw_flow_con_en = 0; + hw->swfc_conf0_sync.force_xon = 0; + uart_ll_update(hw); } /** @@ -1388,10 +1338,8 @@ FORCE_INLINE_ATTR void uart_ll_force_xon(uart_port_t uart_num) */ FORCE_INLINE_ATTR uint32_t uart_ll_get_tx_fsm_status(uart_port_t uart_num) { - // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) - // uart_dev_t *hw = UART_LL_GET_HW(uart_num); - // return hw->fsm_status.st_utx_out; - return (uint32_t)0; + uart_dev_t *hw = UART_LL_GET_HW(uart_num); + return hw->fsm_status.st_utx_out; } /** @@ -1403,9 +1351,8 @@ FORCE_INLINE_ATTR uint32_t uart_ll_get_tx_fsm_status(uart_port_t uart_num) */ FORCE_INLINE_ATTR void uart_ll_discard_error_data(uart_dev_t *hw, bool discard) { - // TODO: [ESP32C5] IDF-8722, IDF-8633 (inherit from C6) - // hw->conf0_sync.err_wr_mask = discard ? 1 : 0; - // uart_ll_update(hw); + hw->conf0_sync.err_wr_mask = discard ? 1 : 0; + uart_ll_update(hw); } #ifdef __cplusplus diff --git a/components/hal/esp32c5/modem_clock_hal.c b/components/hal/esp32c5/modem_clock_hal.c new file mode 100644 index 0000000000..5beb69f955 --- /dev/null +++ b/components/hal/esp32c5/modem_clock_hal.c @@ -0,0 +1,267 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +// The HAL layer for MODEM CLOCK (ESP32-C6 specific part) +#include +#include "soc/soc.h" +#include "esp_attr.h" +#include "hal/modem_clock_hal.h" +#include "hal/modem_clock_types.h" +#include "hal/efuse_hal.h" +#include "hal/assert.h" + +typedef enum { + MODEM_CLOCK_XTAL32K_CODE = 0, + MODEM_CLOCK_RC32K_CODE = 1, + MODEM_CLOCK_EXT32K_CODE = 2 +} modem_clock_32k_clk_src_code_t; + +void IRAM_ATTR modem_clock_hal_set_clock_domain_icg_bitmap(modem_clock_hal_context_t *hal, modem_clock_domain_t domain, uint32_t bitmap) +{ + HAL_ASSERT(domain < MODEM_CLOCK_DOMAIN_MAX); + switch (domain) + { + case MODEM_CLOCK_DOMAIN_MODEM_APB: + modem_syscon_ll_set_modem_apb_icg_bitmap(hal->syscon_dev, bitmap); + break; + case MODEM_CLOCK_DOMAIN_MODEM_PERIPH: + modem_syscon_ll_set_modem_periph_icg_bitmap(hal->syscon_dev, bitmap); + break; + case MODEM_CLOCK_DOMAIN_WIFI: + modem_syscon_ll_set_wifi_icg_bitmap(hal->syscon_dev, bitmap); + break; + case MODEM_CLOCK_DOMAIN_BT: + modem_syscon_ll_set_bt_icg_bitmap(hal->syscon_dev, bitmap); + break; + case MODEM_CLOCK_DOMAIN_MODEM_FE: + modem_syscon_ll_set_fe_icg_bitmap(hal->syscon_dev, bitmap); + break; + case MODEM_CLOCK_DOMAIN_IEEE802154: + modem_syscon_ll_set_ieee802154_icg_bitmap(hal->syscon_dev, bitmap); + break; + case MODEM_CLOCK_DOMAIN_LP_APB: + modem_lpcon_ll_set_lp_apb_icg_bitmap(hal->lpcon_dev, bitmap); + break; + case MODEM_CLOCK_DOMAIN_I2C_MASTER: + modem_lpcon_ll_set_i2c_master_icg_bitmap(hal->lpcon_dev, bitmap); + break; + case MODEM_CLOCK_DOMAIN_COEX: + modem_lpcon_ll_set_coex_icg_bitmap(hal->lpcon_dev, bitmap); + break; + case MODEM_CLOCK_DOMAIN_WIFIPWR: + modem_lpcon_ll_set_wifipwr_icg_bitmap(hal->lpcon_dev, bitmap); + break; + default: + HAL_ASSERT(0); + } +} + +uint32_t modem_clock_hal_get_clock_domain_icg_bitmap(modem_clock_hal_context_t *hal, modem_clock_domain_t domain) +{ + HAL_ASSERT(domain < MODEM_CLOCK_DOMAIN_MAX); + uint32_t bitmap = 0; + switch (domain) + { + case MODEM_CLOCK_DOMAIN_MODEM_APB: + bitmap = modem_syscon_ll_get_modem_apb_icg_bitmap(hal->syscon_dev); + break; + case MODEM_CLOCK_DOMAIN_MODEM_PERIPH: + bitmap = modem_syscon_ll_get_modem_periph_icg_bitmap(hal->syscon_dev); + break; + case MODEM_CLOCK_DOMAIN_WIFI: + bitmap = modem_syscon_ll_get_wifi_icg_bitmap(hal->syscon_dev); + break; + case MODEM_CLOCK_DOMAIN_BT: + bitmap = modem_syscon_ll_get_bt_icg_bitmap(hal->syscon_dev); + break; + case MODEM_CLOCK_DOMAIN_MODEM_FE: + bitmap = modem_syscon_ll_get_fe_icg_bitmap(hal->syscon_dev); + break; + case MODEM_CLOCK_DOMAIN_IEEE802154: + bitmap = modem_syscon_ll_get_ieee802154_icg_bitmap(hal->syscon_dev); + break; + case MODEM_CLOCK_DOMAIN_LP_APB: + bitmap = modem_lpcon_ll_get_lp_apb_icg_bitmap(hal->lpcon_dev); + break; + case MODEM_CLOCK_DOMAIN_I2C_MASTER: + bitmap = modem_lpcon_ll_get_i2c_master_icg_bitmap(hal->lpcon_dev); + break; + case MODEM_CLOCK_DOMAIN_COEX: + bitmap = modem_lpcon_ll_get_coex_icg_bitmap(hal->lpcon_dev); + break; + case MODEM_CLOCK_DOMAIN_WIFIPWR: + bitmap = modem_lpcon_ll_get_wifipwr_icg_bitmap(hal->lpcon_dev); + break; + default: + HAL_ASSERT(0); + } + return bitmap; +} + +void IRAM_ATTR modem_clock_hal_enable_modem_adc_common_fe_clock(modem_clock_hal_context_t *hal, bool enable) +{ + if (enable) { + modem_syscon_ll_enable_fe_apb_clock(hal->syscon_dev, enable); + modem_syscon_ll_enable_fe_80m_clock(hal->syscon_dev, enable); + } +} + +void IRAM_ATTR modem_clock_hal_enable_modem_private_fe_clock(modem_clock_hal_context_t *hal, bool enable) +{ + if (enable) { + modem_syscon_ll_enable_fe_cal_160m_clock(hal->syscon_dev, enable); + modem_syscon_ll_enable_fe_160m_clock(hal->syscon_dev, enable); + } +} + +void modem_clock_hal_set_ble_rtc_timer_divisor_value(modem_clock_hal_context_t *hal, uint32_t divider) +{ + modem_lpcon_ll_set_ble_rtc_timer_divisor_value(hal->lpcon_dev, divider); +} + +void modem_clock_hal_enable_ble_rtc_timer_clock(modem_clock_hal_context_t *hal, bool enable) +{ + modem_lpcon_ll_enable_ble_rtc_timer_clock(hal->lpcon_dev, enable); +} + +void modem_clock_hal_deselect_all_ble_rtc_timer_lpclk_source(modem_clock_hal_context_t *hal) +{ + modem_lpcon_ll_enable_ble_rtc_timer_slow_osc(hal->lpcon_dev, false); + modem_lpcon_ll_enable_ble_rtc_timer_fast_osc(hal->lpcon_dev, false); + modem_lpcon_ll_enable_ble_rtc_timer_32k_xtal(hal->lpcon_dev, false); + modem_lpcon_ll_enable_ble_rtc_timer_main_xtal(hal->lpcon_dev, false); +} + +void modem_clock_hal_select_ble_rtc_timer_lpclk_source(modem_clock_hal_context_t *hal, modem_clock_lpclk_src_t src) +{ + HAL_ASSERT(src < MODEM_CLOCK_LPCLK_SRC_MAX); + + switch (src) + { + case MODEM_CLOCK_LPCLK_SRC_RC_SLOW: + modem_lpcon_ll_enable_ble_rtc_timer_slow_osc(hal->lpcon_dev, true); + break; + case MODEM_CLOCK_LPCLK_SRC_RC_FAST: + modem_lpcon_ll_enable_ble_rtc_timer_fast_osc(hal->lpcon_dev, true); + break; + case MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL: + modem_lpcon_ll_enable_ble_rtc_timer_main_xtal(hal->lpcon_dev, true); + break; + case MODEM_CLOCK_LPCLK_SRC_RC32K: + modem_lpcon_ll_enable_ble_rtc_timer_32k_xtal(hal->lpcon_dev, true); + modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_RC32K_CODE); + break; + case MODEM_CLOCK_LPCLK_SRC_XTAL32K: + modem_lpcon_ll_enable_ble_rtc_timer_32k_xtal(hal->lpcon_dev, true); + modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_XTAL32K_CODE); + break; + case MODEM_CLOCK_LPCLK_SRC_EXT32K: + modem_lpcon_ll_enable_ble_rtc_timer_32k_xtal(hal->lpcon_dev, true); + modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_EXT32K_CODE); + break; + default: + HAL_ASSERT(0); + } +} + +void modem_clock_hal_deselect_all_coex_lpclk_source(modem_clock_hal_context_t *hal) +{ + modem_lpcon_ll_enable_coex_lpclk_slow_osc(hal->lpcon_dev, false); + modem_lpcon_ll_enable_coex_lpclk_fast_osc(hal->lpcon_dev, false); + modem_lpcon_ll_enable_coex_lpclk_32k_xtal(hal->lpcon_dev, false); + modem_lpcon_ll_enable_coex_lpclk_main_xtal(hal->lpcon_dev, false); +} + +void modem_clock_hal_select_coex_lpclk_source(modem_clock_hal_context_t *hal, modem_clock_lpclk_src_t src) +{ + HAL_ASSERT(src < MODEM_CLOCK_LPCLK_SRC_MAX); + + switch (src) + { + case MODEM_CLOCK_LPCLK_SRC_RC_SLOW: + modem_lpcon_ll_enable_coex_lpclk_slow_osc(hal->lpcon_dev, true); + break; + case MODEM_CLOCK_LPCLK_SRC_RC_FAST: + modem_lpcon_ll_enable_coex_lpclk_fast_osc(hal->lpcon_dev, true); + break; + case MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL: + modem_lpcon_ll_enable_coex_lpclk_main_xtal(hal->lpcon_dev, true); + break; + case MODEM_CLOCK_LPCLK_SRC_RC32K: + modem_lpcon_ll_enable_coex_lpclk_32k_xtal(hal->lpcon_dev, true); + modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_RC32K_CODE); + break; + case MODEM_CLOCK_LPCLK_SRC_XTAL32K: + modem_lpcon_ll_enable_coex_lpclk_32k_xtal(hal->lpcon_dev, true); + modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_XTAL32K_CODE); + break; + case MODEM_CLOCK_LPCLK_SRC_EXT32K: + modem_lpcon_ll_enable_coex_lpclk_32k_xtal(hal->lpcon_dev, true); + modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_EXT32K_CODE); + break; + default: + HAL_ASSERT(0); + } +} + +void modem_clock_hal_deselect_all_wifi_lpclk_source(modem_clock_hal_context_t *hal) +{ + modem_lpcon_ll_enable_wifi_lpclk_slow_osc(hal->lpcon_dev, false); + modem_lpcon_ll_enable_wifi_lpclk_fast_osc(hal->lpcon_dev, false); + modem_lpcon_ll_enable_wifi_lpclk_32k_xtal(hal->lpcon_dev, false); + modem_lpcon_ll_enable_wifi_lpclk_main_xtal(hal->lpcon_dev, false); +} + +void modem_clock_hal_select_wifi_lpclk_source(modem_clock_hal_context_t *hal, modem_clock_lpclk_src_t src) +{ + HAL_ASSERT(src < MODEM_CLOCK_LPCLK_SRC_MAX); + + switch (src) + { + case MODEM_CLOCK_LPCLK_SRC_RC_SLOW: + modem_lpcon_ll_enable_wifi_lpclk_slow_osc(hal->lpcon_dev, true); + break; + case MODEM_CLOCK_LPCLK_SRC_RC_FAST: + modem_lpcon_ll_enable_wifi_lpclk_fast_osc(hal->lpcon_dev, true); + break; + case MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL: + modem_lpcon_ll_enable_wifi_lpclk_main_xtal(hal->lpcon_dev, true); + break; + case MODEM_CLOCK_LPCLK_SRC_RC32K: + modem_lpcon_ll_enable_wifi_lpclk_32k_xtal(hal->lpcon_dev, true); + modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_RC32K_CODE); + break; + case MODEM_CLOCK_LPCLK_SRC_XTAL32K: + modem_lpcon_ll_enable_wifi_lpclk_32k_xtal(hal->lpcon_dev, true); + modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_XTAL32K_CODE); + break; + case MODEM_CLOCK_LPCLK_SRC_EXT32K: + modem_lpcon_ll_enable_wifi_lpclk_32k_xtal(hal->lpcon_dev, true); + modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_EXT32K_CODE); + break; + default: + HAL_ASSERT(0); + } +} + +void modem_clock_hal_enable_wifipwr_clock(modem_clock_hal_context_t *hal, bool enable) +{ + if (efuse_hal_chip_revision() == 0) { /* eco0 */ + modem_lpcon_ll_enable_wifipwr_clock(hal->lpcon_dev, enable); + } else { + static int ref = 0; + if (enable) { + if (ref++ == 0) { + modem_lpcon_ll_enable_wifipwr_clock(hal->lpcon_dev, enable); + } + } else { + if (--ref == 0) { + modem_lpcon_ll_enable_wifipwr_clock(hal->lpcon_dev, enable); + } + } + HAL_ASSERT(ref > 0); + } +} diff --git a/components/hal/esp32c5/pmu_hal.c b/components/hal/esp32c5/pmu_hal.c new file mode 100644 index 0000000000..d4e2a7514c --- /dev/null +++ b/components/hal/esp32c5/pmu_hal.c @@ -0,0 +1,70 @@ +/* + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +// The HAL layer for PMU (ESP32-C5 specific part) + +#include "soc/soc.h" +#include "esp_attr.h" +#include "hal/pmu_hal.h" +#include "hal/pmu_types.h" + +void pmu_hal_hp_set_digital_power_up_wait_cycle(pmu_hal_context_t *hal, uint32_t power_supply_wait_cycle, uint32_t power_up_wait_cycle) +{ + pmu_ll_hp_set_digital_power_supply_wait_cycle(hal->dev, power_supply_wait_cycle); + pmu_ll_hp_set_digital_power_up_wait_cycle(hal->dev, power_up_wait_cycle); +} + +uint32_t pmu_hal_hp_get_digital_power_up_wait_cycle(pmu_hal_context_t *hal) +{ + uint32_t power_supply_wait_cycle = pmu_ll_hp_get_digital_power_supply_wait_cycle(hal->dev); + uint32_t power_up_wait_cycle = pmu_ll_hp_get_digital_power_up_wait_cycle(hal->dev); + return power_supply_wait_cycle + power_up_wait_cycle; +} + +void pmu_hal_lp_set_digital_power_up_wait_cycle(pmu_hal_context_t *hal, uint32_t power_supply_wait_cycle, uint32_t power_up_wait_cycle) +{ + pmu_ll_lp_set_digital_power_supply_wait_cycle(hal->dev, power_supply_wait_cycle); + pmu_ll_lp_set_digital_power_up_wait_cycle(hal->dev, power_up_wait_cycle); +} + +uint32_t pmu_hal_lp_get_digital_power_up_wait_cycle(pmu_hal_context_t *hal) +{ + uint32_t power_supply_wait_cycle = pmu_ll_lp_get_digital_power_supply_wait_cycle(hal->dev); + uint32_t power_up_wait_cycle = pmu_ll_lp_get_digital_power_up_wait_cycle(hal->dev); + return power_supply_wait_cycle + power_up_wait_cycle; +} + +void pmu_hal_hp_set_sleep_active_backup_enable(pmu_hal_context_t *hal) +{ + pmu_ll_hp_set_active_to_sleep_backup_enable(hal->dev); + pmu_ll_hp_set_sleep_to_active_backup_enable(hal->dev); +} + +void pmu_hal_hp_set_sleep_active_backup_disable(pmu_hal_context_t *hal) +{ + pmu_ll_hp_set_sleep_to_active_backup_disable(hal->dev); + pmu_ll_hp_set_active_to_sleep_backup_disable(hal->dev); +} + +void pmu_hal_hp_set_sleep_modem_backup_enable(pmu_hal_context_t *hal) +{ + pmu_ll_hp_set_sleep_to_modem_backup_enable(hal->dev); +} + +void pmu_hal_hp_set_sleep_modem_backup_disable(pmu_hal_context_t *hal) +{ + pmu_ll_hp_set_sleep_to_modem_backup_disable(hal->dev); +} + +void pmu_hal_hp_set_modem_active_backup_enable(pmu_hal_context_t *hal) +{ + pmu_ll_hp_set_modem_to_active_backup_enable(hal->dev); +} + +void pmu_hal_hp_set_modem_active_backup_disable(pmu_hal_context_t *hal) +{ + pmu_ll_hp_set_modem_to_active_backup_disable(hal->dev); +} diff --git a/components/hal/include/hal/rtc_hal.h b/components/hal/include/hal/rtc_hal.h index 99f7c07e66..dec7912554 100644 --- a/components/hal/include/hal/rtc_hal.h +++ b/components/hal/include/hal/rtc_hal.h @@ -11,11 +11,11 @@ #include "hal/gpio_types.h" #include "sdkconfig.h" -#if !CONFIG_IDF_TARGET_ESP32P4 //TODO: IDF-7532 +#if !CONFIG_IDF_TARGET_ESP32P4 && ! CONFIG_IDF_TARGET_ESP32C5 //TODO: IDF-7532, [ESP32C5] IDF-8636 #if !SOC_LP_TIMER_SUPPORTED #include "hal/rtc_cntl_ll.h" #endif -#endif //#if !CONFIG_IDF_TARGET_ESP32P4 +#endif //#if !CONFIG_IDF_TARGET_ESP32P4 && ! CONFIG_IDF_TARGET_ESP32C5 #if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED #include "hal/rtc_io_ll.h" #endif diff --git a/components/hal/include/hal/sha_types.h b/components/hal/include/hal/sha_types.h index bcc8cc1e44..921660e594 100644 --- a/components/hal/include/hal/sha_types.h +++ b/components/hal/include/hal/sha_types.h @@ -21,6 +21,8 @@ #include "esp32c2/rom/sha.h" #elif CONFIG_IDF_TARGET_ESP32C6 #include "esp32c6/rom/sha.h" +#elif CONFIG_IDF_TARGET_ESP32C5 +#include "esp32c5/rom/sha.h" #elif CONFIG_IDF_TARGET_ESP32H2 #include "esp32h2/rom/sha.h" #elif CONFIG_IDF_TARGET_ESP32P4 diff --git a/components/hal/include/hal/spi_slave_hal.h b/components/hal/include/hal/spi_slave_hal.h index 30b8f2fbc2..e8807c84a2 100644 --- a/components/hal/include/hal/spi_slave_hal.h +++ b/components/hal/include/hal/spi_slave_hal.h @@ -28,7 +28,9 @@ #include "esp_types.h" #include "soc/soc_caps.h" #include "hal/dma_types.h" +#if SOC_GDMA_SUPPORTED #include "soc/gdma_channel.h" +#endif #if SOC_GPSPI_SUPPORTED #include "hal/spi_ll.h" #endif diff --git a/components/soc/esp32c5/include/modem/modem_lpcon_reg.h b/components/soc/esp32c5/include/modem/modem_lpcon_reg.h new file mode 100644 index 0000000000..75830a7f71 --- /dev/null +++ b/components/soc/esp32c5/include/modem/modem_lpcon_reg.h @@ -0,0 +1,359 @@ +/* + * SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef _SOC_MODEM_LPCON_REG_H_ +#define _SOC_MODEM_LPCON_REG_H_ + + +#ifdef __cplusplus +extern "C" { +#endif + +#include "modem/reg_base.h" + +#define MODEM_LPCON_TEST_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x0) +/* MODEM_LPCON_CLK_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_EN (BIT(0)) +#define MODEM_LPCON_CLK_EN_M (BIT(0)) +#define MODEM_LPCON_CLK_EN_V 0x1 +#define MODEM_LPCON_CLK_EN_S 0 + +#define MODEM_LPCON_LP_TIMER_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x4) +/* MODEM_LPCON_CLK_LP_TIMER_DIV_NUM : R/W ;bitpos:[15:4] ;default: 12'h0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_LP_TIMER_DIV_NUM 0x00000FFF +#define MODEM_LPCON_CLK_LP_TIMER_DIV_NUM_M ((MODEM_LPCON_CLK_LP_TIMER_DIV_NUM_V)<<(MODEM_LPCON_CLK_LP_TIMER_DIV_NUM_S)) +#define MODEM_LPCON_CLK_LP_TIMER_DIV_NUM_V 0xFFF +#define MODEM_LPCON_CLK_LP_TIMER_DIV_NUM_S 4 +/* MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K (BIT(3)) +#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K_M (BIT(3)) +#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K_V 0x1 +#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K_S 3 +/* MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL (BIT(2)) +#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL_M (BIT(2)) +#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL_V 0x1 +#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL_S 2 +/* MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST (BIT(1)) +#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST_M (BIT(1)) +#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST_V 0x1 +#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST_S 1 +/* MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW (BIT(0)) +#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW_M (BIT(0)) +#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW_V 0x1 +#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW_S 0 + +#define MODEM_LPCON_COEX_LP_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x8) +/* MODEM_LPCON_CLK_COEX_LP_DIV_NUM : R/W ;bitpos:[15:4] ;default: 12'h0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_COEX_LP_DIV_NUM 0x00000FFF +#define MODEM_LPCON_CLK_COEX_LP_DIV_NUM_M ((MODEM_LPCON_CLK_COEX_LP_DIV_NUM_V)<<(MODEM_LPCON_CLK_COEX_LP_DIV_NUM_S)) +#define MODEM_LPCON_CLK_COEX_LP_DIV_NUM_V 0xFFF +#define MODEM_LPCON_CLK_COEX_LP_DIV_NUM_S 4 +/* MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K (BIT(3)) +#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K_M (BIT(3)) +#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K_V 0x1 +#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K_S 3 +/* MODEM_LPCON_CLK_COEX_LP_SEL_XTAL : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL (BIT(2)) +#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL_M (BIT(2)) +#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL_V 0x1 +#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL_S 2 +/* MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST (BIT(1)) +#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST_M (BIT(1)) +#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST_V 0x1 +#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST_S 1 +/* MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW (BIT(0)) +#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW_M (BIT(0)) +#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW_V 0x1 +#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW_S 0 + +#define MODEM_LPCON_WIFI_LP_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0xC) +/* MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM : R/W ;bitpos:[15:4] ;default: 12'h0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM 0x00000FFF +#define MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM_M ((MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM_V)<<(MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM_S)) +#define MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM_V 0xFFF +#define MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM_S 4 +/* MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K (BIT(3)) +#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K_M (BIT(3)) +#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K_V 0x1 +#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K_S 3 +/* MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL (BIT(2)) +#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL_M (BIT(2)) +#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL_V 0x1 +#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL_S 2 +/* MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST (BIT(1)) +#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST_M (BIT(1)) +#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST_V 0x1 +#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST_S 1 +/* MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW (BIT(0)) +#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW_M (BIT(0)) +#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW_V 0x1 +#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW_S 0 + +#define MODEM_LPCON_I2C_MST_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x10) +/* MODEM_LPCON_CLK_I2C_MST_SEL_160M : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_I2C_MST_SEL_160M (BIT(0)) +#define MODEM_LPCON_CLK_I2C_MST_SEL_160M_M (BIT(0)) +#define MODEM_LPCON_CLK_I2C_MST_SEL_160M_V 0x1 +#define MODEM_LPCON_CLK_I2C_MST_SEL_160M_S 0 + +#define MODEM_LPCON_MODEM_32K_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x14) +/* MODEM_LPCON_CLK_MODEM_32K_SEL : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_MODEM_32K_SEL 0x00000003 +#define MODEM_LPCON_CLK_MODEM_32K_SEL_M ((MODEM_LPCON_CLK_MODEM_32K_SEL_V)<<(MODEM_LPCON_CLK_MODEM_32K_SEL_S)) +#define MODEM_LPCON_CLK_MODEM_32K_SEL_V 0x3 +#define MODEM_LPCON_CLK_MODEM_32K_SEL_S 0 + +#define MODEM_LPCON_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x18) +/* MODEM_LPCON_CLK_LP_TIMER_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_LP_TIMER_EN (BIT(3)) +#define MODEM_LPCON_CLK_LP_TIMER_EN_M (BIT(3)) +#define MODEM_LPCON_CLK_LP_TIMER_EN_V 0x1 +#define MODEM_LPCON_CLK_LP_TIMER_EN_S 3 +/* MODEM_LPCON_CLK_I2C_MST_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_I2C_MST_EN (BIT(2)) +#define MODEM_LPCON_CLK_I2C_MST_EN_M (BIT(2)) +#define MODEM_LPCON_CLK_I2C_MST_EN_V 0x1 +#define MODEM_LPCON_CLK_I2C_MST_EN_S 2 +/* MODEM_LPCON_CLK_COEX_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_COEX_EN (BIT(1)) +#define MODEM_LPCON_CLK_COEX_EN_M (BIT(1)) +#define MODEM_LPCON_CLK_COEX_EN_V 0x1 +#define MODEM_LPCON_CLK_COEX_EN_S 1 +/* MODEM_LPCON_CLK_WIFIPWR_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_WIFIPWR_EN (BIT(0)) +#define MODEM_LPCON_CLK_WIFIPWR_EN_M (BIT(0)) +#define MODEM_LPCON_CLK_WIFIPWR_EN_V 0x1 +#define MODEM_LPCON_CLK_WIFIPWR_EN_S 0 + +#define MODEM_LPCON_CLK_CONF_FORCE_ON_REG (DR_REG_MODEM_LPCON_BASE + 0x1C) +/* MODEM_LPCON_CLK_FE_MEM_FO : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_FE_MEM_FO (BIT(4)) +#define MODEM_LPCON_CLK_FE_MEM_FO_M (BIT(4)) +#define MODEM_LPCON_CLK_FE_MEM_FO_V 0x1 +#define MODEM_LPCON_CLK_FE_MEM_FO_S 4 +/* MODEM_LPCON_CLK_LP_TIMER_FO : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_LP_TIMER_FO (BIT(3)) +#define MODEM_LPCON_CLK_LP_TIMER_FO_M (BIT(3)) +#define MODEM_LPCON_CLK_LP_TIMER_FO_V 0x1 +#define MODEM_LPCON_CLK_LP_TIMER_FO_S 3 +/* MODEM_LPCON_CLK_I2C_MST_FO : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_I2C_MST_FO (BIT(2)) +#define MODEM_LPCON_CLK_I2C_MST_FO_M (BIT(2)) +#define MODEM_LPCON_CLK_I2C_MST_FO_V 0x1 +#define MODEM_LPCON_CLK_I2C_MST_FO_S 2 +/* MODEM_LPCON_CLK_COEX_FO : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_COEX_FO (BIT(1)) +#define MODEM_LPCON_CLK_COEX_FO_M (BIT(1)) +#define MODEM_LPCON_CLK_COEX_FO_V 0x1 +#define MODEM_LPCON_CLK_COEX_FO_S 1 +/* MODEM_LPCON_CLK_WIFIPWR_FO : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_WIFIPWR_FO (BIT(0)) +#define MODEM_LPCON_CLK_WIFIPWR_FO_M (BIT(0)) +#define MODEM_LPCON_CLK_WIFIPWR_FO_V 0x1 +#define MODEM_LPCON_CLK_WIFIPWR_FO_S 0 + +#define MODEM_LPCON_CLK_CONF_POWER_ST_REG (DR_REG_MODEM_LPCON_BASE + 0x20) +/* MODEM_LPCON_CLK_LP_APB_ST_MAP : R/W ;bitpos:[31:28] ;default: 4'h0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_LP_APB_ST_MAP 0x0000000F +#define MODEM_LPCON_CLK_LP_APB_ST_MAP_M ((MODEM_LPCON_CLK_LP_APB_ST_MAP_V)<<(MODEM_LPCON_CLK_LP_APB_ST_MAP_S)) +#define MODEM_LPCON_CLK_LP_APB_ST_MAP_V 0xF +#define MODEM_LPCON_CLK_LP_APB_ST_MAP_S 28 +/* MODEM_LPCON_CLK_I2C_MST_ST_MAP : R/W ;bitpos:[27:24] ;default: 4'h0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_I2C_MST_ST_MAP 0x0000000F +#define MODEM_LPCON_CLK_I2C_MST_ST_MAP_M ((MODEM_LPCON_CLK_I2C_MST_ST_MAP_V)<<(MODEM_LPCON_CLK_I2C_MST_ST_MAP_S)) +#define MODEM_LPCON_CLK_I2C_MST_ST_MAP_V 0xF +#define MODEM_LPCON_CLK_I2C_MST_ST_MAP_S 24 +/* MODEM_LPCON_CLK_COEX_ST_MAP : R/W ;bitpos:[23:20] ;default: 4'h0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_COEX_ST_MAP 0x0000000F +#define MODEM_LPCON_CLK_COEX_ST_MAP_M ((MODEM_LPCON_CLK_COEX_ST_MAP_V)<<(MODEM_LPCON_CLK_COEX_ST_MAP_S)) +#define MODEM_LPCON_CLK_COEX_ST_MAP_V 0xF +#define MODEM_LPCON_CLK_COEX_ST_MAP_S 20 +/* MODEM_LPCON_CLK_WIFIPWR_ST_MAP : R/W ;bitpos:[19:16] ;default: 4'h0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_WIFIPWR_ST_MAP 0x0000000F +#define MODEM_LPCON_CLK_WIFIPWR_ST_MAP_M ((MODEM_LPCON_CLK_WIFIPWR_ST_MAP_V)<<(MODEM_LPCON_CLK_WIFIPWR_ST_MAP_S)) +#define MODEM_LPCON_CLK_WIFIPWR_ST_MAP_V 0xF +#define MODEM_LPCON_CLK_WIFIPWR_ST_MAP_S 16 + +#define MODEM_LPCON_RST_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x24) +/* MODEM_LPCON_RST_LP_TIMER : WO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_RST_LP_TIMER (BIT(3)) +#define MODEM_LPCON_RST_LP_TIMER_M (BIT(3)) +#define MODEM_LPCON_RST_LP_TIMER_V 0x1 +#define MODEM_LPCON_RST_LP_TIMER_S 3 +/* MODEM_LPCON_RST_I2C_MST : WO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_RST_I2C_MST (BIT(2)) +#define MODEM_LPCON_RST_I2C_MST_M (BIT(2)) +#define MODEM_LPCON_RST_I2C_MST_V 0x1 +#define MODEM_LPCON_RST_I2C_MST_S 2 +/* MODEM_LPCON_RST_COEX : WO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_RST_COEX (BIT(1)) +#define MODEM_LPCON_RST_COEX_M (BIT(1)) +#define MODEM_LPCON_RST_COEX_V 0x1 +#define MODEM_LPCON_RST_COEX_S 1 +/* MODEM_LPCON_RST_WIFIPWR : WO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_RST_WIFIPWR (BIT(0)) +#define MODEM_LPCON_RST_WIFIPWR_M (BIT(0)) +#define MODEM_LPCON_RST_WIFIPWR_V 0x1 +#define MODEM_LPCON_RST_WIFIPWR_S 0 + +#define MODEM_LPCON_TICK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x28) +/* MODEM_LPCON_MODEM_PWR_TICK_TARGET : R/W ;bitpos:[5:0] ;default: 6'd39 ; */ +/*description: .*/ +#define MODEM_LPCON_MODEM_PWR_TICK_TARGET 0x0000003F +#define MODEM_LPCON_MODEM_PWR_TICK_TARGET_M ((MODEM_LPCON_MODEM_PWR_TICK_TARGET_V)<<(MODEM_LPCON_MODEM_PWR_TICK_TARGET_S)) +#define MODEM_LPCON_MODEM_PWR_TICK_TARGET_V 0x3F +#define MODEM_LPCON_MODEM_PWR_TICK_TARGET_S 0 + +#define MODEM_LPCON_MEM_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x2C) +/* MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PD : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PD (BIT(11)) +#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PD_M (BIT(11)) +#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PD_V 0x1 +#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PD_S 11 +/* MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PU : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PU (BIT(10)) +#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PU_M (BIT(10)) +#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PU_V 0x1 +#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PU_S 10 +/* MODEM_LPCON_I2C_MST_MEM_FORCE_PD : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_I2C_MST_MEM_FORCE_PD (BIT(9)) +#define MODEM_LPCON_I2C_MST_MEM_FORCE_PD_M (BIT(9)) +#define MODEM_LPCON_I2C_MST_MEM_FORCE_PD_V 0x1 +#define MODEM_LPCON_I2C_MST_MEM_FORCE_PD_S 9 +/* MODEM_LPCON_I2C_MST_MEM_FORCE_PU : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_I2C_MST_MEM_FORCE_PU (BIT(8)) +#define MODEM_LPCON_I2C_MST_MEM_FORCE_PU_M (BIT(8)) +#define MODEM_LPCON_I2C_MST_MEM_FORCE_PU_V 0x1 +#define MODEM_LPCON_I2C_MST_MEM_FORCE_PU_S 8 +/* MODEM_LPCON_BC_MEM_FORCE_PD : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_BC_MEM_FORCE_PD (BIT(7)) +#define MODEM_LPCON_BC_MEM_FORCE_PD_M (BIT(7)) +#define MODEM_LPCON_BC_MEM_FORCE_PD_V 0x1 +#define MODEM_LPCON_BC_MEM_FORCE_PD_S 7 +/* MODEM_LPCON_BC_MEM_FORCE_PU : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_BC_MEM_FORCE_PU (BIT(6)) +#define MODEM_LPCON_BC_MEM_FORCE_PU_M (BIT(6)) +#define MODEM_LPCON_BC_MEM_FORCE_PU_V 0x1 +#define MODEM_LPCON_BC_MEM_FORCE_PU_S 6 +/* MODEM_LPCON_PBUS_MEM_FORCE_PD : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_PBUS_MEM_FORCE_PD (BIT(5)) +#define MODEM_LPCON_PBUS_MEM_FORCE_PD_M (BIT(5)) +#define MODEM_LPCON_PBUS_MEM_FORCE_PD_V 0x1 +#define MODEM_LPCON_PBUS_MEM_FORCE_PD_S 5 +/* MODEM_LPCON_PBUS_MEM_FORCE_PU : R/W ;bitpos:[4] ;default: 1'b1 ; */ +/*description: .*/ +#define MODEM_LPCON_PBUS_MEM_FORCE_PU (BIT(4)) +#define MODEM_LPCON_PBUS_MEM_FORCE_PU_M (BIT(4)) +#define MODEM_LPCON_PBUS_MEM_FORCE_PU_V 0x1 +#define MODEM_LPCON_PBUS_MEM_FORCE_PU_S 4 +/* MODEM_LPCON_AGC_MEM_FORCE_PD : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_AGC_MEM_FORCE_PD (BIT(3)) +#define MODEM_LPCON_AGC_MEM_FORCE_PD_M (BIT(3)) +#define MODEM_LPCON_AGC_MEM_FORCE_PD_V 0x1 +#define MODEM_LPCON_AGC_MEM_FORCE_PD_S 3 +/* MODEM_LPCON_AGC_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */ +/*description: .*/ +#define MODEM_LPCON_AGC_MEM_FORCE_PU (BIT(2)) +#define MODEM_LPCON_AGC_MEM_FORCE_PU_M (BIT(2)) +#define MODEM_LPCON_AGC_MEM_FORCE_PU_V 0x1 +#define MODEM_LPCON_AGC_MEM_FORCE_PU_S 2 +/* MODEM_LPCON_DC_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_DC_MEM_FORCE_PD (BIT(1)) +#define MODEM_LPCON_DC_MEM_FORCE_PD_M (BIT(1)) +#define MODEM_LPCON_DC_MEM_FORCE_PD_V 0x1 +#define MODEM_LPCON_DC_MEM_FORCE_PD_S 1 +/* MODEM_LPCON_DC_MEM_FORCE_PU : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: .*/ +#define MODEM_LPCON_DC_MEM_FORCE_PU (BIT(0)) +#define MODEM_LPCON_DC_MEM_FORCE_PU_M (BIT(0)) +#define MODEM_LPCON_DC_MEM_FORCE_PU_V 0x1 +#define MODEM_LPCON_DC_MEM_FORCE_PU_S 0 + +#define MODEM_LPCON_MEM_RF1_AUX_CTRL_REG (DR_REG_MODEM_LPCON_BASE + 0x30) +/* MODEM_LPCON_MODEM_PWR_RF1_AUX_CTRL : R/W ;bitpos:[31:0] ;default: 32'h2070 ; */ +/*description: .*/ +#define MODEM_LPCON_MODEM_PWR_RF1_AUX_CTRL 0xFFFFFFFF +#define MODEM_LPCON_MODEM_PWR_RF1_AUX_CTRL_M ((MODEM_LPCON_MODEM_PWR_RF1_AUX_CTRL_V)<<(MODEM_LPCON_MODEM_PWR_RF1_AUX_CTRL_S)) +#define MODEM_LPCON_MODEM_PWR_RF1_AUX_CTRL_V 0xFFFFFFFF +#define MODEM_LPCON_MODEM_PWR_RF1_AUX_CTRL_S 0 + +#define MODEM_LPCON_MEM_RF2_AUX_CTRL_REG (DR_REG_MODEM_LPCON_BASE + 0x34) +/* MODEM_LPCON_MODEM_PWR_RF2_AUX_CTRL : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: .*/ +#define MODEM_LPCON_MODEM_PWR_RF2_AUX_CTRL 0xFFFFFFFF +#define MODEM_LPCON_MODEM_PWR_RF2_AUX_CTRL_M ((MODEM_LPCON_MODEM_PWR_RF2_AUX_CTRL_V)<<(MODEM_LPCON_MODEM_PWR_RF2_AUX_CTRL_S)) +#define MODEM_LPCON_MODEM_PWR_RF2_AUX_CTRL_V 0xFFFFFFFF +#define MODEM_LPCON_MODEM_PWR_RF2_AUX_CTRL_S 0 + +#define MODEM_LPCON_DATE_REG (DR_REG_MODEM_LPCON_BASE + 0x38) +/* MODEM_LPCON_DATE : R/W ;bitpos:[27:0] ;default: 28'h2304240 ; */ +/*description: .*/ +#define MODEM_LPCON_DATE 0x0FFFFFFF +#define MODEM_LPCON_DATE_M ((MODEM_LPCON_DATE_V)<<(MODEM_LPCON_DATE_S)) +#define MODEM_LPCON_DATE_V 0xFFFFFFF +#define MODEM_LPCON_DATE_S 0 + + +#ifdef __cplusplus +} +#endif + + + +#endif /*_SOC_MODEM_LPCON_REG_H_ */ diff --git a/components/soc/esp32c5/include/modem/modem_lpcon_struct.h b/components/soc/esp32c5/include/modem/modem_lpcon_struct.h new file mode 100644 index 0000000000..9155a7ec31 --- /dev/null +++ b/components/soc/esp32c5/include/modem/modem_lpcon_struct.h @@ -0,0 +1,247 @@ +/* + * SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +typedef volatile struct { + union { + struct { + uint32_t clk_en : 1; + uint32_t reserved1 : 1; + uint32_t reserved2 : 30; + }; + uint32_t val; + } test_conf; + union { + struct { + uint32_t clk_lp_timer_sel_osc_slow : 1; + uint32_t clk_lp_timer_sel_osc_fast : 1; + uint32_t clk_lp_timer_sel_xtal : 1; + uint32_t clk_lp_timer_sel_xtal32k : 1; + uint32_t clk_lp_timer_div_num : 12; + uint32_t reserved16 : 16; + }; + uint32_t val; + } lp_timer_conf; + union { + struct { + uint32_t clk_coex_lp_sel_osc_slow : 1; + uint32_t clk_coex_lp_sel_osc_fast : 1; + uint32_t clk_coex_lp_sel_xtal : 1; + uint32_t clk_coex_lp_sel_xtal32k : 1; + uint32_t clk_coex_lp_div_num : 12; + uint32_t reserved16 : 16; + }; + uint32_t val; + } coex_lp_clk_conf; + union { + struct { + uint32_t clk_wifipwr_lp_sel_osc_slow: 1; + uint32_t clk_wifipwr_lp_sel_osc_fast: 1; + uint32_t clk_wifipwr_lp_sel_xtal : 1; + uint32_t clk_wifipwr_lp_sel_xtal32k: 1; + uint32_t clk_wifipwr_lp_div_num : 12; + uint32_t reserved16 : 16; + }; + uint32_t val; + } wifi_lp_clk_conf; + union { + struct { + uint32_t clk_i2c_mst_sel_160m : 1; + uint32_t reserved1 : 31; + }; + uint32_t val; + } i2c_mst_clk_conf; + union { + struct { + uint32_t clk_modem_32k_sel : 2; + uint32_t reserved2 : 30; + }; + uint32_t val; + } modem_32k_clk_conf; + union { + struct { + uint32_t clk_wifipwr_en : 1; + uint32_t clk_coex_en : 1; + uint32_t clk_i2c_mst_en : 1; + uint32_t clk_lp_timer_en : 1; + uint32_t reserved4 : 1; + uint32_t reserved5 : 1; + uint32_t reserved6 : 1; + uint32_t reserved7 : 1; + uint32_t reserved8 : 1; + uint32_t reserved9 : 1; + uint32_t reserved10 : 1; + uint32_t reserved11 : 1; + uint32_t reserved12 : 1; + uint32_t reserved13 : 1; + uint32_t reserved14 : 1; + uint32_t reserved15 : 1; + uint32_t reserved16 : 1; + uint32_t reserved17 : 1; + uint32_t reserved18 : 1; + uint32_t reserved19 : 1; + uint32_t reserved20 : 1; + uint32_t reserved21 : 1; + uint32_t reserved22 : 1; + uint32_t reserved23 : 1; + uint32_t reserved24 : 1; + uint32_t reserved25 : 1; + uint32_t reserved26 : 1; + uint32_t reserved27 : 1; + uint32_t reserved28 : 1; + uint32_t reserved29 : 1; + uint32_t reserved30 : 1; + uint32_t reserved31 : 1; + }; + uint32_t val; + } clk_conf; + union { + struct { + uint32_t clk_wifipwr_fo : 1; + uint32_t clk_coex_fo : 1; + uint32_t clk_i2c_mst_fo : 1; + uint32_t clk_lp_timer_fo : 1; + uint32_t clk_fe_mem_fo : 1; + uint32_t reserved5 : 1; + uint32_t reserved6 : 1; + uint32_t reserved7 : 1; + uint32_t reserved8 : 1; + uint32_t reserved9 : 1; + uint32_t reserved10 : 1; + uint32_t reserved11 : 1; + uint32_t reserved12 : 1; + uint32_t reserved13 : 1; + uint32_t reserved14 : 1; + uint32_t reserved15 : 1; + uint32_t reserved16 : 1; + uint32_t reserved17 : 1; + uint32_t reserved18 : 1; + uint32_t reserved19 : 1; + uint32_t reserved20 : 1; + uint32_t reserved21 : 1; + uint32_t reserved22 : 1; + uint32_t reserved23 : 1; + uint32_t reserved24 : 1; + uint32_t reserved25 : 1; + uint32_t reserved26 : 1; + uint32_t reserved27 : 1; + uint32_t reserved28 : 1; + uint32_t reserved29 : 1; + uint32_t reserved30 : 1; + uint32_t reserved31 : 1; + }; + uint32_t val; + } clk_conf_force_on; + union { + struct { + uint32_t reserved0 : 16; + uint32_t clk_wifipwr_st_map : 4; + uint32_t clk_coex_st_map : 4; + uint32_t clk_i2c_mst_st_map : 4; + uint32_t clk_lp_apb_st_map : 4; + }; + uint32_t val; + } clk_conf_power_st; + union { + struct { + uint32_t rst_wifipwr : 1; + uint32_t rst_coex : 1; + uint32_t rst_i2c_mst : 1; + uint32_t rst_lp_timer : 1; + uint32_t reserved4 : 1; + uint32_t reserved5 : 1; + uint32_t reserved6 : 1; + uint32_t reserved7 : 1; + uint32_t reserved8 : 1; + uint32_t reserved9 : 1; + uint32_t reserved10 : 1; + uint32_t reserved11 : 1; + uint32_t reserved12 : 1; + uint32_t reserved13 : 1; + uint32_t reserved14 : 1; + uint32_t reserved15 : 1; + uint32_t reserved16 : 1; + uint32_t reserved17 : 1; + uint32_t reserved18 : 1; + uint32_t reserved19 : 1; + uint32_t reserved20 : 1; + uint32_t reserved21 : 1; + uint32_t reserved22 : 1; + uint32_t reserved23 : 1; + uint32_t reserved24 : 1; + uint32_t reserved25 : 1; + uint32_t reserved26 : 1; + uint32_t reserved27 : 1; + uint32_t reserved28 : 1; + uint32_t reserved29 : 1; + uint32_t reserved30 : 1; + uint32_t reserved31 : 1; + }; + uint32_t val; + } rst_conf; + union { + struct { + uint32_t modem_pwr_tick_target : 6; + uint32_t reserved6 : 26; + }; + uint32_t val; + } tick_conf; + union { + struct { + uint32_t dc_mem_force_pu : 1; + uint32_t dc_mem_force_pd : 1; + uint32_t agc_mem_force_pu : 1; + uint32_t agc_mem_force_pd : 1; + uint32_t pbus_mem_force_pu : 1; + uint32_t pbus_mem_force_pd : 1; + uint32_t bc_mem_force_pu : 1; + uint32_t bc_mem_force_pd : 1; + uint32_t i2c_mst_mem_force_pu : 1; + uint32_t i2c_mst_mem_force_pd : 1; + uint32_t chan_freq_mem_force_pu : 1; + uint32_t chan_freq_mem_force_pd : 1; + uint32_t reserved12 : 8; + uint32_t reserved20 : 1; + uint32_t reserved21 : 1; + uint32_t reserved22 : 1; + uint32_t reserved23 : 1; + uint32_t reserved24 : 1; + uint32_t reserved25 : 1; + uint32_t reserved26 : 1; + uint32_t reserved27 : 1; + uint32_t reserved28 : 1; + uint32_t reserved29 : 1; + uint32_t reserved30 : 1; + uint32_t reserved31 : 1; + }; + uint32_t val; + } mem_conf; + uint32_t mem_rf1_aux_ctrl; + uint32_t mem_rf2_aux_ctrl; + union { + struct { + uint32_t date : 28; + uint32_t reserved28 : 4; + }; + uint32_t val; + } date; +} modem_lpcon_dev_t; + +extern modem_lpcon_dev_t MODEM_LPCON; + +#ifndef __cplusplus +_Static_assert(sizeof(modem_lpcon_dev_t) == 0x3c, "Invalid size of modem_lpcon_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/modem/modem_syscon_reg.h b/components/soc/esp32c5/include/modem/modem_syscon_reg.h new file mode 100644 index 0000000000..e150c13f2e --- /dev/null +++ b/components/soc/esp32c5/include/modem/modem_syscon_reg.h @@ -0,0 +1,517 @@ +/* + * SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef _SOC_MODEM_SYSCON_REG_H_ +#define _SOC_MODEM_SYSCON_REG_H_ + + +#ifdef __cplusplus +extern "C" { +#endif + +#include "reg_base.h" + +#define MODEM_SYSCON_TEST_CONF_REG (DR_REG_MODEM_SYSCON_BASE + 0x0) +/* MODEM_SYSCON_MODEM_ANT_FORCE_SEL_WIFI : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_MODEM_ANT_FORCE_SEL_WIFI (BIT(2)) +#define MODEM_SYSCON_MODEM_ANT_FORCE_SEL_WIFI_M (BIT(2)) +#define MODEM_SYSCON_MODEM_ANT_FORCE_SEL_WIFI_V 0x1 +#define MODEM_SYSCON_MODEM_ANT_FORCE_SEL_WIFI_S 2 +/* MODEM_SYSCON_MODEM_ANT_FORCE_SEL_BT : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_MODEM_ANT_FORCE_SEL_BT (BIT(1)) +#define MODEM_SYSCON_MODEM_ANT_FORCE_SEL_BT_M (BIT(1)) +#define MODEM_SYSCON_MODEM_ANT_FORCE_SEL_BT_V 0x1 +#define MODEM_SYSCON_MODEM_ANT_FORCE_SEL_BT_S 1 +/* MODEM_SYSCON_CLK_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_EN (BIT(0)) +#define MODEM_SYSCON_CLK_EN_M (BIT(0)) +#define MODEM_SYSCON_CLK_EN_V 0x1 +#define MODEM_SYSCON_CLK_EN_S 0 + +#define MODEM_SYSCON_CLK_CONF_REG (DR_REG_MODEM_SYSCON_BASE + 0x4) +/* MODEM_SYSCON_CLK_DATA_DUMP_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_DATA_DUMP_EN (BIT(31)) +#define MODEM_SYSCON_CLK_DATA_DUMP_EN_M (BIT(31)) +#define MODEM_SYSCON_CLK_DATA_DUMP_EN_V 0x1 +#define MODEM_SYSCON_CLK_DATA_DUMP_EN_S 31 +/* MODEM_SYSCON_CLK_BLE_TIMER_EN : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_BLE_TIMER_EN (BIT(30)) +#define MODEM_SYSCON_CLK_BLE_TIMER_EN_M (BIT(30)) +#define MODEM_SYSCON_CLK_BLE_TIMER_EN_V 0x1 +#define MODEM_SYSCON_CLK_BLE_TIMER_EN_S 30 +/* MODEM_SYSCON_CLK_MODEM_SEC_EN : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_MODEM_SEC_EN (BIT(29)) +#define MODEM_SYSCON_CLK_MODEM_SEC_EN_M (BIT(29)) +#define MODEM_SYSCON_CLK_MODEM_SEC_EN_V 0x1 +#define MODEM_SYSCON_CLK_MODEM_SEC_EN_S 29 +/* MODEM_SYSCON_CLK_MODEM_SEC_APB_EN : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_MODEM_SEC_APB_EN (BIT(28)) +#define MODEM_SYSCON_CLK_MODEM_SEC_APB_EN_M (BIT(28)) +#define MODEM_SYSCON_CLK_MODEM_SEC_APB_EN_V 0x1 +#define MODEM_SYSCON_CLK_MODEM_SEC_APB_EN_S 28 +/* MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN (BIT(27)) +#define MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN_M (BIT(27)) +#define MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN_V 0x1 +#define MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN_S 27 +/* MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN (BIT(26)) +#define MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN_M (BIT(26)) +#define MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN_V 0x1 +#define MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN_S 26 +/* MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN (BIT(25)) +#define MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN_M (BIT(25)) +#define MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN_V 0x1 +#define MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN_S 25 +/* MODEM_SYSCON_CLK_ZBMAC_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_ZBMAC_EN (BIT(24)) +#define MODEM_SYSCON_CLK_ZBMAC_EN_M (BIT(24)) +#define MODEM_SYSCON_CLK_ZBMAC_EN_V 0x1 +#define MODEM_SYSCON_CLK_ZBMAC_EN_S 24 +/* MODEM_SYSCON_CLK_ZB_APB_EN : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_ZB_APB_EN (BIT(23)) +#define MODEM_SYSCON_CLK_ZB_APB_EN_M (BIT(23)) +#define MODEM_SYSCON_CLK_ZB_APB_EN_V 0x1 +#define MODEM_SYSCON_CLK_ZB_APB_EN_S 23 +/* MODEM_SYSCON_CLK_ETM_EN : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_ETM_EN (BIT(22)) +#define MODEM_SYSCON_CLK_ETM_EN_M (BIT(22)) +#define MODEM_SYSCON_CLK_ETM_EN_V 0x1 +#define MODEM_SYSCON_CLK_ETM_EN_S 22 +/* MODEM_SYSCON_CLK_DATA_DUMP_MUX : R/W ;bitpos:[21] ;default: 1'b1 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_DATA_DUMP_MUX (BIT(21)) +#define MODEM_SYSCON_CLK_DATA_DUMP_MUX_M (BIT(21)) +#define MODEM_SYSCON_CLK_DATA_DUMP_MUX_V 0x1 +#define MODEM_SYSCON_CLK_DATA_DUMP_MUX_S 21 + +#define MODEM_SYSCON_CLK_CONF_FORCE_ON_REG (DR_REG_MODEM_SYSCON_BASE + 0x8) +/* MODEM_SYSCON_CLK_DATA_DUMP_FO : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_DATA_DUMP_FO (BIT(31)) +#define MODEM_SYSCON_CLK_DATA_DUMP_FO_M (BIT(31)) +#define MODEM_SYSCON_CLK_DATA_DUMP_FO_V 0x1 +#define MODEM_SYSCON_CLK_DATA_DUMP_FO_S 31 +/* MODEM_SYSCON_CLK_BLE_TIMER_FO : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_BLE_TIMER_FO (BIT(30)) +#define MODEM_SYSCON_CLK_BLE_TIMER_FO_M (BIT(30)) +#define MODEM_SYSCON_CLK_BLE_TIMER_FO_V 0x1 +#define MODEM_SYSCON_CLK_BLE_TIMER_FO_S 30 +/* MODEM_SYSCON_CLK_MODEM_SEC_FO : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_MODEM_SEC_FO (BIT(29)) +#define MODEM_SYSCON_CLK_MODEM_SEC_FO_M (BIT(29)) +#define MODEM_SYSCON_CLK_MODEM_SEC_FO_V 0x1 +#define MODEM_SYSCON_CLK_MODEM_SEC_FO_S 29 +/* MODEM_SYSCON_CLK_ETM_FO : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_ETM_FO (BIT(28)) +#define MODEM_SYSCON_CLK_ETM_FO_M (BIT(28)) +#define MODEM_SYSCON_CLK_ETM_FO_V 0x1 +#define MODEM_SYSCON_CLK_ETM_FO_S 28 +/* MODEM_SYSCON_CLK_ZBMAC_APB_FO : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_ZBMAC_APB_FO (BIT(9)) +#define MODEM_SYSCON_CLK_ZBMAC_APB_FO_M (BIT(9)) +#define MODEM_SYSCON_CLK_ZBMAC_APB_FO_V 0x1 +#define MODEM_SYSCON_CLK_ZBMAC_APB_FO_S 9 +/* MODEM_SYSCON_CLK_ZBMAC_FO : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_ZBMAC_FO (BIT(8)) +#define MODEM_SYSCON_CLK_ZBMAC_FO_M (BIT(8)) +#define MODEM_SYSCON_CLK_ZBMAC_FO_V 0x1 +#define MODEM_SYSCON_CLK_ZBMAC_FO_S 8 +/* MODEM_SYSCON_CLK_BT_APB_FO : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_BT_APB_FO (BIT(7)) +#define MODEM_SYSCON_CLK_BT_APB_FO_M (BIT(7)) +#define MODEM_SYSCON_CLK_BT_APB_FO_V 0x1 +#define MODEM_SYSCON_CLK_BT_APB_FO_S 7 +/* MODEM_SYSCON_CLK_BTMAC_FO : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_BTMAC_FO (BIT(6)) +#define MODEM_SYSCON_CLK_BTMAC_FO_M (BIT(6)) +#define MODEM_SYSCON_CLK_BTMAC_FO_V 0x1 +#define MODEM_SYSCON_CLK_BTMAC_FO_S 6 +/* MODEM_SYSCON_CLK_BTBB_FO : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_BTBB_FO (BIT(5)) +#define MODEM_SYSCON_CLK_BTBB_FO_M (BIT(5)) +#define MODEM_SYSCON_CLK_BTBB_FO_V 0x1 +#define MODEM_SYSCON_CLK_BTBB_FO_S 5 +/* MODEM_SYSCON_CLK_FE_APB_FO : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_FE_APB_FO (BIT(4)) +#define MODEM_SYSCON_CLK_FE_APB_FO_M (BIT(4)) +#define MODEM_SYSCON_CLK_FE_APB_FO_V 0x1 +#define MODEM_SYSCON_CLK_FE_APB_FO_S 4 +/* MODEM_SYSCON_CLK_FE_FO : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_FE_FO (BIT(3)) +#define MODEM_SYSCON_CLK_FE_FO_M (BIT(3)) +#define MODEM_SYSCON_CLK_FE_FO_V 0x1 +#define MODEM_SYSCON_CLK_FE_FO_S 3 +/* MODEM_SYSCON_CLK_WIFI_APB_FO : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_WIFI_APB_FO (BIT(2)) +#define MODEM_SYSCON_CLK_WIFI_APB_FO_M (BIT(2)) +#define MODEM_SYSCON_CLK_WIFI_APB_FO_V 0x1 +#define MODEM_SYSCON_CLK_WIFI_APB_FO_S 2 +/* MODEM_SYSCON_CLK_WIFIMAC_FO : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_WIFIMAC_FO (BIT(1)) +#define MODEM_SYSCON_CLK_WIFIMAC_FO_M (BIT(1)) +#define MODEM_SYSCON_CLK_WIFIMAC_FO_V 0x1 +#define MODEM_SYSCON_CLK_WIFIMAC_FO_S 1 +/* MODEM_SYSCON_CLK_WIFIBB_FO : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_WIFIBB_FO (BIT(0)) +#define MODEM_SYSCON_CLK_WIFIBB_FO_M (BIT(0)) +#define MODEM_SYSCON_CLK_WIFIBB_FO_V 0x1 +#define MODEM_SYSCON_CLK_WIFIBB_FO_S 0 + +#define MODEM_SYSCON_CLK_CONF_POWER_ST_REG (DR_REG_MODEM_SYSCON_BASE + 0xC) +/* MODEM_SYSCON_CLK_MODEM_APB_ST_MAP : R/W ;bitpos:[31:28] ;default: 4'h0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_MODEM_APB_ST_MAP 0x0000000F +#define MODEM_SYSCON_CLK_MODEM_APB_ST_MAP_M ((MODEM_SYSCON_CLK_MODEM_APB_ST_MAP_V)<<(MODEM_SYSCON_CLK_MODEM_APB_ST_MAP_S)) +#define MODEM_SYSCON_CLK_MODEM_APB_ST_MAP_V 0xF +#define MODEM_SYSCON_CLK_MODEM_APB_ST_MAP_S 28 +/* MODEM_SYSCON_CLK_MODEM_PERI_ST_MAP : R/W ;bitpos:[27:24] ;default: 4'h0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_MODEM_PERI_ST_MAP 0x0000000F +#define MODEM_SYSCON_CLK_MODEM_PERI_ST_MAP_M ((MODEM_SYSCON_CLK_MODEM_PERI_ST_MAP_V)<<(MODEM_SYSCON_CLK_MODEM_PERI_ST_MAP_S)) +#define MODEM_SYSCON_CLK_MODEM_PERI_ST_MAP_V 0xF +#define MODEM_SYSCON_CLK_MODEM_PERI_ST_MAP_S 24 +/* MODEM_SYSCON_CLK_WIFI_ST_MAP : R/W ;bitpos:[23:20] ;default: 4'h0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_WIFI_ST_MAP 0x0000000F +#define MODEM_SYSCON_CLK_WIFI_ST_MAP_M ((MODEM_SYSCON_CLK_WIFI_ST_MAP_V)<<(MODEM_SYSCON_CLK_WIFI_ST_MAP_S)) +#define MODEM_SYSCON_CLK_WIFI_ST_MAP_V 0xF +#define MODEM_SYSCON_CLK_WIFI_ST_MAP_S 20 +/* MODEM_SYSCON_CLK_BT_ST_MAP : R/W ;bitpos:[19:16] ;default: 4'h0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_BT_ST_MAP 0x0000000F +#define MODEM_SYSCON_CLK_BT_ST_MAP_M ((MODEM_SYSCON_CLK_BT_ST_MAP_V)<<(MODEM_SYSCON_CLK_BT_ST_MAP_S)) +#define MODEM_SYSCON_CLK_BT_ST_MAP_V 0xF +#define MODEM_SYSCON_CLK_BT_ST_MAP_S 16 +/* MODEM_SYSCON_CLK_FE_ST_MAP : R/W ;bitpos:[15:12] ;default: 4'h0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_FE_ST_MAP 0x0000000F +#define MODEM_SYSCON_CLK_FE_ST_MAP_M ((MODEM_SYSCON_CLK_FE_ST_MAP_V)<<(MODEM_SYSCON_CLK_FE_ST_MAP_S)) +#define MODEM_SYSCON_CLK_FE_ST_MAP_V 0xF +#define MODEM_SYSCON_CLK_FE_ST_MAP_S 12 +/* MODEM_SYSCON_CLK_ZB_ST_MAP : R/W ;bitpos:[11:8] ;default: 4'h0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_ZB_ST_MAP 0x0000000F +#define MODEM_SYSCON_CLK_ZB_ST_MAP_M ((MODEM_SYSCON_CLK_ZB_ST_MAP_V)<<(MODEM_SYSCON_CLK_ZB_ST_MAP_S)) +#define MODEM_SYSCON_CLK_ZB_ST_MAP_V 0xF +#define MODEM_SYSCON_CLK_ZB_ST_MAP_S 8 + +#define MODEM_SYSCON_MODEM_RST_CONF_REG (DR_REG_MODEM_SYSCON_BASE + 0x10) +/* MODEM_SYSCON_RST_DATA_DUMP : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_RST_DATA_DUMP (BIT(31)) +#define MODEM_SYSCON_RST_DATA_DUMP_M (BIT(31)) +#define MODEM_SYSCON_RST_DATA_DUMP_V 0x1 +#define MODEM_SYSCON_RST_DATA_DUMP_S 31 +/* MODEM_SYSCON_RST_BLE_TIMER : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_RST_BLE_TIMER (BIT(30)) +#define MODEM_SYSCON_RST_BLE_TIMER_M (BIT(30)) +#define MODEM_SYSCON_RST_BLE_TIMER_V 0x1 +#define MODEM_SYSCON_RST_BLE_TIMER_S 30 +/* MODEM_SYSCON_RST_MODEM_SEC : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_RST_MODEM_SEC (BIT(29)) +#define MODEM_SYSCON_RST_MODEM_SEC_M (BIT(29)) +#define MODEM_SYSCON_RST_MODEM_SEC_V 0x1 +#define MODEM_SYSCON_RST_MODEM_SEC_S 29 +/* MODEM_SYSCON_RST_MODEM_BAH : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_RST_MODEM_BAH (BIT(27)) +#define MODEM_SYSCON_RST_MODEM_BAH_M (BIT(27)) +#define MODEM_SYSCON_RST_MODEM_BAH_V 0x1 +#define MODEM_SYSCON_RST_MODEM_BAH_S 27 +/* MODEM_SYSCON_RST_MODEM_CCM : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_RST_MODEM_CCM (BIT(26)) +#define MODEM_SYSCON_RST_MODEM_CCM_M (BIT(26)) +#define MODEM_SYSCON_RST_MODEM_CCM_V 0x1 +#define MODEM_SYSCON_RST_MODEM_CCM_S 26 +/* MODEM_SYSCON_RST_MODEM_ECB : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_RST_MODEM_ECB (BIT(25)) +#define MODEM_SYSCON_RST_MODEM_ECB_M (BIT(25)) +#define MODEM_SYSCON_RST_MODEM_ECB_V 0x1 +#define MODEM_SYSCON_RST_MODEM_ECB_S 25 +/* MODEM_SYSCON_RST_ZBMAC : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_RST_ZBMAC (BIT(24)) +#define MODEM_SYSCON_RST_ZBMAC_M (BIT(24)) +#define MODEM_SYSCON_RST_ZBMAC_V 0x1 +#define MODEM_SYSCON_RST_ZBMAC_S 24 +/* MODEM_SYSCON_RST_ETM : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_RST_ETM (BIT(22)) +#define MODEM_SYSCON_RST_ETM_M (BIT(22)) +#define MODEM_SYSCON_RST_ETM_V 0x1 +#define MODEM_SYSCON_RST_ETM_S 22 +/* MODEM_SYSCON_RST_BTBB : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_RST_BTBB (BIT(18)) +#define MODEM_SYSCON_RST_BTBB_M (BIT(18)) +#define MODEM_SYSCON_RST_BTBB_V 0x1 +#define MODEM_SYSCON_RST_BTBB_S 18 +/* MODEM_SYSCON_RST_BTBB_APB : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_RST_BTBB_APB (BIT(17)) +#define MODEM_SYSCON_RST_BTBB_APB_M (BIT(17)) +#define MODEM_SYSCON_RST_BTBB_APB_V 0x1 +#define MODEM_SYSCON_RST_BTBB_APB_S 17 +/* MODEM_SYSCON_RST_BTMAC : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_RST_BTMAC (BIT(16)) +#define MODEM_SYSCON_RST_BTMAC_M (BIT(16)) +#define MODEM_SYSCON_RST_BTMAC_V 0x1 +#define MODEM_SYSCON_RST_BTMAC_S 16 +/* MODEM_SYSCON_RST_BTMAC_APB : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_RST_BTMAC_APB (BIT(15)) +#define MODEM_SYSCON_RST_BTMAC_APB_M (BIT(15)) +#define MODEM_SYSCON_RST_BTMAC_APB_V 0x1 +#define MODEM_SYSCON_RST_BTMAC_APB_S 15 +/* MODEM_SYSCON_RST_FE : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_RST_FE (BIT(14)) +#define MODEM_SYSCON_RST_FE_M (BIT(14)) +#define MODEM_SYSCON_RST_FE_V 0x1 +#define MODEM_SYSCON_RST_FE_S 14 +/* MODEM_SYSCON_RST_FE_AHB : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_RST_FE_AHB (BIT(13)) +#define MODEM_SYSCON_RST_FE_AHB_M (BIT(13)) +#define MODEM_SYSCON_RST_FE_AHB_V 0x1 +#define MODEM_SYSCON_RST_FE_AHB_S 13 +/* MODEM_SYSCON_RST_FE_ADC : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_RST_FE_ADC (BIT(12)) +#define MODEM_SYSCON_RST_FE_ADC_M (BIT(12)) +#define MODEM_SYSCON_RST_FE_ADC_V 0x1 +#define MODEM_SYSCON_RST_FE_ADC_S 12 +/* MODEM_SYSCON_RST_FE_DAC : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_RST_FE_DAC (BIT(11)) +#define MODEM_SYSCON_RST_FE_DAC_M (BIT(11)) +#define MODEM_SYSCON_RST_FE_DAC_V 0x1 +#define MODEM_SYSCON_RST_FE_DAC_S 11 +/* MODEM_SYSCON_RST_FE_PWDET_ADC : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_RST_FE_PWDET_ADC (BIT(10)) +#define MODEM_SYSCON_RST_FE_PWDET_ADC_M (BIT(10)) +#define MODEM_SYSCON_RST_FE_PWDET_ADC_V 0x1 +#define MODEM_SYSCON_RST_FE_PWDET_ADC_S 10 +/* MODEM_SYSCON_RST_WIFIMAC : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_RST_WIFIMAC (BIT(9)) +#define MODEM_SYSCON_RST_WIFIMAC_M (BIT(9)) +#define MODEM_SYSCON_RST_WIFIMAC_V 0x1 +#define MODEM_SYSCON_RST_WIFIMAC_S 9 +/* MODEM_SYSCON_RST_WIFIBB : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_RST_WIFIBB (BIT(8)) +#define MODEM_SYSCON_RST_WIFIBB_M (BIT(8)) +#define MODEM_SYSCON_RST_WIFIBB_V 0x1 +#define MODEM_SYSCON_RST_WIFIBB_S 8 + +#define MODEM_SYSCON_CLK_CONF1_REG (DR_REG_MODEM_SYSCON_BASE + 0x14) +/* MODEM_SYSCON_CLK_FE_DAC_EN : R/W ;bitpos:[21] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_FE_DAC_EN (BIT(21)) +#define MODEM_SYSCON_CLK_FE_DAC_EN_M (BIT(21)) +#define MODEM_SYSCON_CLK_FE_DAC_EN_V 0x1 +#define MODEM_SYSCON_CLK_FE_DAC_EN_S 21 +/* MODEM_SYSCON_CLK_FE_ADC_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_FE_ADC_EN (BIT(20)) +#define MODEM_SYSCON_CLK_FE_ADC_EN_M (BIT(20)) +#define MODEM_SYSCON_CLK_FE_ADC_EN_V 0x1 +#define MODEM_SYSCON_CLK_FE_ADC_EN_S 20 +/* MODEM_SYSCON_CLK_FE_PWDET_ADC_EN : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_FE_PWDET_ADC_EN (BIT(19)) +#define MODEM_SYSCON_CLK_FE_PWDET_ADC_EN_M (BIT(19)) +#define MODEM_SYSCON_CLK_FE_PWDET_ADC_EN_V 0x1 +#define MODEM_SYSCON_CLK_FE_PWDET_ADC_EN_S 19 +/* MODEM_SYSCON_CLK_BTMAC_EN : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_BTMAC_EN (BIT(18)) +#define MODEM_SYSCON_CLK_BTMAC_EN_M (BIT(18)) +#define MODEM_SYSCON_CLK_BTMAC_EN_V 0x1 +#define MODEM_SYSCON_CLK_BTMAC_EN_S 18 +/* MODEM_SYSCON_CLK_BTBB_EN : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_BTBB_EN (BIT(17)) +#define MODEM_SYSCON_CLK_BTBB_EN_M (BIT(17)) +#define MODEM_SYSCON_CLK_BTBB_EN_V 0x1 +#define MODEM_SYSCON_CLK_BTBB_EN_S 17 +/* MODEM_SYSCON_CLK_BT_APB_EN : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_BT_APB_EN (BIT(16)) +#define MODEM_SYSCON_CLK_BT_APB_EN_M (BIT(16)) +#define MODEM_SYSCON_CLK_BT_APB_EN_V 0x1 +#define MODEM_SYSCON_CLK_BT_APB_EN_S 16 +/* MODEM_SYSCON_CLK_FE_APB_EN : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_FE_APB_EN (BIT(15)) +#define MODEM_SYSCON_CLK_FE_APB_EN_M (BIT(15)) +#define MODEM_SYSCON_CLK_FE_APB_EN_V 0x1 +#define MODEM_SYSCON_CLK_FE_APB_EN_S 15 +/* MODEM_SYSCON_CLK_FE_160M_EN : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_FE_160M_EN (BIT(14)) +#define MODEM_SYSCON_CLK_FE_160M_EN_M (BIT(14)) +#define MODEM_SYSCON_CLK_FE_160M_EN_V 0x1 +#define MODEM_SYSCON_CLK_FE_160M_EN_S 14 +/* MODEM_SYSCON_CLK_FE_80M_EN : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_FE_80M_EN (BIT(13)) +#define MODEM_SYSCON_CLK_FE_80M_EN_M (BIT(13)) +#define MODEM_SYSCON_CLK_FE_80M_EN_V 0x1 +#define MODEM_SYSCON_CLK_FE_80M_EN_S 13 +/* MODEM_SYSCON_CLK_FE_40M_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_FE_40M_EN (BIT(12)) +#define MODEM_SYSCON_CLK_FE_40M_EN_M (BIT(12)) +#define MODEM_SYSCON_CLK_FE_40M_EN_V 0x1 +#define MODEM_SYSCON_CLK_FE_40M_EN_S 12 +/* MODEM_SYSCON_CLK_FE_20M_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_FE_20M_EN (BIT(11)) +#define MODEM_SYSCON_CLK_FE_20M_EN_M (BIT(11)) +#define MODEM_SYSCON_CLK_FE_20M_EN_V 0x1 +#define MODEM_SYSCON_CLK_FE_20M_EN_S 11 +/* MODEM_SYSCON_CLK_WIFI_APB_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_WIFI_APB_EN (BIT(10)) +#define MODEM_SYSCON_CLK_WIFI_APB_EN_M (BIT(10)) +#define MODEM_SYSCON_CLK_WIFI_APB_EN_V 0x1 +#define MODEM_SYSCON_CLK_WIFI_APB_EN_S 10 +/* MODEM_SYSCON_CLK_WIFIMAC_EN : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_WIFIMAC_EN (BIT(9)) +#define MODEM_SYSCON_CLK_WIFIMAC_EN_M (BIT(9)) +#define MODEM_SYSCON_CLK_WIFIMAC_EN_V 0x1 +#define MODEM_SYSCON_CLK_WIFIMAC_EN_S 9 +/* MODEM_SYSCON_CLK_WIFIBB_160X1_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_WIFIBB_160X1_EN (BIT(8)) +#define MODEM_SYSCON_CLK_WIFIBB_160X1_EN_M (BIT(8)) +#define MODEM_SYSCON_CLK_WIFIBB_160X1_EN_V 0x1 +#define MODEM_SYSCON_CLK_WIFIBB_160X1_EN_S 8 +/* MODEM_SYSCON_CLK_WIFIBB_80X1_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_WIFIBB_80X1_EN (BIT(7)) +#define MODEM_SYSCON_CLK_WIFIBB_80X1_EN_M (BIT(7)) +#define MODEM_SYSCON_CLK_WIFIBB_80X1_EN_V 0x1 +#define MODEM_SYSCON_CLK_WIFIBB_80X1_EN_S 7 +/* MODEM_SYSCON_CLK_WIFIBB_40X1_EN : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_WIFIBB_40X1_EN (BIT(6)) +#define MODEM_SYSCON_CLK_WIFIBB_40X1_EN_M (BIT(6)) +#define MODEM_SYSCON_CLK_WIFIBB_40X1_EN_V 0x1 +#define MODEM_SYSCON_CLK_WIFIBB_40X1_EN_S 6 +/* MODEM_SYSCON_CLK_WIFIBB_80X_EN : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_WIFIBB_80X_EN (BIT(5)) +#define MODEM_SYSCON_CLK_WIFIBB_80X_EN_M (BIT(5)) +#define MODEM_SYSCON_CLK_WIFIBB_80X_EN_V 0x1 +#define MODEM_SYSCON_CLK_WIFIBB_80X_EN_S 5 +/* MODEM_SYSCON_CLK_WIFIBB_40X_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_WIFIBB_40X_EN (BIT(4)) +#define MODEM_SYSCON_CLK_WIFIBB_40X_EN_M (BIT(4)) +#define MODEM_SYSCON_CLK_WIFIBB_40X_EN_V 0x1 +#define MODEM_SYSCON_CLK_WIFIBB_40X_EN_S 4 +/* MODEM_SYSCON_CLK_WIFIBB_80M_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_WIFIBB_80M_EN (BIT(3)) +#define MODEM_SYSCON_CLK_WIFIBB_80M_EN_M (BIT(3)) +#define MODEM_SYSCON_CLK_WIFIBB_80M_EN_V 0x1 +#define MODEM_SYSCON_CLK_WIFIBB_80M_EN_S 3 +/* MODEM_SYSCON_CLK_WIFIBB_44M_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_WIFIBB_44M_EN (BIT(2)) +#define MODEM_SYSCON_CLK_WIFIBB_44M_EN_M (BIT(2)) +#define MODEM_SYSCON_CLK_WIFIBB_44M_EN_V 0x1 +#define MODEM_SYSCON_CLK_WIFIBB_44M_EN_S 2 +/* MODEM_SYSCON_CLK_WIFIBB_40M_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_WIFIBB_40M_EN (BIT(1)) +#define MODEM_SYSCON_CLK_WIFIBB_40M_EN_M (BIT(1)) +#define MODEM_SYSCON_CLK_WIFIBB_40M_EN_V 0x1 +#define MODEM_SYSCON_CLK_WIFIBB_40M_EN_S 1 +/* MODEM_SYSCON_CLK_WIFIBB_22M_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_WIFIBB_22M_EN (BIT(0)) +#define MODEM_SYSCON_CLK_WIFIBB_22M_EN_M (BIT(0)) +#define MODEM_SYSCON_CLK_WIFIBB_22M_EN_V 0x1 +#define MODEM_SYSCON_CLK_WIFIBB_22M_EN_S 0 + +#define MODEM_SYSCON_WIFI_BB_CFG_REG (DR_REG_MODEM_SYSCON_BASE + 0x18) +/* MODEM_SYSCON_WIFI_BB_CFG : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: .*/ +#define MODEM_SYSCON_WIFI_BB_CFG 0xFFFFFFFF +#define MODEM_SYSCON_WIFI_BB_CFG_M ((MODEM_SYSCON_WIFI_BB_CFG_V)<<(MODEM_SYSCON_WIFI_BB_CFG_S)) +#define MODEM_SYSCON_WIFI_BB_CFG_V 0xFFFFFFFF +#define MODEM_SYSCON_WIFI_BB_CFG_S 0 + +#define MODEM_SYSCON_MEM_RF1_CONF_REG (DR_REG_MODEM_SYSCON_BASE + 0x1C) +/* MODEM_SYSCON_MODEM_RF1_MEM_AUX_CTRL : R/W ;bitpos:[31:0] ;default: 32'h2070 ; */ +/*description: .*/ +#define MODEM_SYSCON_MODEM_RF1_MEM_AUX_CTRL 0xFFFFFFFF +#define MODEM_SYSCON_MODEM_RF1_MEM_AUX_CTRL_M ((MODEM_SYSCON_MODEM_RF1_MEM_AUX_CTRL_V)<<(MODEM_SYSCON_MODEM_RF1_MEM_AUX_CTRL_S)) +#define MODEM_SYSCON_MODEM_RF1_MEM_AUX_CTRL_V 0xFFFFFFFF +#define MODEM_SYSCON_MODEM_RF1_MEM_AUX_CTRL_S 0 + +#define MODEM_SYSCON_MEM_RF2_CONF_REG (DR_REG_MODEM_SYSCON_BASE + 0x20) +/* MODEM_SYSCON_MODEM_RF2_MEM_AUX_CTRL : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: .*/ +#define MODEM_SYSCON_MODEM_RF2_MEM_AUX_CTRL 0xFFFFFFFF +#define MODEM_SYSCON_MODEM_RF2_MEM_AUX_CTRL_M ((MODEM_SYSCON_MODEM_RF2_MEM_AUX_CTRL_V)<<(MODEM_SYSCON_MODEM_RF2_MEM_AUX_CTRL_S)) +#define MODEM_SYSCON_MODEM_RF2_MEM_AUX_CTRL_V 0xFFFFFFFF +#define MODEM_SYSCON_MODEM_RF2_MEM_AUX_CTRL_S 0 + +#define MODEM_SYSCON_DATE_REG (DR_REG_MODEM_SYSCON_BASE + 0x24) +/* MODEM_SYSCON_DATE : R/W ;bitpos:[27:0] ;default: 28'h2304170 ; */ +/*description: .*/ +#define MODEM_SYSCON_DATE 0x0FFFFFFF +#define MODEM_SYSCON_DATE_M ((MODEM_SYSCON_DATE_V)<<(MODEM_SYSCON_DATE_S)) +#define MODEM_SYSCON_DATE_V 0xFFFFFFF +#define MODEM_SYSCON_DATE_S 0 + + +#ifdef __cplusplus +} +#endif + + + +#endif /*_SOC_MODEM_SYSCON_REG_H_ */ diff --git a/components/soc/esp32c5/include/modem/modem_syscon_struct.h b/components/soc/esp32c5/include/modem/modem_syscon_struct.h new file mode 100644 index 0000000000..ff9ff72f25 --- /dev/null +++ b/components/soc/esp32c5/include/modem/modem_syscon_struct.h @@ -0,0 +1,164 @@ +/* + * SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +typedef volatile struct { + union { + struct { + uint32_t clk_en : 1; + uint32_t modem_ant_force_sel_bt : 1; + uint32_t modem_ant_force_sel_wifi : 1; + uint32_t reserved3 : 29; + }; + uint32_t val; + } test_conf; + union { + struct { + uint32_t reserved0 : 21; + uint32_t clk_data_dump_mux : 1; + uint32_t clk_etm_en : 1; + uint32_t clk_zb_apb_en : 1; + uint32_t clk_zbmac_en : 1; + uint32_t clk_modem_sec_ecb_en : 1; + uint32_t clk_modem_sec_ccm_en : 1; + uint32_t clk_modem_sec_bah_en : 1; + uint32_t clk_modem_sec_apb_en : 1; + uint32_t clk_modem_sec_en : 1; + uint32_t clk_ble_timer_en : 1; + uint32_t clk_data_dump_en : 1; + }; + uint32_t val; + } clk_conf; + union { + struct { + uint32_t clk_wifibb_fo : 1; + uint32_t clk_wifimac_fo : 1; + uint32_t clk_wifi_apb_fo : 1; + uint32_t clk_fe_fo : 1; + uint32_t clk_fe_apb_fo : 1; + uint32_t clk_btbb_fo : 1; + uint32_t clk_btmac_fo : 1; + uint32_t clk_bt_apb_fo : 1; + uint32_t clk_zbmac_fo : 1; + uint32_t clk_zbmac_apb_fo : 1; + uint32_t reserved10 : 13; + uint32_t reserved23 : 1; + uint32_t reserved24 : 1; + uint32_t reserved25 : 1; + uint32_t reserved26 : 1; + uint32_t reserved27 : 1; + uint32_t clk_etm_fo : 1; + uint32_t clk_modem_sec_fo : 1; + uint32_t clk_ble_timer_fo : 1; + uint32_t clk_data_dump_fo : 1; + }; + uint32_t val; + } clk_conf_force_on; + union { + struct { + uint32_t reserved0 : 8; + uint32_t clk_zb_st_map : 4; + uint32_t clk_fe_st_map : 4; + uint32_t clk_bt_st_map : 4; + uint32_t clk_wifi_st_map : 4; + uint32_t clk_modem_peri_st_map : 4; + uint32_t clk_modem_apb_st_map : 4; + }; + uint32_t val; + } clk_conf_power_st; + union { + struct { + uint32_t reserved0 : 1; + uint32_t reserved1 : 1; + uint32_t reserved2 : 1; + uint32_t reserved3 : 1; + uint32_t reserved4 : 1; + uint32_t reserved5 : 1; + uint32_t reserved6 : 1; + uint32_t reserved7 : 1; + uint32_t rst_wifibb : 1; + uint32_t rst_wifimac : 1; + uint32_t rst_fe_pwdet_adc : 1; + uint32_t rst_fe_dac : 1; + uint32_t rst_fe_adc : 1; + uint32_t rst_fe_ahb : 1; + uint32_t rst_fe : 1; + uint32_t rst_btmac_apb : 1; + uint32_t rst_btmac : 1; + uint32_t rst_btbb_apb : 1; + uint32_t rst_btbb : 1; + uint32_t reserved19 : 3; + uint32_t rst_etm : 1; + uint32_t reserved23 : 1; + uint32_t rst_zbmac : 1; + uint32_t rst_modem_ecb : 1; + uint32_t rst_modem_ccm : 1; + uint32_t rst_modem_bah : 1; + uint32_t reserved28 : 1; + uint32_t rst_modem_sec : 1; + uint32_t rst_ble_timer : 1; + uint32_t rst_data_dump : 1; + }; + uint32_t val; + } modem_rst_conf; + union { + struct { + uint32_t clk_wifibb_22m_en : 1; + uint32_t clk_wifibb_40m_en : 1; + uint32_t clk_wifibb_44m_en : 1; + uint32_t clk_wifibb_80m_en : 1; + uint32_t clk_wifibb_40x_en : 1; + uint32_t clk_wifibb_80x_en : 1; + uint32_t clk_wifibb_40x1_en : 1; + uint32_t clk_wifibb_80x1_en : 1; + uint32_t clk_wifibb_160x1_en : 1; + uint32_t clk_wifimac_en : 1; + uint32_t clk_wifi_apb_en : 1; + uint32_t clk_fe_20m_en : 1; + uint32_t clk_fe_40m_en : 1; + uint32_t clk_fe_80m_en : 1; + uint32_t clk_fe_160m_en : 1; + uint32_t clk_fe_apb_en : 1; + uint32_t clk_bt_apb_en : 1; + uint32_t clk_btbb_en : 1; + uint32_t clk_btmac_en : 1; + uint32_t clk_fe_pwdet_adc_en : 1; + uint32_t clk_fe_adc_en : 1; + uint32_t clk_fe_dac_en : 1; + uint32_t reserved22 : 1; + uint32_t reserved23 : 1; + uint32_t reserved24 : 8; + }; + uint32_t val; + } clk_conf1; + uint32_t wifi_bb_cfg; + uint32_t mem_rf1_conf; + uint32_t mem_rf2_conf; + union { + struct { + uint32_t date : 28; + uint32_t reserved28 : 4; + }; + uint32_t val; + } date; +} modem_syscon_dev_t; + +extern modem_syscon_dev_t MODEM_SYSCON; + +#ifndef __cplusplus +_Static_assert(sizeof(modem_syscon_dev_t) == 0x28, "Invalid size of modem_syscon_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/modem/reg_base.h b/components/soc/esp32c5/include/modem/reg_base.h new file mode 100644 index 0000000000..7a0254eac0 --- /dev/null +++ b/components/soc/esp32c5/include/modem/reg_base.h @@ -0,0 +1,9 @@ +/* + * SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once +#define DR_REG_MODEM_SYSCON_BASE 0x600A9800 +#define DR_REG_MODEM_LPCON_BASE 0x600AF000 diff --git a/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in index bf54e30ab7..280d500f2d 100644 --- a/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in @@ -3,22 +3,158 @@ # using gen_soc_caps_kconfig.py, do not edit manually ##################################################### +config SOC_UART_SUPPORTED + bool + default y + +config SOC_EFUSE_KEY_PURPOSE_FIELD + bool + default y + +config SOC_EFUSE_SUPPORTED + bool + default y + +config SOC_RTC_FAST_MEM_SUPPORTED + bool + default y + +config SOC_RTC_MEM_SUPPORTED + bool + default y + +config SOC_SYSTIMER_SUPPORTED + bool + default y + +config SOC_FLASH_ENC_SUPPORTED + bool + default y + +config SOC_PMU_SUPPORTED + bool + default y + +config SOC_SPI_FLASH_SUPPORTED + bool + default y + config SOC_INT_HW_NESTED_SUPPORTED bool default y +config SOC_XTAL_SUPPORT_40M + bool + default y + +config SOC_XTAL_SUPPORT_48M + bool + default y + +config SOC_ADC_PERIPH_NUM + int + default 1 + +config SOC_ADC_MAX_CHANNEL_NUM + int + default 7 + +config SOC_SHARED_IDCACHE_SUPPORTED + bool + default y + +config SOC_CACHE_FREEZE_SUPPORTED + bool + default y + config SOC_CPU_CORES_NUM int default 1 +config SOC_CPU_INTR_NUM + int + default 32 + +config SOC_CPU_HAS_FLEXIBLE_INTC + bool + default y + config SOC_INT_CLIC_SUPPORTED bool default y +config SOC_BRANCH_PREDICTOR_SUPPORTED + bool + default y + +config SOC_CPU_BREAKPOINTS_NUM + int + default 4 + +config SOC_CPU_WATCHPOINTS_NUM + int + default 4 + +config SOC_CPU_WATCHPOINT_MAX_REGION_SIZE + hex + default 0x100 + +config SOC_CPU_HAS_PMA + bool + default y + +config SOC_CPU_IDRAM_SPLIT_USING_PMP + bool + default y + config SOC_GPIO_PIN_COUNT int default 31 +config SOC_GPIO_IN_RANGE_MAX + int + default 30 + +config SOC_GPIO_OUT_RANGE_MAX + int + default 30 + +config SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP + bool + default y + +config SOC_RTCIO_PIN_COUNT + bool + default n + +config SOC_I2C_NUM + int + default 2 + +config SOC_LEDC_SUPPORT_PLL_DIV_CLOCK + bool + default y + +config SOC_LEDC_SUPPORT_XTAL_CLOCK + bool + default y + +config SOC_MMU_PERIPH_NUM + int + default 1 + +config SOC_MMU_LINEAR_ADDRESS_REGION_NUM + int + default 1 + +config SOC_MMU_DI_VADDR_SHARED + bool + default y + +config SOC_RSA_MAX_BIT_LEN + int + default 3072 + config SOC_SPI_PERIPH_NUM int default 2 @@ -27,6 +163,50 @@ config SOC_SPI_MAX_CS_NUM int default 6 +config SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED + bool + default y + +config SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED + bool + default y + +config SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED + bool + default y + +config SOC_SYSTIMER_COUNTER_NUM + int + default 2 + +config SOC_SYSTIMER_ALARM_NUM + int + default 3 + +config SOC_SYSTIMER_BIT_WIDTH_LO + int + default 32 + +config SOC_SYSTIMER_BIT_WIDTH_HI + int + default 20 + +config SOC_SYSTIMER_FIXED_DIVIDER + bool + default y + +config SOC_SYSTIMER_SUPPORT_RC_FAST + bool + default y + +config SOC_SYSTIMER_INT_LEVEL + bool + default y + +config SOC_SYSTIMER_ALARM_MISS_COMPENSATE + bool + default y + config SOC_TIMER_GROUPS int default 2 @@ -35,6 +215,18 @@ config SOC_TIMER_GROUP_TIMERS_PER_GROUP int default 1 +config SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS + int + default 3 + +config SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX + int + default 64 + +config SOC_FLASH_ENCRYPTION_XTS_AES_128 + bool + default y + config SOC_UART_NUM int default 3 @@ -46,3 +238,75 @@ config SOC_UART_HP_NUM config SOC_UART_LP_NUM int default 1 + +config SOC_UART_FIFO_LEN + int + default 128 + +config SOC_LP_UART_FIFO_LEN + int + default 16 + +config SOC_UART_SUPPORT_XTAL_CLK + bool + default y + +config SOC_PM_SUPPORT_CPU_PD + bool + default y + +config SOC_PM_SUPPORT_MODEM_PD + bool + default y + +config SOC_PM_SUPPORT_XTAL32K_PD + bool + default y + +config SOC_PM_SUPPORT_RC32K_PD + bool + default y + +config SOC_PM_SUPPORT_RC_FAST_PD + bool + default y + +config SOC_PM_SUPPORT_VDDSDIO_PD + bool + default y + +config SOC_PM_SUPPORT_TOP_PD + bool + default y + +config SOC_PM_SUPPORT_HP_AON_PD + bool + default y + +config SOC_PM_SUPPORT_RTC_PERIPH_PD + bool + default y + +config SOC_CLK_RC_FAST_SUPPORT_CALIBRATION + bool + default y + +config SOC_MODEM_CLOCK_IS_INDEPENDENT + bool + default y + +config SOC_CLK_XTAL32K_SUPPORTED + bool + default y + +config SOC_CLK_OSC_SLOW_SUPPORTED + bool + default y + +config SOC_CLK_RC32K_SUPPORTED + bool + default y + +config SOC_RCC_IS_INDEPENDENT + bool + default y diff --git a/components/soc/esp32c5/include/soc/adc_channel.h b/components/soc/esp32c5/include/soc/adc_channel.h new file mode 100644 index 0000000000..dcdfb8633b --- /dev/null +++ b/components/soc/esp32c5/include/soc/adc_channel.h @@ -0,0 +1,28 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define ADC1_GPIO0_CHANNEL 0 +#define ADC1_CHANNEL_0_GPIO_NUM 0 + +#define ADC1_GPIO1_CHANNEL 1 +#define ADC1_CHANNEL_1_GPIO_NUM 1 + +#define ADC1_GPIO2_CHANNEL 2 +#define ADC1_CHANNEL_2_GPIO_NUM 2 + +#define ADC1_GPIO3_CHANNEL 3 +#define ADC1_CHANNEL_3_GPIO_NUM 3 + +#define ADC1_GPIO4_CHANNEL 4 +#define ADC1_CHANNEL_4_GPIO_NUM 4 + +#define ADC1_GPIO5_CHANNEL 5 +#define ADC1_CHANNEL_5_GPIO_NUM 5 + +#define ADC1_GPIO6_CHANNEL 6 +#define ADC1_CHANNEL_6_GPIO_NUM 6 diff --git a/components/soc/esp32c5/include/soc/clk_tree_defs.h b/components/soc/esp32c5/include/soc/clk_tree_defs.h index 7741223400..787a7ffef9 100644 --- a/components/soc/esp32c5/include/soc/clk_tree_defs.h +++ b/components/soc/esp32c5/include/soc/clk_tree_defs.h @@ -73,8 +73,10 @@ typedef enum { // TODO: [ESP32C5] IDF-8642 (inherit from C6) */ typedef enum { // TODO: [ESP32C5] IDF-8642 (inherit from C6) SOC_CPU_CLK_SRC_XTAL = 0, /*!< Select XTAL_CLK as CPU_CLK source */ - SOC_CPU_CLK_SRC_PLL = 1, /*!< Select PLL_CLK as CPU_CLK source (PLL_CLK is the output of 40MHz crystal oscillator frequency multiplier, 480MHz) */ - SOC_CPU_CLK_SRC_RC_FAST = 2, /*!< Select RC_FAST_CLK as CPU_CLK source */ + SOC_CPU_CLK_SRC_RC_FAST = 1, /*!< Select RC_FAST_CLK as CPU_CLK source */ + SOC_CPU_CLK_SRC_PLL_F160 = 2, /*!< Select PLL_CLK as CPU_CLK source (PLL_CLK is the output of 40MHz crystal oscillator frequency multiplier, 480MHz) */ + SOC_CPU_CLK_SRC_PLL = SOC_CPU_CLK_SRC_PLL_F160, /*!< Select PLL_CLK as CPU_CLK source (PLL_CLK is the output of 40MHz crystal oscillator frequency multiplier, 480MHz) */ + SOC_CPU_CLK_SRC_PLL_F240 = 3, /*!< Select PLL_CLK as CPU_CLK source (PLL_CLK is the output of 40MHz crystal oscillator frequency multiplier, 480MHz) */ SOC_CPU_CLK_SRC_INVALID, /*!< Invalid CPU_CLK source */ } soc_cpu_clk_src_t; @@ -83,7 +85,7 @@ typedef enum { // TODO: [ESP32C5] IDF-8642 (inherit from C6) * @note Enum values are matched with the register field values on purpose */ typedef enum { // TODO: [ESP32C5] IDF-8642 (inherit from C6) - SOC_RTC_SLOW_CLK_SRC_RC_SLOW = 0, /*!< Select RC_SLOW_CLK as RTC_SLOW_CLK source */ + // SOC_RTC_SLOW_CLK_SRC_RC_SLOW = 0, /*!< Select RC_SLOW_CLK as RTC_SLOW_CLK source */ !!! can't do calibration on esp32c5, don't use it SOC_RTC_SLOW_CLK_SRC_XTAL32K = 1, /*!< Select XTAL32K_CLK as RTC_SLOW_CLK source */ SOC_RTC_SLOW_CLK_SRC_RC32K = 2, /*!< Select RC32K_CLK as RTC_SLOW_CLK source */ SOC_RTC_SLOW_CLK_SRC_OSC_SLOW = 3, /*!< Select OSC_SLOW_CLK (external slow clock) as RTC_SLOW_CLK source */ @@ -97,6 +99,7 @@ typedef enum { // TODO: [ESP32C5] IDF-8642 (inherit from C6) typedef enum { // TODO: [ESP32C5] IDF-8642 (inherit from C6) SOC_RTC_FAST_CLK_SRC_RC_FAST = 0, /*!< Select RC_FAST_CLK as RTC_FAST_CLK source */ SOC_RTC_FAST_CLK_SRC_XTAL_D2 = 1, /*!< Select XTAL_D2_CLK as RTC_FAST_CLK source */ + SOC_RTC_FAST_CLK_SRC_XTAL_D1 = 2, /*!< Select XTAL_D1_CLK as RTC_FAST_CLK source */ SOC_RTC_FAST_CLK_SRC_XTAL_DIV = SOC_RTC_FAST_CLK_SRC_XTAL_D2, /*!< Alias name for `SOC_RTC_FAST_CLK_SRC_XTAL_D2` */ SOC_RTC_FAST_CLK_SRC_INVALID, /*!< Invalid RTC_FAST_CLK source */ } soc_rtc_fast_clk_src_t; @@ -119,6 +122,7 @@ typedef enum { // TODO: [ESP32C5] IDF-8642 (inherit from C6) SOC_MOD_CLK_PLL_F80M, /*!< PLL_F80M_CLK is derived from PLL (clock gating + fixed divider of 6), it has a fixed frequency of 80MHz */ SOC_MOD_CLK_PLL_F160M, /*!< PLL_F160M_CLK is derived from PLL (clock gating + fixed divider of 3), it has a fixed frequency of 160MHz */ SOC_MOD_CLK_PLL_F240M, /*!< PLL_F240M_CLK is derived from PLL (clock gating + fixed divider of 2), it has a fixed frequency of 240MHz */ + SOC_MOD_CLK_PLL_F480M, SOC_MOD_CLK_XTAL32K, /*!< XTAL32K_CLK comes from the external 32kHz crystal, passing a clock gating to the peripherals */ SOC_MOD_CLK_RC_FAST, /*!< RC_FAST_CLK comes from the internal 20MHz rc oscillator, passing a clock gating to the peripherals */ SOC_MOD_CLK_XTAL, /*!< XTAL_CLK comes from the external 40MHz crystal */ @@ -464,6 +468,21 @@ typedef enum { // TODO: [ESP32C5] IDF-8685, IDF-8686 (inherit from C6) PARLIO_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F240M, /*!< Select PLL_F240M as the default clock choice */ } soc_periph_parlio_clk_src_t; +//////////////////////////////////////////////////MSPI/////////////////////////////////////////////////////////////////// +/** + * @brief Array initializer for all supported clock sources of MSPI digital controller + */ +#define SOC_MSPI_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_PLL_F480M} +/** + * @brief MSPI digital controller clock source + */ +typedef enum { // TODO: [ESP32C5] IDF-8649 + MSPI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ + MSPI_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */ + MSPI_CLK_SRC_SPLL = SOC_MOD_CLK_PLL_F480M, /*!< Select PLL_F64M as the source clock */ + MSPI_CLK_SRC_ROM_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as ROM default clock source */ +} soc_periph_mspi_clk_src_t; + //////////////////////////////////////////////CLOCK OUTPUT/////////////////////////////////////////////////////////// typedef enum { // TODO: [ESP32C5] IDF-8642 (inherit from C6) CLKOUT_SIG_PLL = 1, /*!< PLL_CLK is the output of crystal oscillator frequency multiplier */ diff --git a/components/soc/esp32c5/include/soc/ext_mem_defs.h b/components/soc/esp32c5/include/soc/ext_mem_defs.h new file mode 100644 index 0000000000..4c83c66c09 --- /dev/null +++ b/components/soc/esp32c5/include/soc/ext_mem_defs.h @@ -0,0 +1,152 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include "esp_bit_defs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#if !SOC_MMU_PAGE_SIZE +/** + * We define `SOC_MMU_PAGE_SIZE` in soc/CMakeLists.txt. + * Here we give a default definition, if SOC_MMU_PAGE_SIZE doesn't exist. This is to pass the check_public_headers.py + */ +#define SOC_MMU_PAGE_SIZE 0x10000 +#endif + + +#define SOC_IRAM0_CACHE_ADDRESS_LOW 0x41000000 +#define SOC_IRAM0_CACHE_ADDRESS_HIGH (SOC_IRAM0_CACHE_ADDRESS_LOW + ((SOC_MMU_PAGE_SIZE) * SOC_MMU_ENTRY_NUM)) + +#define SOC_DRAM0_CACHE_ADDRESS_LOW SOC_IRAM0_CACHE_ADDRESS_LOW //I/D share the same vaddr range +#define SOC_DRAM0_CACHE_ADDRESS_HIGH SOC_IRAM0_CACHE_ADDRESS_HIGH //I/D share the same vaddr range + +#define SOC_IRAM_FLASH_ADDRESS_LOW SOC_IRAM0_CACHE_ADDRESS_LOW +#define SOC_IRAM_FLASH_ADDRESS_HIGH SOC_IRAM0_CACHE_ADDRESS_HIGH + +#define SOC_DRAM_FLASH_ADDRESS_LOW SOC_DRAM0_CACHE_ADDRESS_LOW +#define SOC_DRAM_FLASH_ADDRESS_HIGH SOC_DRAM0_CACHE_ADDRESS_HIGH + +#define SOC_BUS_SIZE(bus_name) (bus_name##_ADDRESS_HIGH - bus_name##_ADDRESS_LOW) +#define SOC_ADDRESS_IN_BUS(bus_name, vaddr) ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name##_ADDRESS_HIGH) + +#define SOC_ADDRESS_IN_IRAM0(vaddr) SOC_ADDRESS_IN_BUS(SOC_IRAM0, vaddr) +#define SOC_ADDRESS_IN_IRAM0_CACHE(vaddr) SOC_ADDRESS_IN_BUS(SOC_IRAM0_CACHE, vaddr) +#define SOC_ADDRESS_IN_DRAM0(vaddr) SOC_ADDRESS_IN_BUS(SOC_DRAM0, vaddr) +#define SOC_ADDRESS_IN_DRAM0_CACHE(vaddr) SOC_ADDRESS_IN_BUS(SOC_DRAM0_CACHE, vaddr) + +#define SOC_MMU_ACCESS_FLASH 0 +#define SOC_MMU_VALID BIT(9) +#define SOC_MMU_SENSITIVE BIT(10) +#define SOC_MMU_INVALID_MASK BIT(9) +#define SOC_MMU_INVALID 0 + +/** + * MMU entry valid bit mask for mapping value. For an entry: + * valid bit + value bits + * valid bit is BIT(9), so value bits are 0x1ff + */ +#define SOC_MMU_VALID_VAL_MASK 0x1ff +/** + * Max MMU available paddr page num. + * `SOC_MMU_MAX_PADDR_PAGE_NUM * SOC_MMU_PAGE_SIZE` means the max paddr address supported by the MMU. e.g.: + * 256 * 64KB, means MMU can support 16MB paddr at most + */ +#define SOC_MMU_MAX_PADDR_PAGE_NUM 256 +//MMU entry num +#define SOC_MMU_ENTRY_NUM 256 + +/** + * This is the mask used for mapping. e.g.: + * 0x4200_0000 & SOC_MMU_VADDR_MASK + */ +#define SOC_MMU_VADDR_MASK ((SOC_MMU_PAGE_SIZE) * SOC_MMU_ENTRY_NUM - 1) + +#define SOC_MMU_DBUS_VADDR_BASE 0x41000000 +#define SOC_MMU_IBUS_VADDR_BASE 0x41000000 + +/*------------------------------------------------------------------------------ + * MMU Linear Address + *----------------------------------------------------------------------------*/ +#if (SOC_MMU_PAGE_SIZE == 0x10000) +/** + * - 64KB MMU page size: the last 0xFFFF, which is the offset + * - 128 MMU entries, needs 0x7F to hold it. + * + * Therefore, 0x7F,FFFF + */ +#define SOC_MMU_LINEAR_ADDR_MASK 0x7FFFFF + +#elif (SOC_MMU_PAGE_SIZE == 0x8000) +/** + * - 32KB MMU page size: the last 0x7FFF, which is the offset + * - 128 MMU entries, needs 0x7F to hold it. + * + * Therefore, 0x3F,FFFF + */ +#define SOC_MMU_LINEAR_ADDR_MASK 0x3FFFFF + +#elif (SOC_MMU_PAGE_SIZE == 0x4000) +/** + * - 16KB MMU page size: the last 0x3FFF, which is the offset + * - 128 MMU entries, needs 0x7F to hold it. + * + * Therefore, 0x1F,FFFF + */ +#define SOC_MMU_LINEAR_ADDR_MASK 0x1FFFFF +#endif //SOC_MMU_PAGE_SIZE + +/** + * - If high linear address isn't 0, this means MMU can recognize these addresses + * - If high linear address is 0, this means MMU linear address range is equal or smaller than vaddr range. + * Under this condition, we use the max linear space. + */ +#define SOC_MMU_IRAM0_LINEAR_ADDRESS_LOW (SOC_IRAM0_CACHE_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK) +#if ((SOC_IRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK) > 0) +#define SOC_MMU_IRAM0_LINEAR_ADDRESS_HIGH (SOC_IRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK) +#else +#define SOC_MMU_IRAM0_LINEAR_ADDRESS_HIGH (SOC_MMU_LINEAR_ADDR_MASK + 1) +#endif + +#define SOC_MMU_DRAM0_LINEAR_ADDRESS_LOW (SOC_DRAM0_CACHE_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK) +#if ((SOC_DRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK) > 0) +#define SOC_MMU_DRAM0_LINEAR_ADDRESS_HIGH (SOC_DRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK) +#else +#define SOC_MMU_DRAM0_LINEAR_ADDRESS_HIGH (SOC_MMU_LINEAR_ADDR_MASK + 1) +#endif + +/** + * I/D share the MMU linear address range + */ +#ifndef __cplusplus +_Static_assert(SOC_MMU_IRAM0_LINEAR_ADDRESS_LOW == SOC_MMU_DRAM0_LINEAR_ADDRESS_LOW, "IRAM0 and DRAM0 linear address should be same"); +#endif + + +/** + * ROM flash mmap driver needs below definitions + */ +#define CACHE_IROM_MMU_START 0 +#define CACHE_IROM_MMU_END Cache_Get_IROM_MMU_End() +#define CACHE_IROM_MMU_SIZE (CACHE_IROM_MMU_END - CACHE_IROM_MMU_START) + +#define CACHE_DROM_MMU_START CACHE_IROM_MMU_END +#define CACHE_DROM_MMU_END Cache_Get_DROM_MMU_End() +#define CACHE_DROM_MMU_SIZE (CACHE_DROM_MMU_END - CACHE_DROM_MMU_START) + +#define CACHE_DROM_MMU_MAX_END 0x400 + +#define ICACHE_MMU_SIZE 0x200 +#define DCACHE_MMU_SIZE 0x200 + +#define MMU_BUS_START(i) 0 +#define MMU_BUS_SIZE(i) 0x200 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/gdma_channel.h b/components/soc/esp32c5/include/soc/gdma_channel.h new file mode 100644 index 0000000000..2fdaa3f146 --- /dev/null +++ b/components/soc/esp32c5/include/soc/gdma_channel.h @@ -0,0 +1,32 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +// TODO: [ESP32C5] IDF-8710 + +// The following macros have a format SOC_[periph][instance_id] to make it work with `GDMA_MAKE_TRIGGER` +#define SOC_GDMA_TRIG_PERIPH_M2M0 (-1) +#define SOC_GDMA_TRIG_PERIPH_SPI2 (0) +#define SOC_GDMA_TRIG_PERIPH_UHCI0 (2) +#define SOC_GDMA_TRIG_PERIPH_I2S0 (3) +#define SOC_GDMA_TRIG_PERIPH_AES0 (6) +#define SOC_GDMA_TRIG_PERIPH_SHA0 (7) +#define SOC_GDMA_TRIG_PERIPH_ADC0 (8) +#define SOC_GDMA_TRIG_PERIPH_PARLIO0 (9) + +// On which system bus is the DMA instance of the peripheral connection mounted +#define SOC_GDMA_BUS_ANY (-1) +#define SOC_GDMA_BUS_AHB (0) + +#define SOC_GDMA_TRIG_PERIPH_M2M0_BUS SOC_GDMA_BUS_ANY +#define SOC_GDMA_TRIG_PERIPH_SPI2_BUS SOC_GDMA_BUS_AHB +#define SOC_GDMA_TRIG_PERIPH_UHCI0_BUS SOC_GDMA_BUS_AHB +#define SOC_GDMA_TRIG_PERIPH_I2S0_BUS SOC_GDMA_BUS_AHB +#define SOC_GDMA_TRIG_PERIPH_AES0_BUS SOC_GDMA_BUS_AHB +#define SOC_GDMA_TRIG_PERIPH_SHA0_BUS SOC_GDMA_BUS_AHB +#define SOC_GDMA_TRIG_PERIPH_ADC0_BUS SOC_GDMA_BUS_AHB +#define SOC_GDMA_TRIG_PERIPH_PARLIO0_BUS SOC_GDMA_BUS_AHB diff --git a/components/soc/esp32c5/include/soc/gdma_struct.h b/components/soc/esp32c5/include/soc/gdma_struct.h index 429106c9e0..ec5e9a5ad9 100644 --- a/components/soc/esp32c5/include/soc/gdma_struct.h +++ b/components/soc/esp32c5/include/soc/gdma_struct.h @@ -12,46 +12,46 @@ extern "C" { /** Group: Interrupt Registers in */ /** Type of in_int_raw_chn register - * Raw status interrupt of channel 0 + * Raw status interrupt of channel n */ typedef union { struct { /** in_done_chn_int_raw : R/WTC/SS; bitpos: [0]; default: 0; * The raw interrupt bit turns to high level when the last data pointed by one inlink - * descriptor has been received for Rx channel 0. + * descriptor has been received for Rx channel n. */ uint32_t in_done_chn_int_raw:1; /** in_suc_eof_chn_int_raw : R/WTC/SS; bitpos: [1]; default: 0; * The raw interrupt bit turns to high level when the last data pointed by one inlink - * descriptor has been received for Rx channel 0. For UHCI0 the raw interrupt bit + * descriptor has been received for Rx channel n. For UHCI0 the raw interrupt bit * turns to high level when the last data pointed by one inlink descriptor has been - * received and no data error is detected for Rx channel 0. + * received and no data error is detected for Rx channel n. */ uint32_t in_suc_eof_chn_int_raw:1; /** in_err_eof_chn_int_raw : R/WTC/SS; bitpos: [2]; default: 0; * The raw interrupt bit turns to high level when data error is detected only in the - * case that the peripheral is UHCI0 for Rx channel 0. For other peripherals this raw + * case that the peripheral is UHCI0 for Rx channel n. For other peripherals this raw * interrupt is reserved. */ uint32_t in_err_eof_chn_int_raw:1; /** in_dscr_err_chn_int_raw : R/WTC/SS; bitpos: [3]; default: 0; * The raw interrupt bit turns to high level when detecting inlink descriptor error * including owner error and the second and third word error of inlink descriptor for - * Rx channel 0. + * Rx channel n. */ uint32_t in_dscr_err_chn_int_raw:1; /** in_dscr_empty_chn_int_raw : R/WTC/SS; bitpos: [4]; default: 0; * The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full - * and receiving data is not completed but there is no more inlink for Rx channel 0. + * and receiving data is not completed but there is no more inlink for Rx channel n. */ uint32_t in_dscr_empty_chn_int_raw:1; /** infifo_ovf_chn_int_raw : R/WTC/SS; bitpos: [5]; default: 0; - * This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is + * This raw interrupt bit turns to high level when level 1 fifo of Rx channel n is * overflow. */ uint32_t infifo_ovf_chn_int_raw:1; /** infifo_udf_chn_int_raw : R/WTC/SS; bitpos: [6]; default: 0; - * This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is + * This raw interrupt bit turns to high level when level 1 fifo of Rx channel n is * underflow. */ uint32_t infifo_udf_chn_int_raw:1; @@ -61,7 +61,7 @@ typedef union { } gdma_in_int_raw_chn_reg_t; /** Type of in_int_st_chn register - * Masked interrupt of channel 0 + * Masked interrupt of channel n */ typedef union { struct { @@ -99,7 +99,7 @@ typedef union { } gdma_in_int_st_chn_reg_t; /** Type of in_int_ena_chn register - * Interrupt enable bits of channel 0 + * Interrupt enable bits of channel n */ typedef union { struct { @@ -137,7 +137,7 @@ typedef union { } gdma_in_int_ena_chn_reg_t; /** Type of in_int_clr_chn register - * Interrupt clear bits of channel 0 + * Interrupt clear bits of channel n */ typedef union { struct { @@ -177,39 +177,39 @@ typedef union { /** Group: Interrupt Registers out */ /** Type of out_int_raw_chn register - * Raw status interrupt of channel 0 + * Raw status interrupt of channel n */ typedef union { struct { /** out_done_chn_int_raw : R/WTC/SS; bitpos: [0]; default: 0; * The raw interrupt bit turns to high level when the last data pointed by one outlink - * descriptor has been transmitted to peripherals for Tx channel 0. + * descriptor has been transmitted to peripherals for Tx channel n. */ uint32_t out_done_chn_int_raw:1; /** out_eof_chn_int_raw : R/WTC/SS; bitpos: [1]; default: 0; * The raw interrupt bit turns to high level when the last data pointed by one outlink - * descriptor has been read from memory for Tx channel 0. + * descriptor has been read from memory for Tx channel n. */ uint32_t out_eof_chn_int_raw:1; /** out_dscr_err_chn_int_raw : R/WTC/SS; bitpos: [2]; default: 0; * The raw interrupt bit turns to high level when detecting outlink descriptor error * including owner error and the second and third word error of outlink descriptor for - * Tx channel 0. + * Tx channel n. */ uint32_t out_dscr_err_chn_int_raw:1; /** out_total_eof_chn_int_raw : R/WTC/SS; bitpos: [3]; default: 0; * The raw interrupt bit turns to high level when data corresponding a outlink * (includes one link descriptor or few link descriptors) is transmitted out for Tx - * channel 0. + * channel n. */ uint32_t out_total_eof_chn_int_raw:1; /** outfifo_ovf_chn_int_raw : R/WTC/SS; bitpos: [4]; default: 0; - * This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is + * This raw interrupt bit turns to high level when level 1 fifo of Tx channel n is * overflow. */ uint32_t outfifo_ovf_chn_int_raw:1; /** outfifo_udf_chn_int_raw : R/WTC/SS; bitpos: [5]; default: 0; - * This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is + * This raw interrupt bit turns to high level when level 1 fifo of Tx channel n is * underflow. */ uint32_t outfifo_udf_chn_int_raw:1; @@ -219,7 +219,7 @@ typedef union { } gdma_out_int_raw_chn_reg_t; /** Type of out_int_st_chn register - * Masked interrupt of channel 0 + * Masked interrupt of channel n */ typedef union { struct { @@ -253,7 +253,7 @@ typedef union { } gdma_out_int_st_chn_reg_t; /** Type of out_int_ena_chn register - * Interrupt enable bits of channel 0 + * Interrupt enable bits of channel n */ typedef union { struct { @@ -287,7 +287,7 @@ typedef union { } gdma_out_int_ena_chn_reg_t; /** Type of out_int_clr_chn register - * Interrupt clear bits of channel 0 + * Interrupt clear bits of channel n */ typedef union { struct { @@ -385,12 +385,12 @@ typedef union { /** Group: Configuration Registers0 */ /** Type of in_conf0_chn register - * Configure 0 register of Rx channel 0 + * Configure 0 register of Rx channel n */ typedef union { struct { /** in_rst_chn : R/W; bitpos: [0]; default: 0; - * This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer. + * This bit is used to reset DMA channel n Rx FSM and Rx FIFO pointer. */ uint32_t in_rst_chn:1; /** in_loop_test_chn : R/W; bitpos: [1]; default: 0; @@ -398,12 +398,12 @@ typedef union { */ uint32_t in_loop_test_chn:1; /** indscr_burst_en_chn : R/W; bitpos: [2]; default: 0; - * Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link + * Set this bit to 1 to enable INCR burst transfer for Rx channel n reading link * descriptor when accessing internal SRAM. */ uint32_t indscr_burst_en_chn:1; /** in_data_burst_en_chn : R/W; bitpos: [3]; default: 0; - * Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data + * Set this bit to 1 to enable INCR burst transfer for Rx channel n receiving data * when accessing internal SRAM. */ uint32_t in_data_burst_en_chn:1; @@ -412,7 +412,7 @@ typedef union { */ uint32_t mem_trans_en_chn:1; /** in_etm_en_chn : R/W; bitpos: [5]; default: 0; - * Set this bit to 1 to enable etm control mode, dma Rx channel 0 is triggered by etm + * Set this bit to 1 to enable etm control mode, dma Rx channel n is triggered by etm * task. */ uint32_t in_etm_en_chn:1; @@ -422,7 +422,7 @@ typedef union { } gdma_in_conf0_chn_reg_t; /** Type of in_conf1_chn register - * Configure 1 register of Rx channel 0 + * Configure 1 register of Rx channel n */ typedef union { struct { @@ -437,20 +437,20 @@ typedef union { } gdma_in_conf1_chn_reg_t; /** Type of infifo_status_chn register - * Receive FIFO status of Rx channel 0 + * Receive FIFO status of Rx channel n */ typedef union { struct { /** infifo_full_chn : RO; bitpos: [0]; default: 1; - * L1 Rx FIFO full signal for Rx channel 0. + * L1 Rx FIFO full signal for Rx channel n. */ uint32_t infifo_full_chn:1; /** infifo_empty_chn : RO; bitpos: [1]; default: 1; - * L1 Rx FIFO empty signal for Rx channel 0. + * L1 Rx FIFO empty signal for Rx channel n. */ uint32_t infifo_empty_chn:1; /** infifo_cnt_chn : RO; bitpos: [7:2]; default: 0; - * The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0. + * The register stores the byte number of the data in L1 Rx FIFO for Rx channel n. */ uint32_t infifo_cnt_chn:6; uint32_t reserved_8:15; @@ -480,7 +480,7 @@ typedef union { } gdma_infifo_status_chn_reg_t; /** Type of in_pop_chn register - * Pop control register of Rx channel 0 + * Pop control register of Rx channel n */ typedef union { struct { @@ -498,7 +498,7 @@ typedef union { } gdma_in_pop_chn_reg_t; /** Type of in_link_chn register - * Link descriptor configure and control register of Rx channel 0 + * Link descriptor configure and control register of Rx channel n */ typedef union { struct { @@ -535,7 +535,7 @@ typedef union { } gdma_in_link_chn_reg_t; /** Type of in_state_chn register - * Receive status of Rx channel 0 + * Receive status of Rx channel n */ typedef union { struct { @@ -557,7 +557,7 @@ typedef union { } gdma_in_state_chn_reg_t; /** Type of in_suc_eof_des_addr_chn register - * Inlink descriptor address when EOF occurs of Rx channel 0 + * Inlink descriptor address when EOF occurs of Rx channel n */ typedef union { struct { @@ -571,7 +571,7 @@ typedef union { } gdma_in_suc_eof_des_addr_chn_reg_t; /** Type of in_err_eof_des_addr_chn register - * Inlink descriptor address when errors occur of Rx channel 0 + * Inlink descriptor address when errors occur of Rx channel n */ typedef union { struct { @@ -585,7 +585,7 @@ typedef union { } gdma_in_err_eof_des_addr_chn_reg_t; /** Type of in_dscr_chn register - * Current inlink descriptor address of Rx channel 0 + * Current inlink descriptor address of Rx channel n */ typedef union { struct { @@ -598,7 +598,7 @@ typedef union { } gdma_in_dscr_chn_reg_t; /** Type of in_dscr_bf0_chn register - * The last inlink descriptor address of Rx channel 0 + * The last inlink descriptor address of Rx channel n */ typedef union { struct { @@ -611,7 +611,7 @@ typedef union { } gdma_in_dscr_bf0_chn_reg_t; /** Type of in_dscr_bf1_chn register - * The second-to-last inlink descriptor address of Rx channel 0 + * The second-to-last inlink descriptor address of Rx channel n */ typedef union { struct { @@ -624,12 +624,12 @@ typedef union { } gdma_in_dscr_bf1_chn_reg_t; /** Type of in_pri_chn register - * Priority register of Rx channel 0 + * Priority register of Rx channel n */ typedef union { struct { /** rx_pri_chn : R/W; bitpos: [3:0]; default: 0; - * The priority of Rx channel 0. The larger of the value the higher of the priority. + * The priority of Rx channel n. The larger of the value the higher of the priority. */ uint32_t rx_pri_chn:4; uint32_t reserved_4:28; @@ -638,549 +638,12 @@ typedef union { } gdma_in_pri_chn_reg_t; /** Type of in_peri_sel_chn register - * Peripheral selection of Rx channel 0 + * Peripheral selection of Rx channel n */ typedef union { struct { /** peri_in_sel_chn : R/W; bitpos: [5:0]; default: 63; - * This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: Dummy. 2: - * UHCI0. 3: I2S0. 4: Dummy. 5: Dummy. 6: AES. 7: SHA. 8: ADC_DAC. 9: Parallel_IO. - * 10~15: Dummy - */ - uint32_t peri_in_sel_chn:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} gdma_in_peri_sel_chn_reg_t; - -/** Type of out_conf0_ch0 register - * Configure 0 register of Tx channel 0 - */ -typedef union { - struct { - /** out_rst_ch0 : R/W; bitpos: [0]; default: 0; - * This bit is used to reset DMA channel 0 Tx FSM and Tx FIFO pointer. - */ - uint32_t out_rst_ch0:1; - /** out_loop_test_ch0 : R/W; bitpos: [1]; default: 0; - * reserved - */ - uint32_t out_loop_test_ch0:1; - /** out_auto_wrback_ch0 : R/W; bitpos: [2]; default: 0; - * Set this bit to enable automatic outlink-writeback when all the data in tx buffer - * has been transmitted. - */ - uint32_t out_auto_wrback_ch0:1; - /** out_eof_mode_ch0 : R/W; bitpos: [3]; default: 1; - * EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 0 is - * generated when data need to transmit has been popped from FIFO in DMA - */ - uint32_t out_eof_mode_ch0:1; - /** outdscr_burst_en_ch0 : R/W; bitpos: [4]; default: 0; - * Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link - * descriptor when accessing internal SRAM. - */ - uint32_t outdscr_burst_en_ch0:1; - /** out_data_burst_en_ch0 : R/W; bitpos: [5]; default: 0; - * Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitting data - * when accessing internal SRAM. - */ - uint32_t out_data_burst_en_ch0:1; - /** out_etm_en_ch0 : R/W; bitpos: [6]; default: 0; - * Set this bit to 1 to enable etm control mode, dma Tx channel 0 is triggered by etm - * task. - */ - uint32_t out_etm_en_ch0:1; - uint32_t reserved_7:25; - }; - uint32_t val; -} gdma_out_conf0_ch0_reg_t; - -/** Type of out_conf1_chn register - * Configure 1 register of Tx channel 0 - */ -typedef union { - struct { - uint32_t reserved_0:12; - /** out_check_owner_chn : R/W; bitpos: [12]; default: 0; - * Set this bit to enable checking the owner attribute of the link descriptor. - */ - uint32_t out_check_owner_chn:1; - uint32_t reserved_13:19; - }; - uint32_t val; -} gdma_out_conf1_chn_reg_t; - -/** Type of outfifo_status_chn register - * Transmit FIFO status of Tx channel 0 - */ -typedef union { - struct { - /** outfifo_full_chn : RO; bitpos: [0]; default: 0; - * L1 Tx FIFO full signal for Tx channel 0. - */ - uint32_t outfifo_full_chn:1; - /** outfifo_empty_chn : RO; bitpos: [1]; default: 1; - * L1 Tx FIFO empty signal for Tx channel 0. - */ - uint32_t outfifo_empty_chn:1; - /** outfifo_cnt_chn : RO; bitpos: [7:2]; default: 0; - * The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0. - */ - uint32_t outfifo_cnt_chn:6; - uint32_t reserved_8:15; - /** out_remain_under_1b_chn : RO; bitpos: [23]; default: 1; - * reserved - */ - uint32_t out_remain_under_1b_chn:1; - /** out_remain_under_2b_chn : RO; bitpos: [24]; default: 1; - * reserved - */ - uint32_t out_remain_under_2b_chn:1; - /** out_remain_under_3b_chn : RO; bitpos: [25]; default: 1; - * reserved - */ - uint32_t out_remain_under_3b_chn:1; - /** out_remain_under_4b_chn : RO; bitpos: [26]; default: 1; - * reserved - */ - uint32_t out_remain_under_4b_chn:1; - uint32_t reserved_27:5; - }; - uint32_t val; -} gdma_outfifo_status_chn_reg_t; - -/** Type of out_push_chn register - * Push control register of Rx channel 0 - */ -typedef union { - struct { - /** outfifo_wdata_chn : R/W; bitpos: [8:0]; default: 0; - * This register stores the data that need to be pushed into DMA FIFO. - */ - uint32_t outfifo_wdata_chn:9; - /** outfifo_push_chn : WT; bitpos: [9]; default: 0; - * Set this bit to push data into DMA FIFO. - */ - uint32_t outfifo_push_chn:1; - uint32_t reserved_10:22; - }; - uint32_t val; -} gdma_out_push_chn_reg_t; - -/** Type of out_link_chn register - * Link descriptor configure and control register of Tx channel 0 - */ -typedef union { - struct { - /** outlink_addr_chn : R/W; bitpos: [19:0]; default: 0; - * This register stores the 20 least significant bits of the first outlink - * descriptor's address. - */ - uint32_t outlink_addr_chn:20; - /** outlink_stop_chn : WT; bitpos: [20]; default: 0; - * Set this bit to stop dealing with the outlink descriptors. - */ - uint32_t outlink_stop_chn:1; - /** outlink_start_chn : WT; bitpos: [21]; default: 0; - * Set this bit to start dealing with the outlink descriptors. - */ - uint32_t outlink_start_chn:1; - /** outlink_restart_chn : WT; bitpos: [22]; default: 0; - * Set this bit to restart a new outlink from the last address. - */ - uint32_t outlink_restart_chn:1; - /** outlink_park_chn : RO; bitpos: [23]; default: 1; - * 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM - * is working. - */ - uint32_t outlink_park_chn:1; - uint32_t reserved_24:8; - }; - uint32_t val; -} gdma_out_link_chn_reg_t; - -/** Type of out_state_chn register - * Transmit status of Tx channel 0 - */ -typedef union { - struct { - /** outlink_dscr_addr_chn : RO; bitpos: [17:0]; default: 0; - * This register stores the current outlink descriptor's address. - */ - uint32_t outlink_dscr_addr_chn:18; - /** out_dscr_state_chn : RO; bitpos: [19:18]; default: 0; - * reserved - */ - uint32_t out_dscr_state_chn:2; - /** out_state_chn : RO; bitpos: [22:20]; default: 0; - * reserved - */ - uint32_t out_state_chn:3; - uint32_t reserved_23:9; - }; - uint32_t val; -} gdma_out_state_chn_reg_t; - -/** Type of out_eof_des_addr_chn register - * Outlink descriptor address when EOF occurs of Tx channel 0 - */ -typedef union { - struct { - /** out_eof_des_addr_chn : RO; bitpos: [31:0]; default: 0; - * This register stores the address of the outlink descriptor when the EOF bit in this - * descriptor is 1. - */ - uint32_t out_eof_des_addr_chn:32; - }; - uint32_t val; -} gdma_out_eof_des_addr_chn_reg_t; - -/** Type of out_eof_bfr_des_addr_chn register - * The last outlink descriptor address when EOF occurs of Tx channel 0 - */ -typedef union { - struct { - /** out_eof_bfr_des_addr_chn : RO; bitpos: [31:0]; default: 0; - * This register stores the address of the outlink descriptor before the last outlink - * descriptor. - */ - uint32_t out_eof_bfr_des_addr_chn:32; - }; - uint32_t val; -} gdma_out_eof_bfr_des_addr_chn_reg_t; - -/** Type of out_dscr_chn register - * Current inlink descriptor address of Tx channel 0 - */ -typedef union { - struct { - /** outlink_dscr_chn : RO; bitpos: [31:0]; default: 0; - * The address of the current outlink descriptor y. - */ - uint32_t outlink_dscr_chn:32; - }; - uint32_t val; -} gdma_out_dscr_chn_reg_t; - -/** Type of out_dscr_bf0_chn register - * The last inlink descriptor address of Tx channel 0 - */ -typedef union { - struct { - /** outlink_dscr_bf0_chn : RO; bitpos: [31:0]; default: 0; - * The address of the last outlink descriptor y-1. - */ - uint32_t outlink_dscr_bf0_chn:32; - }; - uint32_t val; -} gdma_out_dscr_bf0_chn_reg_t; - -/** Type of out_dscr_bf1_chn register - * The second-to-last inlink descriptor address of Tx channel 0 - */ -typedef union { - struct { - /** outlink_dscr_bf1_chn : RO; bitpos: [31:0]; default: 0; - * The address of the second-to-last inlink descriptor x-2. - */ - uint32_t outlink_dscr_bf1_chn:32; - }; - uint32_t val; -} gdma_out_dscr_bf1_chn_reg_t; - -/** Type of out_pri_chn register - * Priority register of Tx channel 0. - */ -typedef union { - struct { - /** tx_pri_chn : R/W; bitpos: [3:0]; default: 0; - * The priority of Tx channel 0. The larger of the value the higher of the priority. - */ - uint32_t tx_pri_chn:4; - uint32_t reserved_4:28; - }; - uint32_t val; -} gdma_out_pri_chn_reg_t; - -/** Type of out_peri_sel_chn register - * Peripheral selection of Tx channel 0 - */ -typedef union { - struct { - /** peri_out_sel_chn : R/W; bitpos: [5:0]; default: 63; - * This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: Dummy. 2: - * UHCI0. 3: I2S0. 4: Dummy. 5: Dummy. 6: AES. 7: SHA. 8: ADC_DAC. 9: Parallel_IO. - * 10~15: Dummy - */ - uint32_t peri_out_sel_chn:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} gdma_out_peri_sel_chn_reg_t; - - -/** Group: Configuration Registers1 */ -/** Type of in_conf0_chn register - * Configure 0 register of Rx channel 1 - */ -typedef union { - struct { - /** in_rst_chn : R/W; bitpos: [0]; default: 0; - * This bit is used to reset DMA channel 1 Rx FSM and Rx FIFO pointer. - */ - uint32_t in_rst_chn:1; - /** in_loop_test_chn : R/W; bitpos: [1]; default: 0; - * reserved - */ - uint32_t in_loop_test_chn:1; - /** indscr_burst_en_chn : R/W; bitpos: [2]; default: 0; - * Set this bit to 1 to enable INCR burst transfer for Rx channel 1 reading link - * descriptor when accessing internal SRAM. - */ - uint32_t indscr_burst_en_chn:1; - /** in_data_burst_en_chn : R/W; bitpos: [3]; default: 0; - * Set this bit to 1 to enable INCR burst transfer for Rx channel 1 receiving data - * when accessing internal SRAM. - */ - uint32_t in_data_burst_en_chn:1; - /** mem_trans_en_chn : R/W; bitpos: [4]; default: 0; - * Set this bit 1 to enable automatic transmitting data from memory to memory via DMA. - */ - uint32_t mem_trans_en_chn:1; - /** in_etm_en_chn : R/W; bitpos: [5]; default: 0; - * Set this bit to 1 to enable etm control mode, dma Rx channel 1 is triggered by etm - * task. - */ - uint32_t in_etm_en_chn:1; - uint32_t reserved_6:26; - }; - uint32_t val; -} gdma_in_conf0_chn_reg_t; - -/** Type of in_conf1_chn register - * Configure 1 register of Rx channel 1 - */ -typedef union { - struct { - uint32_t reserved_0:12; - /** in_check_owner_chn : R/W; bitpos: [12]; default: 0; - * Set this bit to enable checking the owner attribute of the link descriptor. - */ - uint32_t in_check_owner_chn:1; - uint32_t reserved_13:19; - }; - uint32_t val; -} gdma_in_conf1_chn_reg_t; - -/** Type of infifo_status_chn register - * Receive FIFO status of Rx channel 1 - */ -typedef union { - struct { - /** infifo_full_chn : RO; bitpos: [0]; default: 1; - * L1 Rx FIFO full signal for Rx channel 1. - */ - uint32_t infifo_full_chn:1; - /** infifo_empty_chn : RO; bitpos: [1]; default: 1; - * L1 Rx FIFO empty signal for Rx channel 1. - */ - uint32_t infifo_empty_chn:1; - /** infifo_cnt_chn : RO; bitpos: [7:2]; default: 0; - * The register stores the byte number of the data in L1 Rx FIFO for Rx channel 1. - */ - uint32_t infifo_cnt_chn:6; - uint32_t reserved_8:15; - /** in_remain_under_1b_chn : RO; bitpos: [23]; default: 1; - * reserved - */ - uint32_t in_remain_under_1b_chn:1; - /** in_remain_under_2b_chn : RO; bitpos: [24]; default: 1; - * reserved - */ - uint32_t in_remain_under_2b_chn:1; - /** in_remain_under_3b_chn : RO; bitpos: [25]; default: 1; - * reserved - */ - uint32_t in_remain_under_3b_chn:1; - /** in_remain_under_4b_chn : RO; bitpos: [26]; default: 1; - * reserved - */ - uint32_t in_remain_under_4b_chn:1; - /** in_buf_hungry_chn : RO; bitpos: [27]; default: 0; - * reserved - */ - uint32_t in_buf_hungry_chn:1; - uint32_t reserved_28:4; - }; - uint32_t val; -} gdma_infifo_status_chn_reg_t; - -/** Type of in_pop_chn register - * Pop control register of Rx channel 1 - */ -typedef union { - struct { - /** infifo_rdata_chn : RO; bitpos: [11:0]; default: 2048; - * This register stores the data popping from DMA FIFO. - */ - uint32_t infifo_rdata_chn:12; - /** infifo_pop_chn : WT; bitpos: [12]; default: 0; - * Set this bit to pop data from DMA FIFO. - */ - uint32_t infifo_pop_chn:1; - uint32_t reserved_13:19; - }; - uint32_t val; -} gdma_in_pop_chn_reg_t; - -/** Type of in_link_chn register - * Link descriptor configure and control register of Rx channel 1 - */ -typedef union { - struct { - /** inlink_addr_chn : R/W; bitpos: [19:0]; default: 0; - * This register stores the 20 least significant bits of the first inlink descriptor's - * address. - */ - uint32_t inlink_addr_chn:20; - /** inlink_auto_ret_chn : R/W; bitpos: [20]; default: 1; - * Set this bit to return to current inlink descriptor's address when there are some - * errors in current receiving data. - */ - uint32_t inlink_auto_ret_chn:1; - /** inlink_stop_chn : WT; bitpos: [21]; default: 0; - * Set this bit to stop dealing with the inlink descriptors. - */ - uint32_t inlink_stop_chn:1; - /** inlink_start_chn : WT; bitpos: [22]; default: 0; - * Set this bit to start dealing with the inlink descriptors. - */ - uint32_t inlink_start_chn:1; - /** inlink_restart_chn : WT; bitpos: [23]; default: 0; - * Set this bit to mount a new inlink descriptor. - */ - uint32_t inlink_restart_chn:1; - /** inlink_park_chn : RO; bitpos: [24]; default: 1; - * 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is - * working. - */ - uint32_t inlink_park_chn:1; - uint32_t reserved_25:7; - }; - uint32_t val; -} gdma_in_link_chn_reg_t; - -/** Type of in_state_chn register - * Receive status of Rx channel 1 - */ -typedef union { - struct { - /** inlink_dscr_addr_chn : RO; bitpos: [17:0]; default: 0; - * This register stores the current inlink descriptor's address. - */ - uint32_t inlink_dscr_addr_chn:18; - /** in_dscr_state_chn : RO; bitpos: [19:18]; default: 0; - * reserved - */ - uint32_t in_dscr_state_chn:2; - /** in_state_chn : RO; bitpos: [22:20]; default: 0; - * reserved - */ - uint32_t in_state_chn:3; - uint32_t reserved_23:9; - }; - uint32_t val; -} gdma_in_state_chn_reg_t; - -/** Type of in_suc_eof_des_addr_chn register - * Inlink descriptor address when EOF occurs of Rx channel 1 - */ -typedef union { - struct { - /** in_suc_eof_des_addr_chn : RO; bitpos: [31:0]; default: 0; - * This register stores the address of the inlink descriptor when the EOF bit in this - * descriptor is 1. - */ - uint32_t in_suc_eof_des_addr_chn:32; - }; - uint32_t val; -} gdma_in_suc_eof_des_addr_chn_reg_t; - -/** Type of in_err_eof_des_addr_chn register - * Inlink descriptor address when errors occur of Rx channel 1 - */ -typedef union { - struct { - /** in_err_eof_des_addr_chn : RO; bitpos: [31:0]; default: 0; - * This register stores the address of the inlink descriptor when there are some - * errors in current receiving data. Only used when peripheral is UHCI0. - */ - uint32_t in_err_eof_des_addr_chn:32; - }; - uint32_t val; -} gdma_in_err_eof_des_addr_chn_reg_t; - -/** Type of in_dscr_chn register - * Current inlink descriptor address of Rx channel 1 - */ -typedef union { - struct { - /** inlink_dscr_chn : RO; bitpos: [31:0]; default: 0; - * The address of the current inlink descriptor x. - */ - uint32_t inlink_dscr_chn:32; - }; - uint32_t val; -} gdma_in_dscr_chn_reg_t; - -/** Type of in_dscr_bf0_chn register - * The last inlink descriptor address of Rx channel 1 - */ -typedef union { - struct { - /** inlink_dscr_bf0_chn : RO; bitpos: [31:0]; default: 0; - * The address of the last inlink descriptor x-1. - */ - uint32_t inlink_dscr_bf0_chn:32; - }; - uint32_t val; -} gdma_in_dscr_bf0_chn_reg_t; - -/** Type of in_dscr_bf1_chn register - * The second-to-last inlink descriptor address of Rx channel 1 - */ -typedef union { - struct { - /** inlink_dscr_bf1_chn : RO; bitpos: [31:0]; default: 0; - * The address of the second-to-last inlink descriptor x-2. - */ - uint32_t inlink_dscr_bf1_chn:32; - }; - uint32_t val; -} gdma_in_dscr_bf1_chn_reg_t; - -/** Type of in_pri_chn register - * Priority register of Rx channel 1 - */ -typedef union { - struct { - /** rx_pri_chn : R/W; bitpos: [3:0]; default: 0; - * The priority of Rx channel 1. The larger of the value the higher of the priority. - */ - uint32_t rx_pri_chn:4; - uint32_t reserved_4:28; - }; - uint32_t val; -} gdma_in_pri_chn_reg_t; - -/** Type of in_peri_sel_chn register - * Peripheral selection of Rx channel 1 - */ -typedef union { - struct { - /** peri_in_sel_chn : R/W; bitpos: [5:0]; default: 63; - * This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: Dummy. 2: + * This register is used to select peripheral for Rx channel n. 0:SPI2. 1: Dummy. 2: * UHCI0. 3: I2S0. 4: Dummy. 5: Dummy. 6: AES. 7: SHA. 8: ADC_DAC. 9: Parallel_IO. * 10~15: Dummy */ @@ -1191,12 +654,12 @@ typedef union { } gdma_in_peri_sel_chn_reg_t; /** Type of out_conf0_chn register - * Configure 0 register of Tx channel 1 + * Configure 0 register of Tx channel n */ typedef union { struct { /** out_rst_chn : R/W; bitpos: [0]; default: 0; - * This bit is used to reset DMA channel 1 Tx FSM and Tx FIFO pointer. + * This bit is used to reset DMA channel n Tx FSM and Tx FIFO pointer. */ uint32_t out_rst_chn:1; /** out_loop_test_chn : R/W; bitpos: [1]; default: 0; @@ -1209,22 +672,22 @@ typedef union { */ uint32_t out_auto_wrback_chn:1; /** out_eof_mode_chn : R/W; bitpos: [3]; default: 1; - * EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 1 is + * EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel n is * generated when data need to transmit has been popped from FIFO in DMA */ uint32_t out_eof_mode_chn:1; /** outdscr_burst_en_chn : R/W; bitpos: [4]; default: 0; - * Set this bit to 1 to enable INCR burst transfer for Tx channel 1 reading link + * Set this bit to 1 to enable INCR burst transfer for Tx channel n reading link * descriptor when accessing internal SRAM. */ uint32_t outdscr_burst_en_chn:1; /** out_data_burst_en_chn : R/W; bitpos: [5]; default: 0; - * Set this bit to 1 to enable INCR burst transfer for Tx channel 1 transmitting data + * Set this bit to 1 to enable INCR burst transfer for Tx channel n transmitting data * when accessing internal SRAM. */ uint32_t out_data_burst_en_chn:1; /** out_etm_en_chn : R/W; bitpos: [6]; default: 0; - * Set this bit to 1 to enable etm control mode, dma Tx channel 1 is triggered by etm + * Set this bit to 1 to enable etm control mode, dma Tx channel n is triggered by etm * task. */ uint32_t out_etm_en_chn:1; @@ -1234,7 +697,7 @@ typedef union { } gdma_out_conf0_chn_reg_t; /** Type of out_conf1_chn register - * Configure 1 register of Tx channel 1 + * Configure 1 register of Tx channel n */ typedef union { struct { @@ -1249,20 +712,20 @@ typedef union { } gdma_out_conf1_chn_reg_t; /** Type of outfifo_status_chn register - * Transmit FIFO status of Tx channel 1 + * Transmit FIFO status of Tx channel n */ typedef union { struct { /** outfifo_full_chn : RO; bitpos: [0]; default: 0; - * L1 Tx FIFO full signal for Tx channel 1. + * L1 Tx FIFO full signal for Tx channel n. */ uint32_t outfifo_full_chn:1; /** outfifo_empty_chn : RO; bitpos: [1]; default: 1; - * L1 Tx FIFO empty signal for Tx channel 1. + * L1 Tx FIFO empty signal for Tx channel n. */ uint32_t outfifo_empty_chn:1; /** outfifo_cnt_chn : RO; bitpos: [7:2]; default: 0; - * The register stores the byte number of the data in L1 Tx FIFO for Tx channel 1. + * The register stores the byte number of the data in L1 Tx FIFO for Tx channel n. */ uint32_t outfifo_cnt_chn:6; uint32_t reserved_8:15; @@ -1288,7 +751,7 @@ typedef union { } gdma_outfifo_status_chn_reg_t; /** Type of out_push_chn register - * Push control register of Rx channel 1 + * Push control register of Rx channel n */ typedef union { struct { @@ -1306,7 +769,7 @@ typedef union { } gdma_out_push_chn_reg_t; /** Type of out_link_chn register - * Link descriptor configure and control register of Tx channel 1 + * Link descriptor configure and control register of Tx channel n */ typedef union { struct { @@ -1338,7 +801,7 @@ typedef union { } gdma_out_link_chn_reg_t; /** Type of out_state_chn register - * Transmit status of Tx channel 1 + * Transmit status of Tx channel n */ typedef union { struct { @@ -1360,7 +823,7 @@ typedef union { } gdma_out_state_chn_reg_t; /** Type of out_eof_des_addr_chn register - * Outlink descriptor address when EOF occurs of Tx channel 1 + * Outlink descriptor address when EOF occurs of Tx channel n */ typedef union { struct { @@ -1374,7 +837,7 @@ typedef union { } gdma_out_eof_des_addr_chn_reg_t; /** Type of out_eof_bfr_des_addr_chn register - * The last outlink descriptor address when EOF occurs of Tx channel 1 + * The last outlink descriptor address when EOF occurs of Tx channel n */ typedef union { struct { @@ -1388,7 +851,7 @@ typedef union { } gdma_out_eof_bfr_des_addr_chn_reg_t; /** Type of out_dscr_chn register - * Current inlink descriptor address of Tx channel 1 + * Current inlink descriptor address of Tx channel n */ typedef union { struct { @@ -1401,7 +864,7 @@ typedef union { } gdma_out_dscr_chn_reg_t; /** Type of out_dscr_bf0_chn register - * The last inlink descriptor address of Tx channel 1 + * The last inlink descriptor address of Tx channel n */ typedef union { struct { @@ -1414,7 +877,7 @@ typedef union { } gdma_out_dscr_bf0_chn_reg_t; /** Type of out_dscr_bf1_chn register - * The second-to-last inlink descriptor address of Tx channel 1 + * The second-to-last inlink descriptor address of Tx channel n */ typedef union { struct { @@ -1427,12 +890,12 @@ typedef union { } gdma_out_dscr_bf1_chn_reg_t; /** Type of out_pri_chn register - * Priority register of Tx channel 1 + * Priority register of Tx channel n. */ typedef union { struct { /** tx_pri_chn : R/W; bitpos: [3:0]; default: 0; - * The priority of Tx channel 1. The larger of the value the higher of the priority. + * The priority of Tx channel n. The larger of the value the higher of the priority. */ uint32_t tx_pri_chn:4; uint32_t reserved_4:28; @@ -1441,549 +904,12 @@ typedef union { } gdma_out_pri_chn_reg_t; /** Type of out_peri_sel_chn register - * Peripheral selection of Tx channel 1 + * Peripheral selection of Tx channel n */ typedef union { struct { /** peri_out_sel_chn : R/W; bitpos: [5:0]; default: 63; - * This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: Dummy. 2: - * UHCI0. 3: I2S0. 4: Dummy. 5: Dummy. 6: AES. 7: SHA. 8: ADC_DAC. 9: Parallel_IO. - * 10~15: Dummy - */ - uint32_t peri_out_sel_chn:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} gdma_out_peri_sel_chn_reg_t; - - -/** Group: Configuration Registers2 */ -/** Type of in_conf0_chn register - * Configure 0 register of Rx channel 2 - */ -typedef union { - struct { - /** in_rst_chn : R/W; bitpos: [0]; default: 0; - * This bit is used to reset DMA channel 2 Rx FSM and Rx FIFO pointer. - */ - uint32_t in_rst_chn:1; - /** in_loop_test_chn : R/W; bitpos: [1]; default: 0; - * reserved - */ - uint32_t in_loop_test_chn:1; - /** indscr_burst_en_chn : R/W; bitpos: [2]; default: 0; - * Set this bit to 1 to enable INCR burst transfer for Rx channel 2 reading link - * descriptor when accessing internal SRAM. - */ - uint32_t indscr_burst_en_chn:1; - /** in_data_burst_en_chn : R/W; bitpos: [3]; default: 0; - * Set this bit to 1 to enable INCR burst transfer for Rx channel 2 receiving data - * when accessing internal SRAM. - */ - uint32_t in_data_burst_en_chn:1; - /** mem_trans_en_chn : R/W; bitpos: [4]; default: 0; - * Set this bit 1 to enable automatic transmitting data from memory to memory via DMA. - */ - uint32_t mem_trans_en_chn:1; - /** in_etm_en_chn : R/W; bitpos: [5]; default: 0; - * Set this bit to 1 to enable etm control mode, dma Rx channel 2 is triggered by etm - * task. - */ - uint32_t in_etm_en_chn:1; - uint32_t reserved_6:26; - }; - uint32_t val; -} gdma_in_conf0_chn_reg_t; - -/** Type of in_conf1_chn register - * Configure 1 register of Rx channel 2 - */ -typedef union { - struct { - uint32_t reserved_0:12; - /** in_check_owner_chn : R/W; bitpos: [12]; default: 0; - * Set this bit to enable checking the owner attribute of the link descriptor. - */ - uint32_t in_check_owner_chn:1; - uint32_t reserved_13:19; - }; - uint32_t val; -} gdma_in_conf1_chn_reg_t; - -/** Type of infifo_status_chn register - * Receive FIFO status of Rx channel 2 - */ -typedef union { - struct { - /** infifo_full_chn : RO; bitpos: [0]; default: 1; - * L1 Rx FIFO full signal for Rx channel 2. - */ - uint32_t infifo_full_chn:1; - /** infifo_empty_chn : RO; bitpos: [1]; default: 1; - * L1 Rx FIFO empty signal for Rx channel 2. - */ - uint32_t infifo_empty_chn:1; - /** infifo_cnt_chn : RO; bitpos: [7:2]; default: 0; - * The register stores the byte number of the data in L1 Rx FIFO for Rx channel 2. - */ - uint32_t infifo_cnt_chn:6; - uint32_t reserved_8:15; - /** in_remain_under_1b_chn : RO; bitpos: [23]; default: 1; - * reserved - */ - uint32_t in_remain_under_1b_chn:1; - /** in_remain_under_2b_chn : RO; bitpos: [24]; default: 1; - * reserved - */ - uint32_t in_remain_under_2b_chn:1; - /** in_remain_under_3b_chn : RO; bitpos: [25]; default: 1; - * reserved - */ - uint32_t in_remain_under_3b_chn:1; - /** in_remain_under_4b_chn : RO; bitpos: [26]; default: 1; - * reserved - */ - uint32_t in_remain_under_4b_chn:1; - /** in_buf_hungry_chn : RO; bitpos: [27]; default: 0; - * reserved - */ - uint32_t in_buf_hungry_chn:1; - uint32_t reserved_28:4; - }; - uint32_t val; -} gdma_infifo_status_chn_reg_t; - -/** Type of in_pop_chn register - * Pop control register of Rx channel 2 - */ -typedef union { - struct { - /** infifo_rdata_chn : RO; bitpos: [11:0]; default: 2048; - * This register stores the data popping from DMA FIFO. - */ - uint32_t infifo_rdata_chn:12; - /** infifo_pop_chn : WT; bitpos: [12]; default: 0; - * Set this bit to pop data from DMA FIFO. - */ - uint32_t infifo_pop_chn:1; - uint32_t reserved_13:19; - }; - uint32_t val; -} gdma_in_pop_chn_reg_t; - -/** Type of in_link_chn register - * Link descriptor configure and control register of Rx channel 2 - */ -typedef union { - struct { - /** inlink_addr_chn : R/W; bitpos: [19:0]; default: 0; - * This register stores the 20 least significant bits of the first inlink descriptor's - * address. - */ - uint32_t inlink_addr_chn:20; - /** inlink_auto_ret_chn : R/W; bitpos: [20]; default: 1; - * Set this bit to return to current inlink descriptor's address when there are some - * errors in current receiving data. - */ - uint32_t inlink_auto_ret_chn:1; - /** inlink_stop_chn : WT; bitpos: [21]; default: 0; - * Set this bit to stop dealing with the inlink descriptors. - */ - uint32_t inlink_stop_chn:1; - /** inlink_start_chn : WT; bitpos: [22]; default: 0; - * Set this bit to start dealing with the inlink descriptors. - */ - uint32_t inlink_start_chn:1; - /** inlink_restart_chn : WT; bitpos: [23]; default: 0; - * Set this bit to mount a new inlink descriptor. - */ - uint32_t inlink_restart_chn:1; - /** inlink_park_chn : RO; bitpos: [24]; default: 1; - * 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is - * working. - */ - uint32_t inlink_park_chn:1; - uint32_t reserved_25:7; - }; - uint32_t val; -} gdma_in_link_chn_reg_t; - -/** Type of in_state_chn register - * Receive status of Rx channel 2 - */ -typedef union { - struct { - /** inlink_dscr_addr_chn : RO; bitpos: [17:0]; default: 0; - * This register stores the current inlink descriptor's address. - */ - uint32_t inlink_dscr_addr_chn:18; - /** in_dscr_state_chn : RO; bitpos: [19:18]; default: 0; - * reserved - */ - uint32_t in_dscr_state_chn:2; - /** in_state_chn : RO; bitpos: [22:20]; default: 0; - * reserved - */ - uint32_t in_state_chn:3; - uint32_t reserved_23:9; - }; - uint32_t val; -} gdma_in_state_chn_reg_t; - -/** Type of in_suc_eof_des_addr_chn register - * Inlink descriptor address when EOF occurs of Rx channel 2 - */ -typedef union { - struct { - /** in_suc_eof_des_addr_chn : RO; bitpos: [31:0]; default: 0; - * This register stores the address of the inlink descriptor when the EOF bit in this - * descriptor is 1. - */ - uint32_t in_suc_eof_des_addr_chn:32; - }; - uint32_t val; -} gdma_in_suc_eof_des_addr_chn_reg_t; - -/** Type of in_err_eof_des_addr_chn register - * Inlink descriptor address when errors occur of Rx channel 2 - */ -typedef union { - struct { - /** in_err_eof_des_addr_chn : RO; bitpos: [31:0]; default: 0; - * This register stores the address of the inlink descriptor when there are some - * errors in current receiving data. Only used when peripheral is UHCI0. - */ - uint32_t in_err_eof_des_addr_chn:32; - }; - uint32_t val; -} gdma_in_err_eof_des_addr_chn_reg_t; - -/** Type of in_dscr_chn register - * Current inlink descriptor address of Rx channel 2 - */ -typedef union { - struct { - /** inlink_dscr_chn : RO; bitpos: [31:0]; default: 0; - * The address of the current inlink descriptor x. - */ - uint32_t inlink_dscr_chn:32; - }; - uint32_t val; -} gdma_in_dscr_chn_reg_t; - -/** Type of in_dscr_bf0_chn register - * The last inlink descriptor address of Rx channel 2 - */ -typedef union { - struct { - /** inlink_dscr_bf0_chn : RO; bitpos: [31:0]; default: 0; - * The address of the last inlink descriptor x-1. - */ - uint32_t inlink_dscr_bf0_chn:32; - }; - uint32_t val; -} gdma_in_dscr_bf0_chn_reg_t; - -/** Type of in_dscr_bf1_chn register - * The second-to-last inlink descriptor address of Rx channel 2 - */ -typedef union { - struct { - /** inlink_dscr_bf1_chn : RO; bitpos: [31:0]; default: 0; - * The address of the second-to-last inlink descriptor x-2. - */ - uint32_t inlink_dscr_bf1_chn:32; - }; - uint32_t val; -} gdma_in_dscr_bf1_chn_reg_t; - -/** Type of in_pri_chn register - * Priority register of Rx channel 2 - */ -typedef union { - struct { - /** rx_pri_chn : R/W; bitpos: [3:0]; default: 0; - * The priority of Rx channel 2. The larger of the value the higher of the priority. - */ - uint32_t rx_pri_chn:4; - uint32_t reserved_4:28; - }; - uint32_t val; -} gdma_in_pri_chn_reg_t; - -/** Type of in_peri_sel_chn register - * Peripheral selection of Rx channel 2 - */ -typedef union { - struct { - /** peri_in_sel_chn : R/W; bitpos: [5:0]; default: 63; - * This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: Dummy. 2: - * UHCI0. 3: I2S0. 4: Dummy. 5: Dummy. 6: AES. 7: SHA. 8: ADC_DAC. 9: Parallel_IO. - * 10~15: Dummy - */ - uint32_t peri_in_sel_chn:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} gdma_in_peri_sel_chn_reg_t; - -/** Type of out_conf0_chn register - * Configure 0 register of Tx channel 2 - */ -typedef union { - struct { - /** out_rst_chn : R/W; bitpos: [0]; default: 0; - * This bit is used to reset DMA channel 2 Tx FSM and Tx FIFO pointer. - */ - uint32_t out_rst_chn:1; - /** out_loop_test_chn : R/W; bitpos: [1]; default: 0; - * reserved - */ - uint32_t out_loop_test_chn:1; - /** out_auto_wrback_chn : R/W; bitpos: [2]; default: 0; - * Set this bit to enable automatic outlink-writeback when all the data in tx buffer - * has been transmitted. - */ - uint32_t out_auto_wrback_chn:1; - /** out_eof_mode_chn : R/W; bitpos: [3]; default: 1; - * EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 2 is - * generated when data need to transmit has been popped from FIFO in DMA - */ - uint32_t out_eof_mode_chn:1; - /** outdscr_burst_en_chn : R/W; bitpos: [4]; default: 0; - * Set this bit to 1 to enable INCR burst transfer for Tx channel 2 reading link - * descriptor when accessing internal SRAM. - */ - uint32_t outdscr_burst_en_chn:1; - /** out_data_burst_en_chn : R/W; bitpos: [5]; default: 0; - * Set this bit to 1 to enable INCR burst transfer for Tx channel 2 transmitting data - * when accessing internal SRAM. - */ - uint32_t out_data_burst_en_chn:1; - /** out_etm_en_chn : R/W; bitpos: [6]; default: 0; - * Set this bit to 1 to enable etm control mode, dma Tx channel 2 is triggered by etm - * task. - */ - uint32_t out_etm_en_chn:1; - uint32_t reserved_7:25; - }; - uint32_t val; -} gdma_out_conf0_chn_reg_t; - -/** Type of out_conf1_chn register - * Configure 1 register of Tx channel 2 - */ -typedef union { - struct { - uint32_t reserved_0:12; - /** out_check_owner_chn : R/W; bitpos: [12]; default: 0; - * Set this bit to enable checking the owner attribute of the link descriptor. - */ - uint32_t out_check_owner_chn:1; - uint32_t reserved_13:19; - }; - uint32_t val; -} gdma_out_conf1_chn_reg_t; - -/** Type of outfifo_status_chn register - * Transmit FIFO status of Tx channel 2 - */ -typedef union { - struct { - /** outfifo_full_chn : RO; bitpos: [0]; default: 0; - * L1 Tx FIFO full signal for Tx channel 2. - */ - uint32_t outfifo_full_chn:1; - /** outfifo_empty_chn : RO; bitpos: [1]; default: 1; - * L1 Tx FIFO empty signal for Tx channel 2. - */ - uint32_t outfifo_empty_chn:1; - /** outfifo_cnt_chn : RO; bitpos: [7:2]; default: 0; - * The register stores the byte number of the data in L1 Tx FIFO for Tx channel 2. - */ - uint32_t outfifo_cnt_chn:6; - uint32_t reserved_8:15; - /** out_remain_under_1b_chn : RO; bitpos: [23]; default: 1; - * reserved - */ - uint32_t out_remain_under_1b_chn:1; - /** out_remain_under_2b_chn : RO; bitpos: [24]; default: 1; - * reserved - */ - uint32_t out_remain_under_2b_chn:1; - /** out_remain_under_3b_chn : RO; bitpos: [25]; default: 1; - * reserved - */ - uint32_t out_remain_under_3b_chn:1; - /** out_remain_under_4b_chn : RO; bitpos: [26]; default: 1; - * reserved - */ - uint32_t out_remain_under_4b_chn:1; - uint32_t reserved_27:5; - }; - uint32_t val; -} gdma_outfifo_status_chn_reg_t; - -/** Type of out_push_chn register - * Push control register of Rx channel 2 - */ -typedef union { - struct { - /** outfifo_wdata_chn : R/W; bitpos: [8:0]; default: 0; - * This register stores the data that need to be pushed into DMA FIFO. - */ - uint32_t outfifo_wdata_chn:9; - /** outfifo_push_chn : WT; bitpos: [9]; default: 0; - * Set this bit to push data into DMA FIFO. - */ - uint32_t outfifo_push_chn:1; - uint32_t reserved_10:22; - }; - uint32_t val; -} gdma_out_push_chn_reg_t; - -/** Type of out_link_chn register - * Link descriptor configure and control register of Tx channel 2 - */ -typedef union { - struct { - /** outlink_addr_chn : R/W; bitpos: [19:0]; default: 0; - * This register stores the 20 least significant bits of the first outlink - * descriptor's address. - */ - uint32_t outlink_addr_chn:20; - /** outlink_stop_chn : WT; bitpos: [20]; default: 0; - * Set this bit to stop dealing with the outlink descriptors. - */ - uint32_t outlink_stop_chn:1; - /** outlink_start_chn : WT; bitpos: [21]; default: 0; - * Set this bit to start dealing with the outlink descriptors. - */ - uint32_t outlink_start_chn:1; - /** outlink_restart_chn : WT; bitpos: [22]; default: 0; - * Set this bit to restart a new outlink from the last address. - */ - uint32_t outlink_restart_chn:1; - /** outlink_park_chn : RO; bitpos: [23]; default: 1; - * 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM - * is working. - */ - uint32_t outlink_park_chn:1; - uint32_t reserved_24:8; - }; - uint32_t val; -} gdma_out_link_chn_reg_t; - -/** Type of out_state_chn register - * Transmit status of Tx channel 2 - */ -typedef union { - struct { - /** outlink_dscr_addr_chn : RO; bitpos: [17:0]; default: 0; - * This register stores the current outlink descriptor's address. - */ - uint32_t outlink_dscr_addr_chn:18; - /** out_dscr_state_chn : RO; bitpos: [19:18]; default: 0; - * reserved - */ - uint32_t out_dscr_state_chn:2; - /** out_state_chn : RO; bitpos: [22:20]; default: 0; - * reserved - */ - uint32_t out_state_chn:3; - uint32_t reserved_23:9; - }; - uint32_t val; -} gdma_out_state_chn_reg_t; - -/** Type of out_eof_des_addr_chn register - * Outlink descriptor address when EOF occurs of Tx channel 2 - */ -typedef union { - struct { - /** out_eof_des_addr_chn : RO; bitpos: [31:0]; default: 0; - * This register stores the address of the outlink descriptor when the EOF bit in this - * descriptor is 1. - */ - uint32_t out_eof_des_addr_chn:32; - }; - uint32_t val; -} gdma_out_eof_des_addr_chn_reg_t; - -/** Type of out_eof_bfr_des_addr_chn register - * The last outlink descriptor address when EOF occurs of Tx channel 2 - */ -typedef union { - struct { - /** out_eof_bfr_des_addr_chn : RO; bitpos: [31:0]; default: 0; - * This register stores the address of the outlink descriptor before the last outlink - * descriptor. - */ - uint32_t out_eof_bfr_des_addr_chn:32; - }; - uint32_t val; -} gdma_out_eof_bfr_des_addr_chn_reg_t; - -/** Type of out_dscr_chn register - * Current inlink descriptor address of Tx channel 2 - */ -typedef union { - struct { - /** outlink_dscr_chn : RO; bitpos: [31:0]; default: 0; - * The address of the current outlink descriptor y. - */ - uint32_t outlink_dscr_chn:32; - }; - uint32_t val; -} gdma_out_dscr_chn_reg_t; - -/** Type of out_dscr_bf0_chn register - * The last inlink descriptor address of Tx channel 2 - */ -typedef union { - struct { - /** outlink_dscr_bf0_chn : RO; bitpos: [31:0]; default: 0; - * The address of the last outlink descriptor y-1. - */ - uint32_t outlink_dscr_bf0_chn:32; - }; - uint32_t val; -} gdma_out_dscr_bf0_chn_reg_t; - -/** Type of out_dscr_bf1_chn register - * The second-to-last inlink descriptor address of Tx channel 2 - */ -typedef union { - struct { - /** outlink_dscr_bf1_chn : RO; bitpos: [31:0]; default: 0; - * The address of the second-to-last inlink descriptor x-2. - */ - uint32_t outlink_dscr_bf1_chn:32; - }; - uint32_t val; -} gdma_out_dscr_bf1_chn_reg_t; - -/** Type of out_pri_chn register - * Priority register of Tx channel 2 - */ -typedef union { - struct { - /** tx_pri_chn : R/W; bitpos: [3:0]; default: 0; - * The priority of Tx channel 2. The larger of the value the higher of the priority. - */ - uint32_t tx_pri_chn:4; - uint32_t reserved_4:28; - }; - uint32_t val; -} gdma_out_pri_chn_reg_t; - -/** Type of out_peri_sel_chn register - * Peripheral selection of Tx channel 2 - */ -typedef union { - struct { - /** peri_out_sel_chn : R/W; bitpos: [5:0]; default: 63; - * This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: Dummy. 2: + * This register is used to select peripheral for Tx channel n. 0:SPI2. 1: Dummy. 2: * UHCI0. 3: I2S0. 4: Dummy. 5: Dummy. 6: AES. 7: SHA. 8: ADC_DAC. 9: Parallel_IO. * 10~15: Dummy */ @@ -2083,7 +1009,7 @@ typedef struct gdma_dev_t { volatile gdma_in_pri_chn_reg_t in_pri_ch0; volatile gdma_in_peri_sel_chn_reg_t in_peri_sel_ch0; uint32_t reserved_0a4[11]; - volatile gdma_out_conf0_ch0_reg_t out_conf0_ch0; + volatile gdma_out_conf0_chn_reg_t out_conf0_ch0; volatile gdma_out_conf1_chn_reg_t out_conf1_ch0; volatile gdma_outfifo_status_chn_reg_t outfifo_status_ch0; volatile gdma_out_push_chn_reg_t out_push_ch0; diff --git a/components/soc/esp32c5/include/soc/gpio_num.h b/components/soc/esp32c5/include/soc/gpio_num.h new file mode 100644 index 0000000000..bc11f40b64 --- /dev/null +++ b/components/soc/esp32c5/include/soc/gpio_num.h @@ -0,0 +1,56 @@ +/* + * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +// TODO: [ESP32C5] IDF-8717 + +/** + * @brief GPIO number + */ +typedef enum { + GPIO_NUM_NC = -1, /*!< Use to signal not connected to S/W */ + GPIO_NUM_0 = 0, /*!< GPIO0, input and output */ + GPIO_NUM_1 = 1, /*!< GPIO1, input and output */ + GPIO_NUM_2 = 2, /*!< GPIO2, input and output */ + GPIO_NUM_3 = 3, /*!< GPIO3, input and output */ + GPIO_NUM_4 = 4, /*!< GPIO4, input and output */ + GPIO_NUM_5 = 5, /*!< GPIO5, input and output */ + GPIO_NUM_6 = 6, /*!< GPIO6, input and output */ + GPIO_NUM_7 = 7, /*!< GPIO7, input and output */ + GPIO_NUM_8 = 8, /*!< GPIO8, input and output */ + GPIO_NUM_9 = 9, /*!< GPIO9, input and output */ + GPIO_NUM_10 = 10, /*!< GPIO10, input and output */ + GPIO_NUM_11 = 11, /*!< GPIO11, input and output */ + GPIO_NUM_12 = 12, /*!< GPIO12, input and output */ + GPIO_NUM_13 = 13, /*!< GPIO13, input and output */ + GPIO_NUM_14 = 14, /*!< GPIO14, input and output */ + GPIO_NUM_15 = 15, /*!< GPIO15, input and output */ + GPIO_NUM_16 = 16, /*!< GPIO16, input and output */ + GPIO_NUM_17 = 17, /*!< GPIO17, input and output */ + GPIO_NUM_18 = 18, /*!< GPIO18, input and output */ + GPIO_NUM_19 = 19, /*!< GPIO19, input and output */ + GPIO_NUM_20 = 20, /*!< GPIO20, input and output */ + GPIO_NUM_21 = 21, /*!< GPIO21, input and output */ + GPIO_NUM_22 = 22, /*!< GPIO22, input and output */ + GPIO_NUM_23 = 23, /*!< GPIO23, input and output */ + GPIO_NUM_24 = 24, /*!< GPIO24, input and output */ + GPIO_NUM_25 = 25, /*!< GPIO25, input and output */ + GPIO_NUM_26 = 26, /*!< GPIO26, input and output */ + GPIO_NUM_27 = 27, /*!< GPIO27, input and output */ + GPIO_NUM_28 = 28, /*!< GPIO28, input and output */ + GPIO_NUM_29 = 29, /*!< GPIO29, input and output */ + GPIO_NUM_30 = 30, /*!< GPIO30, input and output */ + GPIO_NUM_MAX, +} gpio_num_t; + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/gpio_sig_map.h b/components/soc/esp32c5/include/soc/gpio_sig_map.h index b998fffc80..b37e940d6b 100644 --- a/components/soc/esp32c5/include/soc/gpio_sig_map.h +++ b/components/soc/esp32c5/include/soc/gpio_sig_map.h @@ -174,4 +174,5 @@ #define CLK_OUT_OUT1_IDX 125 #define CLK_OUT_OUT2_IDX 126 #define CLK_OUT_OUT3_IDX 127 +#define SIG_GPIO_OUT_IDX 128 #define GPIO_MAP_DATE_IDX 0x2301100 diff --git a/components/soc/esp32c5/include/soc/gpio_struct.h b/components/soc/esp32c5/include/soc/gpio_struct.h index 0044e173fc..d8c1203e97 100644 --- a/components/soc/esp32c5/include/soc/gpio_struct.h +++ b/components/soc/esp32c5/include/soc/gpio_struct.h @@ -239,40 +239,40 @@ typedef union { */ typedef union { struct { - /** pinn_sync2_bypass : R/W; bitpos: [1:0]; default: 0; + /** sync2_bypass : R/W; bitpos: [1:0]; default: 0; * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at * posedge. */ - uint32_t pinn_sync2_bypass:2; - /** pinn_pad_driver : R/W; bitpos: [2]; default: 0; + uint32_t sync2_bypass:2; + /** pad_driver : R/W; bitpos: [2]; default: 0; * set this bit to select pad driver. 1:open-drain. 0:normal. */ - uint32_t pinn_pad_driver:1; - /** pinn_sync1_bypass : R/W; bitpos: [4:3]; default: 0; + uint32_t pad_driver:1; + /** sync1_bypass : R/W; bitpos: [4:3]; default: 0; * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at * posedge. */ - uint32_t pinn_sync1_bypass:2; + uint32_t sync1_bypass:2; uint32_t reserved_5:2; - /** pinn_int_type : R/W; bitpos: [9:7]; default: 0; + /** int_type : R/W; bitpos: [9:7]; default: 0; * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid * at high level */ - uint32_t pinn_int_type:3; - /** pinn_wakeup_enable : R/W; bitpos: [10]; default: 0; + uint32_t int_type:3; + /** wakeup_enable : R/W; bitpos: [10]; default: 0; * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) */ - uint32_t pinn_wakeup_enable:1; - /** pinn_config : R/W; bitpos: [12:11]; default: 0; + uint32_t wakeup_enable:1; + /** config : R/W; bitpos: [12:11]; default: 0; * reserved */ - uint32_t pinn_config:2; - /** pinn_int_ena : R/W; bitpos: [17:13]; default: 0; + uint32_t config:2; + /** int_ena : R/W; bitpos: [17:13]; default: 0; * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) * interrupt. */ - uint32_t pinn_int_ena:5; + uint32_t int_ena:5; uint32_t reserved_18:14; }; uint32_t val; @@ -292,2196 +292,57 @@ typedef union { uint32_t val; } gpio_status_next_reg_t; -/** Type of func0_in_sel_cfg register +/** Type of func_in_sel_cfg register * GPIO input function configuration register */ typedef union { struct { - /** func0_in_sel : R/W; bitpos: [5:0]; default: 60; + /** in_sel : R/W; bitpos: [5:0]; default: 60; * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always * high level. s=0x3C: set this port always low level. */ - uint32_t func0_in_sel:6; - /** func0_in_inv_sel : R/W; bitpos: [6]; default: 0; + uint32_t in_sel:6; + /** in_inv_sel : R/W; bitpos: [6]; default: 0; * set this bit to invert input signal. 1:invert. 0:not invert. */ - uint32_t func0_in_inv_sel:1; - /** sig0_in_sel : R/W; bitpos: [7]; default: 0; + uint32_t in_inv_sel:1; + /** sig_in_sel : R/W; bitpos: [7]; default: 0; * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. */ - uint32_t sig0_in_sel:1; + uint32_t sig_in_sel:1; uint32_t reserved_8:24; }; uint32_t val; -} gpio_func0_in_sel_cfg_reg_t; +} gpio_func_in_sel_cfg_reg_t; -/** Type of func6_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func6_in_sel : R/W; bitpos: [5:0]; default: 60; - * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ - uint32_t func6_in_sel:6; - /** func6_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func6_in_inv_sel:1; - /** sig6_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig6_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func6_in_sel_cfg_reg_t; - -/** Type of func7_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func7_in_sel : R/W; bitpos: [5:0]; default: 60; - * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ - uint32_t func7_in_sel:6; - /** func7_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func7_in_inv_sel:1; - /** sig7_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig7_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func7_in_sel_cfg_reg_t; - -/** Type of func8_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func8_in_sel : R/W; bitpos: [5:0]; default: 60; - * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ - uint32_t func8_in_sel:6; - /** func8_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func8_in_inv_sel:1; - /** sig8_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig8_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func8_in_sel_cfg_reg_t; - -/** Type of func9_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func9_in_sel : R/W; bitpos: [5:0]; default: 56; - * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ - uint32_t func9_in_sel:6; - /** func9_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func9_in_inv_sel:1; - /** sig9_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig9_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func9_in_sel_cfg_reg_t; - -/** Type of func10_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func10_in_sel : R/W; bitpos: [5:0]; default: 60; - * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ - uint32_t func10_in_sel:6; - /** func10_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func10_in_inv_sel:1; - /** sig10_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig10_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func10_in_sel_cfg_reg_t; - -/** Type of func11_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func11_in_sel : R/W; bitpos: [5:0]; default: 60; - * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ - uint32_t func11_in_sel:6; - /** func11_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func11_in_inv_sel:1; - /** sig11_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig11_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func11_in_sel_cfg_reg_t; - -/** Type of func12_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func12_in_sel : R/W; bitpos: [5:0]; default: 60; - * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ - uint32_t func12_in_sel:6; - /** func12_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func12_in_inv_sel:1; - /** sig12_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig12_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func12_in_sel_cfg_reg_t; - -/** Type of func13_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func13_in_sel : R/W; bitpos: [5:0]; default: 60; - * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ - uint32_t func13_in_sel:6; - /** func13_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func13_in_inv_sel:1; - /** sig13_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig13_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func13_in_sel_cfg_reg_t; - -/** Type of func14_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func14_in_sel : R/W; bitpos: [5:0]; default: 60; - * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ - uint32_t func14_in_sel:6; - /** func14_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func14_in_inv_sel:1; - /** sig14_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig14_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func14_in_sel_cfg_reg_t; - -/** Type of func15_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func15_in_sel : R/W; bitpos: [5:0]; default: 60; - * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ - uint32_t func15_in_sel:6; - /** func15_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func15_in_inv_sel:1; - /** sig15_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig15_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func15_in_sel_cfg_reg_t; - -/** Type of func16_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func16_in_sel : R/W; bitpos: [5:0]; default: 60; - * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ - uint32_t func16_in_sel:6; - /** func16_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func16_in_inv_sel:1; - /** sig16_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig16_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func16_in_sel_cfg_reg_t; - -/** Type of func17_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func17_in_sel : R/W; bitpos: [5:0]; default: 60; - * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ - uint32_t func17_in_sel:6; - /** func17_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func17_in_inv_sel:1; - /** sig17_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig17_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func17_in_sel_cfg_reg_t; - -/** Type of func19_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func19_in_sel : R/W; bitpos: [5:0]; default: 60; - * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ - uint32_t func19_in_sel:6; - /** func19_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func19_in_inv_sel:1; - /** sig19_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig19_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func19_in_sel_cfg_reg_t; - -/** Type of func21_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func21_in_sel : R/W; bitpos: [5:0]; default: 60; - * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ - uint32_t func21_in_sel:6; - /** func21_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func21_in_inv_sel:1; - /** sig21_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig21_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func21_in_sel_cfg_reg_t; - -/** Type of func22_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func22_in_sel : R/W; bitpos: [5:0]; default: 60; - * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ - uint32_t func22_in_sel:6; - /** func22_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func22_in_inv_sel:1; - /** sig22_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig22_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func22_in_sel_cfg_reg_t; - -/** Type of func23_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func23_in_sel : R/W; bitpos: [5:0]; default: 60; - * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ - uint32_t func23_in_sel:6; - /** func23_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func23_in_inv_sel:1; - /** sig23_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig23_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func23_in_sel_cfg_reg_t; - -/** Type of func24_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func24_in_sel : R/W; bitpos: [5:0]; default: 60; - * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ - uint32_t func24_in_sel:6; - /** func24_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func24_in_inv_sel:1; - /** sig24_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig24_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func24_in_sel_cfg_reg_t; - -/** Type of func28_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func28_in_sel : R/W; bitpos: [5:0]; default: 60; - * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ - uint32_t func28_in_sel:6; - /** func28_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func28_in_inv_sel:1; - /** sig28_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig28_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func28_in_sel_cfg_reg_t; - -/** Type of func29_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func29_in_sel : R/W; bitpos: [5:0]; default: 60; - * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ - uint32_t func29_in_sel:6; - /** func29_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func29_in_inv_sel:1; - /** sig29_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig29_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func29_in_sel_cfg_reg_t; - -/** Type of func30_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func30_in_sel : R/W; bitpos: [5:0]; default: 60; - * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ - uint32_t func30_in_sel:6; - /** func30_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func30_in_inv_sel:1; - /** sig30_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig30_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func30_in_sel_cfg_reg_t; - -/** Type of func31_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func31_in_sel : R/W; bitpos: [5:0]; default: 60; - * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ - uint32_t func31_in_sel:6; - /** func31_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func31_in_inv_sel:1; - /** sig31_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig31_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func31_in_sel_cfg_reg_t; - -/** Type of func32_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func32_in_sel : R/W; bitpos: [5:0]; default: 60; - * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ - uint32_t func32_in_sel:6; - /** func32_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func32_in_inv_sel:1; - /** sig32_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig32_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func32_in_sel_cfg_reg_t; - -/** Type of func33_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func33_in_sel : R/W; bitpos: [5:0]; default: 60; - * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ - uint32_t func33_in_sel:6; - /** func33_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func33_in_inv_sel:1; - /** sig33_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig33_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func33_in_sel_cfg_reg_t; - -/** Type of func34_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func34_in_sel : R/W; bitpos: [5:0]; default: 60; - * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ - uint32_t func34_in_sel:6; - /** func34_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func34_in_inv_sel:1; - /** sig34_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig34_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func34_in_sel_cfg_reg_t; - -/** Type of func35_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func35_in_sel : R/W; bitpos: [5:0]; default: 60; - * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ - uint32_t func35_in_sel:6; - /** func35_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func35_in_inv_sel:1; - /** sig35_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig35_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func35_in_sel_cfg_reg_t; - -/** Type of func40_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func40_in_sel : R/W; bitpos: [5:0]; default: 60; - * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ - uint32_t func40_in_sel:6; - /** func40_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func40_in_inv_sel:1; - /** sig40_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig40_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func40_in_sel_cfg_reg_t; - -/** Type of func41_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func41_in_sel : R/W; bitpos: [5:0]; default: 60; - * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ - uint32_t func41_in_sel:6; - /** func41_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func41_in_inv_sel:1; - /** sig41_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig41_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func41_in_sel_cfg_reg_t; - -/** Type of func42_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func42_in_sel : R/W; bitpos: [5:0]; default: 60; - * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ - uint32_t func42_in_sel:6; - /** func42_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func42_in_inv_sel:1; - /** sig42_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig42_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func42_in_sel_cfg_reg_t; - -/** Type of func45_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func45_in_sel : R/W; bitpos: [5:0]; default: 56; - * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ - uint32_t func45_in_sel:6; - /** func45_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func45_in_inv_sel:1; - /** sig45_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig45_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func45_in_sel_cfg_reg_t; - -/** Type of func46_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func46_in_sel : R/W; bitpos: [5:0]; default: 56; - * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ - uint32_t func46_in_sel:6; - /** func46_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func46_in_inv_sel:1; - /** sig46_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig46_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func46_in_sel_cfg_reg_t; - -/** Type of func47_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func47_in_sel : R/W; bitpos: [5:0]; default: 60; - * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ - uint32_t func47_in_sel:6; - /** func47_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func47_in_inv_sel:1; - /** sig47_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig47_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func47_in_sel_cfg_reg_t; - -/** Type of func48_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func48_in_sel : R/W; bitpos: [5:0]; default: 60; - * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ - uint32_t func48_in_sel:6; - /** func48_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func48_in_inv_sel:1; - /** sig48_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig48_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func48_in_sel_cfg_reg_t; - -/** Type of func49_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func49_in_sel : R/W; bitpos: [5:0]; default: 60; - * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ - uint32_t func49_in_sel:6; - /** func49_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func49_in_inv_sel:1; - /** sig49_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig49_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func49_in_sel_cfg_reg_t; - -/** Type of func50_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func50_in_sel : R/W; bitpos: [5:0]; default: 60; - * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ - uint32_t func50_in_sel:6; - /** func50_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func50_in_inv_sel:1; - /** sig50_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig50_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func50_in_sel_cfg_reg_t; - -/** Type of func51_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func51_in_sel : R/W; bitpos: [5:0]; default: 60; - * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ - uint32_t func51_in_sel:6; - /** func51_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func51_in_inv_sel:1; - /** sig51_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig51_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func51_in_sel_cfg_reg_t; - -/** Type of func52_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func52_in_sel : R/W; bitpos: [5:0]; default: 60; - * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ - uint32_t func52_in_sel:6; - /** func52_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func52_in_inv_sel:1; - /** sig52_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig52_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func52_in_sel_cfg_reg_t; - -/** Type of func53_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func53_in_sel : R/W; bitpos: [5:0]; default: 60; - * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ - uint32_t func53_in_sel:6; - /** func53_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func53_in_inv_sel:1; - /** sig53_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig53_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func53_in_sel_cfg_reg_t; - -/** Type of func54_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func54_in_sel : R/W; bitpos: [5:0]; default: 60; - * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ - uint32_t func54_in_sel:6; - /** func54_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func54_in_inv_sel:1; - /** sig54_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig54_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func54_in_sel_cfg_reg_t; - -/** Type of func63_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func63_in_sel : R/W; bitpos: [5:0]; default: 60; - * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ - uint32_t func63_in_sel:6; - /** func63_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func63_in_inv_sel:1; - /** sig63_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig63_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func63_in_sel_cfg_reg_t; - -/** Type of func64_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func64_in_sel : R/W; bitpos: [5:0]; default: 60; - * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ - uint32_t func64_in_sel:6; - /** func64_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func64_in_inv_sel:1; - /** sig64_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig64_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func64_in_sel_cfg_reg_t; - -/** Type of func65_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func65_in_sel : R/W; bitpos: [5:0]; default: 60; - * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ - uint32_t func65_in_sel:6; - /** func65_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func65_in_inv_sel:1; - /** sig65_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig65_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func65_in_sel_cfg_reg_t; - -/** Type of func66_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func66_in_sel : R/W; bitpos: [5:0]; default: 60; - * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ - uint32_t func66_in_sel:6; - /** func66_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func66_in_inv_sel:1; - /** sig66_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig66_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func66_in_sel_cfg_reg_t; - -/** Type of func67_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func67_in_sel : R/W; bitpos: [5:0]; default: 60; - * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ - uint32_t func67_in_sel:6; - /** func67_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func67_in_inv_sel:1; - /** sig67_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig67_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func67_in_sel_cfg_reg_t; - -/** Type of func68_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func68_in_sel : R/W; bitpos: [5:0]; default: 60; - * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ - uint32_t func68_in_sel:6; - /** func68_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func68_in_inv_sel:1; - /** sig68_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig68_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func68_in_sel_cfg_reg_t; - -/** Type of func69_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func69_in_sel : R/W; bitpos: [5:0]; default: 60; - * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ - uint32_t func69_in_sel:6; - /** func69_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func69_in_inv_sel:1; - /** sig69_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig69_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func69_in_sel_cfg_reg_t; - -/** Type of func70_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func70_in_sel : R/W; bitpos: [5:0]; default: 60; - * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ - uint32_t func70_in_sel:6; - /** func70_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func70_in_inv_sel:1; - /** sig70_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig70_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func70_in_sel_cfg_reg_t; - -/** Type of func71_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func71_in_sel : R/W; bitpos: [5:0]; default: 60; - * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ - uint32_t func71_in_sel:6; - /** func71_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func71_in_inv_sel:1; - /** sig71_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig71_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func71_in_sel_cfg_reg_t; - -/** Type of func72_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func72_in_sel : R/W; bitpos: [5:0]; default: 60; - * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ - uint32_t func72_in_sel:6; - /** func72_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func72_in_inv_sel:1; - /** sig72_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig72_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func72_in_sel_cfg_reg_t; - -/** Type of func73_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func73_in_sel : R/W; bitpos: [5:0]; default: 56; - * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ - uint32_t func73_in_sel:6; - /** func73_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func73_in_inv_sel:1; - /** sig73_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig73_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func73_in_sel_cfg_reg_t; - -/** Type of func77_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func77_in_sel : R/W; bitpos: [5:0]; default: 56; - * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ - uint32_t func77_in_sel:6; - /** func77_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func77_in_inv_sel:1; - /** sig77_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig77_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func77_in_sel_cfg_reg_t; - -/** Type of func81_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func81_in_sel : R/W; bitpos: [5:0]; default: 60; - * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ - uint32_t func81_in_sel:6; - /** func81_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func81_in_inv_sel:1; - /** sig81_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig81_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func81_in_sel_cfg_reg_t; - -/** Type of func82_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func82_in_sel : R/W; bitpos: [5:0]; default: 60; - * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ - uint32_t func82_in_sel:6; - /** func82_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func82_in_inv_sel:1; - /** sig82_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig82_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func82_in_sel_cfg_reg_t; - -/** Type of func83_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func83_in_sel : R/W; bitpos: [5:0]; default: 60; - * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ - uint32_t func83_in_sel:6; - /** func83_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func83_in_inv_sel:1; - /** sig83_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig83_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func83_in_sel_cfg_reg_t; - -/** Type of func84_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func84_in_sel : R/W; bitpos: [5:0]; default: 60; - * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ - uint32_t func84_in_sel:6; - /** func84_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func84_in_inv_sel:1; - /** sig84_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig84_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func84_in_sel_cfg_reg_t; - -/** Type of func85_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func85_in_sel : R/W; bitpos: [5:0]; default: 60; - * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ - uint32_t func85_in_sel:6; - /** func85_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func85_in_inv_sel:1; - /** sig85_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig85_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func85_in_sel_cfg_reg_t; - -/** Type of func86_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func86_in_sel : R/W; bitpos: [5:0]; default: 60; - * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ - uint32_t func86_in_sel:6; - /** func86_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func86_in_inv_sel:1; - /** sig86_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig86_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func86_in_sel_cfg_reg_t; - -/** Type of func87_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func87_in_sel : R/W; bitpos: [5:0]; default: 60; - * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ - uint32_t func87_in_sel:6; - /** func87_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func87_in_inv_sel:1; - /** sig87_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig87_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func87_in_sel_cfg_reg_t; - -/** Type of func88_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func88_in_sel : R/W; bitpos: [5:0]; default: 60; - * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ - uint32_t func88_in_sel:6; - /** func88_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func88_in_inv_sel:1; - /** sig88_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig88_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func88_in_sel_cfg_reg_t; - -/** Type of func89_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func89_in_sel : R/W; bitpos: [5:0]; default: 60; - * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ - uint32_t func89_in_sel:6; - /** func89_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func89_in_inv_sel:1; - /** sig89_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig89_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func89_in_sel_cfg_reg_t; - -/** Type of func90_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func90_in_sel : R/W; bitpos: [5:0]; default: 60; - * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ - uint32_t func90_in_sel:6; - /** func90_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func90_in_inv_sel:1; - /** sig90_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig90_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func90_in_sel_cfg_reg_t; - -/** Type of func91_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func91_in_sel : R/W; bitpos: [5:0]; default: 60; - * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ - uint32_t func91_in_sel:6; - /** func91_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func91_in_inv_sel:1; - /** sig91_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig91_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func91_in_sel_cfg_reg_t; - -/** Type of func92_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func92_in_sel : R/W; bitpos: [5:0]; default: 60; - * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ - uint32_t func92_in_sel:6; - /** func92_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func92_in_inv_sel:1; - /** sig92_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig92_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func92_in_sel_cfg_reg_t; - -/** Type of func93_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func93_in_sel : R/W; bitpos: [5:0]; default: 60; - * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ - uint32_t func93_in_sel:6; - /** func93_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func93_in_inv_sel:1; - /** sig93_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig93_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func93_in_sel_cfg_reg_t; - -/** Type of func94_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func94_in_sel : R/W; bitpos: [5:0]; default: 60; - * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ - uint32_t func94_in_sel:6; - /** func94_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func94_in_inv_sel:1; - /** sig94_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig94_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func94_in_sel_cfg_reg_t; - -/** Type of func95_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func95_in_sel : R/W; bitpos: [5:0]; default: 60; - * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ - uint32_t func95_in_sel:6; - /** func95_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func95_in_inv_sel:1; - /** sig95_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig95_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func95_in_sel_cfg_reg_t; - -/** Type of func97_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func97_in_sel : R/W; bitpos: [5:0]; default: 60; - * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ - uint32_t func97_in_sel:6; - /** func97_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func97_in_inv_sel:1; - /** sig97_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig97_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func97_in_sel_cfg_reg_t; - -/** Type of func98_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func98_in_sel : R/W; bitpos: [5:0]; default: 60; - * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ - uint32_t func98_in_sel:6; - /** func98_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func98_in_inv_sel:1; - /** sig98_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig98_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func98_in_sel_cfg_reg_t; - -/** Type of func99_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func99_in_sel : R/W; bitpos: [5:0]; default: 60; - * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ - uint32_t func99_in_sel:6; - /** func99_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func99_in_inv_sel:1; - /** sig99_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig99_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func99_in_sel_cfg_reg_t; - -/** Type of func100_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func100_in_sel : R/W; bitpos: [5:0]; default: 60; - * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ - uint32_t func100_in_sel:6; - /** func100_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func100_in_inv_sel:1; - /** sig100_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig100_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func100_in_sel_cfg_reg_t; - -/** Type of func101_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func101_in_sel : R/W; bitpos: [5:0]; default: 60; - * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ - uint32_t func101_in_sel:6; - /** func101_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func101_in_inv_sel:1; - /** sig101_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig101_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func101_in_sel_cfg_reg_t; - -/** Type of func102_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func102_in_sel : R/W; bitpos: [5:0]; default: 60; - * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ - uint32_t func102_in_sel:6; - /** func102_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func102_in_inv_sel:1; - /** sig102_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig102_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func102_in_sel_cfg_reg_t; - -/** Type of func103_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func103_in_sel : R/W; bitpos: [5:0]; default: 60; - * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ - uint32_t func103_in_sel:6; - /** func103_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func103_in_inv_sel:1; - /** sig103_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig103_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func103_in_sel_cfg_reg_t; - -/** Type of func104_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func104_in_sel : R/W; bitpos: [5:0]; default: 60; - * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ - uint32_t func104_in_sel:6; - /** func104_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func104_in_inv_sel:1; - /** sig104_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig104_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func104_in_sel_cfg_reg_t; - -/** Type of func105_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func105_in_sel : R/W; bitpos: [5:0]; default: 60; - * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ - uint32_t func105_in_sel:6; - /** func105_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func105_in_inv_sel:1; - /** sig105_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig105_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func105_in_sel_cfg_reg_t; - -/** Type of func106_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func106_in_sel : R/W; bitpos: [5:0]; default: 60; - * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ - uint32_t func106_in_sel:6; - /** func106_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func106_in_inv_sel:1; - /** sig106_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig106_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func106_in_sel_cfg_reg_t; - -/** Type of func107_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func107_in_sel : R/W; bitpos: [5:0]; default: 60; - * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ - uint32_t func107_in_sel:6; - /** func107_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func107_in_inv_sel:1; - /** sig107_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig107_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func107_in_sel_cfg_reg_t; - -/** Type of func108_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func108_in_sel : R/W; bitpos: [5:0]; default: 60; - * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ - uint32_t func108_in_sel:6; - /** func108_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func108_in_inv_sel:1; - /** sig108_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig108_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func108_in_sel_cfg_reg_t; - -/** Type of func109_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func109_in_sel : R/W; bitpos: [5:0]; default: 60; - * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ - uint32_t func109_in_sel:6; - /** func109_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func109_in_inv_sel:1; - /** sig109_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig109_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func109_in_sel_cfg_reg_t; - -/** Type of func110_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func110_in_sel : R/W; bitpos: [5:0]; default: 60; - * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ - uint32_t func110_in_sel:6; - /** func110_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func110_in_inv_sel:1; - /** sig110_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig110_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func110_in_sel_cfg_reg_t; - -/** Type of func111_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func111_in_sel : R/W; bitpos: [5:0]; default: 60; - * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ - uint32_t func111_in_sel:6; - /** func111_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func111_in_inv_sel:1; - /** sig111_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig111_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func111_in_sel_cfg_reg_t; - -/** Type of func112_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func112_in_sel : R/W; bitpos: [5:0]; default: 60; - * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ - uint32_t func112_in_sel:6; - /** func112_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func112_in_inv_sel:1; - /** sig112_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig112_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func112_in_sel_cfg_reg_t; - -/** Type of func113_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func113_in_sel : R/W; bitpos: [5:0]; default: 60; - * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ - uint32_t func113_in_sel:6; - /** func113_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func113_in_inv_sel:1; - /** sig113_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig113_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func113_in_sel_cfg_reg_t; - -/** Type of func114_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func114_in_sel : R/W; bitpos: [5:0]; default: 60; - * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ - uint32_t func114_in_sel:6; - /** func114_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func114_in_inv_sel:1; - /** sig114_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig114_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func114_in_sel_cfg_reg_t; - -/** Type of func115_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func115_in_sel : R/W; bitpos: [5:0]; default: 60; - * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ - uint32_t func115_in_sel:6; - /** func115_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func115_in_inv_sel:1; - /** sig115_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig115_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func115_in_sel_cfg_reg_t; - -/** Type of func116_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func116_in_sel : R/W; bitpos: [5:0]; default: 60; - * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ - uint32_t func116_in_sel:6; - /** func116_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func116_in_inv_sel:1; - /** sig116_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig116_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func116_in_sel_cfg_reg_t; - -/** Type of func117_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func117_in_sel : R/W; bitpos: [5:0]; default: 60; - * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ - uint32_t func117_in_sel:6; - /** func117_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func117_in_inv_sel:1; - /** sig117_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig117_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func117_in_sel_cfg_reg_t; - -/** Type of func118_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func118_in_sel : R/W; bitpos: [5:0]; default: 60; - * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ - uint32_t func118_in_sel:6; - /** func118_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func118_in_inv_sel:1; - /** sig118_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig118_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func118_in_sel_cfg_reg_t; - -/** Type of func119_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func119_in_sel : R/W; bitpos: [5:0]; default: 60; - * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ - uint32_t func119_in_sel:6; - /** func119_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func119_in_inv_sel:1; - /** sig119_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig119_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func119_in_sel_cfg_reg_t; - -/** Type of func120_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func120_in_sel : R/W; bitpos: [5:0]; default: 60; - * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ - uint32_t func120_in_sel:6; - /** func120_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func120_in_inv_sel:1; - /** sig120_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig120_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func120_in_sel_cfg_reg_t; - -/** Type of func121_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func121_in_sel : R/W; bitpos: [5:0]; default: 60; - * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ - uint32_t func121_in_sel:6; - /** func121_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func121_in_inv_sel:1; - /** sig121_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig121_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func121_in_sel_cfg_reg_t; - -/** Type of func122_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func122_in_sel : R/W; bitpos: [5:0]; default: 60; - * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ - uint32_t func122_in_sel:6; - /** func122_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func122_in_inv_sel:1; - /** sig122_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig122_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func122_in_sel_cfg_reg_t; - -/** Type of func123_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func123_in_sel : R/W; bitpos: [5:0]; default: 60; - * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ - uint32_t func123_in_sel:6; - /** func123_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func123_in_inv_sel:1; - /** sig123_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig123_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func123_in_sel_cfg_reg_t; - -/** Type of func124_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func124_in_sel : R/W; bitpos: [5:0]; default: 60; - * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ - uint32_t func124_in_sel:6; - /** func124_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func124_in_inv_sel:1; - /** sig124_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig124_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func124_in_sel_cfg_reg_t; - -/** Type of funcn_out_sel_cfg register +/** Type of func_out_sel_cfg register * GPIO output function select register */ typedef union { struct { - /** funcn_out_sel : R/W/SC; bitpos: [7:0]; default: 128; + /** out_sel : R/W/SC; bitpos: [7:0]; default: 128; * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals * GPIO_OUT_REG[n]. */ - uint32_t funcn_out_sel:8; - /** funcn_out_inv_sel : R/W/SC; bitpos: [8]; default: 0; + uint32_t out_sel:8; + /** out_inv_sel : R/W/SC; bitpos: [8]; default: 0; * set this bit to invert output signal.1:invert.0:not invert. */ - uint32_t funcn_out_inv_sel:1; - /** funcn_oen_sel : R/W; bitpos: [9]; default: 0; + uint32_t out_inv_sel:1; + /** oen_sel : R/W; bitpos: [9]; default: 0; * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output * enable signal.0:use peripheral output enable signal. */ - uint32_t funcn_oen_sel:1; - /** funcn_oen_inv_sel : R/W; bitpos: [10]; default: 0; + uint32_t oen_sel:1; + /** oen_inv_sel : R/W; bitpos: [10]; default: 0; * set this bit to invert output enable signal.1:invert.0:not invert. */ - uint32_t funcn_oen_inv_sel:1; + uint32_t oen_inv_sel:1; uint32_t reserved_11:21; }; uint32_t val; -} gpio_funcn_out_sel_cfg_reg_t; +} gpio_func_out_sel_cfg_reg_t; /** Type of clock_gate register * GPIO clock gate register @@ -2534,116 +395,13 @@ typedef struct gpio_dev_t { volatile gpio_pcpu_nmi_int_reg_t pcpu_nmi_int; volatile gpio_cpusdio_int_reg_t cpusdio_int; uint32_t reserved_068[3]; - volatile gpio_pinn_reg_t pinn[31]; + volatile gpio_pinn_reg_t pin[31]; uint32_t reserved_0f0[23]; volatile gpio_status_next_reg_t status_next; uint32_t reserved_150; - volatile gpio_func0_in_sel_cfg_reg_t func0_in_sel_cfg; - uint32_t reserved_158[5]; - volatile gpio_func6_in_sel_cfg_reg_t func6_in_sel_cfg; - volatile gpio_func7_in_sel_cfg_reg_t func7_in_sel_cfg; - volatile gpio_func8_in_sel_cfg_reg_t func8_in_sel_cfg; - volatile gpio_func9_in_sel_cfg_reg_t func9_in_sel_cfg; - volatile gpio_func10_in_sel_cfg_reg_t func10_in_sel_cfg; - volatile gpio_func11_in_sel_cfg_reg_t func11_in_sel_cfg; - volatile gpio_func12_in_sel_cfg_reg_t func12_in_sel_cfg; - volatile gpio_func13_in_sel_cfg_reg_t func13_in_sel_cfg; - volatile gpio_func14_in_sel_cfg_reg_t func14_in_sel_cfg; - volatile gpio_func15_in_sel_cfg_reg_t func15_in_sel_cfg; - volatile gpio_func16_in_sel_cfg_reg_t func16_in_sel_cfg; - volatile gpio_func17_in_sel_cfg_reg_t func17_in_sel_cfg; - uint32_t reserved_19c; - volatile gpio_func19_in_sel_cfg_reg_t func19_in_sel_cfg; - uint32_t reserved_1a4; - volatile gpio_func21_in_sel_cfg_reg_t func21_in_sel_cfg; - volatile gpio_func22_in_sel_cfg_reg_t func22_in_sel_cfg; - volatile gpio_func23_in_sel_cfg_reg_t func23_in_sel_cfg; - volatile gpio_func24_in_sel_cfg_reg_t func24_in_sel_cfg; - uint32_t reserved_1b8[3]; - volatile gpio_func28_in_sel_cfg_reg_t func28_in_sel_cfg; - volatile gpio_func29_in_sel_cfg_reg_t func29_in_sel_cfg; - volatile gpio_func30_in_sel_cfg_reg_t func30_in_sel_cfg; - volatile gpio_func31_in_sel_cfg_reg_t func31_in_sel_cfg; - volatile gpio_func32_in_sel_cfg_reg_t func32_in_sel_cfg; - volatile gpio_func33_in_sel_cfg_reg_t func33_in_sel_cfg; - volatile gpio_func34_in_sel_cfg_reg_t func34_in_sel_cfg; - volatile gpio_func35_in_sel_cfg_reg_t func35_in_sel_cfg; - uint32_t reserved_1e4[4]; - volatile gpio_func40_in_sel_cfg_reg_t func40_in_sel_cfg; - volatile gpio_func41_in_sel_cfg_reg_t func41_in_sel_cfg; - volatile gpio_func42_in_sel_cfg_reg_t func42_in_sel_cfg; - uint32_t reserved_200[2]; - volatile gpio_func45_in_sel_cfg_reg_t func45_in_sel_cfg; - volatile gpio_func46_in_sel_cfg_reg_t func46_in_sel_cfg; - volatile gpio_func47_in_sel_cfg_reg_t func47_in_sel_cfg; - volatile gpio_func48_in_sel_cfg_reg_t func48_in_sel_cfg; - volatile gpio_func49_in_sel_cfg_reg_t func49_in_sel_cfg; - volatile gpio_func50_in_sel_cfg_reg_t func50_in_sel_cfg; - volatile gpio_func51_in_sel_cfg_reg_t func51_in_sel_cfg; - volatile gpio_func52_in_sel_cfg_reg_t func52_in_sel_cfg; - volatile gpio_func53_in_sel_cfg_reg_t func53_in_sel_cfg; - volatile gpio_func54_in_sel_cfg_reg_t func54_in_sel_cfg; - uint32_t reserved_230[8]; - volatile gpio_func63_in_sel_cfg_reg_t func63_in_sel_cfg; - volatile gpio_func64_in_sel_cfg_reg_t func64_in_sel_cfg; - volatile gpio_func65_in_sel_cfg_reg_t func65_in_sel_cfg; - volatile gpio_func66_in_sel_cfg_reg_t func66_in_sel_cfg; - volatile gpio_func67_in_sel_cfg_reg_t func67_in_sel_cfg; - volatile gpio_func68_in_sel_cfg_reg_t func68_in_sel_cfg; - volatile gpio_func69_in_sel_cfg_reg_t func69_in_sel_cfg; - volatile gpio_func70_in_sel_cfg_reg_t func70_in_sel_cfg; - volatile gpio_func71_in_sel_cfg_reg_t func71_in_sel_cfg; - volatile gpio_func72_in_sel_cfg_reg_t func72_in_sel_cfg; - volatile gpio_func73_in_sel_cfg_reg_t func73_in_sel_cfg; - uint32_t reserved_27c[3]; - volatile gpio_func77_in_sel_cfg_reg_t func77_in_sel_cfg; - uint32_t reserved_28c[3]; - volatile gpio_func81_in_sel_cfg_reg_t func81_in_sel_cfg; - volatile gpio_func82_in_sel_cfg_reg_t func82_in_sel_cfg; - volatile gpio_func83_in_sel_cfg_reg_t func83_in_sel_cfg; - volatile gpio_func84_in_sel_cfg_reg_t func84_in_sel_cfg; - volatile gpio_func85_in_sel_cfg_reg_t func85_in_sel_cfg; - volatile gpio_func86_in_sel_cfg_reg_t func86_in_sel_cfg; - volatile gpio_func87_in_sel_cfg_reg_t func87_in_sel_cfg; - volatile gpio_func88_in_sel_cfg_reg_t func88_in_sel_cfg; - volatile gpio_func89_in_sel_cfg_reg_t func89_in_sel_cfg; - volatile gpio_func90_in_sel_cfg_reg_t func90_in_sel_cfg; - volatile gpio_func91_in_sel_cfg_reg_t func91_in_sel_cfg; - volatile gpio_func92_in_sel_cfg_reg_t func92_in_sel_cfg; - volatile gpio_func93_in_sel_cfg_reg_t func93_in_sel_cfg; - volatile gpio_func94_in_sel_cfg_reg_t func94_in_sel_cfg; - volatile gpio_func95_in_sel_cfg_reg_t func95_in_sel_cfg; - uint32_t reserved_2d4; - volatile gpio_func97_in_sel_cfg_reg_t func97_in_sel_cfg; - volatile gpio_func98_in_sel_cfg_reg_t func98_in_sel_cfg; - volatile gpio_func99_in_sel_cfg_reg_t func99_in_sel_cfg; - volatile gpio_func100_in_sel_cfg_reg_t func100_in_sel_cfg; - volatile gpio_func101_in_sel_cfg_reg_t func101_in_sel_cfg; - volatile gpio_func102_in_sel_cfg_reg_t func102_in_sel_cfg; - volatile gpio_func103_in_sel_cfg_reg_t func103_in_sel_cfg; - volatile gpio_func104_in_sel_cfg_reg_t func104_in_sel_cfg; - volatile gpio_func105_in_sel_cfg_reg_t func105_in_sel_cfg; - volatile gpio_func106_in_sel_cfg_reg_t func106_in_sel_cfg; - volatile gpio_func107_in_sel_cfg_reg_t func107_in_sel_cfg; - volatile gpio_func108_in_sel_cfg_reg_t func108_in_sel_cfg; - volatile gpio_func109_in_sel_cfg_reg_t func109_in_sel_cfg; - volatile gpio_func110_in_sel_cfg_reg_t func110_in_sel_cfg; - volatile gpio_func111_in_sel_cfg_reg_t func111_in_sel_cfg; - volatile gpio_func112_in_sel_cfg_reg_t func112_in_sel_cfg; - volatile gpio_func113_in_sel_cfg_reg_t func113_in_sel_cfg; - volatile gpio_func114_in_sel_cfg_reg_t func114_in_sel_cfg; - volatile gpio_func115_in_sel_cfg_reg_t func115_in_sel_cfg; - volatile gpio_func116_in_sel_cfg_reg_t func116_in_sel_cfg; - volatile gpio_func117_in_sel_cfg_reg_t func117_in_sel_cfg; - volatile gpio_func118_in_sel_cfg_reg_t func118_in_sel_cfg; - volatile gpio_func119_in_sel_cfg_reg_t func119_in_sel_cfg; - volatile gpio_func120_in_sel_cfg_reg_t func120_in_sel_cfg; - volatile gpio_func121_in_sel_cfg_reg_t func121_in_sel_cfg; - volatile gpio_func122_in_sel_cfg_reg_t func122_in_sel_cfg; - volatile gpio_func123_in_sel_cfg_reg_t func123_in_sel_cfg; - volatile gpio_func124_in_sel_cfg_reg_t func124_in_sel_cfg; - uint32_t reserved_348[131]; - volatile gpio_funcn_out_sel_cfg_reg_t funcn_out_sel_cfg[31]; + volatile gpio_func_in_sel_cfg_reg_t func_in_sel_cfg[128]; /* Reserved func: 1-5, 18, 20, 25-27, 36-39, 43-44, 55-62, 74-76, 78-80, 96, 125-127 */ + uint32_t reserved_34b[128]; + volatile gpio_func_out_sel_cfg_reg_t func_out_sel_cfg[31]; uint32_t reserved_5d0[23]; volatile gpio_clock_gate_reg_t clock_gate; uint32_t reserved_630[51]; diff --git a/components/soc/esp32c5/include/soc/huk_struct.h b/components/soc/esp32c5/include/soc/huk_struct.h index 98f7e666b0..ac2002070a 100644 --- a/components/soc/esp32c5/include/soc/huk_struct.h +++ b/components/soc/esp32c5/include/soc/huk_struct.h @@ -146,13 +146,13 @@ typedef union { typedef union { struct { /** start : WT; bitpos: [0]; default: 0; - * Write 1 to continue HUK Generator operation at LOAD/GAIN state. - */ - uint32_t start:1; - /** continue : WT; bitpos: [1]; default: 0; * Write 1 to start HUK Generator at IDLE state. */ - uint32_t continue:1; + uint32_t start:1; + /** conti : WT; bitpos: [1]; default: 0; + * Write 1 to continue HUK Generator operation at LOAD/GAIN state. + */ + uint32_t conti:1; uint32_t reserved_2:30; }; uint32_t val; diff --git a/components/soc/esp32c5/include/soc/hwcrypto_reg.h b/components/soc/esp32c5/include/soc/hwcrypto_reg.h new file mode 100644 index 0000000000..f19f7139e0 --- /dev/null +++ b/components/soc/esp32c5/include/soc/hwcrypto_reg.h @@ -0,0 +1,12 @@ +/* + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include "soc/aes_reg.h" +#include "soc/ds_reg.h" +#include "soc/hmac_reg.h" +#include "soc/rsa_reg.h" +#include "soc/sha_reg.h" diff --git a/components/soc/esp32c5/include/soc/interrupt_matrix_struct.h b/components/soc/esp32c5/include/soc/interrupt_matrix_struct.h index 4688fd1cc9..360ffb7c3c 100644 --- a/components/soc/esp32c5/include/soc/interrupt_matrix_struct.h +++ b/components/soc/esp32c5/include/soc/interrupt_matrix_struct.h @@ -1374,7 +1374,7 @@ typedef struct intmtx_core0_dev_t { volatile interrupt_core0_interrupt_date_reg_t interrupt_date; } interrupt_core0_dev_t; -extern intmtx_core0_dev_t INTMTX; +extern interrupt_core0_dev_t INTMTX; #ifndef __cplusplus _Static_assert(sizeof(interrupt_core0_dev_t) == 0x800, "Invalid size of interrupt_core0_dev_t structure"); diff --git a/components/soc/esp32c5/include/soc/interrupts.h b/components/soc/esp32c5/include/soc/interrupts.h index c3fce37997..de4c19ffa1 100644 --- a/components/soc/esp32c5/include/soc/interrupts.h +++ b/components/soc/esp32c5/include/soc/interrupts.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2018-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -12,26 +12,25 @@ extern "C" { #endif -// TODO: [ESP32C5] IDF-8654, IDF-8655 (inherit from C6) - +// TODO: [ESP32C5] IDF-8654 need update for MP version //Interrupt hardware source table //This table is decided by hardware, don't touch this. typedef enum { - ETS_WIFI_MAC_INTR_SOURCE = 0, /**< interrupt of WiFi MAC, level*/ - ETS_WIFI_MAC_NMI_SOURCE, /**< interrupt of WiFi MAC, NMI, use if MAC have bug to fix in NMI*/ - ETS_WIFI_PWR_INTR_SOURCE, /**< */ - ETS_WIFI_BB_INTR_SOURCE, /**< interrupt of WiFi BB, level, we can do some calibartion*/ - ETS_BT_MAC_INTR_SOURCE, /**< will be cancelled*/ - ETS_BT_BB_INTR_SOURCE, /**< interrupt of BT BB, level*/ - ETS_BT_BB_NMI_SOURCE, /**< interrupt of BT BB, NMI, use if BB have bug to fix in NMI*/ + ETS_WIFI_MAC_INTR_SOURCE, + ETS_WIFI_MAC_NMI_SOURCE, + ETS_WIFI_PWR_INTR_SOURCE, + ETS_WIFI_BB_INTR_SOURCE, + ETS_BT_MAC_INTR_SOURCE, + ETS_BT_BB_INTR_SOURCE, + ETS_BT_BB_NMI_SOURCE, ETS_LP_TIMER_INTR_SOURCE, ETS_COEX_INTR_SOURCE, ETS_BLE_TIMER_INTR_SOURCE, ETS_BLE_SEC_INTR_SOURCE, - ETS_I2C_MASTER_SOURCE, /**< interrupt of I2C Master, level*/ - ETS_ZB_MAC_SOURCE, + ETS_I2C_MST_INTR_SOURCE, + ETS_ZB_MAC_INTR_SOURCE, ETS_PMU_INTR_SOURCE, - ETS_EFUSE_INTR_SOURCE, /**< interrupt of efuse, level, not likely to use*/ + ETS_EFUSE_INTR_SOURCE, ETS_LP_RTC_TIMER_INTR_SOURCE, ETS_LP_UART_INTR_SOURCE, ETS_LP_I2C_INTR_SOURCE, @@ -39,16 +38,18 @@ typedef enum { ETS_LP_PERI_TIMEOUT_INTR_SOURCE, ETS_LP_APM_M0_INTR_SOURCE, ETS_LP_APM_M1_INTR_SOURCE, - ETS_FROM_CPU_INTR0_SOURCE, /**< interrupt0 generated from a CPU, level*/ /* Used for FreeRTOS */ - ETS_FROM_CPU_INTR1_SOURCE, /**< interrupt1 generated from a CPU, level*/ /* Used for FreeRTOS */ - ETS_FROM_CPU_INTR2_SOURCE, /**< interrupt2 generated from a CPU, level*/ - ETS_FROM_CPU_INTR3_SOURCE, /**< interrupt3 generated from a CPU, level*/ - ETS_ASSIST_DEBUG_INTR_SOURCE, /**< interrupt of Assist debug module, LEVEL*/ + ETS_HUK_INTR_SOURCE, + ETS_FROM_CPU_INTR0_SOURCE, + ETS_FROM_CPU_INTR1_SOURCE, + ETS_FROM_CPU_INTR2_SOURCE, + ETS_FROM_CPU_INTR3_SOURCE, + ETS_ASSIST_DEBUG_INTR_SOURCE, ETS_TRACE_INTR_SOURCE, ETS_CACHE_INTR_SOURCE, ETS_CPU_PERI_TIMEOUT_INTR_SOURCE, - ETS_GPIO_INTR_SOURCE, /**< interrupt of GPIO, level*/ - ETS_GPIO_NMI_SOURCE, /**< interrupt of GPIO, NMI*/ + ETS_GPIO_INTR_SOURCE, + ETS_GPIO_NMI_SOURCE, + ETS_GPIO_PAD_COMP_INTR_SOURCE, ETS_PAU_INTR_SOURCE, ETS_HP_PERI_TIMEOUT_INTR_SOURCE, ETS_MODEM_PERI_TIMEOUT_INTR_SOURCE, @@ -58,44 +59,48 @@ typedef enum { ETS_HP_APM_M3_INTR_SOURCE, ETS_LP_APM0_INTR_SOURCE, ETS_MSPI_INTR_SOURCE, - ETS_I2S1_INTR_SOURCE, /**< interrupt of I2S1, level*/ - ETS_UHCI0_INTR_SOURCE, /**< interrupt of UHCI0, level*/ - ETS_UART0_INTR_SOURCE, /**< interrupt of UART0, level*/ - ETS_UART1_INTR_SOURCE, /**< interrupt of UART1, level*/ - ETS_LEDC_INTR_SOURCE, /**< interrupt of LED PWM, level*/ - ETS_TWAI0_INTR_SOURCE, /**< interrupt of twai0, level*/ - ETS_TWAI1_INTR_SOURCE, /**< interrupt of twai1, level*/ - ETS_USB_SERIAL_JTAG_INTR_SOURCE, /**< interrupt of USB, level*/ - ETS_RMT_INTR_SOURCE, /**< interrupt of remote controller, level*/ - ETS_I2C_EXT0_INTR_SOURCE, /**< interrupt of I2C controller1, level*/ - ETS_TG0_T0_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, TIMER0, level*/ - ETS_TG0_T1_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, TIMER1, level*/ - ETS_TG0_WDT_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, WATCH DOG, level*/ - ETS_TG1_T0_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, TIMER0, level*/ - ETS_TG1_T1_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, TIMER1, level*/ - ETS_TG1_WDT_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, WATCHDOG, level*/ - ETS_SYSTIMER_TARGET0_INTR_SOURCE, /**< interrupt of system timer 0 */ - ETS_SYSTIMER_TARGET1_INTR_SOURCE, /**< interrupt of system timer 1 */ - ETS_SYSTIMER_TARGET2_INTR_SOURCE, /**< interrupt of system timer 2 */ - ETS_SYSTIMER_TARGET0_EDGE_INTR_SOURCE = ETS_SYSTIMER_TARGET0_INTR_SOURCE, /**< use ETS_SYSTIMER_TARGET0_INTR_SOURCE */ - ETS_SYSTIMER_TARGET1_EDGE_INTR_SOURCE = ETS_SYSTIMER_TARGET1_INTR_SOURCE, /**< use ETS_SYSTIMER_TARGET1_INTR_SOURCE */ - ETS_SYSTIMER_TARGET2_EDGE_INTR_SOURCE = ETS_SYSTIMER_TARGET2_INTR_SOURCE, /**< use ETS_SYSTIMER_TARGET2_INTR_SOURCE */ - ETS_APB_ADC_INTR_SOURCE = 60, /**< interrupt of APB ADC, LEVEL*/ - ETS_MCPWM0_INTR_SOURCE, /**< interrupt of MCPWM0, LEVEL*/ + ETS_I2S1_INTR_SOURCE, + ETS_UHCI0_INTR_SOURCE, + ETS_UART0_INTR_SOURCE, + ETS_UART1_INTR_SOURCE, + ETS_LEDC_INTR_SOURCE, + ETS_TWAI0_INTR_SOURCE, + ETS_TWAI1_INTR_SOURCE, + ETS_USB_INTR_SOURCE, + ETS_RMT_INTR_SOURCE, + ETS_I2C_EXT0_INTR_SOURCE, + ETS_TG0_T0_LEVEL_INTR_SOURCE, + ETS_TG0_T1_LEVEL_INTR_SOURCE, + ETS_TG0_WDT_LEVEL_INTR_SOURCE, + ETS_TG1_T0_LEVEL_INTR_SOURCE, + ETS_TG1_T1_LEVEL_INTR_SOURCE, + ETS_TG1_WDT_LEVEL_INTR_SOURCE, + ETS_SYSTIMER_TARGET0_INTR_SOURCE, + ETS_SYSTIMER_TARGET1_INTR_SOURCE, + ETS_SYSTIMER_TARGET2_INTR_SOURCE, + ETS_APB_ADC_INTR_SOURCE, + ETS_PWM_INTR_SOURCE, ETS_PCNT_INTR_SOURCE, - ETS_PARL_IO_INTR_SOURCE, + ETS_PARL_IO_TX_INTR_SOURCE, + ETS_PARL_IO_RX_INTR_SOURCE, ETS_SLC0_INTR_SOURCE, - ETS_DMA_IN_CH0_INTR_SOURCE, /**< interrupt of general DMA IN channel 0, LEVEL*/ - ETS_DMA_IN_CH1_INTR_SOURCE, /**< interrupt of general DMA IN channel 1, LEVEL*/ - ETS_DMA_IN_CH2_INTR_SOURCE, /**< interrupt of general DMA IN channel 2, LEVEL*/ - ETS_DMA_OUT_CH0_INTR_SOURCE, /**< interrupt of general DMA OUT channel 0, LEVEL*/ - ETS_DMA_OUT_CH1_INTR_SOURCE, /**< interrupt of general DMA OUT channel 1, LEVEL*/ - ETS_DMA_OUT_CH2_INTR_SOURCE, /**< interrupt of general DMA OUT channel 2, LEVEL*/ - ETS_GSPI2_INTR_SOURCE, - ETS_AES_INTR_SOURCE, /**< interrupt of AES accelerator, level*/ - ETS_SHA_INTR_SOURCE, /**< interrupt of SHA accelerator, level*/ - ETS_RSA_INTR_SOURCE, /**< interrupt of RSA accelerator, level*/ - ETS_ECC_INTR_SOURCE, /**< interrupt of ECC accelerator, level*/ + ETS_SLC1_INTR_SOURCE, + ETS_USB_OTG20_INTR_SOURCE, + ETS_USB_OTG20_MULTI_PROC_INTR_SOURCE, + ETS_USB_OTG20_MISC_INTR_SOURCE, + ETS_DMA_IN_CH0_INTR_SOURCE, + ETS_DMA_IN_CH1_INTR_SOURCE, + ETS_DMA_IN_CH2_INTR_SOURCE, + ETS_DMA_OUT_CH0_INTR_SOURCE, + ETS_DMA_OUT_CH1_INTR_SOURCE, + ETS_DMA_OUT_CH2_INTR_SOURCE, + ETS_GPSPI2_INTR_SOURCE, + ETS_AES_INTR_SOURCE, + ETS_SHA_INTR_SOURCE, + ETS_RSA_INTR_SOURCE, + ETS_ECC_INTR_SOURCE, + ETS_ECDSA_INTR_SOURCE, + ETS_KM_INTR_SOURCE, ETS_MAX_INTR_SOURCE, } periph_interrput_t; diff --git a/components/soc/esp32c5/include/soc/io_mux_reg.h b/components/soc/esp32c5/include/soc/io_mux_reg.h index f97e3c0b44..c2192ba15d 100644 --- a/components/soc/esp32c5/include/soc/io_mux_reg.h +++ b/components/soc/esp32c5/include/soc/io_mux_reg.h @@ -5,12 +5,279 @@ */ #pragma once -#include #include "soc/soc.h" #ifdef __cplusplus extern "C" { #endif +/* The following are the bit fields for PERIPHS_IO_MUX_x_U registers */ +/* Output enable in sleep mode */ +#define SLP_OE (BIT(0)) +#define SLP_OE_M (BIT(0)) +#define SLP_OE_V 1 +#define SLP_OE_S 0 +/* Used to enable sleep mode pin functions */ +#define SLP_SEL (BIT(1)) +#define SLP_SEL_M (BIT(1)) +#define SLP_SEL_V 1 +#define SLP_SEL_S 1 +/* Pulldown enable in sleep mode */ +#define SLP_PD (BIT(2)) +#define SLP_PD_M (BIT(2)) +#define SLP_PD_V 1 +#define SLP_PD_S 2 +/* Pullup enable in sleep mode */ +#define SLP_PU (BIT(3)) +#define SLP_PU_M (BIT(3)) +#define SLP_PU_V 1 +#define SLP_PU_S 3 +/* Input enable in sleep mode */ +#define SLP_IE (BIT(4)) +#define SLP_IE_M (BIT(4)) +#define SLP_IE_V 1 +#define SLP_IE_S 4 +/* Drive strength in sleep mode */ +#define SLP_DRV 0x3 +#define SLP_DRV_M (SLP_DRV_V << SLP_DRV_S) +#define SLP_DRV_V 0x3 +#define SLP_DRV_S 5 +/* Pulldown enable */ +#define FUN_PD (BIT(7)) +#define FUN_PD_M (BIT(7)) +#define FUN_PD_V 1 +#define FUN_PD_S 7 +/* Pullup enable */ +#define FUN_PU (BIT(8)) +#define FUN_PU_M (BIT(8)) +#define FUN_PU_V 1 +#define FUN_PU_S 8 +/* Input enable */ +#define FUN_IE (BIT(9)) +#define FUN_IE_M (FUN_IE_V << FUN_IE_S) +#define FUN_IE_V 1 +#define FUN_IE_S 9 +/* Drive strength */ +#define FUN_DRV 0x3 +#define FUN_DRV_M (FUN_DRV_V << FUN_DRV_S) +#define FUN_DRV_V 0x3 +#define FUN_DRV_S 10 +/* Function select (possible values are defined for each pin as FUNC_pinname_function below) */ +#define MCU_SEL 0x7 +#define MCU_SEL_M (MCU_SEL_V << MCU_SEL_S) +#define MCU_SEL_V 0x7 +#define MCU_SEL_S 12 +/* Pin filter (Pulse width shorter than 2 clock cycles will be filtered out) */ +#define FILTER_EN (BIT(15)) +#define FILTER_EN_M (FILTER_EN_V << FILTER_EN_S) +#define FILTER_EN_V 1 +#define FILTER_EN_S 15 + +#define PIN_SLP_INPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_IE) +#define PIN_SLP_INPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_IE) +#define PIN_SLP_OUTPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_OE) +#define PIN_SLP_OUTPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_OE) +#define PIN_SLP_PULLUP_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_PU) +#define PIN_SLP_PULLUP_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_PU) +#define PIN_SLP_PULLDOWN_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_PD) +#define PIN_SLP_PULLDOWN_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_PD) +#define PIN_SLP_SEL_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_SEL) +#define PIN_SLP_SEL_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_SEL) + +#define PIN_INPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,FUN_IE) +#define PIN_INPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,FUN_IE) +#define PIN_SET_DRV(PIN_NAME, drv) REG_SET_FIELD(PIN_NAME, FUN_DRV, (drv)); +#define PIN_PULLUP_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FUN_PU) +#define PIN_PULLUP_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PU) +#define PIN_PULLDWN_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FUN_PD) +#define PIN_PULLDWN_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PD) +#define PIN_FUNC_SELECT(PIN_NAME, FUNC) REG_SET_FIELD(PIN_NAME, MCU_SEL, FUNC) +#define PIN_FILTER_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FILTER_EN) +#define PIN_FILTER_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FILTER_EN) + +#define PIN_FUNC_GPIO 1 + +#define GPIO_PAD_PULLUP(num) do{PIN_PULLDWN_DIS(IOMUX_REG_GPIO##num);PIN_PULLUP_EN(IOMUX_REG_GPIO##num);}while(0) +#define GPIO_PAD_PULLDOWN(num) do{PIN_PULLUP_DIS(IOMUX_REG_GPIO##num);PIN_PULLDWN_EN(IOMUX_REG_GPIO##num);}while(0) +#define GPIO_PAD_SET_DRV(num, drv) PIN_SET_DRV(IOMUX_REG_GPIO##num, drv) + +#define SPI_HD_GPIO_NUM 28 +#define SPI_WP_GPIO_NUM 26 +#define SPI_CS0_GPIO_NUM 24 +#define SPI_CLK_GPIO_NUM 29 +#define SPI_D_GPIO_NUM 30 +#define SPI_Q_GPIO_NUM 25 + +#define SD_CLK_GPIO_NUM 19 +#define SD_CMD_GPIO_NUM 18 +#define SD_DATA0_GPIO_NUM 20 +#define SD_DATA1_GPIO_NUM 21 +#define SD_DATA2_GPIO_NUM 22 +#define SD_DATA3_GPIO_NUM 23 + +#define USB_INT_PHY0_DM_GPIO_NUM 12 +#define USB_INT_PHY0_DP_GPIO_NUM 13 + +#define EXT_OSC_SLOW_GPIO_NUM 0 + +#define MAX_RTC_GPIO_NUM 8 +#define MAX_PAD_GPIO_NUM 30 +#define MAX_GPIO_NUM 34 +#define DIG_IO_HOLD_BIT_SHIFT 32 + + +#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE +#define PIN_CTRL (REG_IO_MUX_BASE +0x00) + +#define CLK_OUT3 0x1f +#define CLK_OUT3_V CLK_OUT3 +#define CLK_OUT3_S 10 +#define CLK_OUT3_M (CLK_OUT3_V << CLK_OUT3_S) +#define CLK_OUT2 0x1f +#define CLK_OUT2_V CLK_OUT2 +#define CLK_OUT2_S 5 +#define CLK_OUT2_M (CLK_OUT2_V << CLK_OUT2_S) +#define CLK_OUT1 0x1f +#define CLK_OUT1_V CLK_OUT1 +#define CLK_OUT1_S 0 +#define CLK_OUT1_M (CLK_OUT1_V << CLK_OUT1_S) +// definitions above are inherited from previous version of code, should double check + +// definitions below are generated from pin_txt.csv +#define PERIPHS_IO_MUX_XTAL_32K_P_U (REG_IO_MUX_BASE + 0x4) +#define FUNC_XTAL_32K_P_GPIO0 1 +#define FUNC_XTAL_32K_P_GPIO0_0 0 + +#define PERIPHS_IO_MUX_XTAL_32K_N_U (REG_IO_MUX_BASE + 0x8) +#define FUNC_XTAL_32K_N_GPIO1 1 +#define FUNC_XTAL_32K_N_GPIO1_0 0 + +#define PERIPHS_IO_MUX_GPIO2_U (REG_IO_MUX_BASE + 0xC) +#define FUNC_GPIO2_FSPIQ 2 +#define FUNC_GPIO2_GPIO2 1 +#define FUNC_GPIO2_GPIO2_0 0 + +#define PERIPHS_IO_MUX_GPIO3_U (REG_IO_MUX_BASE + 0x10) +#define FUNC_GPIO3_GPIO3 1 +#define FUNC_GPIO3_GPIO3_0 0 + +#define PERIPHS_IO_MUX_MTMS_U (REG_IO_MUX_BASE + 0x14) +#define FUNC_MTMS_FSPIHD 2 +#define FUNC_MTMS_GPIO4 1 +#define FUNC_MTMS_MTMS 0 + +#define PERIPHS_IO_MUX_MTDI_U (REG_IO_MUX_BASE + 0x18) +#define FUNC_MTDI_FSPIWP 2 +#define FUNC_MTDI_GPIO5 1 +#define FUNC_MTDI_MTDI 0 + +#define PERIPHS_IO_MUX_MTCK_U (REG_IO_MUX_BASE + 0x1C) +#define FUNC_MTCK_FSPICLK 2 +#define FUNC_MTCK_GPIO6 1 +#define FUNC_MTCK_MTCK 0 + +#define PERIPHS_IO_MUX_MTDO_U (REG_IO_MUX_BASE + 0x20) +#define FUNC_MTDO_FSPID 2 +#define FUNC_MTDO_GPIO7 1 +#define FUNC_MTDO_MTDO 0 + +#define PERIPHS_IO_MUX_GPIO8_U (REG_IO_MUX_BASE + 0x24) +#define FUNC_GPIO8_GPIO8 1 +#define FUNC_GPIO8_GPIO8_0 0 + +#define PERIPHS_IO_MUX_GPIO9_U (REG_IO_MUX_BASE + 0x28) +#define FUNC_GPIO9_GPIO9 1 +#define FUNC_GPIO9_GPIO9_0 0 + +#define PERIPHS_IO_MUX_GPIO10_U (REG_IO_MUX_BASE + 0x2C) +#define FUNC_GPIO10_GPIO10 1 +#define FUNC_GPIO10_GPIO10_0 0 + +#define PERIPHS_IO_MUX_GPIO11_U (REG_IO_MUX_BASE + 0x30) +#define FUNC_GPIO11_GPIO11 1 +#define FUNC_GPIO11_GPIO11_0 0 + +#define PERIPHS_IO_MUX_GPIO12_U (REG_IO_MUX_BASE + 0x34) +#define FUNC_GPIO12_GPIO12 1 +#define FUNC_GPIO12_GPIO12_0 0 + +#define PERIPHS_IO_MUX_GPIO13_U (REG_IO_MUX_BASE + 0x38) +#define FUNC_GPIO13_GPIO13 1 +#define FUNC_GPIO13_GPIO13_0 0 + +#define PERIPHS_IO_MUX_GPIO14_U (REG_IO_MUX_BASE + 0x3C) +#define FUNC_GPIO14_GPIO14 1 +#define FUNC_GPIO14_GPIO14_0 0 + +#define PERIPHS_IO_MUX_GPIO15_U (REG_IO_MUX_BASE + 0x40) +#define FUNC_GPIO15_GPIO15 1 +#define FUNC_GPIO15_GPIO15_0 0 + +#define PERIPHS_IO_MUX_U0TXD_U (REG_IO_MUX_BASE + 0x44) +#define FUNC_U0TXD_FSPICS0 2 +#define FUNC_U0TXD_GPIO16 1 +#define FUNC_U0TXD_U0TXD 0 + +#define PERIPHS_IO_MUX_U0RXD_U (REG_IO_MUX_BASE + 0x48) +#define FUNC_U0RXD_FSPICS1 2 +#define FUNC_U0RXD_GPIO17 1 +#define FUNC_U0RXD_U0RXD 0 + +#define PERIPHS_IO_MUX_SDIO_CMD_U (REG_IO_MUX_BASE + 0x4C) +#define FUNC_SDIO_CMD_FSPICS2 2 +#define FUNC_SDIO_CMD_GPIO18 1 +#define FUNC_SDIO_CMD_SDIO_CMD 0 + +#define PERIPHS_IO_MUX_SDIO_CLK_U (REG_IO_MUX_BASE + 0x50) +#define FUNC_SDIO_CLK_FSPICS3 2 +#define FUNC_SDIO_CLK_GPIO19 1 +#define FUNC_SDIO_CLK_SDIO_CLK 0 + +#define PERIPHS_IO_MUX_SDIO_DATA0_U (REG_IO_MUX_BASE + 0x54) +#define FUNC_SDIO_DATA0_FSPICS4 2 +#define FUNC_SDIO_DATA0_GPIO20 1 +#define FUNC_SDIO_DATA0_SDIO_DATA0 0 + +#define PERIPHS_IO_MUX_SDIO_DATA1_U (REG_IO_MUX_BASE + 0x58) +#define FUNC_SDIO_DATA1_FSPICS5 2 +#define FUNC_SDIO_DATA1_GPIO21 1 +#define FUNC_SDIO_DATA1_SDIO_DATA1 0 + +#define PERIPHS_IO_MUX_SDIO_DATA2_U (REG_IO_MUX_BASE + 0x5C) +#define FUNC_SDIO_DATA2_GPIO22 1 +#define FUNC_SDIO_DATA2_SDIO_DATA2 0 + +#define PERIPHS_IO_MUX_SDIO_DATA3_U (REG_IO_MUX_BASE + 0x60) +#define FUNC_SDIO_DATA3_GPIO23 1 +#define FUNC_SDIO_DATA3_SDIO_DATA3 0 + +#define PERIPHS_IO_MUX_SPICS0_U (REG_IO_MUX_BASE + 0x64) +#define FUNC_SPICS0_GPIO24 1 +#define FUNC_SPICS0_SPICS0 0 + +#define PERIPHS_IO_MUX_SPIQ_U (REG_IO_MUX_BASE + 0x68) +#define FUNC_SPIQ_GPIO25 1 +#define FUNC_SPIQ_SPIQ 0 + +#define PERIPHS_IO_MUX_SPIWP_U (REG_IO_MUX_BASE + 0x6C) +#define FUNC_SPIWP_GPIO26 1 +#define FUNC_SPIWP_SPIWP 0 + +#define PERIPHS_IO_MUX_VDD_SPI_U (REG_IO_MUX_BASE + 0x70) +#define FUNC_VDD_SPI_GPIO27 1 +#define FUNC_VDD_SPI_GPIO27_0 0 + +#define PERIPHS_IO_MUX_SPIHD_U (REG_IO_MUX_BASE + 0x74) +#define FUNC_SPIHD_GPIO28 1 +#define FUNC_SPIHD_SPIHD 0 + +#define PERIPHS_IO_MUX_SPICLK_U (REG_IO_MUX_BASE + 0x78) +#define FUNC_SPICLK_GPIO29 1 +#define FUNC_SPICLK_SPICLK 0 + +#define PERIPHS_IO_MUX_SPID_U (REG_IO_MUX_BASE + 0x7C) +#define FUNC_SPID_GPIO30 1 +#define FUNC_SPID_SPID 0 + /** IO_MUX_PIN_CTRL_REG register * Clock Output Configuration Register */ diff --git a/components/soc/esp32c5/include/soc/keymng_struct.h b/components/soc/esp32c5/include/soc/keymng_struct.h index b809a7ce27..47f0630b99 100644 --- a/components/soc/esp32c5/include/soc/keymng_struct.h +++ b/components/soc/esp32c5/include/soc/keymng_struct.h @@ -211,13 +211,13 @@ typedef union { typedef union { struct { /** start : WT; bitpos: [0]; default: 0; - * Write 1 to continue Key Manager operation at LOAD/GAIN state. - */ - uint32_t start:1; - /** continue : WT; bitpos: [1]; default: 0; * Write 1 to start Key Manager at IDLE state. */ - uint32_t continue:1; + uint32_t start:1; + /** conti : WT; bitpos: [1]; default: 0; + * Write 1 to continue Key Manager operation at LOAD/GAIN state. + */ + uint32_t conti:1; uint32_t reserved_2:30; }; uint32_t val; @@ -314,7 +314,7 @@ typedef struct keymng_dev_t { volatile keymng_int_st_reg_t int_st; volatile keymng_int_ena_reg_t int_ena; volatile keymng_int_clr_reg_t int_clr; - volatile keymng_static_reg_t static; + volatile keymng_static_reg_t static_cfg; volatile keymng_lock_reg_t lock; volatile keymng_conf_reg_t conf; volatile keymng_start_reg_t start; diff --git a/components/soc/esp32c5/include/soc/lp_uart_struct.h b/components/soc/esp32c5/include/soc/lp_uart_struct.h index 7500b302af..fe19862be7 100644 --- a/components/soc/esp32c5/include/soc/lp_uart_struct.h +++ b/components/soc/esp32c5/include/soc/lp_uart_struct.h @@ -1116,7 +1116,8 @@ typedef struct lp_uart_dev_t { volatile lp_uart_id_reg_t id; } lp_uart_dev_t; -extern lp_uart_dev_t LP_UART; +// We map the LP_UART instance to the uart_dev_t struct for convinience of using the same HAL/LL. See soc/uart_struct.h +// extern lp_uart_dev_t LP_UART; #ifndef __cplusplus _Static_assert(sizeof(lp_uart_dev_t) == 0xa0, "Invalid size of lp_uart_dev_t structure"); diff --git a/components/soc/esp32c5/include/soc/lp_wdt_struct.h b/components/soc/esp32c5/include/soc/lp_wdt_struct.h index 4e0ee847bd..7772b8f88c 100644 --- a/components/soc/esp32c5/include/soc/lp_wdt_struct.h +++ b/components/soc/esp32c5/include/soc/lp_wdt_struct.h @@ -16,7 +16,14 @@ extern "C" { */ typedef union { struct { - uint32_t reserved_0:9; + /** wdt_chip_reset_width : R/W; bitpos: [7:0]; default: 20; + * need_des + */ + uint32_t wdt_chip_reset_width:8; + /** wdt_chip_reset_en : R/W; bitpos: [8]; default: 0; + * need_des + */ + uint32_t wdt_chip_reset_en:1; /** wdt_pause_in_slp : R/W; bitpos: [9]; default: 1; * need_des */ diff --git a/components/soc/esp32c5/include/soc/pcr_reg.h b/components/soc/esp32c5/include/soc/pcr_reg.h index 58cebfed8c..cab98fdda2 100644 --- a/components/soc/esp32c5/include/soc/pcr_reg.h +++ b/components/soc/esp32c5/include/soc/pcr_reg.h @@ -1839,6 +1839,20 @@ extern "C" { * CPU_WAITI configuration register */ #define PCR_CPU_WAITI_CONF_REG (DR_REG_PCR_BASE + 0x110) +/** PCR_CPUPERIOD_SEL : HRO; bitpos: [1:0]; default: 1; + * Reserved. This filed has been replaced by PCR_CPU_DIV_NUM + */ +#define PCR_CPUPERIOD_SEL 0x00000003U +#define PCR_CPUPERIOD_SEL_M (PCR_CPUPERIOD_SEL_V << PCR_CPUPERIOD_SEL_S) +#define PCR_CPUPERIOD_SEL_V 0x00000003U +#define PCR_CPUPERIOD_SEL_S 0 +/** PCR_PLL_FREQ_SEL : HRO; bitpos: [2]; default: 1; + * Reserved. This filed has been replaced by PCR_CPU_DIV_NUM + */ +#define PCR_PLL_FREQ_SEL (BIT(2)) +#define PCR_PLL_FREQ_SEL_M (PCR_PLL_FREQ_SEL_V << PCR_PLL_FREQ_SEL_S) +#define PCR_PLL_FREQ_SEL_V 0x00000001U +#define PCR_PLL_FREQ_SEL_S 2 /** PCR_CPU_WAIT_MODE_FORCE_ON : R/W; bitpos: [3]; default: 1; * Set 1 to force cpu_waiti_clk enable. */ @@ -2207,6 +2221,32 @@ extern "C" { #define PCR_SEC_RST_EN_V 0x00000001U #define PCR_SEC_RST_EN_S 2 +/** PCR_ADC_DAC_INV_PHASE_CONF_REG register + * xxxx + */ +#define PCR_ADC_DAC_INV_PHASE_CONF_REG (DR_REG_PCR_BASE + 0x140) +/** PCR_CLK_RX_ADC_INV_PHASE_ENA : R/W; bitpos: [0]; default: 0; + * xxxx + */ +#define PCR_CLK_RX_ADC_INV_PHASE_ENA (BIT(0)) +#define PCR_CLK_RX_ADC_INV_PHASE_ENA_M (PCR_CLK_RX_ADC_INV_PHASE_ENA_V << PCR_CLK_RX_ADC_INV_PHASE_ENA_S) +#define PCR_CLK_RX_ADC_INV_PHASE_ENA_V 0x00000001U +#define PCR_CLK_RX_ADC_INV_PHASE_ENA_S 0 +/** PCR_CLK_TX_DAC_INV_PHASE_ENA : R/W; bitpos: [1]; default: 0; + * xxxx + */ +#define PCR_CLK_TX_DAC_INV_PHASE_ENA (BIT(1)) +#define PCR_CLK_TX_DAC_INV_PHASE_ENA_M (PCR_CLK_TX_DAC_INV_PHASE_ENA_V << PCR_CLK_TX_DAC_INV_PHASE_ENA_S) +#define PCR_CLK_TX_DAC_INV_PHASE_ENA_V 0x00000001U +#define PCR_CLK_TX_DAC_INV_PHASE_ENA_S 1 +/** PCR_CLK_PWDET_ADC_INV_PHASE_ENA : R/W; bitpos: [2]; default: 0; + * xxxx + */ +#define PCR_CLK_PWDET_ADC_INV_PHASE_ENA (BIT(2)) +#define PCR_CLK_PWDET_ADC_INV_PHASE_ENA_M (PCR_CLK_PWDET_ADC_INV_PHASE_ENA_V << PCR_CLK_PWDET_ADC_INV_PHASE_ENA_S) +#define PCR_CLK_PWDET_ADC_INV_PHASE_ENA_V 0x00000001U +#define PCR_CLK_PWDET_ADC_INV_PHASE_ENA_S 2 + /** PCR_BUS_CLK_UPDATE_REG register * xxxx */ @@ -2445,6 +2485,55 @@ extern "C" { #define PCR_KM_READY_V 0x00000001U #define PCR_KM_READY_S 2 +/** PCR_RESET_EVENT_BYPASS_REG register + * reset event bypass backdoor configuration register + */ +#define PCR_RESET_EVENT_BYPASS_REG (DR_REG_PCR_BASE + 0xff0) +/** PCR_RESET_EVENT_BYPASS_APM : R/W; bitpos: [0]; default: 0; + * This field is used to control reset event relationship for + * tee_reg/apm_reg/hp_system_reg. 1: tee_reg/apm_reg/hp_system_reg will only be reset + * by power-reset. some reset event will be bypass. 0: tee_reg/apm_reg/hp_system_reg + * will not only be reset by power-reset, but also some reset event. + */ +#define PCR_RESET_EVENT_BYPASS_APM (BIT(0)) +#define PCR_RESET_EVENT_BYPASS_APM_M (PCR_RESET_EVENT_BYPASS_APM_V << PCR_RESET_EVENT_BYPASS_APM_S) +#define PCR_RESET_EVENT_BYPASS_APM_V 0x00000001U +#define PCR_RESET_EVENT_BYPASS_APM_S 0 +/** PCR_RESET_EVENT_BYPASS : R/W; bitpos: [1]; default: 1; + * This field is used to control reset event relationship for system-bus. 1: system + * bus (including arbiter/router) will only be reset by power-reset. some reset event + * will be bypass. 0: system bus (including arbiter/router) will not only be reset by + * power-reset, but also some reset event. + */ +#define PCR_RESET_EVENT_BYPASS (BIT(1)) +#define PCR_RESET_EVENT_BYPASS_M (PCR_RESET_EVENT_BYPASS_V << PCR_RESET_EVENT_BYPASS_S) +#define PCR_RESET_EVENT_BYPASS_V 0x00000001U +#define PCR_RESET_EVENT_BYPASS_S 1 + +/** PCR_FPGA_DEBUG_REG register + * fpga debug register + */ +#define PCR_FPGA_DEBUG_REG (DR_REG_PCR_BASE + 0xff4) +/** PCR_FPGA_DEBUG : R/W; bitpos: [31:0]; default: 4294967295; + * Only used in fpga debug. + */ +#define PCR_FPGA_DEBUG 0xFFFFFFFFU +#define PCR_FPGA_DEBUG_M (PCR_FPGA_DEBUG_V << PCR_FPGA_DEBUG_S) +#define PCR_FPGA_DEBUG_V 0xFFFFFFFFU +#define PCR_FPGA_DEBUG_S 0 + +/** PCR_CLOCK_GATE_REG register + * PCR clock gating configure register + */ +#define PCR_CLOCK_GATE_REG (DR_REG_PCR_BASE + 0xff8) +/** PCR_CLK_EN : R/W; bitpos: [0]; default: 0; + * Set this bit as 1 to force on clock gating. + */ +#define PCR_CLK_EN (BIT(0)) +#define PCR_CLK_EN_M (PCR_CLK_EN_V << PCR_CLK_EN_S) +#define PCR_CLK_EN_V 0x00000001U +#define PCR_CLK_EN_S 0 + /** PCR_DATE_REG register * Date register. */ diff --git a/components/soc/esp32c5/include/soc/pmu_icg_mapping.h b/components/soc/esp32c5/include/soc/pmu_icg_mapping.h new file mode 100644 index 0000000000..c4b995c52a --- /dev/null +++ b/components/soc/esp32c5/include/soc/pmu_icg_mapping.h @@ -0,0 +1,68 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef _SOC_ICG_MAP_H_ +#define _SOC_ICG_MAP_H_ + +#define PMU_ICG_APB_ENA_CAN0 18 +#define PMU_ICG_APB_ENA_CAN1 19 +#define PMU_ICG_APB_ENA_GDMA 1 +#define PMU_ICG_APB_ENA_I2C 13 +#define PMU_ICG_APB_ENA_I2S 4 +#define PMU_ICG_APB_ENA_INTMTX 3 +#define PMU_ICG_APB_ENA_IOMUX 26 +#define PMU_ICG_APB_ENA_LEDC 14 +#define PMU_ICG_APB_ENA_MEM_MONITOR 25 +#define PMU_ICG_APB_ENA_MSPI 5 +#define PMU_ICG_APB_ENA_PARL 23 +#define PMU_ICG_APB_ENA_PCNT 20 +#define PMU_ICG_APB_ENA_PVT_MONITOR 27 +#define PMU_ICG_APB_ENA_PWM 21 +#define PMU_ICG_APB_ENA_REGDMA 24 +#define PMU_ICG_APB_ENA_RMT 15 +#define PMU_ICG_APB_ENA_SARADC 9 +#define PMU_ICG_APB_ENA_SEC 0 +#define PMU_ICG_APB_ENA_SOC_ETM 22 +#define PMU_ICG_APB_ENA_SPI2 2 +#define PMU_ICG_APB_ENA_SYSTIMER 16 +#define PMU_ICG_APB_ENA_TG0 11 +#define PMU_ICG_APB_ENA_TG1 12 +#define PMU_ICG_APB_ENA_UART0 6 +#define PMU_ICG_APB_ENA_UART1 7 +#define PMU_ICG_APB_ENA_UHCI 8 +#define PMU_ICG_APB_ENA_USB_DEVICE 17 +#define PMU_ICG_FUNC_ENA_CAN0 31 +#define PMU_ICG_FUNC_ENA_CAN1 30 +#define PMU_ICG_FUNC_ENA_I2C 29 +#define PMU_ICG_FUNC_ENA_I2S_RX 2 +#define PMU_ICG_FUNC_ENA_I2S_TX 7 +#define PMU_ICG_FUNC_ENA_IOMUX 28 +#define PMU_ICG_FUNC_ENA_LEDC 27 +#define PMU_ICG_FUNC_ENA_MEM_MONITOR 10 +#define PMU_ICG_FUNC_ENA_MSPI 26 +#define PMU_ICG_FUNC_ENA_PARL_RX 25 +#define PMU_ICG_FUNC_ENA_PARL_TX 24 +#define PMU_ICG_FUNC_ENA_PVT_MONITOR 23 +#define PMU_ICG_FUNC_ENA_PWM 22 +#define PMU_ICG_FUNC_ENA_RMT 21 +#define PMU_ICG_FUNC_ENA_SARADC 20 +#define PMU_ICG_FUNC_ENA_SEC 19 +#define PMU_ICG_FUNC_ENA_SPI2 1 +#define PMU_ICG_FUNC_ENA_SYSTIMER 18 +#define PMU_ICG_FUNC_ENA_TG0 14 +#define PMU_ICG_FUNC_ENA_TG1 13 +#define PMU_ICG_FUNC_ENA_TSENS 12 +#define PMU_ICG_FUNC_ENA_UART0 3 +#define PMU_ICG_FUNC_ENA_UART1 4 +#define PMU_ICG_FUNC_ENA_USB_DEVICE 6 +#define PMU_ICG_FUNC_ENA_GDMA 0 +#define PMU_ICG_FUNC_ENA_SOC_ETM 16 +#define PMU_ICG_FUNC_ENA_REGDMA 8 +#define PMU_ICG_FUNC_ENA_RETENTION 9 +#define PMU_ICG_FUNC_ENA_SDIO_SLAVE 11 +#define PMU_ICG_FUNC_ENA_UHCI 5 +#define PMU_ICG_FUNC_ENA_HPCORE 17 +#define PMU_ICG_FUNC_ENA_HPBUS 15 +#endif /* _SOC_ICG_MAP_H_ */ diff --git a/components/soc/esp32c5/include/soc/pmu_struct.h b/components/soc/esp32c5/include/soc/pmu_struct.h index 15c140e2c8..5d06311895 100644 --- a/components/soc/esp32c5/include/soc/pmu_struct.h +++ b/components/soc/esp32c5/include/soc/pmu_struct.h @@ -1,2785 +1,754 @@ /** - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ #pragma once #include +#include #ifdef __cplusplus extern "C" { #endif -/** Group: configure_register */ -/** Type of hp_active_dig_power register - * need_des - */ +#include "soc.h" +#include "soc/pmu_reg.h" + typedef union { struct { - uint32_t reserved_0:21; - /** hp_active_vdd_spi_pd_en : R/W; bitpos: [21]; default: 0; - * need_des - */ - uint32_t hp_active_vdd_spi_pd_en:1; - /** hp_active_hp_mem_dslp : R/W; bitpos: [22]; default: 0; - * need_des - */ - uint32_t hp_active_hp_mem_dslp:1; - /** hp_active_pd_hp_mem_pd_en : R/W; bitpos: [26:23]; default: 0; - * need_des - */ - uint32_t hp_active_pd_hp_mem_pd_en:4; - /** hp_active_pd_hp_wifi_pd_en : R/W; bitpos: [27]; default: 0; - * need_des - */ - uint32_t hp_active_pd_hp_wifi_pd_en:1; - uint32_t reserved_28:1; - /** hp_active_pd_hp_cpu_pd_en : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t hp_active_pd_hp_cpu_pd_en:1; - /** hp_active_pd_hp_aon_pd_en : R/W; bitpos: [30]; default: 0; - * need_des - */ - uint32_t hp_active_pd_hp_aon_pd_en:1; - /** hp_active_pd_top_pd_en : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t hp_active_pd_top_pd_en:1; + uint32_t reserved0 : 21; + uint32_t vdd_spi_pd_en: 1; + uint32_t mem_dslp : 1; + uint32_t mem_pd_en : 4; + uint32_t wifi_pd_en : 1; + uint32_t reserved1 : 1; + uint32_t cpu_pd_en : 1; + uint32_t aon_pd_en : 1; + uint32_t top_pd_en : 1; }; uint32_t val; -} pmu_hp_active_dig_power_reg_t; +} pmu_hp_dig_power_reg_t; -/** Type of hp_active_icg_hp_func register - * need_des - */ typedef union { struct { - /** hp_active_dig_icg_func_en : R/W; bitpos: [31:0]; default: 4294967295; - * need_des - */ - uint32_t hp_active_dig_icg_func_en:32; + uint32_t reserved0: 30; + uint32_t code : 2; }; uint32_t val; -} pmu_hp_active_icg_hp_func_reg_t; +} pmu_hp_icg_modem_reg_t; -/** Type of hp_active_icg_hp_apb register - * need_des - */ typedef union { struct { - /** hp_active_dig_icg_apb_en : R/W; bitpos: [31:0]; default: 4294967295; - * need_des - */ - uint32_t hp_active_dig_icg_apb_en:32; + uint32_t reserved0 : 24; + uint32_t uart_wakeup_en : 1; + uint32_t lp_pad_hold_all: 1; + uint32_t hp_pad_hold_all: 1; + uint32_t dig_pad_slp_sel: 1; + uint32_t dig_pause_wdt : 1; + uint32_t dig_cpu_stall : 1; + uint32_t reserved1 : 2; }; uint32_t val; -} pmu_hp_active_icg_hp_apb_reg_t; +} pmu_hp_sys_cntl_reg_t; -/** Type of hp_active_icg_modem register - * need_des - */ typedef union { struct { - uint32_t reserved_0:30; - /** hp_active_dig_icg_modem_code : R/W; bitpos: [31:30]; default: 0; - * need_des - */ - uint32_t hp_active_dig_icg_modem_code:2; + uint32_t reserved0 : 26; + uint32_t i2c_iso_en : 1; + uint32_t i2c_retention: 1; + uint32_t xpd_bb_i2c : 1; + uint32_t xpd_bbpll_i2c: 1; + uint32_t xpd_bbpll : 1; + uint32_t reserved1 : 1; }; uint32_t val; -} pmu_hp_active_icg_modem_reg_t; +} pmu_hp_clk_power_reg_t; -/** Type of hp_active_hp_sys_cntl register - * need_des - */ typedef union { struct { - uint32_t reserved_0:24; - /** hp_active_uart_wakeup_en : R/W; bitpos: [24]; default: 0; - * need_des - */ - uint32_t hp_active_uart_wakeup_en:1; - /** hp_active_lp_pad_hold_all : R/W; bitpos: [25]; default: 0; - * need_des - */ - uint32_t hp_active_lp_pad_hold_all:1; - /** hp_active_hp_pad_hold_all : R/W; bitpos: [26]; default: 0; - * need_des - */ - uint32_t hp_active_hp_pad_hold_all:1; - /** hp_active_dig_pad_slp_sel : R/W; bitpos: [27]; default: 0; - * need_des - */ - uint32_t hp_active_dig_pad_slp_sel:1; - /** hp_active_dig_pause_wdt : R/W; bitpos: [28]; default: 0; - * need_des - */ - uint32_t hp_active_dig_pause_wdt:1; - /** hp_active_dig_cpu_stall : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t hp_active_dig_cpu_stall:1; - uint32_t reserved_30:2; + uint32_t reserved0 : 25; + uint32_t xpd_bias : 1; + uint32_t dbg_atten : 4; + uint32_t pd_cur : 1; + uint32_t bias_sleep: 1; }; uint32_t val; -} pmu_hp_active_hp_sys_cntl_reg_t; +} pmu_hp_bias_reg_t; -/** Type of hp_active_hp_ck_power register - * need_des - */ typedef union { - struct { - uint32_t reserved_0:26; - /** hp_active_i2c_iso_en : R/W; bitpos: [26]; default: 0; - * need_des - */ - uint32_t hp_active_i2c_iso_en:1; - /** hp_active_i2c_retention : R/W; bitpos: [27]; default: 0; - * need_des - */ - uint32_t hp_active_i2c_retention:1; - /** hp_active_xpd_bb_i2c : R/W; bitpos: [28]; default: 0; - * need_des - */ - uint32_t hp_active_xpd_bb_i2c:1; - /** hp_active_xpd_bbpll_i2c : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t hp_active_xpd_bbpll_i2c:1; - /** hp_active_xpd_bbpll : R/W; bitpos: [30]; default: 0; - * need_des - */ - uint32_t hp_active_xpd_bbpll:1; - uint32_t reserved_31:1; + struct { /* HP: Active State */ + uint32_t reserved0 : 4; + uint32_t hp_sleep2active_backup_modem_clk_code: 2; + uint32_t hp_modem2active_backup_modem_clk_code: 2; + uint32_t reserved1 : 2; + uint32_t hp_active_retention_mode : 1; + uint32_t hp_sleep2active_retention_en : 1; + uint32_t hp_modem2active_retention_en : 1; + uint32_t reserved2 : 1; + uint32_t hp_sleep2active_backup_clk_sel : 2; + uint32_t hp_modem2active_backup_clk_sel : 2; + uint32_t reserved3 : 2; + uint32_t hp_sleep2active_backup_mode : 3; + uint32_t hp_modem2active_backup_mode : 3; + uint32_t reserved4 : 3; + uint32_t hp_sleep2active_backup_en : 1; + uint32_t hp_modem2active_backup_en : 1; + uint32_t reserved5 : 1; + }; + struct { /* HP: Modem State */ + uint32_t reserved6 : 4; + uint32_t hp_sleep2modem_backup_modem_clk_code : 2; + uint32_t reserved7 : 4; + uint32_t hp_modem_retention_mode : 1; + uint32_t hp_sleep2modem_retention_en : 1; + uint32_t reserved8 : 2; + uint32_t hp_sleep2modem_backup_clk_sel : 2; + uint32_t reserved9 : 4; + uint32_t hp_sleep2modem_backup_mode : 3; + uint32_t reserved10 : 6; + uint32_t hp_sleep2modem_backup_en : 1; + uint32_t reserved11 : 2; + }; + struct { /* HP: Sleep State */ + uint32_t reserved12 : 6; + uint32_t hp_modem2sleep_backup_modem_clk_code : 2; + uint32_t hp_active2sleep_backup_modem_clk_code: 2; + uint32_t hp_sleep_retention_mode : 1; + uint32_t reserved13 : 1; + uint32_t hp_modem2sleep_retention_en : 1; + uint32_t hp_active2sleep_retention_en : 1; + uint32_t reserved14 : 2; + uint32_t hp_modem2sleep_backup_clk_sel : 2; + uint32_t hp_active2sleep_backup_clk_sel : 2; + uint32_t reserved15 : 3; + uint32_t hp_modem2sleep_backup_mode : 3; + uint32_t hp_active2sleep_backup_mode : 3; + uint32_t reserved16 : 1; + uint32_t hp_modem2sleep_backup_en : 1; + uint32_t hp_active2sleep_backup_en : 1; }; uint32_t val; -} pmu_hp_active_hp_ck_power_reg_t; +} pmu_hp_backup_reg_t; -/** Type of hp_active_bias register - * need_des - */ typedef union { struct { - uint32_t reserved_0:25; - /** hp_active_xpd_bias : R/W; bitpos: [25]; default: 0; - * need_des - */ - uint32_t hp_active_xpd_bias:1; - /** hp_active_dbg_atten : R/W; bitpos: [29:26]; default: 0; - * need_des - */ - uint32_t hp_active_dbg_atten:4; - /** hp_active_pd_cur : R/W; bitpos: [30]; default: 0; - * need_des - */ - uint32_t hp_active_pd_cur:1; - /** hp_active_bias_sleep : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t hp_active_bias_sleep:1; + uint32_t reserved0 : 26; + uint32_t dig_sysclk_nodiv: 1; + uint32_t icg_sysclk_en : 1; + uint32_t sysclk_slp_sel : 1; + uint32_t icg_slp_sel : 1; + uint32_t dig_sysclk_sel : 2; }; uint32_t val; -} pmu_hp_active_bias_reg_t; +} pmu_hp_sysclk_reg_t; -/** Type of hp_active_backup register - * need_des - */ typedef union { struct { - uint32_t reserved_0:4; - /** hp_sleep2active_backup_modem_clk_code : R/W; bitpos: [5:4]; default: 0; - * need_des - */ - uint32_t hp_sleep2active_backup_modem_clk_code:2; - /** hp_modem2active_backup_modem_clk_code : R/W; bitpos: [7:6]; default: 0; - * need_des - */ - uint32_t hp_modem2active_backup_modem_clk_code:2; - uint32_t reserved_8:2; - /** hp_active_retention_mode : R/W; bitpos: [10]; default: 0; - * need_des - */ - uint32_t hp_active_retention_mode:1; - /** hp_sleep2active_retention_en : R/W; bitpos: [11]; default: 0; - * need_des - */ - uint32_t hp_sleep2active_retention_en:1; - /** hp_modem2active_retention_en : R/W; bitpos: [12]; default: 0; - * need_des - */ - uint32_t hp_modem2active_retention_en:1; - uint32_t reserved_13:1; - /** hp_sleep2active_backup_clk_sel : R/W; bitpos: [15:14]; default: 0; - * need_des - */ - uint32_t hp_sleep2active_backup_clk_sel:2; - /** hp_modem2active_backup_clk_sel : R/W; bitpos: [17:16]; default: 0; - * need_des - */ - uint32_t hp_modem2active_backup_clk_sel:2; - uint32_t reserved_18:2; - /** hp_sleep2active_backup_mode : R/W; bitpos: [22:20]; default: 0; - * need_des - */ - uint32_t hp_sleep2active_backup_mode:3; - /** hp_modem2active_backup_mode : R/W; bitpos: [25:23]; default: 0; - * need_des - */ - uint32_t hp_modem2active_backup_mode:3; - uint32_t reserved_26:3; - /** hp_sleep2active_backup_en : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t hp_sleep2active_backup_en:1; - /** hp_modem2active_backup_en : R/W; bitpos: [30]; default: 0; - * need_des - */ - uint32_t hp_modem2active_backup_en:1; - uint32_t reserved_31:1; + uint32_t reserved0 : 4; /* Only HP_ACTIVE modem under hp system is valid */ + uint32_t lp_dbias_vol : 5; /* Only HP_ACTIVE modem under hp system is valid */ + uint32_t hp_dbias_vol : 5; /* Only HP_ACTIVE modem under hp system is valid */ + uint32_t dbias_sel : 1; /* Only HP_ACTIVE modem under hp system is valid */ + uint32_t dbias_init : 1; /* Only HP_ACTIVE modem under hp system is valid */ + uint32_t slp_mem_xpd : 1; + uint32_t slp_logic_xpd : 1; + uint32_t xpd : 1; + uint32_t slp_mem_dbias : 4; + uint32_t slp_logic_dbias: 4; + uint32_t dbias : 5; }; uint32_t val; -} pmu_hp_active_backup_reg_t; +} pmu_hp_regulator0_reg_t; -/** Type of hp_active_backup_clk register - * need_des - */ typedef union { struct { - /** hp_active_backup_icg_func_en : R/W; bitpos: [31:0]; default: 0; - * need_des - */ - uint32_t hp_active_backup_icg_func_en:32; + uint32_t reserved0: 8; + uint32_t drv_b : 24; }; uint32_t val; -} pmu_hp_active_backup_clk_reg_t; +} pmu_hp_regulator1_reg_t; -/** Type of hp_active_sysclk register - * need_des - */ typedef union { struct { - uint32_t reserved_0:26; - /** hp_active_dig_sys_clk_no_div : R/W; bitpos: [26]; default: 0; - * need_des - */ - uint32_t hp_active_dig_sys_clk_no_div:1; - /** hp_active_icg_sys_clock_en : R/W; bitpos: [27]; default: 0; - * need_des - */ - uint32_t hp_active_icg_sys_clock_en:1; - /** hp_active_sys_clk_slp_sel : R/W; bitpos: [28]; default: 0; - * need_des - */ - uint32_t hp_active_sys_clk_slp_sel:1; - /** hp_active_icg_slp_sel : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t hp_active_icg_slp_sel:1; - /** hp_active_dig_sys_clk_sel : R/W; bitpos: [31:30]; default: 0; - * need_des - */ - uint32_t hp_active_dig_sys_clk_sel:2; + uint32_t reserved0: 31; + uint32_t xpd_xtal : 1; }; uint32_t val; -} pmu_hp_active_sysclk_reg_t; +} pmu_hp_xtal_reg_t; -/** Type of hp_active_hp_regulator0 register - * need_des - */ +typedef struct pmu_hp_hw_regmap_t{ + pmu_hp_dig_power_reg_t dig_power; + uint32_t icg_func; + uint32_t icg_apb; + pmu_hp_icg_modem_reg_t icg_modem; + pmu_hp_sys_cntl_reg_t syscntl; + pmu_hp_clk_power_reg_t clk_power; + pmu_hp_bias_reg_t bias; + pmu_hp_backup_reg_t backup; + uint32_t backup_clk; + pmu_hp_sysclk_reg_t sysclk; + pmu_hp_regulator0_reg_t regulator0; + pmu_hp_regulator1_reg_t regulator1; + pmu_hp_xtal_reg_t xtal; +} pmu_hp_hw_regmap_t; + +/** */ typedef union { struct { - uint32_t reserved_0:4; - /** lp_dbias_vol : RO; bitpos: [8:4]; default: 24; - * need_des - */ - uint32_t lp_dbias_vol:5; - /** hp_dbias_vol : RO; bitpos: [13:9]; default: 24; - * need_des - */ - uint32_t hp_dbias_vol:5; - /** dig_regulator0_dbias_sel : R/W; bitpos: [14]; default: 1; - * need_des - */ - uint32_t dig_regulator0_dbias_sel:1; - /** dig_dbias_init : WT; bitpos: [15]; default: 0; - * need_des - */ - uint32_t dig_dbias_init:1; - /** hp_active_hp_regulator_slp_mem_xpd : R/W; bitpos: [16]; default: 1; - * need_des - */ - uint32_t hp_active_hp_regulator_slp_mem_xpd:1; - /** hp_active_hp_regulator_slp_logic_xpd : R/W; bitpos: [17]; default: 1; - * need_des - */ - uint32_t hp_active_hp_regulator_slp_logic_xpd:1; - /** hp_active_hp_regulator_xpd : R/W; bitpos: [18]; default: 1; - * need_des - */ - uint32_t hp_active_hp_regulator_xpd:1; - /** hp_active_hp_regulator_slp_mem_dbias : R/W; bitpos: [22:19]; default: 12; - * need_des - */ - uint32_t hp_active_hp_regulator_slp_mem_dbias:4; - /** hp_active_hp_regulator_slp_logic_dbias : R/W; bitpos: [26:23]; default: 12; - * need_des - */ - uint32_t hp_active_hp_regulator_slp_logic_dbias:4; - /** hp_active_hp_regulator_dbias : R/W; bitpos: [31:27]; default: 24; - * need_des - */ - uint32_t hp_active_hp_regulator_dbias:5; + uint32_t reserved0: 21; + uint32_t slp_xpd : 1; + uint32_t xpd : 1; + uint32_t slp_dbias: 4; + uint32_t dbias : 5; }; uint32_t val; -} pmu_hp_active_hp_regulator0_reg_t; +} pmu_lp_regulator0_reg_t; -/** Type of hp_active_hp_regulator1 register - * need_des - */ typedef union { struct { - uint32_t reserved_0:8; - /** hp_active_hp_regulator_drv_b : R/W; bitpos: [31:8]; default: 0; - * need_des - */ - uint32_t hp_active_hp_regulator_drv_b:24; + uint32_t reserved0: 28; + uint32_t drv_b : 4; }; uint32_t val; -} pmu_hp_active_hp_regulator1_reg_t; +} pmu_lp_regulator1_reg_t; -/** Type of hp_active_xtal register - * need_des - */ typedef union { struct { - uint32_t reserved_0:31; - /** hp_active_xpd_xtal : R/W; bitpos: [31]; default: 1; - * need_des - */ - uint32_t hp_active_xpd_xtal:1; + uint32_t reserved0: 31; + uint32_t xpd_xtal : 1; }; uint32_t val; -} pmu_hp_active_xtal_reg_t; +} pmu_lp_xtal_reg_t; -/** Type of hp_modem_dig_power register - * need_des - */ typedef union { struct { - uint32_t reserved_0:21; - /** hp_modem_vdd_spi_pd_en : R/W; bitpos: [21]; default: 0; - * need_des - */ - uint32_t hp_modem_vdd_spi_pd_en:1; - /** hp_modem_hp_mem_dslp : R/W; bitpos: [22]; default: 0; - * need_des - */ - uint32_t hp_modem_hp_mem_dslp:1; - /** hp_modem_pd_hp_mem_pd_en : R/W; bitpos: [26:23]; default: 0; - * need_des - */ - uint32_t hp_modem_pd_hp_mem_pd_en:4; - /** hp_modem_pd_hp_wifi_pd_en : R/W; bitpos: [27]; default: 0; - * need_des - */ - uint32_t hp_modem_pd_hp_wifi_pd_en:1; - uint32_t reserved_28:1; - /** hp_modem_pd_hp_cpu_pd_en : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t hp_modem_pd_hp_cpu_pd_en:1; - /** hp_modem_pd_hp_aon_pd_en : R/W; bitpos: [30]; default: 0; - * need_des - */ - uint32_t hp_modem_pd_hp_aon_pd_en:1; - /** hp_modem_pd_top_pd_en : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t hp_modem_pd_top_pd_en:1; + uint32_t reserved0 : 30; + uint32_t mem_dslp : 1; + uint32_t peri_pd_en: 1; }; uint32_t val; -} pmu_hp_modem_dig_power_reg_t; +} pmu_lp_dig_power_reg_t; -/** Type of hp_modem_icg_hp_func register - * need_des - */ typedef union { struct { - /** hp_modem_dig_icg_func_en : R/W; bitpos: [31:0]; default: 4294967295; - * need_des - */ - uint32_t hp_modem_dig_icg_func_en:32; + uint32_t reserved0 : 28; + uint32_t xpd_xtal32k: 1; + uint32_t xpd_rc32k : 1; + uint32_t xpd_fosc : 1; + uint32_t pd_osc : 1; }; uint32_t val; -} pmu_hp_modem_icg_hp_func_reg_t; +} pmu_lp_clk_power_reg_t; -/** Type of hp_modem_icg_hp_apb register - * need_des - */ typedef union { struct { - /** hp_modem_dig_icg_apb_en : R/W; bitpos: [31:0]; default: 4294967295; - * need_des - */ - uint32_t hp_modem_dig_icg_apb_en:32; + uint32_t reserved0 : 25; + uint32_t xpd_bias : 1; + uint32_t dbg_atten : 4; + uint32_t pd_cur : 1; + uint32_t bias_sleep: 1; }; uint32_t val; -} pmu_hp_modem_icg_hp_apb_reg_t; +} pmu_lp_bias_reg_t; + +typedef struct pmu_lp_hw_regmap_t{ + pmu_lp_regulator0_reg_t regulator0; + pmu_lp_regulator1_reg_t regulator1; + pmu_lp_xtal_reg_t xtal; /* Only LP_SLEEP mode under lp system is valid */ + pmu_lp_dig_power_reg_t dig_power; + pmu_lp_clk_power_reg_t clk_power; + pmu_lp_bias_reg_t bias; /* Only LP_SLEEP mode under lp system is valid */ +} pmu_lp_hw_regmap_t; + -/** Type of hp_modem_icg_modem register - * need_des - */ typedef union { struct { - uint32_t reserved_0:30; - /** hp_modem_dig_icg_modem_code : R/W; bitpos: [31:30]; default: 0; - * need_des - */ - uint32_t hp_modem_dig_icg_modem_code:2; + uint32_t tie_low_global_bbpll_icg : 1; + uint32_t tie_low_global_xtal_icg : 1; + uint32_t tie_low_i2c_retention : 1; + uint32_t tie_low_xpd_bb_i2c : 1; + uint32_t tie_low_xpd_bbpll_i2c : 1; + uint32_t tie_low_xpd_bbpll : 1; + uint32_t tie_low_xpd_xtal : 1; + uint32_t reserved0 : 18; + uint32_t tie_high_global_bbpll_icg: 1; + uint32_t tie_high_global_xtal_icg : 1; + uint32_t tie_high_i2c_retention : 1; + uint32_t tie_high_xpd_bb_i2c : 1; + uint32_t tie_high_xpd_bbpll_i2c : 1; + uint32_t tie_high_xpd_bbpll : 1; + uint32_t tie_high_xpd_xtal : 1; }; uint32_t val; -} pmu_hp_modem_icg_modem_reg_t; +} pmu_imm_hp_clk_power_reg_t; -/** Type of hp_modem_hp_sys_cntl register - * need_des - */ typedef union { struct { - uint32_t reserved_0:24; - /** hp_modem_uart_wakeup_en : R/W; bitpos: [24]; default: 0; - * need_des - */ - uint32_t hp_modem_uart_wakeup_en:1; - /** hp_modem_lp_pad_hold_all : R/W; bitpos: [25]; default: 0; - * need_des - */ - uint32_t hp_modem_lp_pad_hold_all:1; - /** hp_modem_hp_pad_hold_all : R/W; bitpos: [26]; default: 0; - * need_des - */ - uint32_t hp_modem_hp_pad_hold_all:1; - /** hp_modem_dig_pad_slp_sel : R/W; bitpos: [27]; default: 0; - * need_des - */ - uint32_t hp_modem_dig_pad_slp_sel:1; - /** hp_modem_dig_pause_wdt : R/W; bitpos: [28]; default: 0; - * need_des - */ - uint32_t hp_modem_dig_pause_wdt:1; - /** hp_modem_dig_cpu_stall : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t hp_modem_dig_cpu_stall:1; - uint32_t reserved_30:2; - }; - uint32_t val; -} pmu_hp_modem_hp_sys_cntl_reg_t; - -/** Type of hp_modem_hp_ck_power register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:26; - /** hp_modem_i2c_iso_en : R/W; bitpos: [26]; default: 0; - * need_des - */ - uint32_t hp_modem_i2c_iso_en:1; - /** hp_modem_i2c_retention : R/W; bitpos: [27]; default: 0; - * need_des - */ - uint32_t hp_modem_i2c_retention:1; - /** hp_modem_xpd_bb_i2c : R/W; bitpos: [28]; default: 0; - * need_des - */ - uint32_t hp_modem_xpd_bb_i2c:1; - /** hp_modem_xpd_bbpll_i2c : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t hp_modem_xpd_bbpll_i2c:1; - /** hp_modem_xpd_bbpll : R/W; bitpos: [30]; default: 0; - * need_des - */ - uint32_t hp_modem_xpd_bbpll:1; - uint32_t reserved_31:1; - }; - uint32_t val; -} pmu_hp_modem_hp_ck_power_reg_t; - -/** Type of hp_modem_bias register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:25; - /** hp_modem_xpd_bias : R/W; bitpos: [25]; default: 0; - * need_des - */ - uint32_t hp_modem_xpd_bias:1; - /** hp_modem_dbg_atten : R/W; bitpos: [29:26]; default: 0; - * need_des - */ - uint32_t hp_modem_dbg_atten:4; - /** hp_modem_pd_cur : R/W; bitpos: [30]; default: 0; - * need_des - */ - uint32_t hp_modem_pd_cur:1; - /** hp_modem_bias_sleep : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t hp_modem_bias_sleep:1; - }; - uint32_t val; -} pmu_hp_modem_bias_reg_t; - -/** Type of hp_modem_backup register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:4; - /** hp_sleep2modem_backup_modem_clk_code : R/W; bitpos: [5:4]; default: 0; - * need_des - */ - uint32_t hp_sleep2modem_backup_modem_clk_code:2; - uint32_t reserved_6:4; - /** hp_modem_retention_mode : R/W; bitpos: [10]; default: 0; - * need_des - */ - uint32_t hp_modem_retention_mode:1; - /** hp_sleep2modem_retention_en : R/W; bitpos: [11]; default: 0; - * need_des - */ - uint32_t hp_sleep2modem_retention_en:1; - uint32_t reserved_12:2; - /** hp_sleep2modem_backup_clk_sel : R/W; bitpos: [15:14]; default: 0; - * need_des - */ - uint32_t hp_sleep2modem_backup_clk_sel:2; - uint32_t reserved_16:4; - /** hp_sleep2modem_backup_mode : R/W; bitpos: [22:20]; default: 0; - * need_des - */ - uint32_t hp_sleep2modem_backup_mode:3; - uint32_t reserved_23:6; - /** hp_sleep2modem_backup_en : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t hp_sleep2modem_backup_en:1; - uint32_t reserved_30:2; - }; - uint32_t val; -} pmu_hp_modem_backup_reg_t; - -/** Type of hp_modem_backup_clk register - * need_des - */ -typedef union { - struct { - /** hp_modem_backup_icg_func_en : R/W; bitpos: [31:0]; default: 0; - * need_des - */ - uint32_t hp_modem_backup_icg_func_en:32; - }; - uint32_t val; -} pmu_hp_modem_backup_clk_reg_t; - -/** Type of hp_modem_sysclk register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:26; - /** hp_modem_dig_sys_clk_no_div : R/W; bitpos: [26]; default: 0; - * need_des - */ - uint32_t hp_modem_dig_sys_clk_no_div:1; - /** hp_modem_icg_sys_clock_en : R/W; bitpos: [27]; default: 0; - * need_des - */ - uint32_t hp_modem_icg_sys_clock_en:1; - /** hp_modem_sys_clk_slp_sel : R/W; bitpos: [28]; default: 0; - * need_des - */ - uint32_t hp_modem_sys_clk_slp_sel:1; - /** hp_modem_icg_slp_sel : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t hp_modem_icg_slp_sel:1; - /** hp_modem_dig_sys_clk_sel : R/W; bitpos: [31:30]; default: 0; - * need_des - */ - uint32_t hp_modem_dig_sys_clk_sel:2; - }; - uint32_t val; -} pmu_hp_modem_sysclk_reg_t; - -/** Type of hp_modem_hp_regulator0 register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:16; - /** hp_modem_hp_regulator_slp_mem_xpd : R/W; bitpos: [16]; default: 1; - * need_des - */ - uint32_t hp_modem_hp_regulator_slp_mem_xpd:1; - /** hp_modem_hp_regulator_slp_logic_xpd : R/W; bitpos: [17]; default: 1; - * need_des - */ - uint32_t hp_modem_hp_regulator_slp_logic_xpd:1; - /** hp_modem_hp_regulator_xpd : R/W; bitpos: [18]; default: 1; - * need_des - */ - uint32_t hp_modem_hp_regulator_xpd:1; - /** hp_modem_hp_regulator_slp_mem_dbias : R/W; bitpos: [22:19]; default: 12; - * need_des - */ - uint32_t hp_modem_hp_regulator_slp_mem_dbias:4; - /** hp_modem_hp_regulator_slp_logic_dbias : R/W; bitpos: [26:23]; default: 12; - * need_des - */ - uint32_t hp_modem_hp_regulator_slp_logic_dbias:4; - /** hp_modem_hp_regulator_dbias : R/W; bitpos: [31:27]; default: 24; - * need_des - */ - uint32_t hp_modem_hp_regulator_dbias:5; - }; - uint32_t val; -} pmu_hp_modem_hp_regulator0_reg_t; - -/** Type of hp_modem_hp_regulator1 register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:8; - /** hp_modem_hp_regulator_drv_b : R/W; bitpos: [31:8]; default: 0; - * need_des - */ - uint32_t hp_modem_hp_regulator_drv_b:24; - }; - uint32_t val; -} pmu_hp_modem_hp_regulator1_reg_t; - -/** Type of hp_modem_xtal register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:31; - /** hp_modem_xpd_xtal : R/W; bitpos: [31]; default: 1; - * need_des - */ - uint32_t hp_modem_xpd_xtal:1; - }; - uint32_t val; -} pmu_hp_modem_xtal_reg_t; - -/** Type of hp_sleep_dig_power register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:21; - /** hp_sleep_vdd_spi_pd_en : R/W; bitpos: [21]; default: 0; - * need_des - */ - uint32_t hp_sleep_vdd_spi_pd_en:1; - /** hp_sleep_hp_mem_dslp : R/W; bitpos: [22]; default: 0; - * need_des - */ - uint32_t hp_sleep_hp_mem_dslp:1; - /** hp_sleep_pd_hp_mem_pd_en : R/W; bitpos: [26:23]; default: 0; - * need_des - */ - uint32_t hp_sleep_pd_hp_mem_pd_en:4; - /** hp_sleep_pd_hp_wifi_pd_en : R/W; bitpos: [27]; default: 0; - * need_des - */ - uint32_t hp_sleep_pd_hp_wifi_pd_en:1; - uint32_t reserved_28:1; - /** hp_sleep_pd_hp_cpu_pd_en : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t hp_sleep_pd_hp_cpu_pd_en:1; - /** hp_sleep_pd_hp_aon_pd_en : R/W; bitpos: [30]; default: 0; - * need_des - */ - uint32_t hp_sleep_pd_hp_aon_pd_en:1; - /** hp_sleep_pd_top_pd_en : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t hp_sleep_pd_top_pd_en:1; - }; - uint32_t val; -} pmu_hp_sleep_dig_power_reg_t; - -/** Type of hp_sleep_icg_hp_func register - * need_des - */ -typedef union { - struct { - /** hp_sleep_dig_icg_func_en : R/W; bitpos: [31:0]; default: 4294967295; - * need_des - */ - uint32_t hp_sleep_dig_icg_func_en:32; - }; - uint32_t val; -} pmu_hp_sleep_icg_hp_func_reg_t; - -/** Type of hp_sleep_icg_hp_apb register - * need_des - */ -typedef union { - struct { - /** hp_sleep_dig_icg_apb_en : R/W; bitpos: [31:0]; default: 4294967295; - * need_des - */ - uint32_t hp_sleep_dig_icg_apb_en:32; - }; - uint32_t val; -} pmu_hp_sleep_icg_hp_apb_reg_t; - -/** Type of hp_sleep_icg_modem register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:30; - /** hp_sleep_dig_icg_modem_code : R/W; bitpos: [31:30]; default: 0; - * need_des - */ - uint32_t hp_sleep_dig_icg_modem_code:2; - }; - uint32_t val; -} pmu_hp_sleep_icg_modem_reg_t; - -/** Type of hp_sleep_hp_sys_cntl register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:24; - /** hp_sleep_uart_wakeup_en : R/W; bitpos: [24]; default: 0; - * need_des - */ - uint32_t hp_sleep_uart_wakeup_en:1; - /** hp_sleep_lp_pad_hold_all : R/W; bitpos: [25]; default: 0; - * need_des - */ - uint32_t hp_sleep_lp_pad_hold_all:1; - /** hp_sleep_hp_pad_hold_all : R/W; bitpos: [26]; default: 0; - * need_des - */ - uint32_t hp_sleep_hp_pad_hold_all:1; - /** hp_sleep_dig_pad_slp_sel : R/W; bitpos: [27]; default: 0; - * need_des - */ - uint32_t hp_sleep_dig_pad_slp_sel:1; - /** hp_sleep_dig_pause_wdt : R/W; bitpos: [28]; default: 0; - * need_des - */ - uint32_t hp_sleep_dig_pause_wdt:1; - /** hp_sleep_dig_cpu_stall : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t hp_sleep_dig_cpu_stall:1; - uint32_t reserved_30:2; - }; - uint32_t val; -} pmu_hp_sleep_hp_sys_cntl_reg_t; - -/** Type of hp_sleep_hp_ck_power register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:26; - /** hp_sleep_i2c_iso_en : R/W; bitpos: [26]; default: 0; - * need_des - */ - uint32_t hp_sleep_i2c_iso_en:1; - /** hp_sleep_i2c_retention : R/W; bitpos: [27]; default: 0; - * need_des - */ - uint32_t hp_sleep_i2c_retention:1; - /** hp_sleep_xpd_bb_i2c : R/W; bitpos: [28]; default: 0; - * need_des - */ - uint32_t hp_sleep_xpd_bb_i2c:1; - /** hp_sleep_xpd_bbpll_i2c : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t hp_sleep_xpd_bbpll_i2c:1; - /** hp_sleep_xpd_bbpll : R/W; bitpos: [30]; default: 0; - * need_des - */ - uint32_t hp_sleep_xpd_bbpll:1; - uint32_t reserved_31:1; - }; - uint32_t val; -} pmu_hp_sleep_hp_ck_power_reg_t; - -/** Type of hp_sleep_bias register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:25; - /** hp_sleep_xpd_bias : R/W; bitpos: [25]; default: 0; - * need_des - */ - uint32_t hp_sleep_xpd_bias:1; - /** hp_sleep_dbg_atten : R/W; bitpos: [29:26]; default: 0; - * need_des - */ - uint32_t hp_sleep_dbg_atten:4; - /** hp_sleep_pd_cur : R/W; bitpos: [30]; default: 0; - * need_des - */ - uint32_t hp_sleep_pd_cur:1; - /** hp_sleep_bias_sleep : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t hp_sleep_bias_sleep:1; - }; - uint32_t val; -} pmu_hp_sleep_bias_reg_t; - -/** Type of hp_sleep_backup register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:6; - /** hp_modem2sleep_backup_modem_clk_code : R/W; bitpos: [7:6]; default: 0; - * need_des - */ - uint32_t hp_modem2sleep_backup_modem_clk_code:2; - /** hp_active2sleep_backup_modem_clk_code : R/W; bitpos: [9:8]; default: 0; - * need_des - */ - uint32_t hp_active2sleep_backup_modem_clk_code:2; - /** hp_sleep_retention_mode : R/W; bitpos: [10]; default: 0; - * need_des - */ - uint32_t hp_sleep_retention_mode:1; - uint32_t reserved_11:1; - /** hp_modem2sleep_retention_en : R/W; bitpos: [12]; default: 0; - * need_des - */ - uint32_t hp_modem2sleep_retention_en:1; - /** hp_active2sleep_retention_en : R/W; bitpos: [13]; default: 0; - * need_des - */ - uint32_t hp_active2sleep_retention_en:1; - uint32_t reserved_14:2; - /** hp_modem2sleep_backup_clk_sel : R/W; bitpos: [17:16]; default: 0; - * need_des - */ - uint32_t hp_modem2sleep_backup_clk_sel:2; - /** hp_active2sleep_backup_clk_sel : R/W; bitpos: [19:18]; default: 0; - * need_des - */ - uint32_t hp_active2sleep_backup_clk_sel:2; - uint32_t reserved_20:3; - /** hp_modem2sleep_backup_mode : R/W; bitpos: [25:23]; default: 0; - * need_des - */ - uint32_t hp_modem2sleep_backup_mode:3; - /** hp_active2sleep_backup_mode : R/W; bitpos: [28:26]; default: 0; - * need_des - */ - uint32_t hp_active2sleep_backup_mode:3; - uint32_t reserved_29:1; - /** hp_modem2sleep_backup_en : R/W; bitpos: [30]; default: 0; - * need_des - */ - uint32_t hp_modem2sleep_backup_en:1; - /** hp_active2sleep_backup_en : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t hp_active2sleep_backup_en:1; - }; - uint32_t val; -} pmu_hp_sleep_backup_reg_t; - -/** Type of hp_sleep_backup_clk register - * need_des - */ -typedef union { - struct { - /** hp_sleep_backup_icg_func_en : R/W; bitpos: [31:0]; default: 0; - * need_des - */ - uint32_t hp_sleep_backup_icg_func_en:32; - }; - uint32_t val; -} pmu_hp_sleep_backup_clk_reg_t; - -/** Type of hp_sleep_sysclk register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:26; - /** hp_sleep_dig_sys_clk_no_div : R/W; bitpos: [26]; default: 0; - * need_des - */ - uint32_t hp_sleep_dig_sys_clk_no_div:1; - /** hp_sleep_icg_sys_clock_en : R/W; bitpos: [27]; default: 0; - * need_des - */ - uint32_t hp_sleep_icg_sys_clock_en:1; - /** hp_sleep_sys_clk_slp_sel : R/W; bitpos: [28]; default: 0; - * need_des - */ - uint32_t hp_sleep_sys_clk_slp_sel:1; - /** hp_sleep_icg_slp_sel : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t hp_sleep_icg_slp_sel:1; - /** hp_sleep_dig_sys_clk_sel : R/W; bitpos: [31:30]; default: 0; - * need_des - */ - uint32_t hp_sleep_dig_sys_clk_sel:2; - }; - uint32_t val; -} pmu_hp_sleep_sysclk_reg_t; - -/** Type of hp_sleep_hp_regulator0 register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:16; - /** hp_sleep_hp_regulator_slp_mem_xpd : R/W; bitpos: [16]; default: 1; - * need_des - */ - uint32_t hp_sleep_hp_regulator_slp_mem_xpd:1; - /** hp_sleep_hp_regulator_slp_logic_xpd : R/W; bitpos: [17]; default: 1; - * need_des - */ - uint32_t hp_sleep_hp_regulator_slp_logic_xpd:1; - /** hp_sleep_hp_regulator_xpd : R/W; bitpos: [18]; default: 1; - * need_des - */ - uint32_t hp_sleep_hp_regulator_xpd:1; - /** hp_sleep_hp_regulator_slp_mem_dbias : R/W; bitpos: [22:19]; default: 12; - * need_des - */ - uint32_t hp_sleep_hp_regulator_slp_mem_dbias:4; - /** hp_sleep_hp_regulator_slp_logic_dbias : R/W; bitpos: [26:23]; default: 12; - * need_des - */ - uint32_t hp_sleep_hp_regulator_slp_logic_dbias:4; - /** hp_sleep_hp_regulator_dbias : R/W; bitpos: [31:27]; default: 24; - * need_des - */ - uint32_t hp_sleep_hp_regulator_dbias:5; - }; - uint32_t val; -} pmu_hp_sleep_hp_regulator0_reg_t; - -/** Type of hp_sleep_hp_regulator1 register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:8; - /** hp_sleep_hp_regulator_drv_b : R/W; bitpos: [31:8]; default: 0; - * need_des - */ - uint32_t hp_sleep_hp_regulator_drv_b:24; - }; - uint32_t val; -} pmu_hp_sleep_hp_regulator1_reg_t; - -/** Type of hp_sleep_xtal register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:31; - /** hp_sleep_xpd_xtal : R/W; bitpos: [31]; default: 1; - * need_des - */ - uint32_t hp_sleep_xpd_xtal:1; - }; - uint32_t val; -} pmu_hp_sleep_xtal_reg_t; - -/** Type of hp_sleep_lp_regulator0 register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:21; - /** hp_sleep_lp_regulator_slp_xpd : R/W; bitpos: [21]; default: 1; - * need_des - */ - uint32_t hp_sleep_lp_regulator_slp_xpd:1; - /** hp_sleep_lp_regulator_xpd : R/W; bitpos: [22]; default: 1; - * need_des - */ - uint32_t hp_sleep_lp_regulator_xpd:1; - /** hp_sleep_lp_regulator_slp_dbias : R/W; bitpos: [26:23]; default: 12; - * need_des - */ - uint32_t hp_sleep_lp_regulator_slp_dbias:4; - /** hp_sleep_lp_regulator_dbias : R/W; bitpos: [31:27]; default: 24; - * need_des - */ - uint32_t hp_sleep_lp_regulator_dbias:5; - }; - uint32_t val; -} pmu_hp_sleep_lp_regulator0_reg_t; - -/** Type of hp_sleep_lp_regulator1 register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:28; - /** hp_sleep_lp_regulator_drv_b : R/W; bitpos: [31:28]; default: 0; - * need_des - */ - uint32_t hp_sleep_lp_regulator_drv_b:4; - }; - uint32_t val; -} pmu_hp_sleep_lp_regulator1_reg_t; - -/** Type of hp_sleep_lp_dig_power register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:30; - /** hp_sleep_lp_mem_dslp : R/W; bitpos: [30]; default: 0; - * need_des - */ - uint32_t hp_sleep_lp_mem_dslp:1; - /** hp_sleep_pd_lp_peri_pd_en : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t hp_sleep_pd_lp_peri_pd_en:1; - }; - uint32_t val; -} pmu_hp_sleep_lp_dig_power_reg_t; - -/** Type of hp_sleep_lp_ck_power register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:28; - /** hp_sleep_xpd_xtal32k : R/W; bitpos: [28]; default: 0; - * need_des - */ - uint32_t hp_sleep_xpd_xtal32k:1; - /** hp_sleep_xpd_rc32k : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t hp_sleep_xpd_rc32k:1; - /** hp_sleep_xpd_fosc_clk : R/W; bitpos: [30]; default: 1; - * need_des - */ - uint32_t hp_sleep_xpd_fosc_clk:1; - /** hp_sleep_pd_osc_clk : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t hp_sleep_pd_osc_clk:1; - }; - uint32_t val; -} pmu_hp_sleep_lp_ck_power_reg_t; - -/** Type of lp_sleep_lp_regulator0 register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:21; - /** lp_sleep_lp_regulator_slp_xpd : R/W; bitpos: [21]; default: 1; - * need_des - */ - uint32_t lp_sleep_lp_regulator_slp_xpd:1; - /** lp_sleep_lp_regulator_xpd : R/W; bitpos: [22]; default: 1; - * need_des - */ - uint32_t lp_sleep_lp_regulator_xpd:1; - /** lp_sleep_lp_regulator_slp_dbias : R/W; bitpos: [26:23]; default: 12; - * need_des - */ - uint32_t lp_sleep_lp_regulator_slp_dbias:4; - /** lp_sleep_lp_regulator_dbias : R/W; bitpos: [31:27]; default: 24; - * need_des - */ - uint32_t lp_sleep_lp_regulator_dbias:5; - }; - uint32_t val; -} pmu_lp_sleep_lp_regulator0_reg_t; - -/** Type of lp_sleep_lp_regulator1 register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:28; - /** lp_sleep_lp_regulator_drv_b : R/W; bitpos: [31:28]; default: 0; - * need_des - */ - uint32_t lp_sleep_lp_regulator_drv_b:4; - }; - uint32_t val; -} pmu_lp_sleep_lp_regulator1_reg_t; - -/** Type of lp_sleep_xtal register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:31; - /** lp_sleep_xpd_xtal : R/W; bitpos: [31]; default: 1; - * need_des - */ - uint32_t lp_sleep_xpd_xtal:1; - }; - uint32_t val; -} pmu_lp_sleep_xtal_reg_t; - -/** Type of lp_sleep_lp_dig_power register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:30; - /** lp_sleep_lp_mem_dslp : R/W; bitpos: [30]; default: 0; - * need_des - */ - uint32_t lp_sleep_lp_mem_dslp:1; - /** lp_sleep_pd_lp_peri_pd_en : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t lp_sleep_pd_lp_peri_pd_en:1; - }; - uint32_t val; -} pmu_lp_sleep_lp_dig_power_reg_t; - -/** Type of lp_sleep_lp_ck_power register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:28; - /** lp_sleep_xpd_xtal32k : R/W; bitpos: [28]; default: 0; - * need_des - */ - uint32_t lp_sleep_xpd_xtal32k:1; - /** lp_sleep_xpd_rc32k : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t lp_sleep_xpd_rc32k:1; - /** lp_sleep_xpd_fosc_clk : R/W; bitpos: [30]; default: 1; - * need_des - */ - uint32_t lp_sleep_xpd_fosc_clk:1; - /** lp_sleep_pd_osc_clk : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t lp_sleep_pd_osc_clk:1; - }; - uint32_t val; -} pmu_lp_sleep_lp_ck_power_reg_t; - -/** Type of lp_sleep_bias register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:25; - /** lp_sleep_xpd_bias : R/W; bitpos: [25]; default: 0; - * need_des - */ - uint32_t lp_sleep_xpd_bias:1; - /** lp_sleep_dbg_atten : R/W; bitpos: [29:26]; default: 0; - * need_des - */ - uint32_t lp_sleep_dbg_atten:4; - /** lp_sleep_pd_cur : R/W; bitpos: [30]; default: 0; - * need_des - */ - uint32_t lp_sleep_pd_cur:1; - /** lp_sleep_bias_sleep : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t lp_sleep_bias_sleep:1; - }; - uint32_t val; -} pmu_lp_sleep_bias_reg_t; - -/** Type of imm_hp_ck_power register - * need_des - */ -typedef union { - struct { - /** tie_low_global_bbpll_icg : WT; bitpos: [0]; default: 0; - * need_des - */ - uint32_t tie_low_global_bbpll_icg:1; - /** tie_low_global_xtal_icg : WT; bitpos: [1]; default: 0; - * need_des - */ - uint32_t tie_low_global_xtal_icg:1; - /** tie_low_i2c_retention : WT; bitpos: [2]; default: 0; - * need_des - */ - uint32_t tie_low_i2c_retention:1; - /** tie_low_xpd_bb_i2c : WT; bitpos: [3]; default: 0; - * need_des - */ - uint32_t tie_low_xpd_bb_i2c:1; - /** tie_low_xpd_bbpll_i2c : WT; bitpos: [4]; default: 0; - * need_des - */ - uint32_t tie_low_xpd_bbpll_i2c:1; - /** tie_low_xpd_bbpll : WT; bitpos: [5]; default: 0; - * need_des - */ - uint32_t tie_low_xpd_bbpll:1; - /** tie_low_xpd_xtal : WT; bitpos: [6]; default: 0; - * need_des - */ - uint32_t tie_low_xpd_xtal:1; - uint32_t reserved_7:18; - /** tie_high_global_bbpll_icg : WT; bitpos: [25]; default: 0; - * need_des - */ - uint32_t tie_high_global_bbpll_icg:1; - /** tie_high_global_xtal_icg : WT; bitpos: [26]; default: 0; - * need_des - */ - uint32_t tie_high_global_xtal_icg:1; - /** tie_high_i2c_retention : WT; bitpos: [27]; default: 0; - * need_des - */ - uint32_t tie_high_i2c_retention:1; - /** tie_high_xpd_bb_i2c : WT; bitpos: [28]; default: 0; - * need_des - */ - uint32_t tie_high_xpd_bb_i2c:1; - /** tie_high_xpd_bbpll_i2c : WT; bitpos: [29]; default: 0; - * need_des - */ - uint32_t tie_high_xpd_bbpll_i2c:1; - /** tie_high_xpd_bbpll : WT; bitpos: [30]; default: 0; - * need_des - */ - uint32_t tie_high_xpd_bbpll:1; - /** tie_high_xpd_xtal : WT; bitpos: [31]; default: 0; - * need_des - */ - uint32_t tie_high_xpd_xtal:1; - }; - uint32_t val; -} pmu_imm_hp_ck_power_reg_t; - -/** Type of imm_sleep_sysclk register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:28; - /** update_dig_icg_switch : WT; bitpos: [28]; default: 0; - * need_des - */ - uint32_t update_dig_icg_switch:1; - /** tie_low_icg_slp_sel : WT; bitpos: [29]; default: 0; - * need_des - */ - uint32_t tie_low_icg_slp_sel:1; - /** tie_high_icg_slp_sel : WT; bitpos: [30]; default: 0; - * need_des - */ - uint32_t tie_high_icg_slp_sel:1; - /** update_dig_sys_clk_sel : WT; bitpos: [31]; default: 0; - * need_des - */ - uint32_t update_dig_sys_clk_sel:1; + uint32_t reserved0 : 28; + uint32_t update_dig_icg_switch: 1; + uint32_t tie_low_icg_slp_sel : 1; + uint32_t tie_high_icg_slp_sel : 1; + uint32_t update_dig_sysclk_sel: 1; }; uint32_t val; } pmu_imm_sleep_sysclk_reg_t; -/** Type of imm_hp_func_icg register - * need_des - */ typedef union { struct { - uint32_t reserved_0:31; - /** update_dig_icg_func_en : WT; bitpos: [31]; default: 0; - * need_des - */ - uint32_t update_dig_icg_func_en:1; + uint32_t reserved0 : 31; + uint32_t update_dig_icg_func_en: 1; }; uint32_t val; } pmu_imm_hp_func_icg_reg_t; -/** Type of imm_hp_apb_icg register - * need_des - */ typedef union { struct { - uint32_t reserved_0:31; - /** update_dig_icg_apb_en : WT; bitpos: [31]; default: 0; - * need_des - */ - uint32_t update_dig_icg_apb_en:1; + uint32_t reserved0 : 31; + uint32_t update_dig_icg_apb_en: 1; }; uint32_t val; } pmu_imm_hp_apb_icg_reg_t; -/** Type of imm_modem_icg register - * need_des - */ typedef union { struct { - uint32_t reserved_0:31; - /** update_dig_icg_modem_en : WT; bitpos: [31]; default: 0; - * need_des - */ - uint32_t update_dig_icg_modem_en:1; + uint32_t reserved0 : 31; + uint32_t update_dig_icg_modem_en: 1; }; uint32_t val; } pmu_imm_modem_icg_reg_t; -/** Type of imm_lp_icg register - * need_des - */ typedef union { struct { - uint32_t reserved_0:30; - /** tie_low_lp_rootclk_sel : WT; bitpos: [30]; default: 0; - * need_des - */ - uint32_t tie_low_lp_rootclk_sel:1; - /** tie_high_lp_rootclk_sel : WT; bitpos: [31]; default: 0; - * need_des - */ - uint32_t tie_high_lp_rootclk_sel:1; + uint32_t reserved0 : 30; + uint32_t tie_low_lp_rootclk_sel : 1; + uint32_t tie_high_lp_rootclk_sel: 1; }; uint32_t val; } pmu_imm_lp_icg_reg_t; -/** Type of imm_pad_hold_all register - * need_des - */ typedef union { struct { - uint32_t reserved_0:28; - /** tie_high_lp_pad_hold_all : WT; bitpos: [28]; default: 0; - * need_des - */ - uint32_t tie_high_lp_pad_hold_all:1; - /** tie_low_lp_pad_hold_all : WT; bitpos: [29]; default: 0; - * need_des - */ - uint32_t tie_low_lp_pad_hold_all:1; - /** tie_high_hp_pad_hold_all : WT; bitpos: [30]; default: 0; - * need_des - */ - uint32_t tie_high_hp_pad_hold_all:1; - /** tie_low_hp_pad_hold_all : WT; bitpos: [31]; default: 0; - * need_des - */ - uint32_t tie_low_hp_pad_hold_all:1; + uint32_t reserved0 : 28; + uint32_t tie_high_lp_pad_hold_all: 1; + uint32_t tie_low_lp_pad_hold_all : 1; + uint32_t tie_high_hp_pad_hold_all: 1; + uint32_t tie_low_hp_pad_hold_all : 1; }; uint32_t val; } pmu_imm_pad_hold_all_reg_t; -/** Type of imm_i2c_iso register - * need_des - */ typedef union { struct { - uint32_t reserved_0:30; - /** tie_high_i2c_iso_en : WT; bitpos: [30]; default: 0; - * need_des - */ - uint32_t tie_high_i2c_iso_en:1; - /** tie_low_i2c_iso_en : WT; bitpos: [31]; default: 0; - * need_des - */ - uint32_t tie_low_i2c_iso_en:1; + uint32_t reserved0 : 30; + uint32_t tie_high_i2c_iso_en: 1; + uint32_t tie_low_i2c_iso_en : 1; }; uint32_t val; -} pmu_imm_i2c_iso_reg_t; +} pmu_imm_i2c_isolate_reg_t; + +typedef struct pmu_imm_hw_regmap_t{ + pmu_imm_hp_clk_power_reg_t clk_power; + pmu_imm_sleep_sysclk_reg_t sleep_sysclk; + pmu_imm_hp_func_icg_reg_t hp_func_icg; + pmu_imm_hp_apb_icg_reg_t hp_apb_icg; + pmu_imm_modem_icg_reg_t modem_icg; + pmu_imm_lp_icg_reg_t lp_icg; + pmu_imm_pad_hold_all_reg_t pad_hold_all; + pmu_imm_i2c_isolate_reg_t i2c_iso; +} pmu_imm_hw_regmap_t; -/** Type of power_wait_timer0 register - * need_des - */ typedef union { struct { - uint32_t reserved_0:5; - /** dg_hp_powerdown_timer : R/W; bitpos: [13:5]; default: 255; - * need_des - */ - uint32_t dg_hp_powerdown_timer:9; - /** dg_hp_powerup_timer : R/W; bitpos: [22:14]; default: 255; - * need_des - */ - uint32_t dg_hp_powerup_timer:9; - /** dg_hp_wait_timer : R/W; bitpos: [31:23]; default: 255; - * need_des - */ - uint32_t dg_hp_wait_timer:9; + uint32_t reserved0 : 5; + uint32_t powerdown_timer: 9; + uint32_t powerup_timer : 9; + uint32_t wait_timer : 9; }; uint32_t val; } pmu_power_wait_timer0_reg_t; -/** Type of power_wait_timer1 register - * need_des - */ typedef union { struct { - uint32_t reserved_0:9; - /** dg_lp_powerdown_timer : R/W; bitpos: [15:9]; default: 255; - * need_des - */ - uint32_t dg_lp_powerdown_timer:7; - /** dg_lp_powerup_timer : R/W; bitpos: [22:16]; default: 255; - * need_des - */ - uint32_t dg_lp_powerup_timer:7; - /** dg_lp_wait_timer : R/W; bitpos: [31:23]; default: 255; - * need_des - */ - uint32_t dg_lp_wait_timer:9; + uint32_t reserved0 : 9; + uint32_t powerdown_timer: 7; + uint32_t powerup_timer : 7; + uint32_t wait_timer : 9; }; uint32_t val; } pmu_power_wait_timer1_reg_t; -/** Type of power_pd_top_cntl register - * need_des - */ typedef union { struct { - /** force_top_reset : R/W; bitpos: [0]; default: 0; - * need_des - */ - uint32_t force_top_reset:1; - /** force_top_iso : R/W; bitpos: [1]; default: 0; - * need_des - */ - uint32_t force_top_iso:1; - /** force_top_pu : R/W; bitpos: [2]; default: 1; - * need_des - */ - uint32_t force_top_pu:1; - /** force_top_no_reset : R/W; bitpos: [3]; default: 1; - * need_des - */ - uint32_t force_top_no_reset:1; - /** force_top_no_iso : R/W; bitpos: [4]; default: 1; - * need_des - */ - uint32_t force_top_no_iso:1; - /** force_top_pd : R/W; bitpos: [5]; default: 0; - * need_des - */ - uint32_t force_top_pd:1; - /** pd_top_mask : R/W; bitpos: [10:6]; default: 0; - * need_des - */ - uint32_t pd_top_mask:5; - uint32_t reserved_11:16; - /** pd_top_pd_mask : R/W; bitpos: [31:27]; default: 0; - * need_des - */ - uint32_t pd_top_pd_mask:5; + uint32_t force_reset : 1; + uint32_t force_iso : 1; + uint32_t force_pu : 1; + uint32_t force_no_reset: 1; + uint32_t force_no_iso : 1; + uint32_t force_pd : 1; + uint32_t mask : 5; /* Invalid of lp peripherals */ + uint32_t reserved0 : 16; /* Invalid of lp peripherals */ + uint32_t pd_mask : 5; /* Invalid of lp peripherals */ }; uint32_t val; -} pmu_power_pd_top_cntl_reg_t; +} pmu_power_domain_cntl_reg_t; -/** Type of power_pd_hpaon_cntl register - * need_des - */ typedef union { struct { - /** force_hp_aon_reset : R/W; bitpos: [0]; default: 0; - * need_des - */ - uint32_t force_hp_aon_reset:1; - /** force_hp_aon_iso : R/W; bitpos: [1]; default: 0; - * need_des - */ - uint32_t force_hp_aon_iso:1; - /** force_hp_aon_pu : R/W; bitpos: [2]; default: 1; - * need_des - */ - uint32_t force_hp_aon_pu:1; - /** force_hp_aon_no_reset : R/W; bitpos: [3]; default: 1; - * need_des - */ - uint32_t force_hp_aon_no_reset:1; - /** force_hp_aon_no_iso : R/W; bitpos: [4]; default: 1; - * need_des - */ - uint32_t force_hp_aon_no_iso:1; - /** force_hp_aon_pd : R/W; bitpos: [5]; default: 0; - * need_des - */ - uint32_t force_hp_aon_pd:1; - /** pd_hp_aon_mask : R/W; bitpos: [10:6]; default: 0; - * need_des - */ - uint32_t pd_hp_aon_mask:5; - uint32_t reserved_11:16; - /** pd_hp_aon_pd_mask : R/W; bitpos: [31:27]; default: 0; - * need_des - */ - uint32_t pd_hp_aon_pd_mask:5; + uint32_t force_hp_mem_iso : 4; + uint32_t force_hp_mem_pd : 4; + uint32_t reserved0 : 16; + uint32_t force_hp_mem_no_iso: 4; + uint32_t force_hp_mem_pu : 4; }; uint32_t val; -} pmu_power_pd_hpaon_cntl_reg_t; +} pmu_power_memory_cntl_reg_t; -/** Type of power_pd_hpcpu_cntl register - * need_des - */ typedef union { struct { - /** force_hp_cpu_reset : R/W; bitpos: [0]; default: 0; - * need_des - */ - uint32_t force_hp_cpu_reset:1; - /** force_hp_cpu_iso : R/W; bitpos: [1]; default: 0; - * need_des - */ - uint32_t force_hp_cpu_iso:1; - /** force_hp_cpu_pu : R/W; bitpos: [2]; default: 1; - * need_des - */ - uint32_t force_hp_cpu_pu:1; - /** force_hp_cpu_no_reset : R/W; bitpos: [3]; default: 1; - * need_des - */ - uint32_t force_hp_cpu_no_reset:1; - /** force_hp_cpu_no_iso : R/W; bitpos: [4]; default: 1; - * need_des - */ - uint32_t force_hp_cpu_no_iso:1; - /** force_hp_cpu_pd : R/W; bitpos: [5]; default: 0; - * need_des - */ - uint32_t force_hp_cpu_pd:1; - /** pd_hp_cpu_mask : R/W; bitpos: [10:6]; default: 0; - * need_des - */ - uint32_t pd_hp_cpu_mask:5; - uint32_t reserved_11:16; - /** pd_hp_cpu_pd_mask : R/W; bitpos: [31:27]; default: 0; - * need_des - */ - uint32_t pd_hp_cpu_pd_mask:5; + uint32_t mem2_pd_mask: 5; + uint32_t mem1_pd_mask: 5; + uint32_t mem0_pd_mask: 5; + uint32_t reserved0 : 2; + uint32_t mem2_mask : 5; + uint32_t mem1_mask : 5; + uint32_t mem0_mask : 5; }; uint32_t val; -} pmu_power_pd_hpcpu_cntl_reg_t; +} pmu_power_memory_mask_reg_t; -/** Type of power_pd_hpwifi_cntl register - * need_des - */ typedef union { struct { - /** force_hp_wifi_reset : R/W; bitpos: [0]; default: 0; - * need_des - */ - uint32_t force_hp_wifi_reset:1; - /** force_hp_wifi_iso : R/W; bitpos: [1]; default: 0; - * need_des - */ - uint32_t force_hp_wifi_iso:1; - /** force_hp_wifi_pu : R/W; bitpos: [2]; default: 1; - * need_des - */ - uint32_t force_hp_wifi_pu:1; - /** force_hp_wifi_no_reset : R/W; bitpos: [3]; default: 1; - * need_des - */ - uint32_t force_hp_wifi_no_reset:1; - /** force_hp_wifi_no_iso : R/W; bitpos: [4]; default: 1; - * need_des - */ - uint32_t force_hp_wifi_no_iso:1; - /** force_hp_wifi_pd : R/W; bitpos: [5]; default: 0; - * need_des - */ - uint32_t force_hp_wifi_pd:1; - /** pd_hp_wifi_mask : R/W; bitpos: [10:6]; default: 0; - * need_des - */ - uint32_t pd_hp_wifi_mask:5; - uint32_t reserved_11:16; - /** pd_hp_wifi_pd_mask : R/W; bitpos: [31:27]; default: 0; - * need_des - */ - uint32_t pd_hp_wifi_pd_mask:5; - }; - uint32_t val; -} pmu_power_pd_hpwifi_cntl_reg_t; - -/** Type of power_pd_lpperi_cntl register - * need_des - */ -typedef union { - struct { - /** force_lp_peri_reset : R/W; bitpos: [0]; default: 0; - * need_des - */ - uint32_t force_lp_peri_reset:1; - /** force_lp_peri_iso : R/W; bitpos: [1]; default: 0; - * need_des - */ - uint32_t force_lp_peri_iso:1; - /** force_lp_peri_pu : R/W; bitpos: [2]; default: 1; - * need_des - */ - uint32_t force_lp_peri_pu:1; - /** force_lp_peri_no_reset : R/W; bitpos: [3]; default: 1; - * need_des - */ - uint32_t force_lp_peri_no_reset:1; - /** force_lp_peri_no_iso : R/W; bitpos: [4]; default: 1; - * need_des - */ - uint32_t force_lp_peri_no_iso:1; - /** force_lp_peri_pd : R/W; bitpos: [5]; default: 0; - * need_des - */ - uint32_t force_lp_peri_pd:1; - uint32_t reserved_6:26; - }; - uint32_t val; -} pmu_power_pd_lpperi_cntl_reg_t; - -/** Type of power_pd_mem_cntl register - * need_des - */ -typedef union { - struct { - /** force_hp_mem_iso : R/W; bitpos: [3:0]; default: 0; - * need_des - */ - uint32_t force_hp_mem_iso:4; - /** force_hp_mem_pd : R/W; bitpos: [7:4]; default: 0; - * need_des - */ - uint32_t force_hp_mem_pd:4; - uint32_t reserved_8:16; - /** force_hp_mem_no_iso : R/W; bitpos: [27:24]; default: 15; - * need_des - */ - uint32_t force_hp_mem_no_iso:4; - /** force_hp_mem_pu : R/W; bitpos: [31:28]; default: 15; - * need_des - */ - uint32_t force_hp_mem_pu:4; - }; - uint32_t val; -} pmu_power_pd_mem_cntl_reg_t; - -/** Type of power_pd_mem_mask register - * need_des - */ -typedef union { - struct { - /** pd_hp_mem2_pd_mask : R/W; bitpos: [4:0]; default: 0; - * need_des - */ - uint32_t pd_hp_mem2_pd_mask:5; - /** pd_hp_mem1_pd_mask : R/W; bitpos: [9:5]; default: 0; - * need_des - */ - uint32_t pd_hp_mem1_pd_mask:5; - /** pd_hp_mem0_pd_mask : R/W; bitpos: [14:10]; default: 0; - * need_des - */ - uint32_t pd_hp_mem0_pd_mask:5; - uint32_t reserved_15:2; - /** pd_hp_mem2_mask : R/W; bitpos: [21:17]; default: 0; - * need_des - */ - uint32_t pd_hp_mem2_mask:5; - /** pd_hp_mem1_mask : R/W; bitpos: [26:22]; default: 0; - * need_des - */ - uint32_t pd_hp_mem1_mask:5; - /** pd_hp_mem0_mask : R/W; bitpos: [31:27]; default: 0; - * need_des - */ - uint32_t pd_hp_mem0_mask:5; - }; - uint32_t val; -} pmu_power_pd_mem_mask_reg_t; - -/** Type of power_hp_pad register - * need_des - */ -typedef union { - struct { - /** force_hp_pad_no_iso_all : R/W; bitpos: [0]; default: 0; - * need_des - */ - uint32_t force_hp_pad_no_iso_all:1; - /** force_hp_pad_iso_all : R/W; bitpos: [1]; default: 0; - * need_des - */ - uint32_t force_hp_pad_iso_all:1; - uint32_t reserved_2:30; + uint32_t force_hp_pad_no_iso_all: 1; + uint32_t force_hp_pad_iso_all : 1; + uint32_t reserved0 : 30; }; uint32_t val; } pmu_power_hp_pad_reg_t; -/** Type of power_vdd_spi_cntl register - * need_des - */ typedef union { struct { - uint32_t reserved_0:18; - /** vdd_spi_pwr_wait : R/W; bitpos: [28:18]; default: 255; - * need_des - */ - uint32_t vdd_spi_pwr_wait:11; - /** vdd_spi_pwr_sw : R/W; bitpos: [30:29]; default: 3; - * need_des - */ - uint32_t vdd_spi_pwr_sw:2; - /** vdd_spi_pwr_sel_sw : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t vdd_spi_pwr_sel_sw:1; + uint32_t reserved0 : 18; + uint32_t pwr_wait : 11; + uint32_t pwr_sw : 2; + uint32_t pwr_sel_sw: 1; }; uint32_t val; } pmu_power_vdd_spi_cntl_reg_t; -/** Type of power_ck_wait_cntl register - * need_des - */ typedef union { struct { - /** wait_xtl_stable : R/W; bitpos: [15:0]; default: 256; - * need_des - */ - uint32_t wait_xtl_stable:16; - /** wait_pll_stable : R/W; bitpos: [31:16]; default: 256; - * need_des - */ - uint32_t wait_pll_stable:16; + uint32_t wait_xtal_stable: 16; + uint32_t wait_pll_stable : 16; }; uint32_t val; -} pmu_power_ck_wait_cntl_reg_t; +} pmu_power_clk_wait_cntl_reg_t; + +typedef struct pmu_power_hw_regmap_t{ + pmu_power_wait_timer0_reg_t wait_timer0; + pmu_power_wait_timer1_reg_t wait_timer1; + pmu_power_domain_cntl_reg_t hp_pd[5]; + pmu_power_domain_cntl_reg_t lp_peri; + pmu_power_memory_cntl_reg_t mem_cntl; + pmu_power_memory_mask_reg_t mem_mask; + pmu_power_hp_pad_reg_t hp_pad; + pmu_power_vdd_spi_cntl_reg_t vdd_spi; + pmu_power_clk_wait_cntl_reg_t clk_wait; +} pmu_power_hw_regmap_t; -/** Type of slp_wakeup_cntl0 register - * need_des - */ typedef union { struct { - uint32_t reserved_0:31; - /** sleep_req : WT; bitpos: [31]; default: 0; - * need_des - */ - uint32_t sleep_req:1; + uint32_t reserved0: 31; + uint32_t sleep_req: 1; }; uint32_t val; } pmu_slp_wakeup_cntl0_reg_t; -/** Type of slp_wakeup_cntl1 register - * need_des - */ typedef union { struct { - /** sleep_reject_ena : R/W; bitpos: [30:0]; default: 0; - * need_des - */ - uint32_t sleep_reject_ena:31; - /** slp_reject_en : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t slp_reject_en:1; + uint32_t sleep_reject_ena: 31; + uint32_t slp_reject_en : 1; }; uint32_t val; } pmu_slp_wakeup_cntl1_reg_t; -/** Type of slp_wakeup_cntl2 register - * need_des - */ typedef union { struct { - /** wakeup_ena : R/W; bitpos: [31:0]; default: 0; - * need_des - */ - uint32_t wakeup_ena:32; - }; - uint32_t val; -} pmu_slp_wakeup_cntl2_reg_t; - -/** Type of slp_wakeup_cntl3 register - * need_des - */ -typedef union { - struct { - /** lp_min_slp_val : R/W; bitpos: [7:0]; default: 0; - * need_des - */ - uint32_t lp_min_slp_val:8; - /** hp_min_slp_val : R/W; bitpos: [15:8]; default: 0; - * need_des - */ - uint32_t hp_min_slp_val:8; - /** sleep_prt_sel : R/W; bitpos: [17:16]; default: 0; - * need_des - */ - uint32_t sleep_prt_sel:2; - uint32_t reserved_18:14; + uint32_t lp_min_slp_val: 8; + uint32_t hp_min_slp_val: 8; + uint32_t sleep_prt_sel : 2; + uint32_t reserved0 : 14; }; uint32_t val; } pmu_slp_wakeup_cntl3_reg_t; -/** Type of slp_wakeup_cntl4 register - * need_des - */ typedef union { struct { - uint32_t reserved_0:31; - /** slp_reject_cause_clr : WT; bitpos: [31]; default: 0; - * need_des - */ - uint32_t slp_reject_cause_clr:1; + uint32_t reserved0 : 31; + uint32_t slp_reject_cause_clr: 1; }; uint32_t val; } pmu_slp_wakeup_cntl4_reg_t; -/** Type of slp_wakeup_cntl5 register - * need_des - */ typedef union { struct { - /** modem_wait_target : R/W; bitpos: [19:0]; default: 128; - * need_des - */ - uint32_t modem_wait_target:20; - uint32_t reserved_20:4; - /** lp_ana_wait_target : R/W; bitpos: [31:24]; default: 1; - * need_des - */ - uint32_t lp_ana_wait_target:8; + uint32_t modem_wait_target : 20; + uint32_t reserved0 : 4; + uint32_t lp_ana_wait_target: 8; }; uint32_t val; } pmu_slp_wakeup_cntl5_reg_t; -/** Type of slp_wakeup_cntl6 register - * need_des - */ typedef union { struct { - /** soc_wakeup_wait : R/W; bitpos: [19:0]; default: 128; - * need_des - */ - uint32_t soc_wakeup_wait:20; - uint32_t reserved_20:10; - /** soc_wakeup_wait_cfg : R/W; bitpos: [31:30]; default: 0; - * need_des - */ - uint32_t soc_wakeup_wait_cfg:2; + uint32_t soc_wakeup_wait : 20; + uint32_t reserved0 : 10; + uint32_t soc_wakeup_wait_cfg: 2; }; uint32_t val; } pmu_slp_wakeup_cntl6_reg_t; -/** Type of slp_wakeup_cntl7 register - * need_des - */ typedef union { struct { - uint32_t reserved_0:16; - /** ana_wait_target : R/W; bitpos: [31:16]; default: 1; - * need_des - */ - uint32_t ana_wait_target:16; + uint32_t reserved0 : 16; + uint32_t ana_wait_target: 16; }; uint32_t val; } pmu_slp_wakeup_cntl7_reg_t; -/** Type of slp_wakeup_status0 register - * need_des - */ +typedef struct pmu_wakeup_hw_regmap_t{ + pmu_slp_wakeup_cntl0_reg_t cntl0; + pmu_slp_wakeup_cntl1_reg_t cntl1; + uint32_t cntl2; + pmu_slp_wakeup_cntl3_reg_t cntl3; + pmu_slp_wakeup_cntl4_reg_t cntl4; + pmu_slp_wakeup_cntl5_reg_t cntl5; + pmu_slp_wakeup_cntl6_reg_t cntl6; + pmu_slp_wakeup_cntl7_reg_t cntl7; + uint32_t status0; + uint32_t status1; +} pmu_wakeup_hw_regmap_t; + typedef union { struct { - /** wakeup_cause : RO; bitpos: [31:0]; default: 0; - * need_des - */ - uint32_t wakeup_cause:32; + uint32_t i2c_por_wait_target: 8; + uint32_t reserved0 : 24; }; uint32_t val; -} pmu_slp_wakeup_status0_reg_t; +} pmu_hp_clk_poweron_reg_t; -/** Type of slp_wakeup_status1 register - * need_des - */ typedef union { struct { - /** reject_cause : RO; bitpos: [31:0]; default: 0; - * need_des - */ - uint32_t reject_cause:32; + uint32_t modify_icg_cntl_wait: 8; + uint32_t switch_icg_cntl_wait: 8; + uint32_t reserved0 : 16; }; uint32_t val; -} pmu_slp_wakeup_status1_reg_t; +} pmu_hp_clk_cntl_reg_t; -/** Type of hp_ck_poweron register - * need_des - */ typedef union { struct { - /** i2c_por_wait_target : R/W; bitpos: [7:0]; default: 50; - * need_des - */ - uint32_t i2c_por_wait_target:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} pmu_hp_ck_poweron_reg_t; - -/** Type of hp_ck_cntl register - * need_des - */ -typedef union { - struct { - /** modify_icg_cntl_wait : R/W; bitpos: [7:0]; default: 10; - * need_des - */ - uint32_t modify_icg_cntl_wait:8; - /** switch_icg_cntl_wait : R/W; bitpos: [15:8]; default: 10; - * need_des - */ - uint32_t switch_icg_cntl_wait:8; - uint32_t reserved_16:16; - }; - uint32_t val; -} pmu_hp_ck_cntl_reg_t; - -/** Type of por_status register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:31; - /** por_done : RO; bitpos: [31]; default: 1; - * need_des - */ - uint32_t por_done:1; + uint32_t reserved0: 31; + uint32_t por_done : 1; }; uint32_t val; } pmu_por_status_reg_t; -/** Type of rf_pwc register - * need_des - */ typedef union { struct { - uint32_t reserved_0:24; - /** xpd_tc5g_i2c : R/W; bitpos: [24]; default: 0; - * need_des - */ - uint32_t xpd_tc5g_i2c:1; - /** xpd_rx5g_i2c : R/W; bitpos: [25]; default: 0; - * need_des - */ - uint32_t xpd_rx5g_i2c:1; - /** perif_i2c_rstb : R/W; bitpos: [26]; default: 0; - * need_des - */ - uint32_t perif_i2c_rstb:1; - /** xpd_perif_i2c : R/W; bitpos: [27]; default: 1; - * need_des - */ - uint32_t xpd_perif_i2c:1; - /** xpd_txrf_i2c : R/W; bitpos: [28]; default: 0; - * need_des - */ - uint32_t xpd_txrf_i2c:1; - /** xpd_rfrx_pbus : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t xpd_rfrx_pbus:1; - /** xpd_ckgen_i2c : R/W; bitpos: [30]; default: 0; - * need_des - */ - uint32_t xpd_ckgen_i2c:1; - /** xpd_pll_i2c : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t xpd_pll_i2c:1; + uint32_t reserved0 : 26; + uint32_t perif_i2c_rstb: 1; + uint32_t xpd_perif_i2c : 1; + uint32_t xpd_txrf_i2c : 1; + uint32_t xpd_rfrx_pbus : 1; + uint32_t xpd_ckgen_i2c : 1; + uint32_t xpd_pll_i2c : 1; }; uint32_t val; } pmu_rf_pwc_reg_t; -/** Type of backup_cfg register - * need_des - */ typedef union { struct { - uint32_t reserved_0:31; - /** backup_sys_clk_no_div : R/W; bitpos: [31]; default: 1; - * need_des - */ - uint32_t backup_sys_clk_no_div:1; + uint32_t reserved0 : 31; + uint32_t backup_sysclk_nodiv: 1; }; uint32_t val; } pmu_backup_cfg_reg_t; -/** Type of int_raw register - * need_des - */ typedef union { struct { - uint32_t reserved_0:27; - /** lp_cpu_exc_int_raw : R/WTC/SS; bitpos: [27]; default: 0; - * need_des - */ - uint32_t lp_cpu_exc_int_raw:1; - /** sdio_idle_int_raw : R/WTC/SS; bitpos: [28]; default: 0; - * need_des - */ - uint32_t sdio_idle_int_raw:1; - /** sw_int_raw : R/WTC/SS; bitpos: [29]; default: 0; - * need_des - */ - uint32_t sw_int_raw:1; - /** soc_sleep_reject_int_raw : R/WTC/SS; bitpos: [30]; default: 0; - * need_des - */ - uint32_t soc_sleep_reject_int_raw:1; - /** soc_wakeup_int_raw : R/WTC/SS; bitpos: [31]; default: 0; - * need_des - */ - uint32_t soc_wakeup_int_raw:1; + uint32_t reserved0 : 27; + uint32_t lp_cpu_exc: 1; + uint32_t sdio_idle : 1; + uint32_t sw : 1; + uint32_t reject : 1; + uint32_t wakeup : 1; }; uint32_t val; -} pmu_int_raw_reg_t; +} pmu_hp_intr_reg_t; + +typedef struct pmu_hp_ext_hw_regmap_t{ + pmu_hp_clk_poweron_reg_t clk_poweron; + pmu_hp_clk_cntl_reg_t clk_cntl; + pmu_por_status_reg_t por_status; + pmu_rf_pwc_reg_t rf_pwc; + pmu_backup_cfg_reg_t backup_cfg; + pmu_hp_intr_reg_t int_raw; + pmu_hp_intr_reg_t int_st; + pmu_hp_intr_reg_t int_ena; + pmu_hp_intr_reg_t int_clr; +} pmu_hp_ext_hw_regmap_t; -/** Type of hp_int_st register - * need_des - */ typedef union { struct { - uint32_t reserved_0:27; - /** lp_cpu_exc_int_st : RO; bitpos: [27]; default: 0; - * need_des - */ - uint32_t lp_cpu_exc_int_st:1; - /** sdio_idle_int_st : RO; bitpos: [28]; default: 0; - * need_des - */ - uint32_t sdio_idle_int_st:1; - /** sw_int_st : RO; bitpos: [29]; default: 0; - * need_des - */ - uint32_t sw_int_st:1; - /** soc_sleep_reject_int_st : RO; bitpos: [30]; default: 0; - * need_des - */ - uint32_t soc_sleep_reject_int_st:1; - /** soc_wakeup_int_st : RO; bitpos: [31]; default: 0; - * need_des - */ - uint32_t soc_wakeup_int_st:1; + uint32_t reserved0 : 20; + uint32_t lp_cpu_wakeup : 1; + uint32_t modem_switch_active_end : 1; + uint32_t sleep_switch_active_end : 1; + uint32_t sleep_switch_modem_end : 1; + uint32_t modem_switch_sleep_end : 1; + uint32_t active_swtich_sleep_end : 1; + uint32_t modem_switch_active_start: 1; + uint32_t sleep_switch_active_start: 1; + uint32_t sleep_switch_modem_start : 1; + uint32_t modem_switch_sleep_start : 1; + uint32_t active_switch_sleep_start: 1; + uint32_t sw_trigger : 1; }; uint32_t val; -} pmu_hp_int_st_reg_t; +} pmu_lp_intr_reg_t; -/** Type of hp_int_ena register - * need_des - */ typedef union { struct { - uint32_t reserved_0:27; - /** lp_cpu_exc_int_ena : R/W; bitpos: [27]; default: 0; - * need_des - */ - uint32_t lp_cpu_exc_int_ena:1; - /** sdio_idle_int_ena : R/W; bitpos: [28]; default: 0; - * need_des - */ - uint32_t sdio_idle_int_ena:1; - /** sw_int_ena : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t sw_int_ena:1; - /** soc_sleep_reject_int_ena : R/W; bitpos: [30]; default: 0; - * need_des - */ - uint32_t soc_sleep_reject_int_ena:1; - /** soc_wakeup_int_ena : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t soc_wakeup_int_ena:1; - }; - uint32_t val; -} pmu_hp_int_ena_reg_t; - -/** Type of hp_int_clr register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:27; - /** lp_cpu_exc_int_clr : WT; bitpos: [27]; default: 0; - * need_des - */ - uint32_t lp_cpu_exc_int_clr:1; - /** sdio_idle_int_clr : WT; bitpos: [28]; default: 0; - * need_des - */ - uint32_t sdio_idle_int_clr:1; - /** sw_int_clr : WT; bitpos: [29]; default: 0; - * need_des - */ - uint32_t sw_int_clr:1; - /** soc_sleep_reject_int_clr : WT; bitpos: [30]; default: 0; - * need_des - */ - uint32_t soc_sleep_reject_int_clr:1; - /** soc_wakeup_int_clr : WT; bitpos: [31]; default: 0; - * need_des - */ - uint32_t soc_wakeup_int_clr:1; - }; - uint32_t val; -} pmu_hp_int_clr_reg_t; - -/** Type of lp_int_raw register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:20; - /** lp_cpu_wakeup_int_raw : R/WTC/SS; bitpos: [20]; default: 0; - * need_des - */ - uint32_t lp_cpu_wakeup_int_raw:1; - /** modem_switch_active_end_int_raw : R/WTC/SS; bitpos: [21]; default: 0; - * need_des - */ - uint32_t modem_switch_active_end_int_raw:1; - /** sleep_switch_active_end_int_raw : R/WTC/SS; bitpos: [22]; default: 0; - * need_des - */ - uint32_t sleep_switch_active_end_int_raw:1; - /** sleep_switch_modem_end_int_raw : R/WTC/SS; bitpos: [23]; default: 0; - * need_des - */ - uint32_t sleep_switch_modem_end_int_raw:1; - /** modem_switch_sleep_end_int_raw : R/WTC/SS; bitpos: [24]; default: 0; - * need_des - */ - uint32_t modem_switch_sleep_end_int_raw:1; - /** active_switch_sleep_end_int_raw : R/WTC/SS; bitpos: [25]; default: 0; - * need_des - */ - uint32_t active_switch_sleep_end_int_raw:1; - /** modem_switch_active_start_int_raw : R/WTC/SS; bitpos: [26]; default: 0; - * need_des - */ - uint32_t modem_switch_active_start_int_raw:1; - /** sleep_switch_active_start_int_raw : R/WTC/SS; bitpos: [27]; default: 0; - * need_des - */ - uint32_t sleep_switch_active_start_int_raw:1; - /** sleep_switch_modem_start_int_raw : R/WTC/SS; bitpos: [28]; default: 0; - * need_des - */ - uint32_t sleep_switch_modem_start_int_raw:1; - /** modem_switch_sleep_start_int_raw : R/WTC/SS; bitpos: [29]; default: 0; - * need_des - */ - uint32_t modem_switch_sleep_start_int_raw:1; - /** active_switch_sleep_start_int_raw : R/WTC/SS; bitpos: [30]; default: 0; - * need_des - */ - uint32_t active_switch_sleep_start_int_raw:1; - /** hp_sw_trigger_int_raw : R/WTC/SS; bitpos: [31]; default: 0; - * need_des - */ - uint32_t hp_sw_trigger_int_raw:1; - }; - uint32_t val; -} pmu_lp_int_raw_reg_t; - -/** Type of lp_int_st register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:20; - /** lp_cpu_wakeup_int_st : RO; bitpos: [20]; default: 0; - * need_des - */ - uint32_t lp_cpu_wakeup_int_st:1; - /** modem_switch_active_end_int_st : RO; bitpos: [21]; default: 0; - * need_des - */ - uint32_t modem_switch_active_end_int_st:1; - /** sleep_switch_active_end_int_st : RO; bitpos: [22]; default: 0; - * need_des - */ - uint32_t sleep_switch_active_end_int_st:1; - /** sleep_switch_modem_end_int_st : RO; bitpos: [23]; default: 0; - * need_des - */ - uint32_t sleep_switch_modem_end_int_st:1; - /** modem_switch_sleep_end_int_st : RO; bitpos: [24]; default: 0; - * need_des - */ - uint32_t modem_switch_sleep_end_int_st:1; - /** active_switch_sleep_end_int_st : RO; bitpos: [25]; default: 0; - * need_des - */ - uint32_t active_switch_sleep_end_int_st:1; - /** modem_switch_active_start_int_st : RO; bitpos: [26]; default: 0; - * need_des - */ - uint32_t modem_switch_active_start_int_st:1; - /** sleep_switch_active_start_int_st : RO; bitpos: [27]; default: 0; - * need_des - */ - uint32_t sleep_switch_active_start_int_st:1; - /** sleep_switch_modem_start_int_st : RO; bitpos: [28]; default: 0; - * need_des - */ - uint32_t sleep_switch_modem_start_int_st:1; - /** modem_switch_sleep_start_int_st : RO; bitpos: [29]; default: 0; - * need_des - */ - uint32_t modem_switch_sleep_start_int_st:1; - /** active_switch_sleep_start_int_st : RO; bitpos: [30]; default: 0; - * need_des - */ - uint32_t active_switch_sleep_start_int_st:1; - /** hp_sw_trigger_int_st : RO; bitpos: [31]; default: 0; - * need_des - */ - uint32_t hp_sw_trigger_int_st:1; - }; - uint32_t val; -} pmu_lp_int_st_reg_t; - -/** Type of lp_int_ena register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:20; - /** lp_cpu_wakeup_int_ena : R/W; bitpos: [20]; default: 0; - * need_des - */ - uint32_t lp_cpu_wakeup_int_ena:1; - /** modem_switch_active_end_int_ena : R/W; bitpos: [21]; default: 0; - * need_des - */ - uint32_t modem_switch_active_end_int_ena:1; - /** sleep_switch_active_end_int_ena : R/W; bitpos: [22]; default: 0; - * need_des - */ - uint32_t sleep_switch_active_end_int_ena:1; - /** sleep_switch_modem_end_int_ena : R/W; bitpos: [23]; default: 0; - * need_des - */ - uint32_t sleep_switch_modem_end_int_ena:1; - /** modem_switch_sleep_end_int_ena : R/W; bitpos: [24]; default: 0; - * need_des - */ - uint32_t modem_switch_sleep_end_int_ena:1; - /** active_switch_sleep_end_int_ena : R/W; bitpos: [25]; default: 0; - * need_des - */ - uint32_t active_switch_sleep_end_int_ena:1; - /** modem_switch_active_start_int_ena : R/W; bitpos: [26]; default: 0; - * need_des - */ - uint32_t modem_switch_active_start_int_ena:1; - /** sleep_switch_active_start_int_ena : R/W; bitpos: [27]; default: 0; - * need_des - */ - uint32_t sleep_switch_active_start_int_ena:1; - /** sleep_switch_modem_start_int_ena : R/W; bitpos: [28]; default: 0; - * need_des - */ - uint32_t sleep_switch_modem_start_int_ena:1; - /** modem_switch_sleep_start_int_ena : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t modem_switch_sleep_start_int_ena:1; - /** active_switch_sleep_start_int_ena : R/W; bitpos: [30]; default: 0; - * need_des - */ - uint32_t active_switch_sleep_start_int_ena:1; - /** hp_sw_trigger_int_ena : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t hp_sw_trigger_int_ena:1; - }; - uint32_t val; -} pmu_lp_int_ena_reg_t; - -/** Type of lp_int_clr register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:20; - /** lp_cpu_wakeup_int_clr : WT; bitpos: [20]; default: 0; - * need_des - */ - uint32_t lp_cpu_wakeup_int_clr:1; - /** modem_switch_active_end_int_clr : WT; bitpos: [21]; default: 0; - * need_des - */ - uint32_t modem_switch_active_end_int_clr:1; - /** sleep_switch_active_end_int_clr : WT; bitpos: [22]; default: 0; - * need_des - */ - uint32_t sleep_switch_active_end_int_clr:1; - /** sleep_switch_modem_end_int_clr : WT; bitpos: [23]; default: 0; - * need_des - */ - uint32_t sleep_switch_modem_end_int_clr:1; - /** modem_switch_sleep_end_int_clr : WT; bitpos: [24]; default: 0; - * need_des - */ - uint32_t modem_switch_sleep_end_int_clr:1; - /** active_switch_sleep_end_int_clr : WT; bitpos: [25]; default: 0; - * need_des - */ - uint32_t active_switch_sleep_end_int_clr:1; - /** modem_switch_active_start_int_clr : WT; bitpos: [26]; default: 0; - * need_des - */ - uint32_t modem_switch_active_start_int_clr:1; - /** sleep_switch_active_start_int_clr : WT; bitpos: [27]; default: 0; - * need_des - */ - uint32_t sleep_switch_active_start_int_clr:1; - /** sleep_switch_modem_start_int_clr : WT; bitpos: [28]; default: 0; - * need_des - */ - uint32_t sleep_switch_modem_start_int_clr:1; - /** modem_switch_sleep_start_int_clr : WT; bitpos: [29]; default: 0; - * need_des - */ - uint32_t modem_switch_sleep_start_int_clr:1; - /** active_switch_sleep_start_int_clr : WT; bitpos: [30]; default: 0; - * need_des - */ - uint32_t active_switch_sleep_start_int_clr:1; - /** hp_sw_trigger_int_clr : WT; bitpos: [31]; default: 0; - * need_des - */ - uint32_t hp_sw_trigger_int_clr:1; - }; - uint32_t val; -} pmu_lp_int_clr_reg_t; - -/** Type of lp_cpu_pwr0 register - * need_des - */ -typedef union { - struct { - /** lp_cpu_waiti_rdy : RO; bitpos: [0]; default: 0; - * need_des - */ - uint32_t lp_cpu_waiti_rdy:1; - /** lp_cpu_stall_rdy : RO; bitpos: [1]; default: 0; - * need_des - */ - uint32_t lp_cpu_stall_rdy:1; - uint32_t reserved_2:16; - /** lp_cpu_force_stall : R/W; bitpos: [18]; default: 0; - * need_des - */ - uint32_t lp_cpu_force_stall:1; - /** lp_cpu_slp_waiti_flag_en : R/W; bitpos: [19]; default: 0; - * need_des - */ - uint32_t lp_cpu_slp_waiti_flag_en:1; - /** lp_cpu_slp_stall_flag_en : R/W; bitpos: [20]; default: 1; - * need_des - */ - uint32_t lp_cpu_slp_stall_flag_en:1; - /** lp_cpu_slp_stall_wait : R/W; bitpos: [28:21]; default: 255; - * need_des - */ - uint32_t lp_cpu_slp_stall_wait:8; - /** lp_cpu_slp_stall_en : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t lp_cpu_slp_stall_en:1; - /** lp_cpu_slp_reset_en : R/W; bitpos: [30]; default: 0; - * need_des - */ - uint32_t lp_cpu_slp_reset_en:1; - /** lp_cpu_slp_bypass_intr_en : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t lp_cpu_slp_bypass_intr_en:1; + uint32_t waiti_rdy : 1; + uint32_t stall_rdy : 1; + uint32_t reserved0 : 16; + uint32_t force_stall : 1; + uint32_t slp_waiti_flag_en : 1; + uint32_t slp_stall_flag_en : 1; + uint32_t slp_stall_wait : 8; + uint32_t slp_stall_en : 1; + uint32_t slp_reset_en : 1; + uint32_t slp_bypass_intr_en: 1; }; uint32_t val; } pmu_lp_cpu_pwr0_reg_t; -/** Type of lp_cpu_pwr1 register - * need_des - */ typedef union { struct { - /** lp_cpu_wakeup_en : R/W; bitpos: [15:0]; default: 0; - * need_des - */ - uint32_t lp_cpu_wakeup_en:16; - uint32_t reserved_16:15; - /** lp_cpu_sleep_req : WT; bitpos: [31]; default: 0; - * need_des - */ - uint32_t lp_cpu_sleep_req:1; + uint32_t wakeup_en: 16; + uint32_t reserved0: 15; + uint32_t sleep_req: 1; }; uint32_t val; } pmu_lp_cpu_pwr1_reg_t; -/** Type of hp_lp_cpu_comm register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:30; - /** lp_trigger_hp : WT; bitpos: [30]; default: 0; - * need_des - */ - uint32_t lp_trigger_hp:1; - /** hp_trigger_lp : WT; bitpos: [31]; default: 0; - * need_des - */ - uint32_t hp_trigger_lp:1; - }; - uint32_t val; -} pmu_hp_lp_cpu_comm_reg_t; +typedef struct pmu_lp_ext_hw_regmap_t{ + pmu_lp_intr_reg_t int_raw; + pmu_lp_intr_reg_t int_st; + pmu_lp_intr_reg_t int_ena; + pmu_lp_intr_reg_t int_clr; + pmu_lp_cpu_pwr0_reg_t pwr0; + pmu_lp_cpu_pwr1_reg_t pwr1; +} pmu_lp_ext_hw_regmap_t; -/** Type of hp_regulator_cfg register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:31; - /** dig_regulator_en_cal : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t dig_regulator_en_cal:1; - }; - uint32_t val; -} pmu_hp_regulator_cfg_reg_t; +typedef struct pmu_dev_t{ + volatile pmu_hp_hw_regmap_t hp_sys[3]; + volatile pmu_lp_hw_regmap_t lp_sys[2]; + volatile pmu_imm_hw_regmap_t imm; + volatile pmu_power_hw_regmap_t power; + volatile pmu_wakeup_hw_regmap_t wakeup; + volatile pmu_hp_ext_hw_regmap_t hp_ext; + volatile pmu_lp_ext_hw_regmap_t lp_ext; -/** Type of main_state register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:11; - /** main_last_st_state : RO; bitpos: [17:11]; default: 1; - * need_des - */ - uint32_t main_last_st_state:7; - /** main_tar_st_state : RO; bitpos: [24:18]; default: 4; - * need_des - */ - uint32_t main_tar_st_state:7; - /** main_cur_st_state : RO; bitpos: [31:25]; default: 4; - * need_des - */ - uint32_t main_cur_st_state:7; - }; - uint32_t val; -} pmu_main_state_reg_t; + union { + struct { + uint32_t reserved0 : 30; + volatile uint32_t lp_trigger_hp: 1; + volatile uint32_t hp_trigger_lp: 1; + }; + volatile uint32_t val; + } hp_lp_cpu_comm; -/** Type of pwr_state register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:13; - /** backup_st_state : RO; bitpos: [17:13]; default: 1; - * need_des - */ - uint32_t backup_st_state:5; - /** lp_pwr_st_state : RO; bitpos: [22:18]; default: 0; - * need_des - */ - uint32_t lp_pwr_st_state:5; - /** hp_pwr_st_state : RO; bitpos: [31:23]; default: 1; - * need_des - */ - uint32_t hp_pwr_st_state:9; - }; - uint32_t val; -} pmu_pwr_state_reg_t; + union { + struct { + uint32_t reserved0 : 31; + volatile uint32_t dig_regulator_en_cal: 1; + }; + volatile uint32_t val; + } hp_regulator_cfg; -/** Type of date register - * need_des - */ -typedef union { - struct { - /** pmu_date : R/W; bitpos: [30:0]; default: 35664432; - * need_des - */ - uint32_t pmu_date:31; - /** clk_en : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t clk_en:1; - }; - uint32_t val; -} pmu_date_reg_t; + union { + struct { + uint32_t reserved0 : 11; + volatile uint32_t last_st : 7; + volatile uint32_t target_st : 7; + volatile uint32_t current_st: 7; + }; + volatile uint32_t val; + } main_state; + union { + struct { + uint32_t reserved0: 13; + volatile uint32_t backup_st: 5; + volatile uint32_t lp_pwr_st: 5; + volatile uint32_t hp_pwr_st: 9; + }; + volatile uint32_t val; + } pwr_state; -/** Group: status_register */ -/** Type of clk_state0 register - * need_des - */ -typedef union { - struct { - /** stable_xpd_bbpll_state : RO; bitpos: [0]; default: 1; - * need_des - */ - uint32_t stable_xpd_bbpll_state:1; - /** stable_xpd_xtal_state : RO; bitpos: [1]; default: 1; - * need_des - */ - uint32_t stable_xpd_xtal_state:1; - uint32_t reserved_2:13; - /** sys_clk_slp_sel_state : RO; bitpos: [15]; default: 0; - * need_des - */ - uint32_t sys_clk_slp_sel_state:1; - /** sys_clk_sel_state : RO; bitpos: [17:16]; default: 0; - * need_des - */ - uint32_t sys_clk_sel_state:2; - /** sys_clk_no_div_state : RO; bitpos: [18]; default: 0; - * need_des - */ - uint32_t sys_clk_no_div_state:1; - /** icg_sys_clk_en_state : RO; bitpos: [19]; default: 0; - * need_des - */ - uint32_t icg_sys_clk_en_state:1; - /** icg_modem_switch_state : RO; bitpos: [20]; default: 0; - * need_des - */ - uint32_t icg_modem_switch_state:1; - /** icg_modem_code_state : RO; bitpos: [22:21]; default: 0; - * need_des - */ - uint32_t icg_modem_code_state:2; - /** icg_slp_sel_state : RO; bitpos: [23]; default: 0; - * need_des - */ - uint32_t icg_slp_sel_state:1; - /** icg_global_xtal_state : RO; bitpos: [24]; default: 0; - * need_des - */ - uint32_t icg_global_xtal_state:1; - /** icg_global_pll_state : RO; bitpos: [25]; default: 0; - * need_des - */ - uint32_t icg_global_pll_state:1; - /** ana_i2c_iso_en_state : RO; bitpos: [26]; default: 0; - * need_des - */ - uint32_t ana_i2c_iso_en_state:1; - /** ana_i2c_retention_state : RO; bitpos: [27]; default: 0; - * need_des - */ - uint32_t ana_i2c_retention_state:1; - /** ana_xpd_bb_i2c_state : RO; bitpos: [28]; default: 0; - * need_des - */ - uint32_t ana_xpd_bb_i2c_state:1; - /** ana_xpd_bbpll_i2c_state : RO; bitpos: [29]; default: 0; - * need_des - */ - uint32_t ana_xpd_bbpll_i2c_state:1; - /** ana_xpd_bbpll_state : RO; bitpos: [30]; default: 0; - * need_des - */ - uint32_t ana_xpd_bbpll_state:1; - /** ana_xpd_xtal_state : RO; bitpos: [31]; default: 0; - * need_des - */ - uint32_t ana_xpd_xtal_state:1; - }; - uint32_t val; -} pmu_clk_state0_reg_t; + union { + struct { + volatile uint32_t stable_xpd_bbpll : 1; + volatile uint32_t stable_xpd_xtal : 1; + volatile uint32_t reserved0 : 13; + volatile uint32_t sysclk_slp_sel : 1; + volatile uint32_t sysclk_sel : 2; + volatile uint32_t sysclk_nodiv : 1; + volatile uint32_t icg_sysclk_en : 1; + volatile uint32_t icg_modem_switch : 1; + volatile uint32_t icg_modem_code : 2; + volatile uint32_t icg_slp_sel : 1; + volatile uint32_t icg_global_xtal : 1; + volatile uint32_t icg_global_pll : 1; + volatile uint32_t ana_i2c_iso_en : 1; + volatile uint32_t ana_i2c_retention: 1; + volatile uint32_t ana_xpd_bb_i2c : 1; + volatile uint32_t ana_xpd_bbpll_i2c: 1; + volatile uint32_t ana_xpd_bbpll : 1; + volatile uint32_t ana_xpd_xtal : 1; + }; + volatile uint32_t val; + } clk_state0; -/** Type of clk_state1 register - * need_des - */ -typedef union { - struct { - /** icg_func_en_state : RO; bitpos: [31:0]; default: 4294967295; - * need_des - */ - uint32_t icg_func_en_state:32; - }; - uint32_t val; -} pmu_clk_state1_reg_t; + volatile uint32_t clk_state1; + volatile uint32_t clk_state2; -/** Type of clk_state2 register - * need_des - */ -typedef union { - struct { - /** icg_apb_en_state : RO; bitpos: [31:0]; default: 4294967295; - * need_des - */ - uint32_t icg_apb_en_state:32; - }; - uint32_t val; -} pmu_clk_state2_reg_t; + union { + struct { + uint32_t reserved0 : 31; + volatile uint32_t stable_vdd_spi_pwr_drv: 1; + }; + volatile uint32_t val; + } vdd_spi_status; -/** Type of vdd_spi_status register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:31; - /** stable_vdd_spi_pwr_drv : RO; bitpos: [31]; default: 0; - * need_des - */ - uint32_t stable_vdd_spi_pwr_drv:1; - }; - uint32_t val; -} pmu_vdd_spi_status_reg_t; + uint32_t reserved[150]; - -typedef struct pmu_dev_t { - volatile pmu_hp_active_dig_power_reg_t hp_active_dig_power; - volatile pmu_hp_active_icg_hp_func_reg_t hp_active_icg_hp_func; - volatile pmu_hp_active_icg_hp_apb_reg_t hp_active_icg_hp_apb; - volatile pmu_hp_active_icg_modem_reg_t hp_active_icg_modem; - volatile pmu_hp_active_hp_sys_cntl_reg_t hp_active_hp_sys_cntl; - volatile pmu_hp_active_hp_ck_power_reg_t hp_active_hp_ck_power; - volatile pmu_hp_active_bias_reg_t hp_active_bias; - volatile pmu_hp_active_backup_reg_t hp_active_backup; - volatile pmu_hp_active_backup_clk_reg_t hp_active_backup_clk; - volatile pmu_hp_active_sysclk_reg_t hp_active_sysclk; - volatile pmu_hp_active_hp_regulator0_reg_t hp_active_hp_regulator0; - volatile pmu_hp_active_hp_regulator1_reg_t hp_active_hp_regulator1; - volatile pmu_hp_active_xtal_reg_t hp_active_xtal; - volatile pmu_hp_modem_dig_power_reg_t hp_modem_dig_power; - volatile pmu_hp_modem_icg_hp_func_reg_t hp_modem_icg_hp_func; - volatile pmu_hp_modem_icg_hp_apb_reg_t hp_modem_icg_hp_apb; - volatile pmu_hp_modem_icg_modem_reg_t hp_modem_icg_modem; - volatile pmu_hp_modem_hp_sys_cntl_reg_t hp_modem_hp_sys_cntl; - volatile pmu_hp_modem_hp_ck_power_reg_t hp_modem_hp_ck_power; - volatile pmu_hp_modem_bias_reg_t hp_modem_bias; - volatile pmu_hp_modem_backup_reg_t hp_modem_backup; - volatile pmu_hp_modem_backup_clk_reg_t hp_modem_backup_clk; - volatile pmu_hp_modem_sysclk_reg_t hp_modem_sysclk; - volatile pmu_hp_modem_hp_regulator0_reg_t hp_modem_hp_regulator0; - volatile pmu_hp_modem_hp_regulator1_reg_t hp_modem_hp_regulator1; - volatile pmu_hp_modem_xtal_reg_t hp_modem_xtal; - volatile pmu_hp_sleep_dig_power_reg_t hp_sleep_dig_power; - volatile pmu_hp_sleep_icg_hp_func_reg_t hp_sleep_icg_hp_func; - volatile pmu_hp_sleep_icg_hp_apb_reg_t hp_sleep_icg_hp_apb; - volatile pmu_hp_sleep_icg_modem_reg_t hp_sleep_icg_modem; - volatile pmu_hp_sleep_hp_sys_cntl_reg_t hp_sleep_hp_sys_cntl; - volatile pmu_hp_sleep_hp_ck_power_reg_t hp_sleep_hp_ck_power; - volatile pmu_hp_sleep_bias_reg_t hp_sleep_bias; - volatile pmu_hp_sleep_backup_reg_t hp_sleep_backup; - volatile pmu_hp_sleep_backup_clk_reg_t hp_sleep_backup_clk; - volatile pmu_hp_sleep_sysclk_reg_t hp_sleep_sysclk; - volatile pmu_hp_sleep_hp_regulator0_reg_t hp_sleep_hp_regulator0; - volatile pmu_hp_sleep_hp_regulator1_reg_t hp_sleep_hp_regulator1; - volatile pmu_hp_sleep_xtal_reg_t hp_sleep_xtal; - volatile pmu_hp_sleep_lp_regulator0_reg_t hp_sleep_lp_regulator0; - volatile pmu_hp_sleep_lp_regulator1_reg_t hp_sleep_lp_regulator1; - uint32_t reserved_0a4; - volatile pmu_hp_sleep_lp_dig_power_reg_t hp_sleep_lp_dig_power; - volatile pmu_hp_sleep_lp_ck_power_reg_t hp_sleep_lp_ck_power; - uint32_t reserved_0b0; - volatile pmu_lp_sleep_lp_regulator0_reg_t lp_sleep_lp_regulator0; - volatile pmu_lp_sleep_lp_regulator1_reg_t lp_sleep_lp_regulator1; - volatile pmu_lp_sleep_xtal_reg_t lp_sleep_xtal; - volatile pmu_lp_sleep_lp_dig_power_reg_t lp_sleep_lp_dig_power; - volatile pmu_lp_sleep_lp_ck_power_reg_t lp_sleep_lp_ck_power; - volatile pmu_lp_sleep_bias_reg_t lp_sleep_bias; - volatile pmu_imm_hp_ck_power_reg_t imm_hp_ck_power; - volatile pmu_imm_sleep_sysclk_reg_t imm_sleep_sysclk; - volatile pmu_imm_hp_func_icg_reg_t imm_hp_func_icg; - volatile pmu_imm_hp_apb_icg_reg_t imm_hp_apb_icg; - volatile pmu_imm_modem_icg_reg_t imm_modem_icg; - volatile pmu_imm_lp_icg_reg_t imm_lp_icg; - volatile pmu_imm_pad_hold_all_reg_t imm_pad_hold_all; - volatile pmu_imm_i2c_iso_reg_t imm_i2c_iso; - volatile pmu_power_wait_timer0_reg_t power_wait_timer0; - volatile pmu_power_wait_timer1_reg_t power_wait_timer1; - volatile pmu_power_pd_top_cntl_reg_t power_pd_top_cntl; - volatile pmu_power_pd_hpaon_cntl_reg_t power_pd_hpaon_cntl; - volatile pmu_power_pd_hpcpu_cntl_reg_t power_pd_hpcpu_cntl; - uint32_t reserved_100; - volatile pmu_power_pd_hpwifi_cntl_reg_t power_pd_hpwifi_cntl; - volatile pmu_power_pd_lpperi_cntl_reg_t power_pd_lpperi_cntl; - volatile pmu_power_pd_mem_cntl_reg_t power_pd_mem_cntl; - volatile pmu_power_pd_mem_mask_reg_t power_pd_mem_mask; - volatile pmu_power_hp_pad_reg_t power_hp_pad; - volatile pmu_power_vdd_spi_cntl_reg_t power_vdd_spi_cntl; - volatile pmu_power_ck_wait_cntl_reg_t power_ck_wait_cntl; - volatile pmu_slp_wakeup_cntl0_reg_t slp_wakeup_cntl0; - volatile pmu_slp_wakeup_cntl1_reg_t slp_wakeup_cntl1; - volatile pmu_slp_wakeup_cntl2_reg_t slp_wakeup_cntl2; - volatile pmu_slp_wakeup_cntl3_reg_t slp_wakeup_cntl3; - volatile pmu_slp_wakeup_cntl4_reg_t slp_wakeup_cntl4; - volatile pmu_slp_wakeup_cntl5_reg_t slp_wakeup_cntl5; - volatile pmu_slp_wakeup_cntl6_reg_t slp_wakeup_cntl6; - volatile pmu_slp_wakeup_cntl7_reg_t slp_wakeup_cntl7; - volatile pmu_slp_wakeup_status0_reg_t slp_wakeup_status0; - volatile pmu_slp_wakeup_status1_reg_t slp_wakeup_status1; - volatile pmu_hp_ck_poweron_reg_t hp_ck_poweron; - volatile pmu_hp_ck_cntl_reg_t hp_ck_cntl; - volatile pmu_por_status_reg_t por_status; - volatile pmu_rf_pwc_reg_t rf_pwc; - volatile pmu_backup_cfg_reg_t backup_cfg; - volatile pmu_int_raw_reg_t int_raw; - volatile pmu_hp_int_st_reg_t hp_int_st; - volatile pmu_hp_int_ena_reg_t hp_int_ena; - volatile pmu_hp_int_clr_reg_t hp_int_clr; - volatile pmu_lp_int_raw_reg_t lp_int_raw; - volatile pmu_lp_int_st_reg_t lp_int_st; - volatile pmu_lp_int_ena_reg_t lp_int_ena; - volatile pmu_lp_int_clr_reg_t lp_int_clr; - volatile pmu_lp_cpu_pwr0_reg_t lp_cpu_pwr0; - volatile pmu_lp_cpu_pwr1_reg_t lp_cpu_pwr1; - volatile pmu_hp_lp_cpu_comm_reg_t hp_lp_cpu_comm; - volatile pmu_hp_regulator_cfg_reg_t hp_regulator_cfg; - volatile pmu_main_state_reg_t main_state; - volatile pmu_pwr_state_reg_t pwr_state; - volatile pmu_clk_state0_reg_t clk_state0; - volatile pmu_clk_state1_reg_t clk_state1; - volatile pmu_clk_state2_reg_t clk_state2; - volatile pmu_vdd_spi_status_reg_t vdd_spi_status; - uint32_t reserved_1a4[150]; - volatile pmu_date_reg_t date; + union { + struct { + volatile uint32_t pmu_date: 31; + volatile uint32_t clk_en : 1; + }; + volatile uint32_t val; + } date; } pmu_dev_t; extern pmu_dev_t PMU; #ifndef __cplusplus _Static_assert(sizeof(pmu_dev_t) == 0x400, "Invalid size of pmu_dev_t structure"); + +_Static_assert(offsetof(pmu_dev_t, reserved) == (PMU_VDD_SPI_STATUS_REG - DR_REG_PMU_BASE) + 4, "Invalid size of pmu_dev_t structure"); + #endif #ifdef __cplusplus diff --git a/components/soc/esp32c5/include/soc/reg_base.h b/components/soc/esp32c5/include/soc/reg_base.h index c91ef0596e..ce5adec458 100644 --- a/components/soc/esp32c5/include/soc/reg_base.h +++ b/components/soc/esp32c5/include/soc/reg_base.h @@ -86,7 +86,7 @@ #define DR_REG_LP_IO_BASE 0x600B2000 #define DR_REG_LP_I2C_ANA_MST_BASE 0x600B2400 #define DR_REG_LPPERI_BASE 0x600B2800 -#define DR_REG_LP_ANA_PERI_BASE 0x600B2C00 +#define DR_REG_LP_ANA_BASE 0x600B2C00 #define DR_REG_HUK_BASE 0x600B3000 #define DR_REG_LP_TEE_BASE 0x600B3400 #define DR_REG_LP_APM_BASE 0x600B3800 @@ -99,4 +99,4 @@ #define DR_REG_TRACE_BASE 0x600C0000 #define DR_REG_ASSIST_DEBUG_BASE 0x600C2000 #define DR_REG_INTPRI_BASE 0x600C5000 -#define DR_REG_CACHE_BASE 0x600C8000 +#define DR_REG_CACHE_BASE 0x600C8000 // CACHE_CONFIG/EXTMEM diff --git a/components/soc/esp32c5/include/soc/regi2c_bbpll.h b/components/soc/esp32c5/include/soc/regi2c_bbpll.h new file mode 100644 index 0000000000..0a5b39a36c --- /dev/null +++ b/components/soc/esp32c5/include/soc/regi2c_bbpll.h @@ -0,0 +1,86 @@ +/* + * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +/** + * @file regi2c_bbpll.h + * @brief Register definitions for digital PLL (BBPLL) + * + * This file lists register fields of BBPLL, located on an internal configuration + * bus. These definitions are used via macros defined in regi2c_ctrl.h, by + * rtc_clk_cpu_freq_set function in rtc_clk.c. + */ + +#define I2C_BBPLL 0x66 +#define I2C_BBPLL_HOSTID 0 + + +#define I2C_BBPLL_IR_CAL_EXT_CAP 1 +#define I2C_BBPLL_IR_CAL_EXT_CAP_MSB 4 +#define I2C_BBPLL_IR_CAL_EXT_CAP_LSB 0 + +#define I2C_BBPLL_IR_CAL_ENX_CAP 1 +#define I2C_BBPLL_IR_CAL_ENX_CAP_MSB 5 +#define I2C_BBPLL_IR_CAL_ENX_CAP_LSB 5 + +#define I2C_BBPLL_IR_CAL_RSTB 1 +#define I2C_BBPLL_IR_CAL_RSTB_MSB 6 +#define I2C_BBPLL_IR_CAL_RSTB_LSB 6 + +#define I2C_BBPLL_IR_CAL_START 1 +#define I2C_BBPLL_IR_CAL_START_MSB 7 +#define I2C_BBPLL_IR_CAL_START_LSB 7 + + + +#define I2C_BBPLL_OC_REF_DIV 2 +#define I2C_BBPLL_OC_REF_DIV_MSB 3 +#define I2C_BBPLL_OC_REF_DIV_LSB 0 + +#define I2C_BBPLL_OC_DCHGP 2 +#define I2C_BBPLL_OC_DCHGP_MSB 6 +#define I2C_BBPLL_OC_DCHGP_LSB 4 + +#define I2C_BBPLL_IR_CAL_UNSTOP 2 +#define I2C_BBPLL_IR_CAL_UNSTOP_MSB 7 +#define I2C_BBPLL_IR_CAL_UNSTOP_LSB 7 + +#define I2C_BBPLL_OC_DIV_7_0 3 +#define I2C_BBPLL_OC_DIV_7_0_MSB 7 +#define I2C_BBPLL_OC_DIV_7_0_LSB 0 + +#define I2C_BBPLL_OC_DR1 5 +#define I2C_BBPLL_OC_DR1_MSB 2 +#define I2C_BBPLL_OC_DR1_LSB 0 + +#define I2C_BBPLL_OC_DR3 5 +#define I2C_BBPLL_OC_DR3_MSB 6 +#define I2C_BBPLL_OC_DR3_LSB 4 + +#define I2C_BBPLL_OC_DHREF_SEL 6 +#define I2C_BBPLL_OC_DHREF_SEL_MSB 5 +#define I2C_BBPLL_OC_DHREF_SEL_LSB 4 + +#define I2C_BBPLL_OC_DLREF_SEL 6 +#define I2C_BBPLL_OC_DLREF_SEL_MSB 7 +#define I2C_BBPLL_OC_DLREF_SEL_LSB 6 + +#define I2C_BBPLL_OR_LOCK 8 +#define I2C_BBPLL_OR_LOCK_MSB 3 +#define I2C_BBPLL_OR_LOCK_LSB 3 + +#define I2C_BBPLL_OC_VCO_DBIAS 9 +#define I2C_BBPLL_OC_VCO_DBIAS_MSB 2 +#define I2C_BBPLL_OC_VCO_DBIAS_LSB 0 + +#define I2C_BBPLL_ENT_PLL 10 +#define I2C_BBPLL_ENT_PLL_MSB 3 +#define I2C_BBPLL_ENT_PLL_LSB 3 + +#define I2C_BBPLL_DTEST 10 +#define I2C_BBPLL_DTEST_MSB 5 +#define I2C_BBPLL_DTEST_LSB 4 diff --git a/components/soc/esp32c5/include/soc/regi2c_defs.h b/components/soc/esp32c5/include/soc/regi2c_defs.h new file mode 100644 index 0000000000..295fda22cf --- /dev/null +++ b/components/soc/esp32c5/include/soc/regi2c_defs.h @@ -0,0 +1,30 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include "esp_bit_defs.h" + +// TODO: [ESP32C5] IDF-8824 +/* Analog function control register */ +#define I2C_MST_ANA_CONF0_REG 0x600AF818 +#define I2C_MST_BBPLL_STOP_FORCE_HIGH (BIT(2)) +#define I2C_MST_BBPLL_STOP_FORCE_LOW (BIT(3)) +#define I2C_MST_BBPLL_CAL_DONE (BIT(24)) + + +#define ANA_CONFIG_REG 0x600AF81C +#define ANA_CONFIG_S (8) +#define ANA_CONFIG_M (0x3FF) + +#define ANA_I2C_SAR_FORCE_PD BIT(18) +#define ANA_I2C_BBPLL_M BIT(17) /* Clear to enable BBPLL */ + + +#define ANA_CONFIG2_REG 0x600AF820 +#define ANA_CONFIG2_M BIT(18) + +#define ANA_I2C_SAR_FORCE_PU BIT(16) diff --git a/components/soc/esp32c5/include/soc/regi2c_dig_reg.h b/components/soc/esp32c5/include/soc/regi2c_dig_reg.h new file mode 100644 index 0000000000..8b277dfcd6 --- /dev/null +++ b/components/soc/esp32c5/include/soc/regi2c_dig_reg.h @@ -0,0 +1,64 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +/** + * @file regi2c_dig_reg.h + * @brief Register definitions for digital to get rtc voltage & digital voltage + * by setting rtc_dbias_Wak & dig_dbias_wak or by analog self-calibration. + */ + +#define I2C_DIG_REG 0x6D +#define I2C_DIG_REG_HOSTID 0 + +#define I2C_DIG_REG_EXT_RTC_DREG 4 +#define I2C_DIG_REG_EXT_RTC_DREG_MSB 4 +#define I2C_DIG_REG_EXT_RTC_DREG_LSB 0 + +#define I2C_DIG_REG_ENX_RTC_DREG 4 +#define I2C_DIG_REG_ENX_RTC_DREG_MSB 7 +#define I2C_DIG_REG_ENX_RTC_DREG_LSB 7 + +#define I2C_DIG_REG_EXT_RTC_DREG_SLEEP 5 +#define I2C_DIG_REG_EXT_RTC_DREG_SLEEP_MSB 4 +#define I2C_DIG_REG_EXT_RTC_DREG_SLEEP_LSB 0 + +#define I2C_DIG_REG_ENIF_RTC_DREG 5 +#define I2C_DIG_REG_ENIF_RTC_DREG_MSB 7 +#define I2C_DIG_REG_ENIF_RTC_DREG_LSB 7 + +#define I2C_DIG_REG_EXT_DIG_DREG 6 +#define I2C_DIG_REG_EXT_DIG_DREG_MSB 4 +#define I2C_DIG_REG_EXT_DIG_DREG_LSB 0 + +#define I2C_DIG_REG_ENX_DIG_DREG 6 +#define I2C_DIG_REG_ENX_DIG_DREG_MSB 7 +#define I2C_DIG_REG_ENX_DIG_DREG_LSB 7 + +#define I2C_DIG_REG_EXT_DIG_DREG_SLEEP 7 +#define I2C_DIG_REG_EXT_DIG_DREG_SLEEP_MSB 4 +#define I2C_DIG_REG_EXT_DIG_DREG_SLEEP_LSB 0 + +#define I2C_DIG_REG_ENIF_DIG_DREG 7 +#define I2C_DIG_REG_ENIF_DIG_DREG_MSB 7 +#define I2C_DIG_REG_ENIF_DIG_DREG_LSB 7 + +#define I2C_DIG_REG_OR_EN_CONT_CAL 9 +#define I2C_DIG_REG_OR_EN_CONT_CAL_MSB 7 +#define I2C_DIG_REG_OR_EN_CONT_CAL_LSB 7 + +#define I2C_DIG_REG_XPD_RTC_REG 13 +#define I2C_DIG_REG_XPD_RTC_REG_MSB 2 +#define I2C_DIG_REG_XPD_RTC_REG_LSB 2 + +#define I2C_DIG_REG_XPD_DIG_REG 13 +#define I2C_DIG_REG_XPD_DIG_REG_MSB 3 +#define I2C_DIG_REG_XPD_DIG_REG_LSB 3 + +#define I2C_DIG_REG_SCK_DCAP 14 +#define I2C_DIG_REG_SCK_DCAP_MSB 7 +#define I2C_DIG_REG_SCK_DCAP_LSB 0 diff --git a/components/soc/esp32c5/include/soc/reset_reasons.h b/components/soc/esp32c5/include/soc/reset_reasons.h index 9576fb759f..76bc3be4ad 100644 --- a/components/soc/esp32c5/include/soc/reset_reasons.h +++ b/components/soc/esp32c5/include/soc/reset_reasons.h @@ -23,30 +23,31 @@ extern "C" { #endif -// TODO: [ESP32C5] IDF-8660 (inherit from P4) +// TODO: [ESP32C5] IDF-8660 (inherit from C6) /** * @brief Naming conventions: RESET_REASON_{reset level}_{reset reason} * @note refer to TRM: chapter */ typedef enum { - RESET_REASON_CHIP_POWER_ON = 0x01, // Power on reset - RESET_REASON_CORE_SW = 0x03, // Software resets the digital core - RESET_REASON_CORE_DEEP_SLEEP = 0x05, // Deep sleep reset the digital core, check when doing sleep bringup if 0x5/0x6 is deepsleep wakeup TODO IDF-7529 - RESET_REASON_SYS_PMU_PWR_DOWN = 0x05, // PMU HP power down system reset - RESET_REASON_CPU_PMU_PWR_DOWN = 0x06, // PMU HP power down CPU reset - RESET_REASON_SYS_HP_WDT = 0x07, // HP WDT resets system - RESET_REASON_SYS_LP_WDT = 0x09, // LP WDT resets system - RESET_REASON_CORE_HP_WDT = 0x0B, // HP WDT resets digital core - RESET_REASON_CPU0_SW = 0x0C, // Software resets CPU 0 - RESET_REASON_CORE_LP_WDT = 0x0D, // LP WDT resets digital core - RESET_REASON_SYS_BROWN_OUT = 0x0F, // VDD voltage is not stable and resets the digital core - RESET_REASON_CHIP_LP_WDT = 0x10, // LP WDT resets chip - RESET_REASON_SYS_SUPER_WDT = 0x12, // Super watch dog resets the digital core and rtc module - RESET_REASON_SYS_CLK_GLITCH = 0x13, // Glitch on clock resets the digital core and rtc module - RESET_REASON_CORE_EFUSE_CRC = 0x14, // eFuse CRC error resets the digital core - RESET_REASON_CORE_USB_JTAG = 0x16, // USB Serial/JTAG controller's JTAG resets the digital core - RESET_REASON_CORE_USB_UART = 0x17, // USB Serial/JTAG controller's UART resets the digital core - RESET_REASON_CPU_JTAG = 0x18, // Glitch on power resets the digital core + RESET_REASON_CHIP_POWER_ON = 0x01, // Power on reset + RESET_REASON_CHIP_BROWN_OUT = 0x01, // VDD voltage is not stable and resets the chip + RESET_REASON_CORE_SW = 0x03, // Software resets the digital core (hp system) by LP_AON_HPSYS_SW_RESET + RESET_REASON_CORE_DEEP_SLEEP = 0x05, // Deep sleep reset the digital core (hp system) + RESET_REASON_CORE_SDIO = 0x06, // SDIO module resets the digital core (hp system) + RESET_REASON_CORE_MWDT0 = 0x07, // Main watch dog 0 resets digital core (hp system) + RESET_REASON_CORE_MWDT1 = 0x08, // Main watch dog 1 resets digital core (hp system) + RESET_REASON_CORE_RTC_WDT = 0x09, // RTC watch dog resets digital core (hp system) + RESET_REASON_CPU0_MWDT0 = 0x0B, // Main watch dog 0 resets CPU 0 + RESET_REASON_CPU0_SW = 0x0C, // Software resets CPU 0 by LP_AON_CPU_CORE0_SW_RESET + RESET_REASON_CPU0_RTC_WDT = 0x0D, // RTC watch dog resets CPU 0 + RESET_REASON_SYS_BROWN_OUT = 0x0F, // VDD voltage is not stable and resets the digital core + RESET_REASON_SYS_RTC_WDT = 0x10, // RTC watch dog resets digital core and rtc module + RESET_REASON_CPU0_MWDT1 = 0x11, // Main watch dog 1 resets CPU 0 + RESET_REASON_SYS_SUPER_WDT = 0x12, // Super watch dog resets the digital core and rtc module + RESET_REASON_CORE_EFUSE_CRC = 0x14, // eFuse CRC error resets the digital core (hp system) + RESET_REASON_CORE_USB_UART = 0x15, // USB UART resets the digital core (hp system) + RESET_REASON_CORE_USB_JTAG = 0x16, // USB JTAG resets the digital core (hp system) + RESET_REASON_CPU0_JTAG = 0x18, // JTAG resets the CPU 0 } soc_reset_reason_t; diff --git a/components/soc/esp32c5/include/soc/rtc.h b/components/soc/esp32c5/include/soc/rtc.h new file mode 100644 index 0000000000..a37bdf668e --- /dev/null +++ b/components/soc/esp32c5/include/soc/rtc.h @@ -0,0 +1,524 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include +#include +#include "soc/soc.h" +#include "soc/clk_tree_defs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @file rtc.h + * @brief Low-level RTC power, clock functions. + * + * Functions in this file facilitate configuration of ESP32's RTC_CNTL peripheral. + * RTC_CNTL peripheral handles many functions: + * - enables/disables clocks and power to various parts of the chip; this is + * done using direct register access (forcing power up or power down) or by + * allowing state machines to control power and clocks automatically + * - handles sleep and wakeup functions + * - maintains a 48-bit counter which can be used for timekeeping + * + * These functions are not thread safe, and should not be viewed as high level + * APIs. For example, while this file provides a function which can switch + * CPU frequency, this function is on its own is not sufficient to implement + * frequency switching in ESP-IDF context: some coordination with RTOS, + * peripheral drivers, and WiFi/BT stacks is also required. + * + * These functions will normally not be used in applications directly. + * ESP-IDF provides, or will provide, drivers and other facilities to use + * RTC subsystem functionality. + * + * The functions are loosely split into the following groups: + * - rtc_clk: clock switching, calibration + * - rtc_time: reading RTC counter, conversion between counter values and time + */ + +#define MHZ (1000000) + +#define RTC_SLOW_CLK_150K_CAL_TIMEOUT_THRES(cycles) (cycles << 10) +#define RTC_SLOW_CLK_32K_CAL_TIMEOUT_THRES(cycles) (cycles << 12) +#define RTC_FAST_CLK_20M_CAL_TIMEOUT_THRES(cycles) (TIMG_RTC_CALI_TIMEOUT_THRES_V) // Just use the max timeout thres value + +#define OTHER_BLOCKS_POWERUP 1 +#define OTHER_BLOCKS_WAIT 1 + +// TODO: [ESP32C5] IDF-8667 +/* Approximate mapping of voltages to RTC_CNTL_DBIAS_WAK, RTC_CNTL_DBIAS_SLP, + * RTC_CNTL_DIG_DBIAS_WAK, RTC_CNTL_DIG_DBIAS_SLP values. + */ +#define RTC_CNTL_DBIAS_SLP 5 //sleep dig_dbias & rtc_dbias +#define RTC_CNTL_DBIAS_0V90 13 //digital voltage +#define RTC_CNTL_DBIAS_0V95 16 +#define RTC_CNTL_DBIAS_1V00 18 +#define RTC_CNTL_DBIAS_1V05 20 +#define RTC_CNTL_DBIAS_1V10 23 +#define RTC_CNTL_DBIAS_1V15 25 +#define RTC_CNTL_DBIAS_1V20 28 +#define RTC_CNTL_DBIAS_1V25 30 +#define RTC_CNTL_DBIAS_1V30 31 //voltage is about 1.34v in fact + +/* Delays for various clock sources to be enabled/switched. + * All values are in microseconds. + */ +#define SOC_DELAY_RTC_FAST_CLK_SWITCH 3 +#define SOC_DELAY_RTC_SLOW_CLK_SWITCH 300 +#define SOC_DELAY_RC_FAST_ENABLE 50 +#define SOC_DELAY_RC_FAST_DIGI_SWITCH 5 +#define SOC_DELAY_RC32K_ENABLE 300 + +/* Core voltage: // TODO: [ESP32C5] IDF-8667 + * Currently, ESP32C5 never adjust its wake voltage in runtime + * Only sets dig/rtc voltage dbias at startup time + */ +#define DIG_DBIAS_80M RTC_CNTL_DBIAS_1V20 +#define DIG_DBIAS_160M RTC_CNTL_DBIAS_1V20 +#define DIG_DBIAS_XTAL RTC_CNTL_DBIAS_1V10 +#define DIG_DBIAS_2M RTC_CNTL_DBIAS_1V00 + +#define RTC_CNTL_PLL_BUF_WAIT_DEFAULT 20 +#define RTC_CNTL_XTL_BUF_WAIT_DEFAULT 100 +#define RTC_CNTL_CK8M_WAIT_DEFAULT 20 +#define RTC_CK8M_ENABLE_WAIT_DEFAULT 5 + +#define RTC_CNTL_CK8M_DFREQ_DEFAULT 100 +#define RTC_CNTL_SCK_DCAP_DEFAULT 128 +#define RTC_CNTL_RC32K_DFREQ_DEFAULT 700 + +/* Various delays to be programmed into power control state machines */ +#define RTC_CNTL_XTL_BUF_WAIT_SLP_US (250) +#define RTC_CNTL_PLL_BUF_WAIT_SLP_CYCLES (1) +#define RTC_CNTL_CK8M_WAIT_SLP_CYCLES (4) +#define RTC_CNTL_WAKEUP_DELAY_CYCLES (5) +#define RTC_CNTL_OTHER_BLOCKS_POWERUP_CYCLES (1) +#define RTC_CNTL_OTHER_BLOCKS_WAIT_CYCLES (1) +#define RTC_CNTL_MIN_SLP_VAL_MIN (2) + +/* +set sleep_init default param +*/ +#define RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT 5 +#define RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_NODROP 0 +#define RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT 15 +#define RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT 0 +#define RTC_CNTL_BIASSLP_MONITOR_DEFAULT 0 +#define RTC_CNTL_BIASSLP_SLEEP_ON 0 +#define RTC_CNTL_BIASSLP_SLEEP_DEFAULT 1 +#define RTC_CNTL_PD_CUR_MONITOR_DEFAULT 0 +#define RTC_CNTL_PD_CUR_SLEEP_ON 0 +#define RTC_CNTL_PD_CUR_SLEEP_DEFAULT 1 +#define RTC_CNTL_DG_VDD_DRV_B_SLP_DEFAULT 254 + +/* +The follow value is used to get a reasonable rtc voltage dbias value according to digital dbias & some other value +storing in efuse (based on ATE 5k ECO3 chips) +*/ +#define K_RTC_MID_MUL10000 215 +#define K_DIG_MID_MUL10000 213 +#define V_RTC_MID_MUL10000 10800 +#define V_DIG_MID_MUL10000 10860 + +/** + * @brief Possible main XTAL frequency values. + * + * Enum values should be equal to frequency in MHz. + */ +typedef enum { + RTC_XTAL_FREQ_40M = 40, //!< 40 MHz XTAL + RTC_XTAL_FREQ_48M = 48, //!< 48 MHz XTAL +} rtc_xtal_freq_t; + +/** + * @brief CPU clock configuration structure + */ +typedef struct rtc_cpu_freq_config_s { + soc_cpu_clk_src_t source; //!< The clock from which CPU clock is derived + uint32_t source_freq_mhz; //!< Source clock frequency + uint32_t div; //!< Divider, freq_mhz = SOC_ROOT_CLK freq_mhz / div + uint32_t freq_mhz; //!< CPU clock frequency +} rtc_cpu_freq_config_t; + +#define RTC_CLK_CAL_FRACT 19 //!< Number of fractional bits in values returned by rtc_clk_cal + +#define RTC_VDDSDIO_TIEH_1_8V 0 //!< TIEH field value for 1.8V VDDSDIO +#define RTC_VDDSDIO_TIEH_3_3V 1 //!< TIEH field value for 3.3V VDDSDIO + + +/** + * @brief Clock source to be calibrated using rtc_clk_cal function + * + * @note On previous targets, the enum values somehow reflects the register field values of TIMG_RTC_CALI_CLK_SEL + * However, this is not true on ESP32C5. The conversion to register field values is explicitly done in + * rtc_clk_cal_internal + */ +typedef enum { + RTC_CAL_RTC_MUX = -1, //!< Currently selected RTC_SLOW_CLK + // RTC_CAL_RC_SLOW = SOC_RTC_SLOW_CLK_SRC_RC_SLOW, //!< Internal 150kHz RC oscillator + RTC_CAL_RC32K = SOC_RTC_SLOW_CLK_SRC_RC32K, //!< Internal 32kHz RC oscillator, as one type of 32k clock + RTC_CAL_32K_XTAL = SOC_RTC_SLOW_CLK_SRC_XTAL32K, //!< External 32kHz XTAL, as one type of 32k clock + RTC_CAL_32K_OSC_SLOW = SOC_RTC_SLOW_CLK_SRC_OSC_SLOW, //!< External slow clock signal input by lp_pad_gpio0, as one type of 32k clock + RTC_CAL_RC_FAST //!< Internal 20MHz RC oscillator +} rtc_cal_sel_t; + +/** + * Initialization parameters for rtc_clk_init + */ +typedef struct { + rtc_xtal_freq_t xtal_freq : 8; //!< Main XTAL frequency + uint32_t cpu_freq_mhz : 10; //!< CPU frequency to set, in MHz + soc_rtc_fast_clk_src_t fast_clk_src : 2; //!< RTC_FAST_CLK clock source to choose + soc_rtc_slow_clk_src_t slow_clk_src : 3; //!< RTC_SLOW_CLK clock source to choose + uint32_t clk_rtc_clk_div : 8; + uint32_t clk_8m_clk_div : 3; //!< RC_FAST clock divider (division is by clk_8m_div+1, i.e. 0 means ~20MHz frequency) + uint32_t slow_clk_dcap : 8; //!< RC_SLOW clock adjustment parameter (higher value leads to lower frequency) + uint32_t clk_8m_dfreq : 10; //!< RC_FAST clock adjustment parameter (higher value leads to higher frequency) + uint32_t rc32k_dfreq : 10; //!< Internal RC32K clock adjustment parameter (higher value leads to higher frequency) +} rtc_clk_config_t; + +/** + * Default initializer for rtc_clk_config_t + */ +#define RTC_CLK_CONFIG_DEFAULT() { \ + .xtal_freq = CONFIG_XTAL_FREQ, \ + .cpu_freq_mhz = 80, \ + .fast_clk_src = SOC_RTC_FAST_CLK_SRC_RC_FAST, \ + .slow_clk_src = SOC_RTC_SLOW_CLK_SRC_RC32K, \ + .clk_rtc_clk_div = 0, \ + .clk_8m_clk_div = 0, \ + .slow_clk_dcap = RTC_CNTL_SCK_DCAP_DEFAULT, \ + .clk_8m_dfreq = RTC_CNTL_CK8M_DFREQ_DEFAULT, \ + .rc32k_dfreq = RTC_CNTL_RC32K_DFREQ_DEFAULT, \ +} + +/** + * Initialize clocks and set CPU frequency + * + * @param cfg clock configuration as rtc_clk_config_t + */ +void rtc_clk_init(rtc_clk_config_t cfg); + +/** + * @brief Get main XTAL frequency + * + * This is the value stored in RTC register RTC_XTAL_FREQ_REG by the bootloader. As passed to + * rtc_clk_init function + * + * @return XTAL frequency, one of rtc_xtal_freq_t + */ +rtc_xtal_freq_t rtc_clk_xtal_freq_get(void); + +/** + * @brief Update XTAL frequency + * + * Updates the XTAL value stored in RTC_XTAL_FREQ_REG. Usually this value is ignored + * after startup. + * + * @param xtal_freq New frequency value + */ +void rtc_clk_xtal_freq_update(rtc_xtal_freq_t xtal_freq); + +/** + * @brief Enable or disable 32 kHz XTAL oscillator + * @param en true to enable, false to disable + */ +void rtc_clk_32k_enable(bool en); + +/** + * @brief Configure 32 kHz XTAL oscillator to accept external clock signal + */ +void rtc_clk_32k_enable_external(void); + +/** + * @brief Get the state of 32k XTAL oscillator + * @return true if 32k XTAL oscillator has been enabled + */ +bool rtc_clk_32k_enabled(void); + +/** + * @brief Enable 32k oscillator, configuring it for fast startup time. + * Note: to achieve higher frequency stability, rtc_clk_32k_enable function + * must be called one the 32k XTAL oscillator has started up. This function + * will initially disable the 32k XTAL oscillator, so it should not be called + * when the system is using 32k XTAL as RTC_SLOW_CLK. + * + * @param cycle Number of 32kHz cycles to bootstrap external crystal. + * If 0, no square wave will be used to bootstrap crystal oscillation. + */ +void rtc_clk_32k_bootstrap(uint32_t cycle); + +/** + * @brief Enable or disable 32 kHz internal rc oscillator + * @param en true to enable, false to disable + */ +void rtc_clk_rc32k_enable(bool enable); + +/** + * @brief Enable or disable 8 MHz internal oscillator + * + * @param clk_8m_en true to enable 8MHz generator + */ +void rtc_clk_8m_enable(bool clk_8m_en); + +/** + * @brief Get the state of 8 MHz internal oscillator + * @return true if the oscillator is enabled + */ +bool rtc_clk_8m_enabled(void); + +/** + * @brief Select source for RTC_SLOW_CLK + * @param clk_src clock source (one of soc_rtc_slow_clk_src_t values) + */ +void rtc_clk_slow_src_set(soc_rtc_slow_clk_src_t clk_src); + +/** + * @brief Get the RTC_SLOW_CLK source + * @return currently selected clock source (one of soc_rtc_slow_clk_src_t values) + */ +soc_rtc_slow_clk_src_t rtc_clk_slow_src_get(void); + +/** + * @brief Get the approximate frequency of RTC_SLOW_CLK, in Hz + * + * - if SOC_RTC_SLOW_CLK_SRC_RC_SLOW is selected, returns 136000 + * - if SOC_RTC_SLOW_CLK_SRC_XTAL32K is selected, returns 32768 + * - if SOC_RTC_SLOW_CLK_SRC_RC32K is selected, returns 32768 + * - if SOC_RTC_SLOW_CLK_SRC_OSC_SLOW is selected, returns 32768 + * + * rtc_clk_cal function can be used to get more precise value by comparing + * RTC_SLOW_CLK frequency to the frequency of main XTAL. + * + * @return RTC_SLOW_CLK frequency, in Hz + */ +uint32_t rtc_clk_slow_freq_get_hz(void); + +/** + * @brief Select source for RTC_FAST_CLK + * @param clk_src clock source (one of soc_rtc_fast_clk_src_t values) + */ +void rtc_clk_fast_src_set(soc_rtc_fast_clk_src_t clk_src); + +/** + * @brief Get the RTC_FAST_CLK source + * @return currently selected clock source (one of soc_rtc_fast_clk_src_t values) + */ +soc_rtc_fast_clk_src_t rtc_clk_fast_src_get(void); + +/** + * @brief Get CPU frequency config for a given frequency + * @param freq_mhz Frequency in MHz + * @param[out] out_config Output, CPU frequency configuration structure + * @return true if frequency can be obtained, false otherwise + */ +bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t *out_config); + +/** + * @brief Switch CPU frequency + * + * This function sets CPU frequency according to the given configuration + * structure. It enables PLLs, if necessary. + * + * @note This function in not intended to be called by applications in FreeRTOS + * environment. This is because it does not adjust various timers based on the + * new CPU frequency. + * + * @param config CPU frequency configuration structure + */ +void rtc_clk_cpu_freq_set_config(const rtc_cpu_freq_config_t *config); + +/** + * @brief Switch CPU frequency (optimized for speed) + * + * This function is a faster equivalent of rtc_clk_cpu_freq_set_config. + * It works faster because it does not disable PLLs when switching from PLL to + * XTAL and does not enabled them when switching back. If PLL is not already + * enabled when this function is called to switch from XTAL to PLL frequency, + * or the PLL which is enabled is the wrong one, this function will fall back + * to calling rtc_clk_cpu_freq_set_config. + * + * Unlike rtc_clk_cpu_freq_set_config, this function relies on static data, + * so it is less safe to use it e.g. from a panic handler (when memory might + * be corrupted). + * + * @note This function in not intended to be called by applications in FreeRTOS + * environment. This is because it does not adjust various timers based on the + * new CPU frequency. + * + * @param config CPU frequency configuration structure + */ +void rtc_clk_cpu_freq_set_config_fast(const rtc_cpu_freq_config_t *config); + +/** + * @brief Get the currently used CPU frequency configuration + * @param[out] out_config Output, CPU frequency configuration structure + */ +void rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t *out_config); + +/** + * @brief Switch CPU clock source to XTAL + * + * Short form for filling in rtc_cpu_freq_config_t structure and calling + * rtc_clk_cpu_freq_set_config when a switch to XTAL is needed. + * Assumes that XTAL frequency has been determined — don't call in startup code. + * + * @note On ESP32C5, this function will check whether BBPLL can be disabled. If there is no consumer, then BBPLL will be + * turned off. The behaviour is the same as using rtc_clk_cpu_freq_set_config to switch cpu clock source to XTAL. + */ +void rtc_clk_cpu_freq_set_xtal(void); + +/** + * @brief Switch root clock source to PLL (only used by sleep) release root clock source locked by PMU + * + * wifi receiving beacon frame in PMU modem state strongly depends on the BBPLL + * clock, PMU will forcibly lock the root clock source as PLL, when the root + * clock source of the software system is selected as PLL, we need to release + * the root clock source locking and switch the root clock source to PLL in the + * sleep process (a critical section). + * + * @param[in] Maximum CPU frequency, in MHz + */ +void rtc_clk_cpu_freq_to_pll_and_pll_lock_release(int cpu_freq_mhz); + +/** + * @brief Get the current APB frequency. + * @return The calculated APB frequency value, in Hz. + */ +uint32_t rtc_clk_apb_freq_get(void); + +/** + * @brief Measure RTC slow clock's period, based on main XTAL frequency + * + * This function will time out and return 0 if the time for the given number + * of cycles to be counted exceeds the expected time twice. This may happen if + * 32k XTAL is being calibrated, but the oscillator has not started up (due to + * incorrect loading capacitance, board design issue, or lack of 32 XTAL on board). + * + * @note When 32k CLK is being calibrated, this function will check the accuracy + * of the clock. Since the xtal 32k or ext osc 32k is generally very stable, if + * the check fails, then consider this an invalid 32k clock and return 0. This + * check can filter some jamming signal. + * + * @param cal_clk clock to be measured + * @param slow_clk_cycles number of slow clock cycles to average + * @return average slow clock period in microseconds, Q13.19 fixed point format, + * or 0 if calibration has timed out + */ +uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slow_clk_cycles); + +/** + * @brief Convert time interval from microseconds to RTC_SLOW_CLK cycles + * @param time_in_us Time interval in microseconds + * @param slow_clk_period Period of slow clock in microseconds, Q13.19 + * fixed point format (as returned by rtc_slowck_cali). + * @return number of slow clock cycles + */ +uint64_t rtc_time_us_to_slowclk(uint64_t time_in_us, uint32_t period); + +/** + * @brief Convert time interval from RTC_SLOW_CLK to microseconds + * @param time_in_us Time interval in RTC_SLOW_CLK cycles + * @param slow_clk_period Period of slow clock in microseconds, Q13.19 + * fixed point format (as returned by rtc_slowck_cali). + * @return time interval in microseconds + */ +uint64_t rtc_time_slowclk_to_us(uint64_t rtc_cycles, uint32_t period); + +/** + * @brief Get current value of RTC counter + * + * RTC has a 48-bit counter which is incremented by 2 every 2 RTC_SLOW_CLK + * cycles. Counter value is not writable by software. The value is not adjusted + * when switching to a different RTC_SLOW_CLK source. + * + * Note: this function may take up to 1 RTC_SLOW_CLK cycle to execute + * + * @return current value of RTC counter + */ +uint64_t rtc_time_get(void); + +/** + * @brief Busy loop until next RTC_SLOW_CLK cycle + * + * This function returns not earlier than the next RTC_SLOW_CLK clock cycle. + * In some cases (e.g. when RTC_SLOW_CLK cycle is very close), it may return + * one RTC_SLOW_CLK cycle later. + */ +void rtc_clk_wait_for_slow_cycle(void); + +/** + * @brief Enable the rtc digital 8M clock + * + * This function is used to enable the digital rtc 8M clock to support peripherals. + * For enabling the analog 8M clock, using `rtc_clk_8M_enable` function above. + */ +void rtc_dig_clk8m_enable(void); + +/** + * @brief Disable the rtc digital 8M clock + * + * This function is used to disable the digital rtc 8M clock, which is only used to support peripherals. + */ +void rtc_dig_clk8m_disable(void); + +/** + * @brief Get whether the rtc digital 8M clock is enabled + */ +bool rtc_dig_8m_enabled(void); + +/** + * @brief Calculate the real clock value after the clock calibration + * + * @param cal_val Average slow clock period in microseconds, fixed point value as returned from `rtc_clk_cal` + * @return Frequency of the clock in Hz + */ +uint32_t rtc_clk_freq_cal(uint32_t cal_val); + + +// -------------------------- CLOCK TREE DEFS ALIAS ---------------------------- +// **WARNING**: The following are only for backwards compatibility. +// Please use the declarations in soc/clk_tree_defs.h instead. +/** + * @brief CPU clock source + */ +typedef soc_cpu_clk_src_t rtc_cpu_freq_src_t; +#define RTC_CPU_FREQ_SRC_XTAL SOC_CPU_CLK_SRC_XTAL //!< XTAL +#define RTC_CPU_FREQ_SRC_PLL SOC_CPU_CLK_SRC_PLL //!< PLL (480M) +#define RTC_CPU_FREQ_SRC_8M SOC_CPU_CLK_SRC_RC_FAST //!< Internal 17.5M RTC oscillator + +/** + * @brief RTC SLOW_CLK frequency values + */ +typedef soc_rtc_slow_clk_src_t rtc_slow_freq_t; +#define RTC_SLOW_FREQ_RTC SOC_RTC_SLOW_CLK_SRC_RC_SLOW //!< Internal 150 kHz RC oscillator +#define RTC_SLOW_FREQ_32K_XTAL SOC_RTC_SLOW_CLK_SRC_XTAL32K //!< External 32 kHz XTAL + +/** + * @brief RTC FAST_CLK frequency values + */ +typedef soc_rtc_fast_clk_src_t rtc_fast_freq_t; +#define RTC_FAST_FREQ_XTALD4 SOC_RTC_FAST_CLK_SRC_XTAL_DIV //!< Main XTAL, divided by 2 +#define RTC_FAST_FREQ_8M SOC_RTC_FAST_CLK_SRC_RC_FAST //!< Internal 17.5 MHz RC oscillator + +/* Alias of frequency related macros */ +#define RTC_FAST_CLK_FREQ_APPROX SOC_CLK_RC_FAST_FREQ_APPROX +#define RTC_FAST_CLK_FREQ_8M SOC_CLK_RC_FAST_FREQ_APPROX +#define RTC_SLOW_CLK_FREQ_150K SOC_CLK_RC_SLOW_FREQ_APPROX +#define RTC_SLOW_CLK_FREQ_32K SOC_CLK_XTAL32K_FREQ_APPROX + +/* Alias of deprecated function names */ +#define rtc_clk_slow_freq_set(slow_freq) rtc_clk_slow_src_set(slow_freq) +#define rtc_clk_slow_freq_get() rtc_clk_slow_src_get() +#define rtc_clk_fast_freq_set(fast_freq) rtc_clk_fast_src_set(fast_freq) +#define rtc_clk_fast_freq_get() rtc_clk_fast_src_get() + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/sha_struct.h b/components/soc/esp32c5/include/soc/sha_struct.h index d65e8e449e..41ae395f7e 100644 --- a/components/soc/esp32c5/include/soc/sha_struct.h +++ b/components/soc/esp32c5/include/soc/sha_struct.h @@ -59,10 +59,10 @@ typedef union { typedef union { struct { uint32_t reserved_0:1; - /** continue : RO; bitpos: [31:1]; default: 0; + /** conti : RO; bitpos: [31:1]; default: 0; * Reserved. */ - uint32_t continue:31; + uint32_t conti:31; }; uint32_t val; } sha_continue_reg_t; @@ -165,7 +165,7 @@ typedef struct sha_dev_t { uint32_t reserved_004[2]; volatile sha_dma_block_num_reg_t dma_block_num; volatile sha_start_reg_t start; - volatile sha_continue_reg_t continue; + volatile sha_continue_reg_t conti; volatile sha_busy_reg_t busy; volatile sha_dma_start_reg_t dma_start; volatile sha_dma_continue_reg_t dma_continue; diff --git a/components/soc/esp32c5/include/soc/soc.h b/components/soc/esp32c5/include/soc/soc.h index f7a2ee0a13..d32981407e 100644 --- a/components/soc/esp32c5/include/soc/soc.h +++ b/components/soc/esp32c5/include/soc/soc.h @@ -26,7 +26,7 @@ #define REG_TIMG_BASE(i) (DR_REG_TIMERG0_BASE + (i) * 0x1000) // TIMERG0 and TIMERG1 #define REG_TWAI_BASE(i) ((i) == 0 ? DR_REG_TWAI0_BASE : DR_REG_TWAI1_BASE) // TWAI0 and TWAI1 #define REG_UART_BASE(i) (DR_REG_UART0_BASE + (i) * 0x1000) // UART0 and UART1 - +#define REG_SPI_MEM_BASE(i) (DR_REG_SPIMEM0_BASE + (i) * 0x1000) //Registers Operation {{ #define ETS_UNCACHED_ADDR(addr) (addr) #define ETS_CACHED_ADDR(addr) (addr) @@ -153,7 +153,7 @@ * should be defined statically! */ -#define SOC_IROM_LOW 0x42000000 +#define SOC_IROM_LOW 0x41000000 #define SOC_IROM_HIGH (SOC_IROM_LOW + (SOC_MMU_PAGE_SIZE<<8)) #define SOC_DROM_LOW SOC_IROM_LOW #define SOC_DROM_HIGH SOC_IROM_HIGH diff --git a/components/soc/esp32c5/include/soc/soc_caps.h b/components/soc/esp32c5/include/soc/soc_caps.h index bd01111d29..f71b8b7e2d 100644 --- a/components/soc/esp32c5/include/soc/soc_caps.h +++ b/components/soc/esp32c5/include/soc/soc_caps.h @@ -17,67 +17,65 @@ #pragma once /*-------------------------- COMMON CAPS ---------------------------------------*/ -// #define SOC_ADC_SUPPORTED 1 -// #define SOC_DEDICATED_GPIO_SUPPORTED 1 -// #define SOC_UART_SUPPORTED 1 -// #define SOC_GDMA_SUPPORTED 1 -// #define SOC_AHB_GDMA_SUPPORTED 1 -// #define SOC_GPTIMER_SUPPORTED 1 -// #define SOC_PCNT_SUPPORTED 1 -// #define SOC_MCPWM_SUPPORTED 1 -// #define SOC_TWAI_SUPPORTED 1 -// #define SOC_ETM_SUPPORTED 1 -// #define SOC_PARLIO_SUPPORTED 1 -// #define SOC_BT_SUPPORTED 1 -// #define SOC_IEEE802154_SUPPORTED 1 -// #define SOC_ASYNC_MEMCPY_SUPPORTED 1 -// #define SOC_USB_SERIAL_JTAG_SUPPORTED 1 -// #define SOC_TEMP_SENSOR_SUPPORTED 1 -// #define SOC_WIFI_SUPPORTED 1 -// #define SOC_SUPPORTS_SECURE_DL_MODE 1 -// #define SOC_ULP_SUPPORTED 1 -// #define SOC_LP_CORE_SUPPORTED 1 -// #define SOC_EFUSE_KEY_PURPOSE_FIELD 1 -// #define SOC_EFUSE_SUPPORTED 1 -// #define SOC_RTC_FAST_MEM_SUPPORTED 1 -// #define SOC_RTC_MEM_SUPPORTED 1 -// #define SOC_I2S_SUPPORTED 1 -// #define SOC_RMT_SUPPORTED 1 -// #define SOC_SDM_SUPPORTED 1 -// #define SOC_GPSPI_SUPPORTED 1 -// #define SOC_LEDC_SUPPORTED 1 -// #define SOC_I2C_SUPPORTED 1 -// #define SOC_SYSTIMER_SUPPORTED 1 -// #define SOC_SUPPORT_COEXISTENCE 1 -// #define SOC_AES_SUPPORTED 1 +// #define SOC_ADC_SUPPORTED 1 // TODO: [ESP32C5] IDF-8701 +// #define SOC_DEDICATED_GPIO_SUPPORTED 1 // TODO: [ESP32C5] IDF-8725 +#define SOC_UART_SUPPORTED 1 // TODO: [ESP32C5] IDF-8722 +// #define SOC_GDMA_SUPPORTED 1 // TODO: [ESP32C5] IDF-8710 +// #define SOC_AHB_GDMA_SUPPORTED 1 // TODO: [ESP32C5] IDF-8710 +// #define SOC_GPTIMER_SUPPORTED 1 // TODO: [ESP32C5] IDF-8705 +// #define SOC_PCNT_SUPPORTED 1 // TODO: [ESP32C5] IDF-8683 +// #define SOC_MCPWM_SUPPORTED 1 // TODO: [ESP32C5] IDF-8709 +// #define SOC_TWAI_SUPPORTED 1 // TODO: [ESP32C5] IDF-8691 +// #define SOC_ETM_SUPPORTED 1 // TODO: [ESP32C5] IDF-8693 +// #define SOC_PARLIO_SUPPORTED 1 // TODO: [ESP32C5] IDF-8685, IDF-8686 +// #define SOC_ASYNC_MEMCPY_SUPPORTED 1 // TODO: [ESP32C5] IDF-8716 +// #define SOC_USB_SERIAL_JTAG_SUPPORTED 1 // TODO: [ESP32C5] IDF-8721 +// #define SOC_TEMP_SENSOR_SUPPORTED 1 // TODO: [ESP32C5] IDF-8727 +// #define SOC_WIFI_SUPPORTED 1 // TODO: [ESP32C5] IDF-8851 +// #define SOC_SUPPORTS_SECURE_DL_MODE 1 // TODO: [ESP32C5] IDF-8622, IDF-8674 +// #define SOC_LP_CORE_SUPPORTED 1 // TODO: [ESP32C5] IDF-8637 +#define SOC_EFUSE_KEY_PURPOSE_FIELD 1 // TODO: [ESP32C5] IDF-8674, need check +#define SOC_EFUSE_SUPPORTED 1 // TODO: [ESP32C5] IDF-8674 +#define SOC_RTC_FAST_MEM_SUPPORTED 1 +#define SOC_RTC_MEM_SUPPORTED 1 +// #define SOC_I2S_SUPPORTED 1 // TODO: [ESP32C5] IDF-8713, IDF-8714 +// #define SOC_RMT_SUPPORTED 1 // TODO: [ESP32C5] IDF-8726 +// #define SOC_SDM_SUPPORTED 1 // TODO: [ESP32C5] IDF-8687 +// #define SOC_GPSPI_SUPPORTED 1 // TODO: [ESP32C5] IDF-8698, IDF-8699 +// #define SOC_LEDC_SUPPORTED 1 // TODO: [ESP32C5] IDF-8684 +// #define SOC_I2C_SUPPORTED 1 // TODO: [ESP32C5] IDF-8694, IDF-8696 +#define SOC_SYSTIMER_SUPPORTED 1 // TODO: [ESP32C5] IDF-8707 +// #define SOC_AES_SUPPORTED 1 // TODO: [ESP32C5] IDF-8627 // #define SOC_MPI_SUPPORTED 1 -// #define SOC_SHA_SUPPORTED 1 -// #define SOC_HMAC_SUPPORTED 1 -// #define SOC_DIG_SIGN_SUPPORTED 1 -// #define SOC_ECC_SUPPORTED 1 -// #define SOC_FLASH_ENC_SUPPORTED 1 -// #define SOC_SECURE_BOOT_SUPPORTED 1 -// #define SOC_SDIO_SLAVE_SUPPORTED 1 -// #define SOC_BOD_SUPPORTED 1 -// #define SOC_APM_SUPPORTED 1 -// #define SOC_PMU_SUPPORTED 1 -// #define SOC_PAU_SUPPORTED 1 -// #define SOC_LP_TIMER_SUPPORTED 1 -// #define SOC_LP_AON_SUPPORTED 1 -// #define SOC_LP_PERIPHERALS_SUPPORTED 1 -// #define SOC_LP_I2C_SUPPORTED 1 -// #define SOC_ULP_LP_UART_SUPPORTED 1 -// #define SOC_CLK_TREE_SUPPORTED 1 -// #define SOC_ASSIST_DEBUG_SUPPORTED 1 -// #define SOC_WDT_SUPPORTED 1 -// #define SOC_SPI_FLASH_SUPPORTED 1 -// #define SOC_BITSCRAMBLER_SUPPORTED 1 -// #define SOC_ECDSA_SUPPORTED 1 -// #define SOC_KEY_MANAGER_SUPPORTED 1 +// #define SOC_SHA_SUPPORTED 1 // TODO: [ESP32C5] IDF-8624 +// #define SOC_RSA_SUPPORTED 1 // TODO: [ESP32C5] IDF-8620 +// #define SOC_HMAC_SUPPORTED 1 // TODO: [ESP32C5] IDF-8616 +// #define SOC_DIG_SIGN_SUPPORTED 1 // TODO: [ESP32C5] IDF-8619 +// #define SOC_ECC_SUPPORTED 1 // TODO: [ESP32C5] IDF-8625 +#define SOC_FLASH_ENC_SUPPORTED 1 // TODO: [ESP32C5] IDF-8622 +// #define SOC_SECURE_BOOT_SUPPORTED 1 // TODO: [ESP32C5] IDF-8623 +// #define SOC_BOD_SUPPORTED 1 // TODO: [ESP32C5] IDF-8647 +// #define SOC_APM_SUPPORTED 1 // TODO: [ESP32C5] IDF-8614 +#define SOC_PMU_SUPPORTED 1 // TODO: [ESP32C5] IDF-8667 +// #define SOC_PAU_SUPPORTED 1 // TODO: [ESP32C5] IDF-8638, IDF-8640 +// #define SOC_LP_TIMER_SUPPORTED 1 // TODO: [ESP32C5] IDF-8636 +// #define SOC_LP_AON_SUPPORTED 1 // TODO: [ESP32C5] IDF-8638, IDF-8640 +// #define SOC_LP_PERIPHERALS_SUPPORTED 1 // TODO: [ESP32C5] IDF-8695, IDF-8723, IDF-8719 +// #define SOC_LP_I2C_SUPPORTED 1 // TODO: [ESP32C5] IDF-8634 +// #define SOC_ULP_LP_UART_SUPPORTED 1 // TODO: [ESP32C5] IDF-8633 +// #define SOC_CLK_TREE_SUPPORTED 1 // TODO: [ESP32C5] IDF-8642 +// #define SOC_ASSIST_DEBUG_SUPPORTED 1 // TODO: [ESP32C5] IDF-8663 +// #define SOC_WDT_SUPPORTED 1 // TODO: [ESP32C5] IDF-8650 +#define SOC_SPI_FLASH_SUPPORTED 1 // TODO: [ESP32C5] IDF-8715 +// #define SOC_BITSCRAMBLER_SUPPORTED 1 // TODO: [ESP32C5] IDF-8711 +// #define SOC_ECDSA_SUPPORTED 1 // TODO: [ESP32C5] IDF-8618 +// #define SOC_KEY_MANAGER_SUPPORTED 1 // TODO: [ESP32C5] IDF-8621 +// #define SOC_HUK_SUPPORTED 1 // TODO: [ESP32C5] IDF-8617 #define SOC_INT_HW_NESTED_SUPPORTED 1 /*-------------------------- XTAL CAPS ---------------------------------------*/ -// #define SOC_XTAL_SUPPORT_40M 1 +#define SOC_XTAL_SUPPORT_40M 1 +#define SOC_XTAL_SUPPORT_48M 1 /*-------------------------- AES CAPS -----------------------------------------*/ // #define SOC_AES_SUPPORT_DMA (1) @@ -95,9 +93,9 @@ // #define SOC_ADC_MONITOR_SUPPORTED 1 // #define SOC_ADC_DIG_SUPPORTED_UNIT(UNIT) 1 //Digital controller supported ADC unit // #define SOC_ADC_DMA_SUPPORTED 1 -// #define SOC_ADC_PERIPH_NUM (1U) +#define SOC_ADC_PERIPH_NUM (1U) // #define SOC_ADC_CHANNEL_NUM(PERIPH_NUM) (7) -// #define SOC_ADC_MAX_CHANNEL_NUM (7) +#define SOC_ADC_MAX_CHANNEL_NUM (7) // #define SOC_ADC_ATTEN_NUM (4) /*!< Digital */ @@ -136,21 +134,23 @@ // #define SOC_BROWNOUT_RESET_SUPPORTED 1 /*-------------------------- CACHE CAPS --------------------------------------*/ -// #define SOC_SHARED_IDCACHE_SUPPORTED 1 //Shared Cache for both instructions and data -// #define SOC_CACHE_FREEZE_SUPPORTED 1 +#define SOC_SHARED_IDCACHE_SUPPORTED 1 //Shared Cache for both instructions and data +#define SOC_CACHE_FREEZE_SUPPORTED 1 /*-------------------------- CPU CAPS ----------------------------------------*/ #define SOC_CPU_CORES_NUM (1U) -// #define SOC_CPU_INTR_NUM 32 -// #define SOC_CPU_HAS_FLEXIBLE_INTC 1 +#define SOC_CPU_INTR_NUM 32 +#define SOC_CPU_HAS_FLEXIBLE_INTC 1 #define SOC_INT_CLIC_SUPPORTED 1 +#define SOC_INT_HW_NESTED_SUPPORTED 1 // Support for hardware interrupts nesting +#define SOC_BRANCH_PREDICTOR_SUPPORTED 1 -// #define SOC_CPU_BREAKPOINTS_NUM 4 -// #define SOC_CPU_WATCHPOINTS_NUM 4 -// #define SOC_CPU_WATCHPOINT_MAX_REGION_SIZE 0x80000000 // bytes +#define SOC_CPU_BREAKPOINTS_NUM 4 +#define SOC_CPU_WATCHPOINTS_NUM 4 +#define SOC_CPU_WATCHPOINT_MAX_REGION_SIZE 0x100 // bytes -// #define SOC_CPU_HAS_PMA 1 -// #define SOC_CPU_IDRAM_SPLIT_USING_PMP 1 +#define SOC_CPU_HAS_PMA 1 +#define SOC_CPU_IDRAM_SPLIT_USING_PMP 1 /*-------------------------- DIGITAL SIGNATURE CAPS ----------------------------------------*/ /** The maximum length of a Digital Signature in bits. */ @@ -174,6 +174,7 @@ // #define SOC_ETM_CHANNELS_PER_GROUP 50 // Number of ETM channels in the group /*-------------------------- GPIO CAPS ---------------------------------------*/ +// TODO: [ESP32C5] IDF-8717 // ESP32-C5 has 1 GPIO peripheral // #define SOC_GPIO_PORT 1U #define SOC_GPIO_PIN_COUNT 31 @@ -191,11 +192,11 @@ // GPIO0~7 on ESP32C5 can support chip deep sleep wakeup // #define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP (1) -// #define SOC_GPIO_VALID_GPIO_MASK ((1U< SPI0/SPI1, host_id = 1 -> SPI2, -// #define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(host_id) ({(void)host_id; 1;}) +#define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(host_id) ({(void)host_id; 1;}) // #define SOC_MEMSPI_IS_INDEPENDENT 1 // #define SOC_SPI_MAX_PRE_DIVIDER 16 @@ -400,19 +403,21 @@ // #define SOC_SPI_MEM_SUPPORT_CHECK_SUS (1) // #define SOC_SPI_MEM_SUPPORT_WRAP (1) -// #define SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED 1 -// #define SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED 1 -// #define SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED 1 +// TODO: [ESP32C5] IDF-8649 +#define SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED 1 +#define SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED 1 +#define SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED 1 /*-------------------------- SYSTIMER CAPS ----------------------------------*/ -// #define SOC_SYSTIMER_COUNTER_NUM 2 // Number of counter units -// #define SOC_SYSTIMER_ALARM_NUM 3 // Number of alarm units -// #define SOC_SYSTIMER_BIT_WIDTH_LO 32 // Bit width of systimer low part -// #define SOC_SYSTIMER_BIT_WIDTH_HI 20 // Bit width of systimer high part -// #define SOC_SYSTIMER_FIXED_DIVIDER 1 // Clock source divider is fixed: 2.5 -// #define SOC_SYSTIMER_SUPPORT_RC_FAST 1 // Systimer can use RC_FAST clock source -// #define SOC_SYSTIMER_INT_LEVEL 1 // Systimer peripheral uses level interrupt -// #define SOC_SYSTIMER_ALARM_MISS_COMPENSATE 1 // Systimer peripheral can generate interrupt immediately if t(target) > t(current) +// TODO: [ESP32C5] IDF-8707 +#define SOC_SYSTIMER_COUNTER_NUM 2 // Number of counter units +#define SOC_SYSTIMER_ALARM_NUM 3 // Number of alarm units +#define SOC_SYSTIMER_BIT_WIDTH_LO 32 // Bit width of systimer low part +#define SOC_SYSTIMER_BIT_WIDTH_HI 20 // Bit width of systimer high part +#define SOC_SYSTIMER_FIXED_DIVIDER 1 // Clock source divider is fixed: 2.5 +#define SOC_SYSTIMER_SUPPORT_RC_FAST 1 // Systimer can use RC_FAST clock source +#define SOC_SYSTIMER_INT_LEVEL 1 // Systimer peripheral uses level interrupt +#define SOC_SYSTIMER_ALARM_MISS_COMPENSATE 1 // Systimer peripheral can generate interrupt immediately if t(target) > t(current) // #define SOC_SYSTIMER_SUPPORT_ETM 1 // Systimer comparator can generate ETM event /*-------------------------- LP_TIMER CAPS ----------------------------------*/ @@ -450,14 +455,14 @@ /*-------------------------- Secure Boot CAPS----------------------------*/ // #define SOC_SECURE_BOOT_V2_RSA 1 // #define SOC_SECURE_BOOT_V2_ECC 1 -// #define SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 3 +#define SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 3 // TODO: [ESP32C5] IDF-8674 // #define SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS 1 // #define SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY 1 /*-------------------------- Flash Encryption CAPS----------------------------*/ -// #define SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX (64) +#define SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX (64) // TODO: [ESP32C5] IDF-8622 // #define SOC_FLASH_ENCRYPTION_XTS_AES 1 -// #define SOC_FLASH_ENCRYPTION_XTS_AES_128 1 +#define SOC_FLASH_ENCRYPTION_XTS_AES_128 1 // TODO: [ESP32C5] IDF-8622 /*------------------------ Anti DPA (Security) CAPS --------------------------*/ // #define SOC_CRYPTO_DPA_PROTECTION_SUPPORTED 1 @@ -467,12 +472,12 @@ #define SOC_UART_NUM (3) #define SOC_UART_HP_NUM (2) #define SOC_UART_LP_NUM (1U) -// #define SOC_UART_FIFO_LEN (128) /*!< The UART hardware FIFO length */ -// #define SOC_LP_UART_FIFO_LEN (16) /*!< The LP UART hardware FIFO length */ +#define SOC_UART_FIFO_LEN (128) /*!< The UART hardware FIFO length */ +#define SOC_LP_UART_FIFO_LEN (16) /*!< The LP UART hardware FIFO length */ // #define SOC_UART_BITRATE_MAX (5000000) /*!< Max bit rate supported by UART */ // #define SOC_UART_SUPPORT_PLL_F80M_CLK (1) /*!< Support PLL_F80M as the clock source */ // #define SOC_UART_SUPPORT_RTC_CLK (1) /*!< Support RTC clock as the clock source */ -// #define SOC_UART_SUPPORT_XTAL_CLK (1) /*!< Support XTAL clock as the clock source */ +#define SOC_UART_SUPPORT_XTAL_CLK (1) /*!< Support XTAL clock as the clock source */ // #define SOC_UART_SUPPORT_WAKEUP_INT (1) /*!< Support UART wakeup interrupt */ // UART has an extra TX_WAIT_SEND state when the FIFO is not empty and XOFF is enabled @@ -497,16 +502,16 @@ // #define SOC_PM_SUPPORT_BT_WAKEUP (1) // #define SOC_PM_SUPPORT_EXT1_WAKEUP (1) // #define SOC_PM_SUPPORT_EXT1_WAKEUP_MODE_PER_PIN (1) /*!