From fd6c710b27d3e67dd38ef2f9b2ca6e294ca05333 Mon Sep 17 00:00:00 2001 From: Mahavir Jain Date: Mon, 11 Mar 2024 16:46:03 +0530 Subject: [PATCH] fix: cleanup memprot files for C6/H2/P4 There is no separate permission control peripheral in C6/H2/P4. Memory protection is achieved using built-in PMA/PMP and hence removing permission control specific files. --- .../include/soc/esp32p4/soc_memprot_types.h | 175 ------------------ .../port/esp32c6/CMakeLists.txt | 4 - .../port/esp32p4/CMakeLists.txt | 4 - .../esp_system/ld/esp32c2/sections.ld.in | 7 +- .../ld/esp32c5/beta3/sections.ld.in | 9 +- .../esp_system/ld/esp32c6/sections.ld.in | 9 +- .../esp_system/ld/esp32h2/sections.ld.in | 9 +- .../esp_system/ld/esp32p4/sections.ld.in | 9 +- components/heap/port/esp32c5/memory_layout.c | 2 +- components/heap/port/esp32c6/memory_layout.c | 2 +- components/heap/port/esp32h2/memory_layout.c | 2 +- components/heap/port/esp32p4/memory_layout.c | 2 +- .../soc/esp32c6/include/soc/memprot_defs.h | 91 --------- .../soc/esp32h2/include/soc/memprot_defs.h | 91 --------- .../soc/esp32p4/include/soc/memprot_defs.h | 91 --------- 15 files changed, 14 insertions(+), 493 deletions(-) delete mode 100644 components/esp_hw_support/include/soc/esp32p4/soc_memprot_types.h delete mode 100644 components/soc/esp32c6/include/soc/memprot_defs.h delete mode 100644 components/soc/esp32h2/include/soc/memprot_defs.h delete mode 100644 components/soc/esp32p4/include/soc/memprot_defs.h diff --git a/components/esp_hw_support/include/soc/esp32p4/soc_memprot_types.h b/components/esp_hw_support/include/soc/esp32p4/soc_memprot_types.h deleted file mode 100644 index 2138e963bc..0000000000 --- a/components/esp_hw_support/include/soc/esp32p4/soc_memprot_types.h +++ /dev/null @@ -1,175 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -////////////////////////////////////////////////////////// -// ESP32-P4 PMS memory protection types -// - -#pragma once - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief Memory types recognized by PMS - */ -typedef enum { - MEMPROT_TYPE_NONE = 0x00000000, - MEMPROT_TYPE_IRAM0_SRAM = 0x00000001, - MEMPROT_TYPE_DRAM0_SRAM = 0x00000002, - MEMPROT_TYPE_IRAM0_RTCFAST = 0x00000004, - MEMPROT_TYPE_ALL = 0x7FFFFFFF, - MEMPROT_TYPE_INVALID = 0x80000000, - MEMPROT_TYPE_IRAM0_ANY = MEMPROT_TYPE_IRAM0_SRAM | MEMPROT_TYPE_IRAM0_RTCFAST -} esp_mprot_mem_t; - -/** - * @brief Splitting address (line) type - */ -typedef enum { - MEMPROT_SPLIT_ADDR_NONE = 0x00000000, - MEMPROT_SPLIT_ADDR_IRAM0_DRAM0 = 0x00000001, - MEMPROT_SPLIT_ADDR_IRAM0_LINE_0 = 0x00000002, - MEMPROT_SPLIT_ADDR_IRAM0_LINE_1 = 0x00000004, - MEMPROT_SPLIT_ADDR_DRAM0_DMA_LINE_0 = 0x00000008, - MEMPROT_SPLIT_ADDR_DRAM0_DMA_LINE_1 = 0x00000010, - MEMPROT_SPLIT_ADDR_ALL = 0x7FFFFFFF, - MEMPROT_SPLIT_ADDR_INVALID = 0x80000000, - MEMPROT_SPLIT_ADDR_MAIN = MEMPROT_SPLIT_ADDR_IRAM0_DRAM0 -} esp_mprot_split_addr_t; - -/** - * @brief PMS area type (memory space between adjacent splitting addresses or above/below the main splt.address) - */ -typedef enum { - MEMPROT_PMS_AREA_NONE = 0x00000000, - MEMPROT_PMS_AREA_IRAM0_0 = 0x00000001, - MEMPROT_PMS_AREA_IRAM0_1 = 0x00000002, - MEMPROT_PMS_AREA_IRAM0_2 = 0x00000004, - MEMPROT_PMS_AREA_IRAM0_3 = 0x00000008, - MEMPROT_PMS_AREA_DRAM0_0 = 0x00000010, - MEMPROT_PMS_AREA_DRAM0_1 = 0x00000020, - MEMPROT_PMS_AREA_DRAM0_2 = 0x00000040, - MEMPROT_PMS_AREA_DRAM0_3 = 0x00000080, - MEMPROT_PMS_AREA_IRAM0_RTCFAST_LO = 0x00000100, - MEMPROT_PMS_AREA_IRAM0_RTCFAST_HI = 0x00000200, - MEMPROT_PMS_AREA_ALL = 0x7FFFFFFF, - MEMPROT_PMS_AREA_INVALID = 0x80000000 -} esp_mprot_pms_area_t; - -/** -* @brief Memory protection configuration -*/ -typedef struct { - bool invoke_panic_handler; /*!< Register PMS violation interrupt for panic-handling */ - bool lock_feature; /*!< Lock all PMS settings */ - void *split_addr; /*!< Main I/D splitting address */ - uint32_t mem_type_mask; /*!< Memory types required to protect. See esp_mprot_mem_t enum */ -} esp_memp_config_t; - -#define ESP_MEMPROT_DEFAULT_CONFIG() { \ - .invoke_panic_handler = true, \ - .lock_feature = true, \ - .split_addr = NULL, \ - .mem_type_mask = MEMPROT_TYPE_ALL \ -} - -/** - * @brief Converts Memory protection type to string - * - * @param mem_type Memory protection type - */ -static inline const char *esp_mprot_mem_type_to_str(const esp_mprot_mem_t mem_type) -{ - switch (mem_type) { - case MEMPROT_TYPE_NONE: - return "NONE"; - case MEMPROT_TYPE_IRAM0_SRAM: - return "IRAM0_SRAM"; - case MEMPROT_TYPE_DRAM0_SRAM: - return "DRAM0_SRAM"; - case MEMPROT_TYPE_IRAM0_RTCFAST: - return "IRAM0_RTCFAST"; - case MEMPROT_TYPE_IRAM0_ANY: - return "IRAM0_ANY"; - case MEMPROT_TYPE_ALL: - return "ALL"; - default: - return "INVALID"; - } -} - -/** - * @brief Converts Splitting address type to string - * - * @param line_type Split line type - */ -static inline const char *esp_mprot_split_addr_to_str(const esp_mprot_split_addr_t line_type) -{ - switch (line_type) { - case MEMPROT_SPLIT_ADDR_NONE: - return "SPLIT_ADDR_NONE"; - case MEMPROT_SPLIT_ADDR_IRAM0_DRAM0: - return "SPLIT_ADDR_IRAM0_DRAM0"; - case MEMPROT_SPLIT_ADDR_IRAM0_LINE_0: - return "SPLIT_ADDR_IRAM0_LINE_0"; - case MEMPROT_SPLIT_ADDR_IRAM0_LINE_1: - return "SPLIT_ADDR_IRAM0_LINE_1"; - case MEMPROT_SPLIT_ADDR_DRAM0_DMA_LINE_0: - return "SPLIT_ADDR_DRAM0_DMA_LINE_0"; - case MEMPROT_SPLIT_ADDR_DRAM0_DMA_LINE_1: - return "SPLIT_ADDR_DRAM0_DMA_LINE_1"; - case MEMPROT_SPLIT_ADDR_ALL: - return "SPLIT_ADDR_ALL"; - default: - return "SPLIT_ADDR_INVALID"; - } -} - -/** - * @brief Converts PMS Area type to string - * - * @param area_type PMS Area type - */ -static inline const char *esp_mprot_pms_area_to_str(const esp_mprot_pms_area_t area_type) -{ - switch (area_type) { - case MEMPROT_PMS_AREA_NONE: - return "PMS_AREA_NONE"; - case MEMPROT_PMS_AREA_IRAM0_0: - return "PMS_AREA_IRAM0_0"; - case MEMPROT_PMS_AREA_IRAM0_1: - return "PMS_AREA_IRAM0_1"; - case MEMPROT_PMS_AREA_IRAM0_2: - return "PMS_AREA_IRAM0_2"; - case MEMPROT_PMS_AREA_IRAM0_3: - return "PMS_AREA_IRAM0_3"; - case MEMPROT_PMS_AREA_DRAM0_0: - return "PMS_AREA_DRAM0_0"; - case MEMPROT_PMS_AREA_DRAM0_1: - return "PMS_AREA_DRAM0_1"; - case MEMPROT_PMS_AREA_DRAM0_2: - return "PMS_AREA_DRAM0_2"; - case MEMPROT_PMS_AREA_DRAM0_3: - return "PMS_AREA_DRAM0_3"; - case MEMPROT_PMS_AREA_IRAM0_RTCFAST_LO: - return "PMS_AREA_IRAM0_RTCFAST_LO"; - case MEMPROT_PMS_AREA_IRAM0_RTCFAST_HI: - return "PMS_AREA_IRAM0_RTCFAST_HI"; - case MEMPROT_PMS_AREA_ALL: - return "PMS_AREA_ALL"; - default: - return "PMS_AREA_INVALID"; - } -} - -#ifdef __cplusplus -} -#endif diff --git a/components/esp_hw_support/port/esp32c6/CMakeLists.txt b/components/esp_hw_support/port/esp32c6/CMakeLists.txt index 6f8117e424..d0057e2ec1 100644 --- a/components/esp_hw_support/port/esp32c6/CMakeLists.txt +++ b/components/esp_hw_support/port/esp32c6/CMakeLists.txt @@ -12,10 +12,6 @@ if(NOT BOOTLOADER_BUILD) list(APPEND srcs "sar_periph_ctrl.c" "esp_crypto_lock.c") - if(CONFIG_ESP_SYSTEM_MEMPROT_FEATURE) - list(APPEND srcs "esp_memprot.c" "../esp_memprot_conv.c") - endif() - endif() add_prefix(srcs "${CMAKE_CURRENT_LIST_DIR}/" "${srcs}") diff --git a/components/esp_hw_support/port/esp32p4/CMakeLists.txt b/components/esp_hw_support/port/esp32p4/CMakeLists.txt index 37bf7d1a3d..f81f017081 100644 --- a/components/esp_hw_support/port/esp32p4/CMakeLists.txt +++ b/components/esp_hw_support/port/esp32p4/CMakeLists.txt @@ -16,10 +16,6 @@ if(NOT BOOTLOADER_BUILD) list(APPEND srcs "mspi_timing_config.c") endif() - if(CONFIG_ESP_SYSTEM_MEMPROT_FEATURE) - list(APPEND srcs "esp_memprot.c" "../esp_memprot_conv.c") - endif() - endif() add_prefix(srcs "${CMAKE_CURRENT_LIST_DIR}/" "${srcs}") diff --git a/components/esp_system/ld/esp32c2/sections.ld.in b/components/esp_system/ld/esp32c2/sections.ld.in index 8e5feaeb17..dc42e6c2d6 100644 --- a/components/esp_system/ld/esp32c2/sections.ld.in +++ b/components/esp_system/ld/esp32c2/sections.ld.in @@ -281,11 +281,8 @@ SECTIONS /* Marks the end of IRAM code segment */ .iram0.text_end (NOLOAD) : { - /* ESP32-C2 memprot requires 16B padding for possible CPU prefetch and 512B alignment for PMS split lines */ - . += _esp_memprot_prefetch_pad_size; - . = ALIGN(_esp_memprot_align_size); - /* iram_end_test section exists for use by memprot unit tests only */ - *(.iram_end_test) + . = ALIGN(4); + _iram_text_end = ABSOLUTE(.); } > iram0_0_seg diff --git a/components/esp_system/ld/esp32c5/beta3/sections.ld.in b/components/esp_system/ld/esp32c5/beta3/sections.ld.in index fcb2f4755b..1de281f3ff 100644 --- a/components/esp_system/ld/esp32c5/beta3/sections.ld.in +++ b/components/esp_system/ld/esp32c5/beta3/sections.ld.in @@ -27,8 +27,6 @@ SECTIONS *rtc_wake_stub*.*(.literal .text .literal.* .text.*) *(.rtc_text_end_test) - /* 16B padding for possible CPU prefetch and 4B alignment for PMS split lines */ - . += _esp_memprot_prefetch_pad_size; . = ALIGN(4); _rtc_text_end = ABSOLUTE(.); @@ -166,11 +164,8 @@ SECTIONS /* Marks the end of IRAM code segment */ .iram0.text_end (NOLOAD) : { - /* ESP32-C5 memprot requires 16B padding for possible CPU prefetch and 512B alignment for PMS split lines */ - . += _esp_memprot_prefetch_pad_size; - . = ALIGN(_esp_memprot_align_size); - /* iram_end_test section exists for use by memprot unit tests only */ - *(.iram_end_test) + . = ALIGN(4); + _iram_text_end = ABSOLUTE(.); } > iram0_0_seg diff --git a/components/esp_system/ld/esp32c6/sections.ld.in b/components/esp_system/ld/esp32c6/sections.ld.in index 8c55675fbf..fdc2aa8d66 100644 --- a/components/esp_system/ld/esp32c6/sections.ld.in +++ b/components/esp_system/ld/esp32c6/sections.ld.in @@ -27,8 +27,6 @@ SECTIONS *rtc_wake_stub*.*(.literal .text .literal.* .text.*) *(.rtc_text_end_test) - /* 16B padding for possible CPU prefetch and 4B alignment for PMS split lines */ - . += _esp_memprot_prefetch_pad_size; . = ALIGN(4); _rtc_text_end = ABSOLUTE(.); @@ -165,11 +163,8 @@ SECTIONS /* Marks the end of IRAM code segment */ .iram0.text_end (NOLOAD) : { - /* ESP32-C6 memprot requires 16B padding for possible CPU prefetch and 512B alignment for PMS split lines */ - . += _esp_memprot_prefetch_pad_size; - . = ALIGN(_esp_memprot_align_size); - /* iram_end_test section exists for use by memprot unit tests only */ - *(.iram_end_test) + . = ALIGN(4); + _iram_text_end = ABSOLUTE(.); } > sram_seg diff --git a/components/esp_system/ld/esp32h2/sections.ld.in b/components/esp_system/ld/esp32h2/sections.ld.in index b353bac612..f69d925ddd 100644 --- a/components/esp_system/ld/esp32h2/sections.ld.in +++ b/components/esp_system/ld/esp32h2/sections.ld.in @@ -27,8 +27,6 @@ SECTIONS *rtc_wake_stub*.*(.literal .text .literal.* .text.*) *(.rtc_text_end_test) - /* 16B padding for possible CPU prefetch and 4B alignment for PMS split lines */ - . += _esp_memprot_prefetch_pad_size; . = ALIGN(4); _rtc_text_end = ABSOLUTE(.); @@ -165,11 +163,8 @@ SECTIONS /* Marks the end of IRAM code segment */ .iram0.text_end (NOLOAD) : { - /* ESP32-H2 memprot requires 16B padding for possible CPU prefetch and 512B alignment for PMS split lines */ - . += _esp_memprot_prefetch_pad_size; - . = ALIGN(_esp_memprot_align_size); - /* iram_end_test section exists for use by memprot unit tests only */ - *(.iram_end_test) + . = ALIGN(4); + _iram_text_end = ABSOLUTE(.); } > sram_seg diff --git a/components/esp_system/ld/esp32p4/sections.ld.in b/components/esp_system/ld/esp32p4/sections.ld.in index ff10f4e550..873cdf87fe 100644 --- a/components/esp_system/ld/esp32p4/sections.ld.in +++ b/components/esp_system/ld/esp32p4/sections.ld.in @@ -27,8 +27,6 @@ SECTIONS *rtc_wake_stub*.*(.literal .text .literal.* .text.*) *(.rtc_text_end_test) - /* 16B padding for possible CPU prefetch and 4B alignment for PMS split lines */ - . += _esp_memprot_prefetch_pad_size; . = ALIGN(4); _rtc_text_end = ABSOLUTE(.); @@ -195,11 +193,8 @@ SECTIONS /* Marks the end of IRAM code segment */ .iram0.text_end (NOLOAD) : { - /* ESP32-C6 memprot requires 16B padding for possible CPU prefetch and 512B alignment for PMS split lines */ - . += _esp_memprot_prefetch_pad_size; - . = ALIGN(_esp_memprot_align_size); - /* iram_end_test section exists for use by memprot unit tests only */ - *(.iram_end_test) + . = ALIGN(4); + _iram_text_end = ABSOLUTE(.); } > sram_low diff --git a/components/heap/port/esp32c5/memory_layout.c b/components/heap/port/esp32c5/memory_layout.c index 8e2fcfe672..b65d0007d6 100644 --- a/components/heap/port/esp32c5/memory_layout.c +++ b/components/heap/port/esp32c5/memory_layout.c @@ -33,7 +33,7 @@ enum { }; /* COMMON_CAPS is the set of attributes common to all types of memory on this chip */ -#ifdef CONFIG_ESP_SYSTEM_MEMPROT_FEATURE +#ifdef CONFIG_ESP_SYSTEM_PMP_IDRAM_SPLIT #define ESP32C5_MEM_COMMON_CAPS (MALLOC_CAP_DEFAULT | MALLOC_CAP_INTERNAL | MALLOC_CAP_32BIT | MALLOC_CAP_8BIT) #else #define ESP32C5_MEM_COMMON_CAPS (MALLOC_CAP_DEFAULT | MALLOC_CAP_INTERNAL | MALLOC_CAP_32BIT | MALLOC_CAP_8BIT | MALLOC_CAP_EXEC) diff --git a/components/heap/port/esp32c6/memory_layout.c b/components/heap/port/esp32c6/memory_layout.c index 6a1349368d..755e09b0b5 100644 --- a/components/heap/port/esp32c6/memory_layout.c +++ b/components/heap/port/esp32c6/memory_layout.c @@ -33,7 +33,7 @@ enum { }; /* COMMON_CAPS is the set of attributes common to all types of memory on this chip */ -#ifdef CONFIG_ESP_SYSTEM_MEMPROT_FEATURE +#ifdef CONFIG_ESP_SYSTEM_PMP_IDRAM_SPLIT #define ESP32C6_MEM_COMMON_CAPS (MALLOC_CAP_DEFAULT | MALLOC_CAP_INTERNAL | MALLOC_CAP_32BIT | MALLOC_CAP_8BIT) #else #define ESP32C6_MEM_COMMON_CAPS (MALLOC_CAP_DEFAULT | MALLOC_CAP_INTERNAL | MALLOC_CAP_32BIT | MALLOC_CAP_8BIT | MALLOC_CAP_EXEC) diff --git a/components/heap/port/esp32h2/memory_layout.c b/components/heap/port/esp32h2/memory_layout.c index e0fa07be32..5a562df7f2 100644 --- a/components/heap/port/esp32h2/memory_layout.c +++ b/components/heap/port/esp32h2/memory_layout.c @@ -31,7 +31,7 @@ enum { }; /* COMMON_CAPS is the set of attributes common to all types of memory on this chip */ -#ifdef CONFIG_ESP_SYSTEM_MEMPROT_FEATURE +#ifdef CONFIG_ESP_SYSTEM_PMP_IDRAM_SPLIT #define ESP32H2_MEM_COMMON_CAPS (MALLOC_CAP_DEFAULT | MALLOC_CAP_INTERNAL | MALLOC_CAP_32BIT | MALLOC_CAP_8BIT) #else #define ESP32H2_MEM_COMMON_CAPS (MALLOC_CAP_DEFAULT | MALLOC_CAP_INTERNAL | MALLOC_CAP_32BIT | MALLOC_CAP_8BIT | MALLOC_CAP_EXEC) diff --git a/components/heap/port/esp32p4/memory_layout.c b/components/heap/port/esp32p4/memory_layout.c index 127f61da45..04e5a9dfe6 100644 --- a/components/heap/port/esp32p4/memory_layout.c +++ b/components/heap/port/esp32p4/memory_layout.c @@ -36,7 +36,7 @@ enum { /* COMMON_CAPS is the set of attributes common to all types of memory on this chip */ #define ESP32P4_MEM_COMMON_CAPS (MALLOC_CAP_DEFAULT | MALLOC_CAP_32BIT | MALLOC_CAP_8BIT) -#ifdef CONFIG_ESP_SYSTEM_MEMPROT_FEATURE +#ifdef CONFIG_ESP_SYSTEM_PMP_IDRAM_SPLIT #define MALLOC_L2MEM_BASE_CAPS ESP32P4_MEM_COMMON_CAPS | MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA #define MALLOC_RTCRAM_BASE_CAPS ESP32P4_MEM_COMMON_CAPS | MALLOC_CAP_INTERNAL #else diff --git a/components/soc/esp32c6/include/soc/memprot_defs.h b/components/soc/esp32c6/include/soc/memprot_defs.h deleted file mode 100644 index 6db06a8b26..0000000000 --- a/components/soc/esp32c6/include/soc/memprot_defs.h +++ /dev/null @@ -1,91 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#pragma once - -#include "soc/soc.h" -#include "esp32c6/rom/cache.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef union { - struct { - uint32_t cat0 : 2; - uint32_t cat1 : 2; - uint32_t cat2 : 2; - uint32_t res0 : 8; - uint32_t splitaddr : 8; - uint32_t res1 : 10; - }; - uint32_t val; -} constrain_reg_fields_t; - -#ifndef I_D_SRAM_SEGMENT_SIZE -#define I_D_SRAM_SEGMENT_SIZE 0x20000 -#endif - -#define I_D_SPLIT_LINE_SHIFT 0x9 -#define I_D_FAULT_ADDR_SHIFT 0x2 - -#define DRAM_SRAM_START 0x3FC7C000 - -//IRAM0 - -//16kB (ICACHE) -#define IRAM0_SRAM_LEVEL_0_LOW SOC_IRAM_LOW //0x40370000 -#define IRAM0_SRAM_LEVEL_0_HIGH (IRAM0_SRAM_LEVEL_0_LOW + CACHE_MEMORY_IBANK_SIZE - 0x1) //0x4037FFFF - -//128kB (LEVEL 1) -#define IRAM0_SRAM_LEVEL_1_LOW (IRAM0_SRAM_LEVEL_0_HIGH + 0x1) //0x40380000 -#define IRAM0_SRAM_LEVEL_1_HIGH (IRAM0_SRAM_LEVEL_1_LOW + I_D_SRAM_SEGMENT_SIZE - 0x1) //0x4039FFFF - -//128kB (LEVEL 2) -#define IRAM0_SRAM_LEVEL_2_LOW (IRAM0_SRAM_LEVEL_1_HIGH + 0x1) //0x403A0000 -#define IRAM0_SRAM_LEVEL_2_HIGH (IRAM0_SRAM_LEVEL_2_LOW + I_D_SRAM_SEGMENT_SIZE - 0x1) //0x403BFFFF - -//128kB (LEVEL 3) -#define IRAM0_SRAM_LEVEL_3_LOW (IRAM0_SRAM_LEVEL_2_HIGH + 0x1) //0x403C0000 -#define IRAM0_SRAM_LEVEL_3_HIGH (IRAM0_SRAM_LEVEL_3_LOW + I_D_SRAM_SEGMENT_SIZE - 0x1) //0x403DFFFF - -//permission bits -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_X_R 0x1 -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_X_W 0x2 -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_X_F 0x4 - -//DRAM0 - -//16kB ICACHE not available from DRAM0 - -//128kB (LEVEL 1) -#define DRAM0_SRAM_LEVEL_1_LOW SOC_DRAM_LOW //0x3FC80000 -#define DRAM0_SRAM_LEVEL_1_HIGH (DRAM0_SRAM_LEVEL_1_LOW + I_D_SRAM_SEGMENT_SIZE - 0x1) //0x3FC9FFFF - -//128kB (LEVEL 2) -#define DRAM0_SRAM_LEVEL_2_LOW (DRAM0_SRAM_LEVEL_1_HIGH + 0x1) //0x3FCA0000 -#define DRAM0_SRAM_LEVEL_2_HIGH (DRAM0_SRAM_LEVEL_2_LOW + I_D_SRAM_SEGMENT_SIZE - 0x1) //0x3FCBFFFF - -//128kB (LEVEL 3) -#define DRAM0_SRAM_LEVEL_3_LOW (DRAM0_SRAM_LEVEL_2_HIGH + 0x1) //0x3FCC0000 -#define DRAM0_SRAM_LEVEL_3_HIGH (DRAM0_SRAM_LEVEL_3_LOW + I_D_SRAM_SEGMENT_SIZE - 0x1) //0x3FCDFFFF - -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_X_R 0x1 -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_X_W 0x2 - -//RTC FAST - -//permission bits -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_X_W 0x1 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_X_R 0x2 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_X_F 0x4 - -#define AREA_LOW 0 -#define AREA_HIGH 1 - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32h2/include/soc/memprot_defs.h b/components/soc/esp32h2/include/soc/memprot_defs.h deleted file mode 100644 index 447ad17e3b..0000000000 --- a/components/soc/esp32h2/include/soc/memprot_defs.h +++ /dev/null @@ -1,91 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#pragma once - -#include "soc/soc.h" -#include "esp32h2/rom/cache.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef union { - struct { - uint32_t cat0 : 2; - uint32_t cat1 : 2; - uint32_t cat2 : 2; - uint32_t res0 : 8; - uint32_t splitaddr : 8; - uint32_t res1 : 10; - }; - uint32_t val; -} constrain_reg_fields_t; - -#ifndef I_D_SRAM_SEGMENT_SIZE -#define I_D_SRAM_SEGMENT_SIZE 0x20000 -#endif - -#define I_D_SPLIT_LINE_SHIFT 0x9 -#define I_D_FAULT_ADDR_SHIFT 0x2 - -#define DRAM_SRAM_START 0x3FC7C000 - -//IRAM0 - -//16kB (ICACHE) -#define IRAM0_SRAM_LEVEL_0_LOW SOC_IRAM_LOW //0x40370000 -#define IRAM0_SRAM_LEVEL_0_HIGH (IRAM0_SRAM_LEVEL_0_LOW + CACHE_MEMORY_IBANK_SIZE - 0x1) //0x4037FFFF - -//128kB (LEVEL 1) -#define IRAM0_SRAM_LEVEL_1_LOW (IRAM0_SRAM_LEVEL_0_HIGH + 0x1) //0x40380000 -#define IRAM0_SRAM_LEVEL_1_HIGH (IRAM0_SRAM_LEVEL_1_LOW + I_D_SRAM_SEGMENT_SIZE - 0x1) //0x4039FFFF - -//128kB (LEVEL 2) -#define IRAM0_SRAM_LEVEL_2_LOW (IRAM0_SRAM_LEVEL_1_HIGH + 0x1) //0x403A0000 -#define IRAM0_SRAM_LEVEL_2_HIGH (IRAM0_SRAM_LEVEL_2_LOW + I_D_SRAM_SEGMENT_SIZE - 0x1) //0x403BFFFF - -//128kB (LEVEL 3) -#define IRAM0_SRAM_LEVEL_3_LOW (IRAM0_SRAM_LEVEL_2_HIGH + 0x1) //0x403C0000 -#define IRAM0_SRAM_LEVEL_3_HIGH (IRAM0_SRAM_LEVEL_3_LOW + I_D_SRAM_SEGMENT_SIZE - 0x1) //0x403DFFFF - -//permission bits -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_X_R 0x1 -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_X_W 0x2 -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_X_F 0x4 - -//DRAM0 - -//16kB ICACHE not available from DRAM0 - -//128kB (LEVEL 1) -#define DRAM0_SRAM_LEVEL_1_LOW SOC_DRAM_LOW //0x3FC80000 -#define DRAM0_SRAM_LEVEL_1_HIGH (DRAM0_SRAM_LEVEL_1_LOW + I_D_SRAM_SEGMENT_SIZE - 0x1) //0x3FC9FFFF - -//128kB (LEVEL 2) -#define DRAM0_SRAM_LEVEL_2_LOW (DRAM0_SRAM_LEVEL_1_HIGH + 0x1) //0x3FCA0000 -#define DRAM0_SRAM_LEVEL_2_HIGH (DRAM0_SRAM_LEVEL_2_LOW + I_D_SRAM_SEGMENT_SIZE - 0x1) //0x3FCBFFFF - -//128kB (LEVEL 3) -#define DRAM0_SRAM_LEVEL_3_LOW (DRAM0_SRAM_LEVEL_2_HIGH + 0x1) //0x3FCC0000 -#define DRAM0_SRAM_LEVEL_3_HIGH (DRAM0_SRAM_LEVEL_3_LOW + I_D_SRAM_SEGMENT_SIZE - 0x1) //0x3FCDFFFF - -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_X_R 0x1 -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_X_W 0x2 - -//RTC FAST - -//permission bits -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_X_W 0x1 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_X_R 0x2 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_X_F 0x4 - -#define AREA_LOW 0 -#define AREA_HIGH 1 - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/include/soc/memprot_defs.h b/components/soc/esp32p4/include/soc/memprot_defs.h deleted file mode 100644 index 9723f61eb5..0000000000 --- a/components/soc/esp32p4/include/soc/memprot_defs.h +++ /dev/null @@ -1,91 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#pragma once - -#include "soc/soc.h" -#include "esp32p4/rom/cache.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef union { - struct { - uint32_t cat0 : 2; - uint32_t cat1 : 2; - uint32_t cat2 : 2; - uint32_t res0 : 8; - uint32_t splitaddr : 8; - uint32_t res1 : 10; - }; - uint32_t val; -} constrain_reg_fields_t; - -#ifndef I_D_SRAM_SEGMENT_SIZE -#define I_D_SRAM_SEGMENT_SIZE 0x20000 -#endif - -#define I_D_SPLIT_LINE_SHIFT 0x9 -#define I_D_FAULT_ADDR_SHIFT 0x2 - -#define DRAM_SRAM_START 0x3FC7C000 - -//IRAM0 - -//16kB (ICACHE) -#define IRAM0_SRAM_LEVEL_0_LOW SOC_IRAM_LOW //0x40370000 -#define IRAM0_SRAM_LEVEL_0_HIGH (IRAM0_SRAM_LEVEL_0_LOW + CACHE_MEMORY_IBANK_SIZE - 0x1) //0x4037FFFF - -//128kB (LEVEL 1) -#define IRAM0_SRAM_LEVEL_1_LOW (IRAM0_SRAM_LEVEL_0_HIGH + 0x1) //0x40380000 -#define IRAM0_SRAM_LEVEL_1_HIGH (IRAM0_SRAM_LEVEL_1_LOW + I_D_SRAM_SEGMENT_SIZE - 0x1) //0x4039FFFF - -//128kB (LEVEL 2) -#define IRAM0_SRAM_LEVEL_2_LOW (IRAM0_SRAM_LEVEL_1_HIGH + 0x1) //0x403A0000 -#define IRAM0_SRAM_LEVEL_2_HIGH (IRAM0_SRAM_LEVEL_2_LOW + I_D_SRAM_SEGMENT_SIZE - 0x1) //0x403BFFFF - -//128kB (LEVEL 3) -#define IRAM0_SRAM_LEVEL_3_LOW (IRAM0_SRAM_LEVEL_2_HIGH + 0x1) //0x403C0000 -#define IRAM0_SRAM_LEVEL_3_HIGH (IRAM0_SRAM_LEVEL_3_LOW + I_D_SRAM_SEGMENT_SIZE - 0x1) //0x403DFFFF - -//permission bits -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_X_R 0x1 -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_X_W 0x2 -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_X_F 0x4 - -//DRAM0 - -//16kB ICACHE not available from DRAM0 - -//128kB (LEVEL 1) -#define DRAM0_SRAM_LEVEL_1_LOW SOC_DRAM_LOW //0x3FC80000 -#define DRAM0_SRAM_LEVEL_1_HIGH (DRAM0_SRAM_LEVEL_1_LOW + I_D_SRAM_SEGMENT_SIZE - 0x1) //0x3FC9FFFF - -//128kB (LEVEL 2) -#define DRAM0_SRAM_LEVEL_2_LOW (DRAM0_SRAM_LEVEL_1_HIGH + 0x1) //0x3FCA0000 -#define DRAM0_SRAM_LEVEL_2_HIGH (DRAM0_SRAM_LEVEL_2_LOW + I_D_SRAM_SEGMENT_SIZE - 0x1) //0x3FCBFFFF - -//128kB (LEVEL 3) -#define DRAM0_SRAM_LEVEL_3_LOW (DRAM0_SRAM_LEVEL_2_HIGH + 0x1) //0x3FCC0000 -#define DRAM0_SRAM_LEVEL_3_HIGH (DRAM0_SRAM_LEVEL_3_LOW + I_D_SRAM_SEGMENT_SIZE - 0x1) //0x3FCDFFFF - -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_X_R 0x1 -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_X_W 0x2 - -//RTC FAST - -//permission bits -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_X_W 0x1 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_X_R 0x2 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_X_F 0x4 - -#define AREA_LOW 0 -#define AREA_HIGH 1 - -#ifdef __cplusplus -} -#endif