4 Commits

Author	SHA1	Message	Date
Omar Chebib	c218f669ba	panic on RISC-V: Take into account Merge Request comments	2020-12-31 15:46:17 +08:00
Omar Chebib	a90dcfba1a	panic: Add support for SoC-level panic ... Activate "invalid access to cache raises panic (PRO CPU)" CI unit test in order to test SoC-level panics.	2020-12-31 15:46:17 +08:00
Omar Chebib	b6a450f824	panic: Add support for SoC-level panic ... SoC level exceptions such as watchdog timer and cache errors are now supported. Such exceptions now triggers a panic, giving more information about how and when it happened.	2020-12-31 15:46:17 +08:00
morris	8330b2541a	esp32c3: added target component	2020-12-11 11:44:01 +08:00