forked from espressif/esp-idf
220 lines
6.7 KiB
C
220 lines
6.7 KiB
C
// Copyright 2010-2017 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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/*
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* DPORT access is used for do protection when dual core access DPORT internal register and APB register via DPORT simultaneously
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* This function will be initialize after FreeRTOS startup.
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* When cpu0 want to access DPORT register, it should notify cpu1 enter in high-priority interrupt for be mute. When cpu1 already in high-priority interrupt,
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* cpu0 can access DPORT register. Currently, cpu1 will wait for cpu0 finish access and exit high-priority interrupt.
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*/
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#include <stdint.h>
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#include <string.h>
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#include <sdkconfig.h>
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#include "esp_attr.h"
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#include "esp_err.h"
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#include "esp_intr.h"
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#include "rom/ets_sys.h"
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#include "rom/uart.h"
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#include "soc/cpu.h"
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#include "soc/dport_reg.h"
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#include "soc/spi_reg.h"
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#include "freertos/FreeRTOS.h"
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#include "freertos/task.h"
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#include "freertos/semphr.h"
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#include "freertos/queue.h"
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#include "freertos/portmacro.h"
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#include "xtensa/core-macros.h"
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#ifndef CONFIG_FREERTOS_UNICORE
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static portMUX_TYPE g_dport_mux = portMUX_INITIALIZER_UNLOCKED;
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#define DPORT_CORE_STATE_IDLE 0
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#define DPORT_CORE_STATE_RUNNING 1
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static uint32_t volatile dport_core_state[portNUM_PROCESSORS]; //cpu is already run
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/* these global variables are accessed from interrupt vector, hence not declared as static */
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uint32_t volatile dport_access_start[portNUM_PROCESSORS]; //dport register could be accessed
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uint32_t volatile dport_access_end[portNUM_PROCESSORS]; //dport register is accessed over
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static uint32_t volatile dport_access_ref[portNUM_PROCESSORS]; //dport access reference
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#ifdef DPORT_ACCESS_BENCHMARK
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#define DPORT_ACCESS_BENCHMARK_STORE_NUM
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static uint32_t ccount_start[portNUM_PROCESSORS];
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static uint32_t ccount_end[portNUM_PROCESSORS];
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static uint32_t ccount_margin[portNUM_PROCESSORS][DPORT_ACCESS_BENCHMARK_STORE_NUM];
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static uint32_t ccount_margin_cnt;
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#endif
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static BaseType_t oldInterruptLevel[2];
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#endif // CONFIG_FREERTOS_UNICORE
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/* stall other cpu that this cpu is pending to access dport register start */
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void IRAM_ATTR esp_dport_access_stall_other_cpu_start(void)
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{
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#ifndef CONFIG_FREERTOS_UNICORE
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if (dport_core_state[0] == DPORT_CORE_STATE_IDLE
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|| dport_core_state[1] == DPORT_CORE_STATE_IDLE) {
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return;
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}
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BaseType_t intLvl = portENTER_CRITICAL_NESTED();
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int cpu_id = xPortGetCoreID();
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#ifdef DPORT_ACCESS_BENCHMARK
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ccount_start[cpu_id] = XTHAL_GET_CCOUNT();
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#endif
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if (dport_access_ref[cpu_id] == 0) {
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portENTER_CRITICAL_ISR(&g_dport_mux);
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oldInterruptLevel[cpu_id]=intLvl;
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dport_access_start[cpu_id] = 0;
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dport_access_end[cpu_id] = 0;
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if (cpu_id == 0) {
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_DPORT_REG_WRITE(DPORT_CPU_INTR_FROM_CPU_3_REG, DPORT_CPU_INTR_FROM_CPU_3); //interrupt on cpu1
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} else {
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_DPORT_REG_WRITE(DPORT_CPU_INTR_FROM_CPU_2_REG, DPORT_CPU_INTR_FROM_CPU_2); //interrupt on cpu0
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}
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while (!dport_access_start[cpu_id]) {};
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REG_READ(SPI_DATE_REG(3)); //just read a APB register sure that the APB-bus is idle
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}
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dport_access_ref[cpu_id]++;
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if (dport_access_ref[cpu_id] > 1) {
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/* Interrupts are already disabled by the parent, we're nested here. */
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portEXIT_CRITICAL_NESTED(intLvl);
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}
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#endif /* CONFIG_FREERTOS_UNICORE */
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}
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/* stall other cpu that this cpu is pending to access dport register end */
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void IRAM_ATTR esp_dport_access_stall_other_cpu_end(void)
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{
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#ifndef CONFIG_FREERTOS_UNICORE
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int cpu_id = xPortGetCoreID();
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if (dport_core_state[0] == DPORT_CORE_STATE_IDLE
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|| dport_core_state[1] == DPORT_CORE_STATE_IDLE) {
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return;
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}
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if (dport_access_ref[cpu_id] == 0) {
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assert(0);
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}
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dport_access_ref[cpu_id]--;
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if (dport_access_ref[cpu_id] == 0) {
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dport_access_end[cpu_id] = 1;
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portEXIT_CRITICAL_ISR(&g_dport_mux);
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portEXIT_CRITICAL_NESTED(oldInterruptLevel[cpu_id]);
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}
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#ifdef DPORT_ACCESS_BENCHMARK
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ccount_end[cpu_id] = XTHAL_GET_CCOUNT();
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ccount_margin[cpu_id][ccount_margin_cnt] = ccount_end[cpu_id] - ccount_start[cpu_id];
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ccount_margin_cnt = (ccount_margin_cnt + 1)&(DPORT_ACCESS_BENCHMARK_STORE_NUM - 1);
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#endif
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#endif /* CONFIG_FREERTOS_UNICORE */
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}
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void IRAM_ATTR esp_dport_access_stall_other_cpu_start_wrap(void)
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{
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DPORT_STALL_OTHER_CPU_START();
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}
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void IRAM_ATTR esp_dport_access_stall_other_cpu_end_wrap(void)
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{
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DPORT_STALL_OTHER_CPU_END();
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}
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#ifndef CONFIG_FREERTOS_UNICORE
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static void dport_access_init_core(void *arg)
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{
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int core_id = 0;
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uint32_t intr_source = ETS_FROM_CPU_INTR2_SOURCE;
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core_id = xPortGetCoreID();
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if (core_id == 1) {
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intr_source = ETS_FROM_CPU_INTR3_SOURCE;
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}
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ESP_INTR_DISABLE(ETS_DPORT_INUM);
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intr_matrix_set(core_id, intr_source, ETS_DPORT_INUM);
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ESP_INTR_ENABLE(ETS_DPORT_INUM);
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dport_access_ref[core_id] = 0;
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dport_access_start[core_id] = 0;
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dport_access_end[core_id] = 0;
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dport_core_state[core_id] = DPORT_CORE_STATE_RUNNING;
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vTaskDelete(NULL);
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}
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#endif
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/* Defer initialisation until after scheduler is running */
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void esp_dport_access_int_init(void)
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{
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#ifndef CONFIG_FREERTOS_UNICORE
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portBASE_TYPE res = xTaskCreatePinnedToCore(&dport_access_init_core, "dport", configMINIMAL_STACK_SIZE, NULL, 5, NULL, xPortGetCoreID());
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assert(res == pdTRUE);
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#endif
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}
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void IRAM_ATTR esp_dport_access_int_pause(void)
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{
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#ifndef CONFIG_FREERTOS_UNICORE
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portENTER_CRITICAL_ISR(&g_dport_mux);
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dport_core_state[0] = DPORT_CORE_STATE_IDLE;
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dport_core_state[1] = DPORT_CORE_STATE_IDLE;
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portEXIT_CRITICAL_ISR(&g_dport_mux);
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#endif
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}
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//Used in panic code: the enter_critical stuff may be messed up so we just stop everything without checking the mux.
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void IRAM_ATTR esp_dport_access_int_abort(void)
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{
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#ifndef CONFIG_FREERTOS_UNICORE
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dport_core_state[0] = DPORT_CORE_STATE_IDLE;
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dport_core_state[1] = DPORT_CORE_STATE_IDLE;
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#endif
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}
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void IRAM_ATTR esp_dport_access_int_resume(void)
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{
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#ifndef CONFIG_FREERTOS_UNICORE
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portENTER_CRITICAL_ISR(&g_dport_mux);
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dport_core_state[0] = DPORT_CORE_STATE_RUNNING;
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dport_core_state[1] = DPORT_CORE_STATE_RUNNING;
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portEXIT_CRITICAL_ISR(&g_dport_mux);
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#endif
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}
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