Omar Chebib 752026a174 Merge branch 'refactor/remove_g0_dep_on_g1_riscv' into 'master' ...

G0: RISC-V targets have now an independent G0 layer

See merge request espressif/esp-idf!17926

2022-06-16 11:53:39 +08:00

..

include/hal

Merge branch 'refactor/remove_g0_dep_on_g1_riscv' into 'master'

2022-06-16 11:53:39 +08:00

brownout_hal.c

G0 RISC-V: Remove "private_include/regi2c_brownout.h" header as it has been moved and simplify "regi2c_ctrl.h"

2022-06-14 15:00:53 +08:00

efuse_hal.c

efuse_hal: Fix error bits for BLOCK0

2022-05-24 03:28:57 +08:00

rtc_cntl_hal.c

i2c: support esp32c2

2022-02-23 15:19:37 +08:00