forked from espressif/esp-idf
Xiao Xufeng
40dd5e3957
When DMA keep writing the memory, some data may be corrupted after reset. For example, the stack of bootloader may be overwritten and failed to boot until a higher scope of reset (Core). Also removed the DPORT_PERIP_RST_EN_REG alias on ESP32S2. Now it's the same as some following chips (EN0).
168 lines
6.3 KiB
C
168 lines
6.3 KiB
C
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/*
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* SPDX-FileCopyrightText: 2018-2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <string.h>
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#include "esp_macros.h"
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#include "sdkconfig.h"
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#include "esp_system.h"
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#include "esp_private/system_internal.h"
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#include "esp_attr.h"
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#include "esp_log.h"
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#include "esp_rom_serial_output.h"
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#include "soc/soc_caps.h"
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#include "soc/dport_reg.h"
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#include "soc/gpio_reg.h"
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#include "soc/timer_group_reg.h"
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#include "esp_cpu.h"
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#include "soc/rtc.h"
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#include "esp_private/rtc_clk.h"
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#include "soc/syscon_reg.h"
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#include "soc/rtc_periph.h"
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#include "hal/wdt_hal.h"
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#include "hal/uart_ll.h"
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#include "soc/soc_memory_layout.h"
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#include "esp32s3/rom/cache.h"
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#include "esp32s3/rom/rtc.h"
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#define ALIGN_DOWN(val, align) ((val) & ~((align) - 1))
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extern int _bss_end;
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void esp_system_reset_modules_on_exit(void)
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{
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// Flush any data left in UART FIFOs before reset the UART peripheral
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for (int i = 0; i < SOC_UART_HP_NUM; ++i) {
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if (uart_ll_is_enabled(i)) {
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esp_rom_output_tx_wait_idle(i);
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}
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}
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// Reset wifi/bluetooth/ethernet/sdio (bb/mac)
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SET_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG,
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SYSTEM_WIFIBB_RST | SYSTEM_FE_RST | SYSTEM_WIFIMAC_RST | SYSTEM_SDIO_RST |
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SYSTEM_EMAC_RST | SYSTEM_MACPWR_RST | SYSTEM_BTBB_RST | SYSTEM_BTBB_REG_RST |
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SYSTEM_RW_BTMAC_RST | SYSTEM_RW_BTLP_RST | SYSTEM_RW_BTMAC_REG_RST | SYSTEM_RW_BTLP_REG_RST);
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REG_WRITE(SYSTEM_CORE_RST_EN_REG, 0);
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// Reset timer, systimer, spi, uart, mcpwm
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SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN0_REG,
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SYSTEM_TIMERS_RST | SYSTEM_SPI01_RST | SYSTEM_UART_RST | SYSTEM_SYSTIMER_RST |
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SYSTEM_PWM0_RST | SYSTEM_PWM1_RST);
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REG_WRITE(SYSTEM_PERIP_RST_EN0_REG, 0);
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// Reset dma and crypto peripherals. This ensures a clean state for the crypto peripherals after a CPU restart
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// and hence avoiding any possibility with crypto failure in ROM security workflows.
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SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN1_REG, SYSTEM_DMA_RST | SYSTEM_CRYPTO_AES_RST | SYSTEM_CRYPTO_DS_RST |
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SYSTEM_CRYPTO_HMAC_RST | SYSTEM_CRYPTO_RSA_RST | SYSTEM_CRYPTO_SHA_RST |
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// The DMA inside SDMMC Host needs to be reset to avoid memory corruption after restart.
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SYSTEM_SDIO_HOST_RST);
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REG_WRITE(SYSTEM_PERIP_RST_EN1_REG, 0);
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SET_PERI_REG_MASK(SYSTEM_EDMA_CTRL_REG, SYSTEM_EDMA_RESET);
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CLEAR_PERI_REG_MASK(SYSTEM_EDMA_CTRL_REG, SYSTEM_EDMA_RESET);
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}
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/* "inner" restart function for after RTOS, interrupts & anything else on this
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* core are already stopped. Stalls other core, resets hardware,
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* triggers restart.
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*/
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void esp_restart_noos(void)
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{
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// Disable interrupts
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esp_cpu_intr_disable(0xFFFFFFFF);
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// Enable RTC watchdog for 1 second
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wdt_hal_context_t rtc_wdt_ctx;
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wdt_hal_init(&rtc_wdt_ctx, WDT_RWDT, 0, false);
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uint32_t stage_timeout_ticks = (uint32_t)(1000ULL * rtc_clk_slow_freq_get_hz() / 1000ULL);
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wdt_hal_write_protect_disable(&rtc_wdt_ctx);
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wdt_hal_config_stage(&rtc_wdt_ctx, WDT_STAGE0, stage_timeout_ticks, WDT_STAGE_ACTION_RESET_SYSTEM);
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wdt_hal_config_stage(&rtc_wdt_ctx, WDT_STAGE1, stage_timeout_ticks, WDT_STAGE_ACTION_RESET_RTC);
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//Enable flash boot mode so that flash booting after restart is protected by the RTC WDT.
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wdt_hal_set_flashboot_en(&rtc_wdt_ctx, true);
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wdt_hal_write_protect_enable(&rtc_wdt_ctx);
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// Disable TG0/TG1 watchdogs
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wdt_hal_context_t wdt0_context = {.inst = WDT_MWDT0, .mwdt_dev = &TIMERG0};
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wdt_hal_write_protect_disable(&wdt0_context);
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wdt_hal_disable(&wdt0_context);
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wdt_hal_write_protect_enable(&wdt0_context);
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wdt_hal_context_t wdt1_context = {.inst = WDT_MWDT1, .mwdt_dev = &TIMERG1};
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wdt_hal_write_protect_disable(&wdt1_context);
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wdt_hal_disable(&wdt1_context);
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wdt_hal_write_protect_enable(&wdt1_context);
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#ifdef CONFIG_FREERTOS_TASK_CREATE_ALLOW_EXT_MEM
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if (esp_ptr_external_ram(esp_cpu_get_sp())) {
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// If stack_addr is from External Memory (CONFIG_FREERTOS_TASK_CREATE_ALLOW_EXT_MEM is used)
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// then need to switch SP to Internal Memory otherwise
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// we will get the "Cache disabled but cached memory region accessed" error after Cache_Read_Disable.
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uint32_t new_sp = ALIGN_DOWN(_bss_end, 16);
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SET_STACK(new_sp);
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}
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#endif
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// Reset and stall the other CPU.
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// CPU must be reset before stalling, in case it was running a s32c1i
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// instruction. This would cause memory pool to be locked by arbiter
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// to the stalled CPU, preventing current CPU from accessing this pool.
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const uint32_t core_id = esp_cpu_get_core_id();
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#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
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const uint32_t other_core_id = (core_id == 0) ? 1 : 0;
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esp_rom_software_reset_cpu(other_core_id);
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esp_cpu_stall(other_core_id);
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#endif
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// Disable cache
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Cache_Disable_ICache();
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Cache_Disable_DCache();
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// 2nd stage bootloader reconfigures SPI flash signals.
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// Reset them to the defaults expected by ROM.
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WRITE_PERI_REG(GPIO_FUNC0_IN_SEL_CFG_REG, 0x30);
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WRITE_PERI_REG(GPIO_FUNC1_IN_SEL_CFG_REG, 0x30);
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WRITE_PERI_REG(GPIO_FUNC2_IN_SEL_CFG_REG, 0x30);
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WRITE_PERI_REG(GPIO_FUNC3_IN_SEL_CFG_REG, 0x30);
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WRITE_PERI_REG(GPIO_FUNC4_IN_SEL_CFG_REG, 0x30);
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WRITE_PERI_REG(GPIO_FUNC5_IN_SEL_CFG_REG, 0x30);
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// reset necessary peripheral modules
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esp_system_reset_modules_on_exit();
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// Set CPU back to XTAL source, same as hard reset, but keep BBPLL on so that USB Serial JTAG can log at 1st stage bootloader.
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#if !CONFIG_IDF_ENV_FPGA
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rtc_clk_cpu_set_to_default_config();
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#endif
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#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
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// Clear entry point for APP CPU
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REG_WRITE(SYSTEM_CORE_1_CONTROL_1_REG, 0);
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#endif
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// Reset CPUs
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if (core_id == 0) {
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// Running on PRO CPU: APP CPU is stalled. Can reset both CPUs.
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#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
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esp_rom_software_reset_cpu(1);
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#endif
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esp_rom_software_reset_cpu(0);
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}
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#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
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else {
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// Running on APP CPU: need to reset PRO CPU and unstall it,
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// then reset APP CPU
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esp_rom_software_reset_cpu(0);
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esp_cpu_unstall(0);
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esp_rom_software_reset_cpu(1);
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}
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#endif
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ESP_INFINITE_LOOP();
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}
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